JP2000311229A - Ic card and its production - Google Patents
Ic card and its productionInfo
- Publication number
- JP2000311229A JP2000311229A JP11119338A JP11933899A JP2000311229A JP 2000311229 A JP2000311229 A JP 2000311229A JP 11119338 A JP11119338 A JP 11119338A JP 11933899 A JP11933899 A JP 11933899A JP 2000311229 A JP2000311229 A JP 2000311229A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- card
- electrode
- wiring board
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は配線基板上に半導体
チップを搭載したＩＣカード及びその製造方法に関する
ものである。[0001] 1. Field of the Invention [0002] The present invention relates to an IC card having a semiconductor chip mounted on a wiring board and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来から広く使われてきている磁気カー
ドは、セキュリティ及び情報の記憶容量の点で不十分な
ことから、近年この要求を満たすことが出来るＩＣカー
ドの需要が急速に高まってきている。ＩＣカードはマイ
クロプロセッサ、半導体メモリー等を組み込んだ半導体
チップを回路基板上に実装し、表裏を絶縁シート等で挟
み込んでカード化したものである。2. Description of the Related Art The demand for IC cards that can satisfy this demand has been rapidly increasing in recent years because magnetic cards that have been widely used in the past are insufficient in terms of security and information storage capacity. I have. An IC card is a card in which a semiconductor chip incorporating a microprocessor, a semiconductor memory, and the like is mounted on a circuit board, and the front and back are sandwiched between insulating sheets or the like.
【０００３】図５、図６を用いて、従来のＩＣカードに
ついて説明する。図５はワイヤボンディング方式によ
り、半導体チップを実装したＩＣカードの断面図であ
る。図において、配線基板１００の上面には配線導体１
０２及び接続パッド１０４が形成されており、この基板
上に半導体チップ１１０が回路面を上にした、いわゆる
フェースアップで配置、固定されている。半導体チップ
１１０の回路面には電極１１２が形成されており、この
電極１１２と接続パッド１０４は金（Ａｕ）等のワイヤ
１１４でボンディングされ、電気的に接続されている。
半導体チップ１１０と接続パッド１０４及びワイヤ１１
４を含む半導体チップ配置部は封止樹脂１２０で覆われ
ている。半導体チップ１１０が配置されるエリアを除い
た部分にはスペーサ１３０が配置されている。配線基板
１００と表カバーシート１４０の間は接着剤１５０によ
って、また、配線基板１００と裏カバーシート１４２と
の間は接着剤１５２によって接着され、表カバーシート
１４０と裏カバーシート１４２で半導体チップ１１０を
搭載した配線基板１００とスペーサー１３０を挟み込ん
で一体化し、ＩＣカードが形成される。この構造及び製
造方法について、例えば、特開平１０−２６４５６３号
公報に記載されている。A conventional IC card will be described with reference to FIGS. FIG. 5 is a sectional view of an IC card on which a semiconductor chip is mounted by a wire bonding method. In the figure, a wiring conductor 1 is provided on the upper surface of a wiring board 100.
The semiconductor chip 110 is disposed and fixed on the substrate in a so-called face-up manner with the circuit surface facing up. An electrode 112 is formed on the circuit surface of the semiconductor chip 110, and the electrode 112 and the connection pad 104 are bonded by a wire 114 such as gold (Au) and are electrically connected.
Semiconductor chip 110, connection pad 104 and wire 11
4 is covered with a sealing resin 120. Spacers 130 are arranged in portions other than the area where the semiconductor chip 110 is arranged. The wiring board 100 and the front cover sheet 140 are adhered by an adhesive 150, and the wiring board 100 and the back cover sheet 142 are adhered by an adhesive 152. The IC card is formed by sandwiching and integrating the wiring board 100 on which the is mounted and the spacer 130. This structure and manufacturing method are described in, for example, Japanese Patent Application Laid-Open No. H10-264563.
【０００４】図６はＦＣＡ（Ｆｌｉｐ Ｃｈｉｐ Ａｔ
ｔａｃｈ）方式により半導体チップを実装したＩＣカー
ドの断面図である。図において、図５と同じ機能を持つ
ものに対しては同一の参照番号をつけ、その説明を省略
する。半導体チップ１１０は回路面を配線基板１００の
接続パッド１０４と向かい合った位置、すなわちフェー
スダウンで配置されている。半導体チップ１１０の上面
には電極１１２が形成され、この電極１１２にはバンプ
１１６が形成され、このバンプ１１６と配線基板上の接
続パッド１０４が電気的に接続されている。接続部を含
む半導体チップ１１０の表面と配線基板１００の表面は
封止樹脂１２０が充填され、機械的な固定と耐湿保護を
行っている。この構造及び製造方法については、例え
ば、特開平８―２３０３６７号公報、特開平１０―３０
５６７９号公報に記載されている。FIG. 6 shows an FCA (Flip Chip At).
FIG. 3 is a cross-sectional view of an IC card on which a semiconductor chip is mounted by a (tach) method. In the drawing, components having the same functions as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. The semiconductor chip 110 is arranged at a position where the circuit surface faces the connection pad 104 of the wiring board 100, that is, face down. An electrode 112 is formed on the upper surface of the semiconductor chip 110, a bump 116 is formed on the electrode 112, and the bump 116 is electrically connected to the connection pad 104 on the wiring board. The surface of the semiconductor chip 110 including the connection portion and the surface of the wiring substrate 100 are filled with a sealing resin 120 to perform mechanical fixing and moisture-proof protection. The structure and manufacturing method are described in, for example, JP-A-8-230367 and JP-A-10-30.
No. 5,679.
【０００５】[0005]
【発明が解決しようとする課題】前述のワイヤボンディ
ング方式では、半導体チップの電極と配線基板の接続パ
ッドをワイヤボンディングした後に、接続部及びワイヤ
部分を機械的に補強し、耐湿保護を行なう目的で絶縁樹
脂による封止を行っている。この樹脂封止はワイヤに余
計な力がかからないように液状の樹脂を用いて、ディス
ペンサー等で接続部に流し込む方法、スクリーン印刷で
塗布する方法等によって行われる。ところが、この樹脂
封止は液状材料を取り扱う関係で作業性が悪い。また、
加熱による硬化処理が必要であるため、その処理に要す
る時間が長く、生産性が悪いという問題があった。In the above-mentioned wire bonding method, after the electrodes of the semiconductor chip and the connection pads of the wiring board are wire-bonded, the connection portions and the wire portions are mechanically reinforced to provide protection against moisture. Sealing with insulating resin is performed. This resin sealing is performed by using a liquid resin so that no extra force is applied to the wires, pouring it into a connection portion with a dispenser or the like, applying screen printing, or the like. However, this resin sealing has poor workability due to the handling of liquid materials. Also,
Since a curing treatment by heating is required, there is a problem that the time required for the treatment is long and productivity is poor.
【０００６】ＦＣＡ方式でも、半導体チップを配線基板
に搭載した後、機械的補強及び耐湿保護の目的で絶縁性
の樹脂によって封止を行っている。特にこの方式ではチ
ップ搭載後、樹脂封止をするまでのチップの保持は、バ
ンプと接続パッドの接着力のみで非常に弱い。このた
め、その後の処理に支障をきたさないように、チップ搭
載後直ぐに樹脂による固定が必要である。また接続部の
耐湿保護も必要なことから、ワイヤボンディング方式と
同様の樹脂封止を行っており、ワイヤボンディング方式
と同様の問題があった。さらに、ＦＣＡ方式では半導体
チップの電極にバンプを形成する必要があり、このバン
プ形成が原価高の原因になるという問題があった。In the FCA method as well, after a semiconductor chip is mounted on a wiring board, sealing is performed with an insulating resin for the purpose of mechanical reinforcement and moisture resistance protection. In particular, in this method, the holding of the chip after mounting the chip until the resin is sealed is very weak only by the adhesive force between the bump and the connection pad. Therefore, it is necessary to fix with a resin immediately after mounting the chip so as not to hinder the subsequent processing. Further, since the connection portion also needs to be protected from moisture, resin sealing similar to that of the wire bonding method is performed, and there is a problem similar to that of the wire bonding method. Further, in the FCA method, it is necessary to form a bump on an electrode of a semiconductor chip, and there is a problem that the formation of the bump causes an increase in cost.
【０００７】本発明の目的は、このような従来の封止樹
脂の作業性が悪い問題を解決し、作業性、生産性が良好
なＩＣカード及びその製造方法を提供することにある。
本発明の他の目的はバンプを必要としない低コストのＩ
Ｃカード及びその製造方法を提供することにある。An object of the present invention is to solve the problem of poor workability of the conventional sealing resin, and to provide an IC card with good workability and productivity and a method of manufacturing the same.
Another object of the present invention is to provide a low cost I without the need for bumps.
An object of the present invention is to provide a C card and a manufacturing method thereof.
【０００８】[0008]
【課題を解決するための手段】本発明は上記の目的を達
成するために、配線基板の構成要素である基材を封止用
の材料として使用するもので、基材と半導体チップ表面
は基材の接着力あるいは基材と半導体チップ表面との間
に配置した接着剤によって接着、固定される。In order to achieve the above object, the present invention uses a base material, which is a component of a wiring board, as a sealing material. It is adhered and fixed by the adhesive force of the material or the adhesive disposed between the substrate and the surface of the semiconductor chip.
【０００９】また、配線基板の接続パッドと半導体チッ
プの電極は、接続パッド上部からボンディングツールに
よる超音波振動の印加と加圧、更には加熱することによ
って、接続パッド下部の基材を軟化させ押し退けて接触
させ、その後の超音波振動の印加によって電気的に接続
される。なお、加熱処理は材料により省くことが出来
る。The connection pads of the wiring board and the electrodes of the semiconductor chip are softened and pushed away from the base of the connection pads by applying ultrasonic vibration by a bonding tool from above the connection pads, applying pressure, and further heating. And are electrically connected by the subsequent application of ultrasonic vibration. Note that the heat treatment can be omitted depending on the material.
【００１０】電気的に接続が完了した配線基板と半導体
チップは、一面に接着剤を塗布した表カバーシートと裏
カバーシートによって挟み込まれて接着固定され、外形
切断されてＩＣカードが完成する。接着部にはカードの
厚さを制御するために必要に応じてスペーサーが配置さ
れる。回路配線に立体交差部が必要な場合は回路パター
ン面の反対面に金属板または金属箔からなるジャンパ配
線を半導体チップと同様な方法で接着固定し、超音波接
続する。[0010] The wiring board and the semiconductor chip that have been electrically connected are sandwiched and fixed between the front cover sheet and the back cover sheet each having an adhesive applied on one surface, and the outer shape is cut to complete an IC card. Spacers are arranged in the bonding portion as needed to control the thickness of the card. If a three-dimensional intersection is required for the circuit wiring, a jumper wiring made of a metal plate or a metal foil is bonded and fixed to the surface opposite to the circuit pattern surface in the same manner as the semiconductor chip, and ultrasonically connected.
【００１１】本発明の目的を達成するために、本発明に
よるＩＣカードは、表カバーシートと、裏カバーシート
と、絶縁性の基材の一面に接続パットと配線導体とが配
置された配線面と、前記配線面の裏側で基材部が露出し
た基材面を有する配線基板と、電極が配置された電極面
が前記基材面に対向して配置された半導体チップとを備
え、前記基材面と前記半導体チップの前記電極面とが密
着され、前記接続パッドが前記電極に接続された前記配
線基板と前記半導体チップを前記表カバーシートと前記
裏カバーシートとの間に配置してこれらと接着する。In order to achieve the object of the present invention, an IC card according to the present invention comprises a front cover sheet, a back cover sheet, and a wiring surface having a connection pad and a wiring conductor arranged on one surface of an insulating base material. A wiring substrate having a substrate surface with a substrate portion exposed on the back side of the wiring surface; and a semiconductor chip having an electrode surface on which electrodes are disposed and disposed opposite the substrate surface. The material surface and the electrode surface of the semiconductor chip are in close contact with each other, and the connection pads are connected to the electrodes, and the wiring board and the semiconductor chip are arranged between the front cover sheet and the back cover sheet. And glue it.
【００１２】また、本発明によるＩＣカードは、配線基
板に搭載された半導体チップを接着剤を介して表カバー
シートと裏カバーシートで挟み込んだＩＣカードにおい
て、基材の一面に回路パターン及び接続パッドが形成さ
れた前記配線基板と、表面に電極が形成された半導体チ
ップとを備え、前記基材面に前記半導体チップの電極面
を密着させると共に、前記配線基板の接続パッドを前記
半導体チップの電極と電気的に接続し、前記配線基板と
半導体チップが接着層を介して、前記表カバーシートと
裏カバーシートによって挟み込まれる。Further, according to the present invention, there is provided an IC card in which a semiconductor chip mounted on a wiring board is sandwiched between a front cover sheet and a back cover sheet via an adhesive. Is formed, and a semiconductor chip having electrodes formed on the surface thereof is provided, and the electrode surface of the semiconductor chip is brought into close contact with the substrate surface, and the connection pads of the wiring substrate are connected to the electrodes of the semiconductor chip. The wiring board and the semiconductor chip are sandwiched between the front cover sheet and the back cover sheet via an adhesive layer.
【００１３】これらのＩＣカードにおいて、前記半導体
チップの表面と対向する前記基材面に接着膜を設ける。
また、前記配線基板の前記基材は接着性樹脂で形成して
もよい。本発明のＩＣカードにおいて、前記配線基板の
前記接続パッドは前記基材を押し退け、凹状に構成さ
れ、前記半導体チップの前記電極と電気的に接続され
る。[0013] In these IC cards, an adhesive film is provided on the substrate surface facing the surface of the semiconductor chip.
Further, the base material of the wiring board may be formed of an adhesive resin. In the IC card according to the aspect of the invention, the connection pad of the wiring board pushes the base material away, is configured in a concave shape, and is electrically connected to the electrode of the semiconductor chip.
【００１４】前記配線基板の前記接続パッドはアルミニ
ウム、銅、ニッケル、金のいずれかを主成分とする金属
及び銀、パラジウムのいずれかを主成分とする導電性ペ
ーストで形成される。また、前記半導体チップの前記電
極がアルミニウム、銅、ニッケル、金のいずれかを主成
分とする金属で形成される。また、本発明によるＩＣカ
ードにおいて、前記基材面に密着されたジャンパ配線
と、前記基材の一面に配置された回路パターンと、前記
回路パターンに接続された他の接続パッドとを設け、前
記他の接続パッドと前記ジャンパ配線とを接続してもよ
い。また、前記ジャンパ配線として金属板または金属箔
を用い、前記ジャンパ配線と前記回路パターンを立体交
差させることができる。The connection pad of the wiring board is formed of a metal containing aluminum, copper, nickel, or gold as a main component, and a conductive paste containing silver or palladium as a main component. Further, the electrode of the semiconductor chip is formed of a metal mainly containing any of aluminum, copper, nickel, and gold. Further, in the IC card according to the present invention, a jumper wiring closely attached to the base material surface, a circuit pattern disposed on one surface of the base material, and another connection pad connected to the circuit pattern are provided. Another connection pad may be connected to the jumper wiring. Further, a metal plate or a metal foil may be used as the jumper wiring, and the jumper wiring and the circuit pattern may be three-dimensionally crossed.
【００１５】また、前記配線基板の前記基材はエポキシ
系樹脂、ポリエステル系樹脂、塩化ビニール系樹脂、フ
ッ素系樹脂、ポリエチレン系樹脂、ポリプロピレン系樹
脂、スチレン系樹脂、ポリアミド系樹脂、ポリビニール
アルコール系樹脂、ポリ塩化ビニリデン系樹脂、セルロ
ース系樹脂、フェノール系樹脂のいずれかで形成され
る。The base material of the wiring board is made of epoxy resin, polyester resin, vinyl chloride resin, fluorine resin, polyethylene resin, polypropylene resin, styrene resin, polyamide resin, polyvinyl alcohol resin. It is formed of any of resin, polyvinylidene chloride resin, cellulose resin, and phenol resin.
【００１６】本発明の目的を達成するために、本発明に
よるＩＣカードの製造方法は、基材の一面に接続パッド
と配線導体を配置した配線基板を設ける工程と、電極が
設けられた半導体チップの電極側を前記基材面に対向し
て配置し、前記接続パッドと前記電極の位置合わせを行
う工程と、前記基材面と前記半導体チップの前記電極が
配置された面を接触させる工程と、ボンディングツール
で前記接続パッドを加圧すると共に前記ボンディングツ
ールを通して前記基材に超音波振動を印加し前記接続パ
ッドと前記電極とを接続する工程と、前記配線基板に接
続された前記半導体チップを表カバーシートと裏カバー
シートとで接着剤を介して挟み込む工程とを備える。In order to achieve the object of the present invention, a method of manufacturing an IC card according to the present invention comprises the steps of: providing a wiring board having connection pads and wiring conductors disposed on one surface of a base; and a semiconductor chip having electrodes provided thereon. A step of positioning the electrode side of the semiconductor chip opposite to the substrate surface, aligning the connection pad and the electrode, and contacting the substrate surface with the surface of the semiconductor chip on which the electrode is disposed. Pressing the connection pad with a bonding tool and applying ultrasonic vibration to the base material through the bonding tool to connect the connection pad and the electrode; and displaying the semiconductor chip connected to the wiring board. Sandwiching the cover sheet and the back cover sheet via an adhesive.
【００１７】また、本発明の目的を達成するために、本
発明によるＩＣカードは、基材の一面に接続パッドと配
線導体を配置した配線基板を設ける工程と、電極が設け
られた半導体チップの電極側を前記基材面に対向して配
置し、前記接続パッドと前記電極の位置合わせを行う工
程と、前記基材面と前記半導体チップの前記電極が配置
された面を接触させる工程と、ボンディングツールで前
記接続パッドを加圧すると共に前記ボンディングツール
を通して前記基材を加熱して前記接続パッドと前記電極
を接続する工程と、前記配線基板に接続された前記半導
体チップを表カバーシートと裏カバーシートとで接着剤
を介して挟み込む工程とを備える。Further, in order to achieve the object of the present invention, an IC card according to the present invention comprises a step of providing a wiring board on which connection pads and wiring conductors are arranged on one surface of a base material; An electrode side is arranged to face the substrate surface, a step of aligning the connection pad and the electrode, and a step of contacting the substrate surface and the surface of the semiconductor chip on which the electrodes are arranged, Pressing the connection pads with a bonding tool and heating the base material through the bonding tool to connect the connection pads and the electrodes; and forming a front cover sheet and a back cover on the semiconductor chip connected to the wiring board. Sandwiching the sheet with the sheet via an adhesive.
【００１８】本発明の目的を達成するために、本発明に
よるＩＣカードは、配線基板の基材上に形成された接続
パッドと、半導体チップ上に形成された電極と電気的に
接続し、前記配線基板と前記半導体チップを、表カバー
シートと裏カバーシートで挟み込こんだＩＣカードの製
造方法において、前記基材の一面に回路パターンと前記
接続パッドを形成した前記配線基板の上方に、前記半導
体チップの前記電極が前記基材面に対向するように配置
する工程と、前記半導体チップの前記電極を、前記配線
基板の前記接続パッドと位置合わせする工程と、前記配
線基板と前記半導体チップを加圧して接着させる工程
と、前記配線基板の前記接続パッド上に、ボンディング
ツールによって超音波振動を印加して前記接続パッドと
前記半導体チップの前記電極を電気的に接続する工程
と、前記配線基板及び前記半導体チップを表カバーシー
トと裏カバーシートによって挟み込み接着固定する工程
とを備える。In order to achieve the object of the present invention, an IC card according to the present invention electrically connects a connection pad formed on a base material of a wiring board to an electrode formed on a semiconductor chip, In a method of manufacturing an IC card in which a wiring board and the semiconductor chip are sandwiched between a front cover sheet and a back cover sheet, the circuit board and the connection pad are formed on one surface of the base material. Arranging the electrodes of the semiconductor chip so as to face the base material surface, aligning the electrodes of the semiconductor chip with the connection pads of the wiring board, and connecting the wiring board and the semiconductor chip to each other; Pressurizing and adhering, and applying an ultrasonic vibration to the connection pads of the wiring substrate with a bonding tool to bond the connection pads to the semiconductor chip. And a step of electrically connecting the serial electrodes, said wiring board and said semiconductor chip and a step of bonding and fixing pinching the front cover sheet and back cover sheet.
【００１９】本発明の目的を達成するために、本発明に
よるＩＣカードは、基材の一面に接続パッドと配線導体
を配置した配線基板を設ける工程と、電極が設けられた
半導体チップの電極側を前記基材面に対向して配置し、
前記接続パッドと前記電極の位置合わせを行う工程と、
前記基材面と前記半導体チップの前記電極が配置された
面を接触させる工程と、ボンディングツールで前記接続
パッドを加圧して前記接続パッドと前記電極と接続する
工程と、前記配線基板に接続された前記半導体チップを
表カバーシートと裏カバーシートとで接着剤介して挟み
込む工程とを備える。In order to achieve the object of the present invention, an IC card according to the present invention comprises a step of providing a wiring board on which connection pads and wiring conductors are arranged on one surface of a base, and an electrode side of a semiconductor chip provided with electrodes. Is disposed facing the substrate surface,
Aligning the connection pad and the electrode;
Contacting the substrate surface with the surface of the semiconductor chip on which the electrodes are arranged; pressing the connection pads with a bonding tool to connect the connection pads to the electrodes; and connecting to the wiring board. Sandwiching the semiconductor chip between the front cover sheet and the back cover sheet via an adhesive.
【００２０】本発明のＩＣカードの製造方法において、
前記接続パッドと前記電極とを接続する工程は、前記ボ
ンディングツールを用いて前記接続パッドを加圧する工
程を備えると好適である。また、前記接続パッドと前記
電極とを接続する工程は、前記ボンディングツールを用
いて前記配線基板の基材と前記半導体チップの表面を加
熱することによって両者を接着させる工程を備えると好
適である。また、前記接続パッドと前記電極とを接続す
る工程は、更に前記ボンディングツールによって、前記
基材に超音波振動を印加する工程を備えると好適であ
る。In the method for manufacturing an IC card according to the present invention,
Preferably, the step of connecting the connection pad and the electrode includes the step of pressing the connection pad using the bonding tool. Preferably, the step of connecting the connection pad and the electrode includes a step of heating the surface of the substrate of the wiring board and the surface of the semiconductor chip using the bonding tool to bond the two to each other. It is preferable that the step of connecting the connection pad and the electrode further includes a step of applying ultrasonic vibration to the base material by the bonding tool.
【００２１】好ましくは、前記接続パッドと前記電極と
を接続する工程は、前記接続パッドが前記半導体チップ
の電極と接触するまでは前記接続パッド面に垂直方向の
超音波振動を印加し、前記接続パッドが前記半導体チッ
プの前記電極と接触した後は水平方向の超音波振動を印
加する工程を備える。Preferably, the step of connecting the connection pad and the electrode includes applying ultrasonic vibration in a vertical direction to the connection pad surface until the connection pad comes into contact with an electrode of the semiconductor chip. After the pad comes into contact with the electrode of the semiconductor chip, a step of applying a horizontal ultrasonic vibration is provided.
【００２２】また、前記基材の一面に他の接続パッドを
設ける工程と、前記基材面にジャンパ配線を接着させる
工程とを設け、前記接続パッドと前記電極の接続工程に
おいて、前記接続パッドと前記ジャンパ配線も接続する
と好適である。A step of providing another connection pad on one surface of the base material; and a step of bonding a jumper wiring to the surface of the base material, wherein in the step of connecting the connection pad and the electrode, It is preferable that the jumper wiring is also connected.
【００２３】[0023]
【発明の実施の形態】以下、本発明の実施の形態を、実
施例を用い、図面を参照して説明する。図１は本発明に
なるＩＣカードの一実施例を示す断面図であり、図２は
図１に示すＩＣカードの配線基板に半導体チップ、ジャ
ンパ配線を配置した平面図であり、図３は図２のＡ−
Ａ’の拡大断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings using examples. FIG. 1 is a sectional view showing an embodiment of an IC card according to the present invention, FIG. 2 is a plan view showing a semiconductor chip and jumper wiring arranged on a wiring board of the IC card shown in FIG. 1, and FIG. 2A-
It is an expanded sectional view of A '.
【００２４】まず、図２、３を用いて、半導体チップ実
装部の構成について説明する。First, the configuration of the semiconductor chip mounting section will be described with reference to FIGS.
【００２５】半導体チップ１０の表面には電極１２が形
成されている。配線基板２０は基材２２とこの基材２２
の表面に形成された中継配線２４、コイルパターン２５
等の回路パターン２８及び接続パッド２６から構成され
ている。配線基板２０上に形成されているコイルパター
ン２５の一端は図２に示すように、半導体チップ１０の
電極１２と接続され、他端はジャンパ配線１４に接続さ
れるように、半導体チップ１０の電極１２と、コイルパ
ターン２５とジャンパ配線１４は配置されている。更
に、ジャンパ配線１４の他端は中継配線２４の一端に接
続され、中継配線２４の他端は半導体チップ１０の電極
１２と接続されるように、ジャンパ配線１４、中継配線
２４及び半導体チップ１０の電極１２は配置されてい
る。An electrode 12 is formed on the surface of the semiconductor chip 10. The wiring substrate 20 includes a base material 22 and the base material 22.
Wiring 24, coil pattern 25 formed on the surface of
And the like and a connection pad 26. As shown in FIG. 2, one end of the coil pattern 25 formed on the wiring board 20 is connected to the electrode 12 of the semiconductor chip 10, and the other end is connected to the jumper wiring 14. 12, the coil pattern 25 and the jumper wiring 14 are arranged. Further, the other end of the jumper wiring 14 is connected to one end of the relay wiring 24, and the other end of the relay wiring 24 is connected to the electrode 12 of the semiconductor chip 10 so that the jumper wiring 14, the relay wiring 24 and the semiconductor chip 10 are connected. The electrode 12 is arranged.
【００２６】配線基板２０の回路パターン２８及び接続
パッド２６等が配置される面と反対の面に、半導体チッ
プ１０の電極１２側の表面が密着固定されている。同様
にジャンパ配線１４の表面も半導体チップ１０が固定さ
れている配線基板２０面の基材２２と密着固定されてい
る。配線基板上の接続パッド２６は接続パッド２６下部
の基材２２を押し退けて半導体チップ１０の電極側に凹
状に変形され、電極１２及びジャンパ配線１４と電気的
に接続されている。The surface of the semiconductor chip 10 on the electrode 12 side is tightly fixed to the surface of the wiring substrate 20 opposite to the surface on which the circuit patterns 28 and the connection pads 26 are arranged. Similarly, the surface of the jumper wiring 14 is tightly fixed to the base material 22 on the wiring board 20 to which the semiconductor chip 10 is fixed. The connection pad 26 on the wiring board is pushed away from the base material 22 below the connection pad 26 and is deformed into a concave shape on the electrode side of the semiconductor chip 10, and is electrically connected to the electrode 12 and the jumper wiring 14.
【００２７】次に図１を用いてＩＣカードの構造につい
て説明する。図１において、図２、３と同じものについ
ては同一の参照符号を付ける。表カバーシート４０と配
線基板２０の一面は接着剤５０によって接着固定され、
裏カバーシート４２と半導体チップ１０及びジャンパ配
線１４は接着剤５２により固定されている。スペーサー
４４は配線基板２０の半導体チップ１０及びジャンパ配
線１４が配置されている面と同一面側に設けられ、配線
基板２０と裏カバーシート４２に挟まれ、接着剤５２に
よって接着固定されている。半導体チップ１０の電極１
２は半導体チップ１０の素子形成時にチップ内を電気的
に接続するチップ内配線と同じプロセスで形成され、ア
ルミニウム（Ａｌ）、銅（Ｃｕ）、ニッケル（Ｎｉ）、
あるいは金（Ａｕ）を主成分とした金属膜で形成されて
いる。Next, the structure of the IC card will be described with reference to FIG. 1, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals. One surface of the front cover sheet 40 and one surface of the wiring board 20 are adhered and fixed by an adhesive 50,
The back cover sheet 42, the semiconductor chip 10, and the jumper wiring 14 are fixed with an adhesive 52. The spacer 44 is provided on the same surface as the surface on which the semiconductor chip 10 and the jumper wiring 14 of the wiring board 20 are arranged, is sandwiched between the wiring board 20 and the back cover sheet 42, and is fixedly adhered by an adhesive 52. Electrode 1 of semiconductor chip 10
2 is formed by the same process as in-chip wiring for electrically connecting the inside of the chip when forming elements of the semiconductor chip 10. Aluminum (Al), copper (Cu), nickel (Ni),
Alternatively, it is formed of a metal film mainly containing gold (Au).
【００２８】配線基板２０を構成する基材２２はエポキ
シ系樹脂、ポリエステル系樹脂、塩化ビニール系樹脂、
フッ素系樹脂、ポリエチレン系樹脂、ポリプロピレン系
樹脂、スチレン系樹脂、ポリアミド系樹脂、ポリビニー
ルアルコール系樹脂、ポリ塩化ビニリデン系樹脂、セル
ロース系樹脂、フェノール系樹脂等の絶縁性を有する例
えばポリエチレンテレフタレート、ポリエステル、ポリ
カーボネート、ポリアリレート、ポリエチレン、ポリ塩
化ビニリデン、ポリアセタール、ポリイミド、エポキシ
レジン、テトロン（登録商標）、ビニロン（登録商
標）、ポリスチレン、ポリスチロール、ポリプロピレ
ン、テフロン（登録商標）、ナイロン（登録商標）等の
材料を用いてフィルムまたはシート状に形成すると好適
である。The base material 22 forming the wiring board 20 is made of epoxy resin, polyester resin, vinyl chloride resin,
For example, polyethylene terephthalate, polyester having insulating properties such as fluorine resin, polyethylene resin, polypropylene resin, styrene resin, polyamide resin, polyvinyl alcohol resin, polyvinylidene chloride resin, cellulose resin, and phenol resin. , Polycarbonate, polyarylate, polyethylene, polyvinylidene chloride, polyacetal, polyimide, epoxy resin, Tetron (registered trademark), vinylon (registered trademark), polystyrene, polystyrene, polypropylene, Teflon (registered trademark), nylon (registered trademark), etc. It is preferable to form a film or a sheet using the above material.
【００２９】配線基板２０上に形成された中継配線２
４、コイルパターン２５及び接続パッド２６は基材２２
の上に通常の方法で成膜され、パターニングされたアル
ミニウム（Ａｌ）、銅（Ｃｕ）、ニッケル（Ｎｉ）、金
（Ａｕ）を主成分とする金属配線、銀（Ａｇ）、パラジ
ウム（Ｐｄ）を主成分とする導電性ペーストを印刷等に
よって形成された配線、あるいはこれらの配線上に金メ
ッキ等を施したものである。ジャンパー配線１４はアル
ミニウム（Ａｌ）、銅（Ｃｕ）、ニッケル（Ｎｉ）、金
（Ａｕ）などの金属板または金属箔で構成される。Relay wiring 2 formed on wiring substrate 20
4. The coil pattern 25 and the connection pad 26 are
(Al), copper (Cu), nickel (Ni), metal wiring mainly composed of gold (Au), silver (Ag), palladium (Pd) The wiring is formed by printing a conductive paste mainly composed of, for example, by printing, or by applying gold plating or the like to these wirings. The jumper wiring 14 is made of a metal plate or a metal foil of aluminum (Al), copper (Cu), nickel (Ni), gold (Au) or the like.
【００３０】このような構成において、配線基板２０の
基材２２と半導体チップ１０の表面は完全に密着されて
おり、半導体チップ１０の電極１２と配線基板２０の接
続パッド２６との接続部では接続パッド２６が基材２２
の一部を押し退けて凹状に変形され、半導体チップ１０
の電極１２と電気的、機械的に完全に接続されている。
ジャンパ配線１４も配線基板２０の半導体チップ１０が
配置される面に密着して取り付けられ、その両端は凹状
の接続パッド２６と接続される。半導体チップ１０と配
線基板１０、及びジャンパ配線１４と配線基板２０を接
着するには配線基板２０に接着性をもたせて接着するが
配線基板２０の基材面に予め接着剤を塗布しておいても
よい。スペーサー４４は半導体チップ１０とジャンパ配
線１４が存在しない部分の厚さバランスを取るために挿
入されるが、場合によっては省略してもよい。表カバー
シート４０及び裏カバーシート４２は、半導体チップ１
０、ジャンパ配線１４、配線基板２０を機械的に補強
し、種々の環境下においてこれらを保護するために設け
られる。In such a configuration, the base material 22 of the wiring board 20 and the surface of the semiconductor chip 10 are completely adhered to each other, and a connection portion between the electrode 12 of the semiconductor chip 10 and the connection pad 26 of the wiring board 20 is connected. The pad 26 is the base material 22
Of the semiconductor chip 10
Electrode 12 is completely electrically and mechanically connected.
The jumper wiring 14 is also attached in close contact with the surface of the wiring board 20 on which the semiconductor chip 10 is arranged, and both ends thereof are connected to the concave connection pads 26. In order to bond the semiconductor chip 10 to the wiring board 10 and the jumper wiring 14 to the wiring board 20, the wiring board 20 is provided with an adhesive property, and an adhesive is applied to the base material surface of the wiring board 20 in advance. Is also good. The spacer 44 is inserted to balance the thickness of the portion where the semiconductor chip 10 and the jumper wiring 14 are not present, but may be omitted in some cases. The front cover sheet 40 and the back cover sheet 42 correspond to the semiconductor chip 1.
0, jumper wiring 14 and wiring board 20 are provided to mechanically reinforce and protect them under various environments.
【００３１】次に本発明になるＩＣカードの製造方法の
一実施例について図４を用いて説明する。図４はＩＣカ
ードの製造方法の一実施例を説明するための断面図であ
り、図４（ａ）は半導体チップとジャンパ配線を配線基
板と対向して配置し、位置合わせを行なった状態を示す
断面図であり、図４（ｂ）は半導体チップとジャンパ配
線を配線基板に密着させた状態を示す断面図であり、図
４（ｃ）は図４（ｂ）に示す物を上下反転して接続パッ
ドを凹部に形成して半導体チップ及びジャンパ配線とを
接続した状態を示す断面図、図４（ｄ）は表カバー、裏
カバーおよびスペーサーを配置した接着前の断面図であ
る。なお、図４において、図１〜３と同一のものには同
一の符号を付して説明する。Next, an embodiment of a method of manufacturing an IC card according to the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view for explaining one embodiment of a method of manufacturing an IC card. FIG. 4A shows a state in which a semiconductor chip and jumper wiring are arranged so as to face a wiring board and alignment is performed. FIG. 4B is a cross-sectional view showing a state in which the semiconductor chip and the jumper wiring are brought into close contact with the wiring board, and FIG. 4C is an inverted view of the thing shown in FIG. FIG. 4D is a sectional view showing a state where connection pads are formed in the recesses to connect the semiconductor chip and the jumper wiring to each other, and a front cover, a back cover, and a spacer are arranged before bonding. In FIG. 4, the same components as those in FIGS.
【００３２】図４（ａ）は半導体チップ１０及びジャン
パ配線１４を配線基板２０に密着させる前の状態を示し
ている。配線基板２０は回路パターン２８が下面になる
ように配置されており、その上方に半導体チップ１０と
ジャンパ配線１４が配線基板２０と対向して配置され
る。この状態で半導体チップ１０の電極１２と配線基板
２０の接続パッド２６の位置合わせを行う。位置合わせ
方法は通常用いられている光学的に位置合わせマークを
読み取り、配線基板２０及び半導体チップ１０を駆動す
る機構にフィードバックさせる方法（図示しない）を用
いている。位置があった時点で図４（ｂ）に示すように
半導体チップ１０と基材２２を接触させ、上下方向から
加圧（図中矢印で示す）して基材２２と半導体チップ１
０を密着、固定させる。この場合、加圧と同時に加熱を
行ってもよい。同様にジャンパ配線１４も基材２２と密
着、固定させる。FIG. 4A shows a state before the semiconductor chip 10 and the jumper wiring 14 are brought into close contact with the wiring board 20. The wiring board 20 is arranged so that the circuit pattern 28 is on the lower surface, and the semiconductor chip 10 and the jumper wiring 14 are arranged above the wiring board 20 so as to face the wiring board 20. In this state, the positioning of the electrode 12 of the semiconductor chip 10 and the connection pad 26 of the wiring board 20 is performed. The alignment method uses a commonly used method (not shown) of reading an alignment mark optically and feeding it back to a mechanism for driving the wiring board 20 and the semiconductor chip 10. When there is a position, the semiconductor chip 10 and the substrate 22 are brought into contact with each other as shown in FIG.
0 is fixed and fixed. In this case, heating may be performed simultaneously with pressurization. Similarly, the jumper wiring 14 is adhered and fixed to the base material 22.
【００３３】次に、図４（ｃ）に示すように、図４
（ｂ）に示す全体を上下反転をしてボンディングツール
６０を接続パッド２６に押しつけ（図中矢印で示す）、
ボンディングツール６０を介して基材２２に超音波振動
を印加する。この超音波振動を印加することによって、
ボンディングツール６０が押し当てられた部分の基材２
２が加熱して軟化する。従って、この超音波振動の印加
とボンディングツール６０の加圧によって接続パッド２
６下部の基材２２は押し退けられ、接続パッド２６は凹
状に変形して電極１２と接触する。この状態でさらに超
音波振動を印加することにより、接続パッド２６と電極
１２は電気的に完全に接続される。この場合、ボンディ
ングツール６０に加熱機構を設けて、例えばヒータ線を
巻き付けて接続パッド２６上面を加熱したり、レーザ光
あるいは熱風等を接続パッド２６に印加する等の局所加
熱する方法も有効である。さらに超音波振動を水平方向
と垂直方向の２方向に印加出来るボンディングツール６
０を用い、まず垂直方向の振動で接続パッド２６下部の
基材２２を軟化させ、次いで水平方向の振動で接続パッ
ド２６と電極１２の接合を行うと更に好適である。同様
にしてジャンパ配線１４と配線基板２０の接続パッドを
接続する。Next, as shown in FIG.
(B) is turned upside down and the bonding tool 60 is pressed against the connection pad 26 (indicated by an arrow in the figure);
Ultrasonic vibration is applied to the substrate 22 via the bonding tool 60. By applying this ultrasonic vibration,
The base material 2 at the portion where the bonding tool 60 is pressed.
2 heats and softens. Therefore, the application of the ultrasonic vibration and the pressurization of the bonding tool 60 cause the connection pad 2
The lower base material 22 is pushed away, and the connection pad 26 is deformed into a concave shape and comes into contact with the electrode 12. By further applying ultrasonic vibration in this state, the connection pad 26 and the electrode 12 are electrically connected completely. In this case, it is also effective to provide a heating mechanism to the bonding tool 60 to heat the upper surface of the connection pad 26 by winding a heater wire, or to locally heat the connection pad 26 by applying a laser beam or hot air to the connection pad 26, for example. . Further, a bonding tool 6 capable of applying ultrasonic vibration in two directions, a horizontal direction and a vertical direction.
It is more preferable to first use 0 to soften the base material 22 below the connection pads 26 by vertical vibration and then to bond the connection pads 26 and the electrodes 12 by horizontal vibration. Similarly, the jumper wiring 14 and the connection pad of the wiring board 20 are connected.
【００３４】次に、図４（ｄ）に示すように、半導体チ
ップ１０及びジャンパ配線１４を接続し、スペーサー４
４を配置した配線基板２０を接着剤５０を塗布した表カ
バーシート４０と接着剤５２を塗布した裏カバーシート
４２の間に配置して、表カバーシート４０と裏カバーシ
ート４２の両側から熱盤によって加圧、加熱を行って接
着、固定することによって、ＩＣカードが完成される。Next, as shown in FIG. 4D, the semiconductor chip 10 and the jumper wiring 14 are connected, and the spacer 4
4 is arranged between the front cover sheet 40 to which the adhesive 50 is applied and the back cover sheet 42 to which the adhesive 52 is applied, and the hot platen is placed on both sides of the front cover sheet 40 and the back cover sheet 42. The IC card is completed by applying pressure and heating to adhere and fix.
【００３５】以上説明したように、本発明によれば配線
基板の基材を封止に使用するため、液状樹脂を使用する
従来製品で問題となっていた取り扱い難さや作業性が悪
いと言う問題、樹脂管理の問題が無くなり、作業性がよ
くなった。また、封止工程は基材と半導体チップ表面を
接触させた後、簡単な加熱、加圧装置で処理可能なこと
から、装置導入等の初期コストの低減が可能で、製品コ
ストを低く押さえることが出来る。As described above, according to the present invention, since the base material of the wiring board is used for sealing, it is difficult to handle and has poor workability, which has been a problem in conventional products using a liquid resin. The problem of resin management was eliminated, and workability was improved. In addition, since the sealing process can be processed with a simple heating and pressurizing device after contacting the substrate and the surface of the semiconductor chip, the initial cost of introducing the device can be reduced and the product cost can be kept low. Can be done.
【００３６】また、配線基板と半導体チップを接着して
機械的に固定した後に接続パッドと電極との接続を行う
ため、接続後の取り扱いが容易になり、作業効率を上げ
ることが出来る。またチップ電極にバンプを形成する必
要がないため、製品コストを大幅に低減することができ
る。Further, since the connection between the connection pad and the electrode is performed after the wiring substrate and the semiconductor chip are bonded and mechanically fixed to each other, handling after the connection is facilitated and work efficiency can be improved. Further, since there is no need to form bumps on the chip electrodes, product cost can be significantly reduced.
【００３７】[0037]
【発明の効果】以上説明したように、本発明によれば配
線基板の基材を封止に使用するため、作業性がよい。ま
た、配線基板と半導体チップを接着して機械的に固定し
た後に、接続パッドと電極との接続を行なっているた
め、接続後の取り扱いが容易になり、作業効率を上げる
ことが出来る。またチップ電極にバンプを形成する必要
がないため、製品コストを低減することができる。As described above, according to the present invention, since the base material of the wiring board is used for sealing, the workability is good. Further, since the connection between the connection pad and the electrode is performed after the wiring board and the semiconductor chip are bonded and mechanically fixed, the handling after the connection is easy, and the working efficiency can be improved. Further, since there is no need to form bumps on the chip electrodes, product cost can be reduced.
【図１】本発明になるＩＣカードの一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of an IC card according to the present invention.
【図２】図１に示すＩＣカードの配線基板に半導体チッ
プ、ジャンパ配線を配置した平面図である。FIG. 2 is a plan view in which a semiconductor chip and jumper wiring are arranged on a wiring board of the IC card shown in FIG. 1;
【図３】図２のＡ−Ａ’の拡大断面図である。FIG. 3 is an enlarged sectional view taken along line A-A 'of FIG.
【図４】ＩＣカードの製造方法の一実施例を説明するた
めの断面図である。FIG. 4 is a cross-sectional view for explaining one embodiment of a method of manufacturing an IC card.
【図５】ワイヤボンディング方式により、半導体チップ
を実装したＩＣカードの断面図である。FIG. 5 is a sectional view of an IC card on which a semiconductor chip is mounted by a wire bonding method.
【図６】ＦＣＡ方式により半導体チップを実装したＩＣ
カードの断面図である。FIG. 6 is an IC in which a semiconductor chip is mounted by the FCA method.
It is sectional drawing of a card.
１０、１１０…半導体チップ、１２、１１２…電極、１
４…ジャンパ配線、２０、１００…配線基板、２２…基
材、２４…中継配線、２５…コイルパターン、２８…回
路パターン、２６、１０４…接続パッド、４０、１４０
…表カバーシート、４２、１４２…裏カバーシート、４
４、１３０…スペーサー、５０、５２、１５０、１５２
…接着剤、６０…ボンディングツール、１１４…ワイ
ヤ、１１６…バンプ、１２０…封止樹脂。10, 110: semiconductor chip, 12, 112: electrode, 1
4: Jumper wiring, 20, 100: Wiring board, 22: Base material, 24: Relay wiring, 25: Coil pattern, 28: Circuit pattern, 26, 104: Connection pad, 40, 140
... front cover sheet, 42, 142 ... back cover sheet, 4
4, 130 ... spacer, 50, 52, 150, 152
... adhesive, 60 ... bonding tool, 114 ... wire, 116 ... bump, 120 ... sealing resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 良雄 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 和井 伸一 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 高岡 勇 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 橋本 豊 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 山口 欣秀 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 Ｆターム(参考） 5B035 AA04 BA03 BA04 BA05 BB09 CA01 CA03 CA08 CA11 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshio Ozeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. Production Technology Laboratory (72) Inventor Shinichi Wai 1- 1 Horiyamashita, Hadano-shi, Kanagawa Stock (72) Inventor: Isamu Takaoka, 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture, Japan Inventor: Yutaka Hashimoto 1st, Horiyamashita, Hadano-shi, Kanagawa, Japan (72) Inventor Yoshihide Yamaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Technology Research Institute F-term (reference) 5B035 AA04 BA03 BA04 BA05 BB09 CA01 CA03 CA08 CA11
Claims (20)
縁性の基材の一面に接続パットと配線導体とが配置され
た配線面と他面に基材部が露出した基材面を有する配線
基板と、電極が配置された電極面が前記基材面に対向し
て配置された半導体チップとを備え、前記基材面と前記
半導体チップの前記電極面とが密着され、前記接続パッ
ドが前記電極に接続された前記配線基板と前記半導体チ
ップを前記表カバーシートと前記裏カバーシートとの間
に配置してこれらと接着することを特徴とするＩＣカー
ド。1. A front cover sheet, a back cover sheet, a wiring surface on which a connection pad and a wiring conductor are arranged on one surface of an insulating substrate, and a substrate surface with a substrate portion exposed on the other surface. A wiring board, comprising: a semiconductor chip in which an electrode surface on which an electrode is arranged is arranged so as to face the substrate surface; the substrate surface and the electrode surface of the semiconductor chip are in close contact with each other; An IC card, wherein the wiring board and the semiconductor chip connected to the electrodes are arranged between the front cover sheet and the back cover sheet and adhered thereto.
剤を介して表カバーシートと裏カバーシートで挟み込ん
だＩＣカードにおいて、基材の一面に回路パターン及び
接続パッドが形成された前記配線基板と、表面に電極が
形成された半導体チップとを備え、前記基材面に前記半
導体チップの表面を密着させると共に、前記配線基板の
接続パッドを前記半導体チップの電極と電気的に接続
し、前記配線基板と半導体チップが接着層を介して、前
記表カバーシートと裏カバーシートによって挟み込まれ
ることを特徴とするＩＣカード。2. An IC card in which a semiconductor chip mounted on a wiring board is sandwiched between a front cover sheet and a back cover sheet via an adhesive, wherein said circuit board has a circuit pattern and connection pads formed on one surface of a base material. And a semiconductor chip having electrodes formed on the surface thereof, and the surface of the semiconductor chip is brought into close contact with the substrate surface, and the connection pads of the wiring board are electrically connected to the electrodes of the semiconductor chip. An IC card, wherein a wiring board and a semiconductor chip are sandwiched between the front cover sheet and the back cover sheet via an adhesive layer.
て、前記半導体チップの表面と対向する前記基材面に接
着膜を有することを特徴とするＩＣカード。3. The IC card according to claim 1, further comprising an adhesive film on the surface of the base material facing the surface of the semiconductor chip.
て、前記配線基板の前記基材は接着性樹脂で形成される
ことを特徴とするＩＣカード。4. The IC card according to claim 1, wherein said base material of said wiring board is formed of an adhesive resin.
て、前記配線基板の前記接続パッドは前記基材を押し退
け、凹状に構成され、前記半導体チップの前記電極と電
気的に接続されることを特徴とするＩＣカード。5. The IC card according to claim 1, wherein the connection pads of the wiring board push away the base material, are formed in a concave shape, and are electrically connected to the electrodes of the semiconductor chip. Characteristic IC card.
て、前記配線基板の前記接続パッドはアルミニウム、
銅、ニッケル、金のいずれかを主成分とする金属及び
銀、パラジウムのいずれかを主成分とする導電性ペース
トで形成されていることを特徴とするＩＣカード。6. The IC card according to claim 1, wherein the connection pads of the wiring board are made of aluminum.
An IC card formed of a metal containing copper, nickel, or gold as a main component and a conductive paste containing silver or palladium as a main component.
て、前記半導体チップの前記電極がアルミニウム、銅、
ニッケル、金のいずれかを主成分とする金属で形成され
ていることを特徴とするＩＣカード。7. The IC card according to claim 1, wherein said electrodes of said semiconductor chip are made of aluminum, copper,
An IC card comprising a metal containing nickel or gold as a main component.
カードにおいて、前記基材面に密着されたジャンパ配線
と、前記基材の一面に配置された回路パターンと、前記
回路パターンに接続された他の接続パッドとを設け、前
記他の接続パッドと前記ジャンパ配線とを接続すること
を特徴とするＩＣカード。8. The IC according to claim 1, 2, 3, 4 or 5.
In the card, a jumper wiring closely adhered to the base material surface, a circuit pattern disposed on one surface of the base material, and another connection pad connected to the circuit pattern are provided, and the other connection pad and the other connection pad are provided. An IC card characterized by connecting jumper wiring.
ジャンパ配線として金属板または金属箔を用い、前記ジ
ャンパ配線と前記回路パターンを立体交差させることを
特徴とするＩＣカード。9. The IC card according to claim 8, wherein a metal plate or a metal foil is used as the jumper wiring, and the jumper wiring and the circuit pattern are three-dimensionally crossed.
いて、前記配線基板の前記基材はエポキシ系樹脂、ポリ
エステル系樹脂、塩化ビニール系樹脂、フッ素系樹脂、
ポリエチレン系樹脂、ポリプロピレン系樹脂、スチレン
系樹脂、ポリアミド系樹脂、ポリビニールアルコール系
樹脂、ポリ塩化ビニリデン系樹脂、セルロース系樹脂、
フェノール系樹脂のいずれかで形成されていることを特
徴とするＩＣカード。10. The IC card according to claim 1, wherein the base material of the wiring board is an epoxy resin, a polyester resin, a vinyl chloride resin, a fluorine resin,
Polyethylene resin, polypropylene resin, styrene resin, polyamide resin, polyvinyl alcohol resin, polyvinylidene chloride resin, cellulose resin,
An IC card formed of any one of phenolic resins.
成した配線面と他面に基材部が露出した基材部を配置し
た配線基板を設ける工程と、電極が設けられた半導体チ
ップの電極面を前記基材面に対向して配置し、前記接続
パッドと前記電極の位置合わせを行う工程と、前記基材
面と前記半導体チップの前記電極面を接触させる工程
と、ボンディングツールで前記接続パッドを加圧すると
共に前記ボンディングツールを通して前記基材に超音波
振動を印加し前記接続パッドと前記電極とを接続する工
程と、前記配線基板と前記半導体チップを表カバーシー
トと裏カバーシートとで接着剤を介して挟み込む工程と
を備えることを特徴とするＩＣカードの製造方法。11. A step of providing a wiring substrate on which a wiring surface having connection pads and wiring conductors formed on one surface of a substrate and a substrate portion having the substrate portion exposed on the other surface are provided, and a semiconductor chip provided with electrodes. Arranging the electrode surface of the semiconductor chip opposite to the substrate surface, aligning the connection pad and the electrode, contacting the substrate surface with the electrode surface of the semiconductor chip, and using a bonding tool. Pressing the connection pads and applying ultrasonic vibration to the base material through the bonding tool to connect the connection pads and the electrodes; and forming the wiring board and the semiconductor chip on the front cover sheet and the back cover sheet. And a step of sandwiching with an adhesive.
成した配線面と他面に基材部が露出した基材部を配置し
た配線基板を設ける工程と、電極が設けられた半導体チ
ップの電極面を前記基材面に対向して配置し、前記接続
パッドと前記電極の位置合わせと行う工程と、前記基材
面と前記半導体チップの前記電極面を接触させる工程
と、ボンディングツールで前記接続パッドを加圧すると
共に前記ボンディングツールを通して前記基材を加熱し
て前記接続パッドと前記電極を接続する工程と、前記配
線基板と前記半導体チップを表カバーシートと裏カバー
シートとで接着剤を介して挟み込む工程とを備えること
を特徴とするＩＣカードの製造方法。12. A step of providing a wiring board on which a wiring surface having connection pads and wiring conductors formed on one surface of a substrate and a substrate portion having the substrate portion exposed on the other surface are provided, and a semiconductor chip provided with electrodes. Arranging the electrode surface of the semiconductor chip opposite to the substrate surface, aligning the connection pad and the electrode, and contacting the substrate surface with the electrode surface of the semiconductor chip; and Connecting the connection pads and the electrodes by pressing the connection pads and heating the base material through the bonding tool, and applying an adhesive to the wiring board and the semiconductor chip with the front cover sheet and the back cover sheet. A method of manufacturing an IC card.
ドと、半導体チップ上に形成された電極と電気的に接続
し、前記配線基板と前記半導体チップを、表カバーシー
トと裏カバーシートで挟み込こんだＩＣカードの製造方
法において、前記基材の一面に回路パターンと前記接続
パッドを形成した前記配線基板の上方に、前記半導体チ
ップの前記電極が前記基材面に対向するように配置する
工程と、前記半導体チップの前記電極を、前記配線基板
の前記接続パッドと位置合わせする工程と、前記配線基
板と前記半導体チップを加圧して接着させる工程と、前
記配線基板の前記接続パッド上に、ボンディングツール
によって超音波振動を印加して前記接続パッドと前記半
導体チップの前記電極を電気的に接続する工程と、前記
配線基板及び前記半導体チップを表カバーシートと裏カ
バーシートによって挟み込み接着固定する工程とを備え
ることを特徴とするＩＣカードの製造方法。13. A connection pad formed on a base material of a wiring board and an electrode formed on a semiconductor chip are electrically connected, and the wiring board and the semiconductor chip are connected to a front cover sheet and a back cover sheet. In the method of manufacturing an IC card sandwiched between the above, the electrode of the semiconductor chip is opposed to the surface of the base material above the wiring substrate having the circuit pattern and the connection pads formed on one surface of the base material. Arranging, aligning the electrode of the semiconductor chip with the connection pad of the wiring board, pressing the wiring board and the semiconductor chip and bonding them, and connecting the connection pad of the wiring board A step of applying ultrasonic vibration by a bonding tool to electrically connect the connection pad and the electrode of the semiconductor chip; IC card manufacturing method characterized by comprising the step of bonding and fixing sandwiched by the conductor chip front cover sheet and back cover sheet.
置した配線基板を設ける工程と、電極が設けられた半導
体チップの電極側を前記基材面に対向して配置し、前記
接続パッドと前記電極の位置合わせと行う工程と、前記
基材の他の面と前記半導体チップの前記電極が配置され
た面を接触させる工程と、ボンディングツールで前記接
続パッドを加圧して前記接続パッドと前記電極と接続す
る工程と、前記配線基板に接続された前記半導体チップ
を表カバーシートと裏カバーシートとで接着剤介して挟
み込む工程とを備えることを特徴とするＩＣカードの製
造方法。14. A step of providing a wiring board on which a connection pad and a wiring conductor are arranged on one surface of a base material, and arranging an electrode side of a semiconductor chip provided with electrodes facing the base material surface; And the step of performing the alignment of the electrodes, the step of contacting the other surface of the base material and the surface of the semiconductor chip on which the electrodes are arranged, and pressing the connection pads with a bonding tool to form the connection pads. A method for manufacturing an IC card, comprising: a step of connecting to the electrode; and a step of sandwiching the semiconductor chip connected to the wiring board between a front cover sheet and a back cover sheet via an adhesive.
において、前記接続パッドと前記電極とを接続する工程
は、前記ボンディングツールを用いて前記接続パッドを
加圧する工程を備えることを特徴とするＩＣカードの製
造方法。15. The method for manufacturing an IC card according to claim 13, wherein the step of connecting the connection pad and the electrode includes the step of pressing the connection pad using the bonding tool. A method for manufacturing an IC card.
において、前記接続パッドと前記電極とを接続する工程
は、前記ボンディングツールを用いて前記配線基板の基
材と前記半導体チップの表面を加熱することによって両
者を接着させる工程を備えることを特徴とするＩＣカー
ドの製造方法。16. The method of manufacturing an IC card according to claim 14, wherein the step of connecting the connection pad and the electrode includes heating the base material of the wiring board and the surface of the semiconductor chip using the bonding tool. A method for manufacturing an IC card, comprising the steps of:
の製造方法において、前記接続パッドと前記電極とを接
続する工程は、更に前記ボンディングツールによって、
前記基材を加熱する工程を含むことを特徴とするＩＣカ
ードの製造方法。17. The method for manufacturing an IC card according to claim 11, wherein the step of connecting the connection pad and the electrode is further performed by the bonding tool.
A method for manufacturing an IC card, comprising a step of heating the base material.
において、前記接続パッドと前記電極とを接続する工程
は、更に前記ボンディングツールによって、前記基材に
超音波振動を印加する工程を含むことを特徴とするＩＣ
カードの製造方法。18. The method for manufacturing an IC card according to claim 12, wherein the step of connecting the connection pad and the electrode further includes the step of applying ultrasonic vibration to the base material by the bonding tool. IC characterized by the following
Card manufacturing method.
の製造方法において、前記接続パッドと前記電極とを接
続する工程は、前記接続パッドが前記半導体チップの電
極と接触するまでは前記接続パッド面に垂直方向の超音
波振動を印加し、前記接続パッドが前記半導体チップの
前記電極と接触した後は水平方向の超音波振動を印加す
る工程を備えることを特徴とするＩＣカードの製造方
法。19. The method for manufacturing an IC card according to claim 11, wherein the step of connecting the connection pad and the electrode is performed until the connection pad comes into contact with an electrode of the semiconductor chip. And applying a horizontal ultrasonic vibration after the connection pad comes into contact with the electrode of the semiconductor chip. 4. A method of manufacturing an IC card, comprising:
のＩＣカードの製造方法において、前記基材の一面に他
の接続パッドを設ける工程と、前記基材面にジャンパ配
線を接着させる工程とを設け、前記接続パッドと前記電
極の接続工程において、前記接続パッドと前記ジャンパ
配線も接続することを特徴とするＩＣカードの製造方
法。20. The method for manufacturing an IC card according to claim 11, 12, 13 or 14, further comprising: providing another connection pad on one surface of said base material; and bonding a jumper wiring to said base material surface. A method of manufacturing an IC card, wherein, in the step of connecting the connection pad and the electrode, the connection pad and the jumper wiring are also connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11119338A JP2000311229A (en) | 1999-04-27 | 1999-04-27 | Ic card and its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11119338A JP2000311229A (en) | 1999-04-27 | 1999-04-27 | Ic card and its production |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000311229A true JP2000311229A (en) | 2000-11-07 |
Family
ID=14759019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11119338A Pending JP2000311229A (en) | 1999-04-27 | 1999-04-27 | Ic card and its production |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000311229A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004242245A (en) * | 2003-02-10 | 2004-08-26 | Minerva:Kk | Booster antenna for ic tag |
| JP2008503076A (en) * | 2004-06-15 | 2008-01-31 | イムベラ エレクトロニクス オサケユキチュア | Manufacturing method of electronic module |
| US8034658B2 (en) | 2003-04-01 | 2011-10-11 | Imbera Electronics Oy | Electronic module with a conductive-pattern layer and a method of manufacturing same |
| US8225499B2 (en) | 2005-06-16 | 2012-07-24 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
| US8240033B2 (en) | 2005-06-16 | 2012-08-14 | Imbera Electronics Oy | Method for manufacturing a circuit board |
| US8368201B2 (en) | 2002-01-31 | 2013-02-05 | Imbera Electronics Oy | Method for embedding a component in a base |
| US8581109B2 (en) | 2005-06-16 | 2013-11-12 | Imbera Electronics Oy | Method for manufacturing a circuit board structure |
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1999
- 1999-04-27 JP JP11119338A patent/JP2000311229A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8368201B2 (en) | 2002-01-31 | 2013-02-05 | Imbera Electronics Oy | Method for embedding a component in a base |
| JP2004242245A (en) * | 2003-02-10 | 2004-08-26 | Minerva:Kk | Booster antenna for ic tag |
| US8704359B2 (en) | 2003-04-01 | 2014-04-22 | Ge Embedded Electronics Oy | Method for manufacturing an electronic module and an electronic module |
| US8034658B2 (en) | 2003-04-01 | 2011-10-11 | Imbera Electronics Oy | Electronic module with a conductive-pattern layer and a method of manufacturing same |
| JP4796057B2 (en) * | 2004-06-15 | 2011-10-19 | イムベラ エレクトロニクス オサケユキチュア | Manufacturing method of electronic module |
| US8240032B2 (en) | 2004-06-15 | 2012-08-14 | Imbera Electronics Oy | Method for manufacturing an electronics module comprising a component electrically connected to a conductor-pattern layer |
| JP2008503076A (en) * | 2004-06-15 | 2008-01-31 | イムベラ エレクトロニクス オサケユキチュア | Manufacturing method of electronic module |
| US8240033B2 (en) | 2005-06-16 | 2012-08-14 | Imbera Electronics Oy | Method for manufacturing a circuit board |
| US8225499B2 (en) | 2005-06-16 | 2012-07-24 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
| US8581109B2 (en) | 2005-06-16 | 2013-11-12 | Imbera Electronics Oy | Method for manufacturing a circuit board structure |
| US9622354B2 (en) | 2005-06-16 | 2017-04-11 | Ge Embedded Electronics Oy | Method for manufacturing a circuit board structure |
| US11134572B2 (en) | 2005-06-16 | 2021-09-28 | Imberatek, Llc | Circuit board structure and method for manufacturing a circuit board structure |
| US11792941B2 (en) | 2005-06-16 | 2023-10-17 | Imberatek, Llc | Circuit board structure and method for manufacturing a circuit board structure |
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