WO2006127943A2 - Circuits durcis contre l'effet d'une particule isolee - Google Patents

Circuits durcis contre l'effet d'une particule isolee Download PDF

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Publication number
WO2006127943A2
WO2006127943A2 PCT/US2006/020318 US2006020318W WO2006127943A2 WO 2006127943 A2 WO2006127943 A2 WO 2006127943A2 US 2006020318 W US2006020318 W US 2006020318W WO 2006127943 A2 WO2006127943 A2 WO 2006127943A2
Authority
WO
WIPO (PCT)
Prior art keywords
output
signal
logic circuit
event
state
Prior art date
Application number
PCT/US2006/020318
Other languages
English (en)
Other versions
WO2006127943A3 (fr
Inventor
David E. Fulkerson
Original Assignee
Honeywell International Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc. filed Critical Honeywell International Inc.
Priority to EP06771225A priority Critical patent/EP1884017A2/fr
Priority to JP2008513725A priority patent/JP2008543179A/ja
Publication of WO2006127943A2 publication Critical patent/WO2006127943A2/fr
Publication of WO2006127943A3 publication Critical patent/WO2006127943A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Definitions

  • Integrated circuits used in devices that operate in outer space, earth orbital space, and high atmospheric altitudes generally have to be highly reliable and operate using very low levels of power.
  • these necessities, space, weight and cost limitations generally cause these integrated circuits to be very densely populated and highly complex.
  • Figure 4 is a second block diagram illustrating a glitch filter for hardening a logic circuit against short duration single-event effect conditions
  • FIG. 4 is a block diagram illustrating a circuit 200 that employs a glitch filter.
  • the glitch filter conveniently provides hardening against short term SEE conditions, i.e., against SET and/or SEU conditions.
  • transfer logic circuitry 208 of the first stage 104 is coupled in series with a feedback-controlled glitch filter 202.
  • the feedback control may be provided by a feedback module 212.
  • feedforward signal The effect of glitch-induced signal on a state of an output signal of the feedforward tri- state inverter 306 (“feedforward signal”) may then passed to the feedforward inverter 308.
  • the feedforward inverter 308 inverts the feedforward signal and passes it to node 328. Without the glitch filter 102, the inverted version of the feedforward signal containing the glitch is passed immediately on to the second stage 106, resulting in a potential SEU condition.
  • the CLK transitions to a LOW state causing the feedforward signal at node 320 to be initially latched in the undesired HIGH state, as shown in Curve 356. But because of the glitch filter 102, the slowed-output signal on node 328 does not quickly transition to a LOW state, but rather, continues to satisfy the HIGH-state threshold 360 and keep the node 328 at the proper HIGH state.

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un appareil et un procédé de durcissement d'un circuit contre une condition d'effet d'une particule isolée. Un premier circuit logique émet un événement de signal de sortie présentant une pointe de tension imprimée dessus. Un filtre à pointes de tension (i) reçoit l'événement de signal de sortie, (ii) ralentit un taux de changement de l'événement de signal de sortie selon une quantité de temps donnée afin de produire un événement de signal de sortie ralenti, et (iii) fournit à un second circuit logique l'événement de signal de sortie ralenti. Lorsqu'une durée de l'événement de signal de sortie est inférieure à la quantité de temps donnée, le filtre à pointes de tension empêche l'événement de signal de sortie ralenti d'atteindre un seuil d'état non souhaité, qui à son tour empêche le second circuit logique de fonctionner dans un état non souhaité. Un module de rétroaction éventuel fournit un événement de signal de rétroaction sans pointe de tension au filtre à pointes de tension. Lorsque l'événement de signal de sortie ralenti ne satisfait pas le seuil d'état non souhaité, l'événement de signal de rétroaction neutralise la pointe de tension imprimée sur l'événement de signal de sortie.
PCT/US2006/020318 2005-05-25 2006-05-24 Circuits durcis contre l'effet d'une particule isolee WO2006127943A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06771225A EP1884017A2 (fr) 2005-05-25 2006-05-24 Circuits durcis contre l'effet d'une particule isolee
JP2008513725A JP2008543179A (ja) 2005-05-25 2006-05-24 シングルイベント効果対策強化回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/136,920 2005-05-25
US11/136,920 US20060267653A1 (en) 2005-05-25 2005-05-25 Single-event-effect hardened circuitry

Publications (2)

Publication Number Publication Date
WO2006127943A2 true WO2006127943A2 (fr) 2006-11-30
WO2006127943A3 WO2006127943A3 (fr) 2007-02-08

Family

ID=37075924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/020318 WO2006127943A2 (fr) 2005-05-25 2006-05-24 Circuits durcis contre l'effet d'une particule isolee

Country Status (4)

Country Link
US (1) US20060267653A1 (fr)
EP (1) EP1884017A2 (fr)
JP (1) JP2008543179A (fr)
WO (1) WO2006127943A2 (fr)

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EP3811403A4 (fr) * 2018-05-31 2022-03-16 BAE SYSTEMS Information and Electronic Systems Integration, Inc. Circuit de verrouillage protégé contre les rayonnements

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DE10343565B3 (de) * 2003-09-19 2005-03-10 Infineon Technologies Ag Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop
FR2883998A1 (fr) * 2005-04-05 2006-10-06 St Microelectronics Sa Coprocesseur securise comprenant un circuit de detection d'un evenement
FR2884000A1 (fr) * 2005-04-05 2006-10-06 St Microelectronics Sa Coprocesseur securise comprenant des moyens pour empecher l'acces a un organe du coprocesseur
TW200828001A (en) * 2006-12-25 2008-07-01 Realtek Semiconductor Corp Reset circuit and the associated method
US7619455B2 (en) * 2007-04-19 2009-11-17 Honeywell International Inc. Digital single event transient hardened register using adaptive hold
US7411411B1 (en) 2007-10-19 2008-08-12 Honeywell International Inc. Methods and systems for hardening a clocked latch against single event effects
US20140157223A1 (en) * 2008-01-17 2014-06-05 Klas Olof Lilja Circuit and layout design methods and logic cells for soft error hard integrated circuits
US7772874B2 (en) * 2008-01-28 2010-08-10 Actel Corporation Single event transient mitigation and measurement in integrated circuits
US8191021B2 (en) * 2008-01-28 2012-05-29 Actel Corporation Single event transient mitigation and measurement in integrated circuits
US8255772B1 (en) 2008-06-18 2012-08-28 Cisco Technology, Inc. Adaptive memory scrub rate
US8254186B2 (en) 2010-04-30 2012-08-28 Freescale Semiconductor, Inc. Circuit for verifying the write enable of a one time programmable memory
CN102082568B (zh) * 2010-11-17 2012-08-22 北京时代民芯科技有限公司 一种抗单粒子瞬态电路
US8378711B2 (en) * 2011-03-01 2013-02-19 Stmicroelectronics S.R.L. Detection of single bit upset at dynamic logic due to soft error in real time
US9013219B2 (en) 2013-09-11 2015-04-21 The Boeing Company Filtered radiation hardened flip flop with reduced power consumption
CN104360781B (zh) * 2014-11-12 2017-10-03 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路、触控面板及驱动方法
US9997210B2 (en) 2015-03-27 2018-06-12 Honeywell International Inc. Data register for radiation hard applications
CN105574270B (zh) * 2015-12-16 2018-09-11 北京时代民芯科技有限公司 一种抗单粒子加固电路单元布局布线方法
KR101939387B1 (ko) * 2017-04-12 2019-04-11 한국과학기술원 암세포의 어트랙터 변화기작에 기반하여 실시간 회로전환 가능한 자가복구 디지털장치
EP3732788A4 (fr) * 2017-12-29 2021-08-25 BAE Systems Circuit de bascule bistable d durci par rayonnement
CN110752841A (zh) * 2019-11-18 2020-02-04 南京航空航天大学 一种高可靠性可自恢复的锁存器结构
CN112737560B (zh) * 2020-12-24 2022-09-13 中国人民解放军国防科技大学 一种无频率损耗的集成电路抗单粒子瞬态加固方法

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Publication number Priority date Publication date Assignee Title
EP3811403A4 (fr) * 2018-05-31 2022-03-16 BAE SYSTEMS Information and Electronic Systems Integration, Inc. Circuit de verrouillage protégé contre les rayonnements

Also Published As

Publication number Publication date
EP1884017A2 (fr) 2008-02-06
WO2006127943A3 (fr) 2007-02-08
US20060267653A1 (en) 2006-11-30
JP2008543179A (ja) 2008-11-27

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