WO2006126445A1 - メモリコントローラ、不揮発性記憶装置、不揮発性記憶システム及びメモリ制御方法 - Google Patents
メモリコントローラ、不揮発性記憶装置、不揮発性記憶システム及びメモリ制御方法 Download PDFInfo
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- WO2006126445A1 WO2006126445A1 PCT/JP2006/309933 JP2006309933W WO2006126445A1 WO 2006126445 A1 WO2006126445 A1 WO 2006126445A1 JP 2006309933 W JP2006309933 W JP 2006309933W WO 2006126445 A1 WO2006126445 A1 WO 2006126445A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Definitions
- the present invention relates to a nonvolatile memory device such as a semiconductor memory card having a flash memory as a main memory, a memory controller built therein, a nonvolatile memory system including a nonvolatile memory device and an access device, and
- the present invention relates to a memory control method.
- Nonvolatile memory devices including a rewritable nonvolatile memory are in increasing demand, particularly for semiconductor memory cards.
- demand for non-volatile storage systems using semiconductor memory cards is growing, especially in digital still cameras and personal computers.
- a semiconductor memory card that is put into practical use normally includes a flash memory that is a nonvolatile memory and a controller LSI that is a control circuit for the flash memory.
- non-volatile memory chips themselves have been increasing in capacity due to multi-level memory.
- the number of non-volatile memory chips mounted on semiconductor memory cards is also increasing. For example, a memory space of a semiconductor memory card exceeding 1G Neut has been put into practical use.
- a distributed management method As an address management method in a semiconductor memory card, a distributed management method has been conventionally used.
- the logical address and the status flag of the page are stored in the management area of the page that is the unit of writing, and the address management table is generated based on the status flag of the logical address page at initialization. This is the method of storing in the RAM in the controller LSI.
- the logical address and the status flag of the page are collectively referred to as “distributed management information”.
- Patent Document 1 As a method for avoiding such a problem, a "centralized management method" has been proposed, and its contents are disclosed in Patent Document 1.
- the nonvolatile memory device of Patent Document 1 divides the address space of the nonvolatile memory mounted on the semiconductor memory card into a plurality of address ranges, and stores a plurality of address management tables corresponding to each address range in the nonvolatile memory.
- the corresponding address management table is read into the RAM in response to a write or erase command to a predetermined logical address from the host.
- Patent Document 2 discloses a method that uses both a distributed management method and a centralized management method that collectively stores an address management table itself in a nonvolatile memory.
- the address management table is not written back to the non-volatile memory for each write command of the access device power such as the host.
- the address management table is written back to the non-volatile memory, and the validity of the address management table is judged at initialization. If it is valid, the address management table is used. If it is not valid, it is based on the distributed management information.
- the address management table is generated.
- Patent Document 1 Japanese Patent Laid-Open No. 2001-142774
- Patent Document 2 Japanese Patent Laid-Open No. 11-73379
- Patent Document 1 since it is only necessary to read the address management table from the nonvolatile memory at the time of initialization, the initialization process is completed in a short time. However, in order to deal with failures such as power shutdown, the address management table on the RAM is usually updated for each write or erase command to a predetermined logical address from the host, and the updated address management table is updated. It was necessary to write back to the non-volatile memory after writing or erasing the data. Compared with the distributed management method described above, this method writes back the address management table. However, if the access speed drops for the amount of processing time, I have a problem!
- Patent Document 2 since there is no access and the address management table is written back to the nonvolatile memory at a predetermined timing, the access speed at the time of data writing does not decrease. However, if the address management table is not correctly written back to the non-volatile memory due to power shutdown or the like, it will be necessary to generate the address management table based on the distributed management information of all areas of the non-volatile memory at the time of initialization. Therefore, the problem that the initialization time becomes long when a failure such as power shutdown occurs cannot be solved.
- the present invention has been made in view of such a conventional problem, and avoids a decrease in access speed due to an address management table write-back process during normal operation, while shutting down the power supply, etc.
- the purpose is to shorten the creation time of the address management table at the time of initialization even in the event of a failure.
- the present invention is a memory controller for writing or reading data in a nonvolatile memory having a plurality of address ranges composed of one or more physical blocks, wherein the memory controller is a state of the physical block
- a read / write memory for temporarily storing an address management table for managing data, and at the time of data writing, data and distributed management information for generating the address management table are written to the physical block, and the read / write memory
- the address management table is updated, and when the data write destination is switched from one address range to another address range, the address management table temporarily stored in the read / write memory is written to the nonvolatile memory.
- the controller and the above-mentioned alarm that was accessed before initialization And from within the address range reading said distributed management information, reads and generates the address management table on the write memory based on the distributed management information has an address management table generating unit.
- the time for creating the address management table at the time of initialization can be shortened. Can do. Furthermore, since it is not necessary to write back the address management table to the nonvolatile memory for each write instruction for access device power, it is possible to avoid a decrease in access speed due to the write-back processing of the address management table during normal operation.
- the address range is an area obtained by dividing the storage area of the nonvolatile memory into predetermined sizes, and includes a plurality of physical blocks corresponding to a plurality of logical units specified by an access device, and the address management
- the table may be a table that collectively manages a plurality of logical units included in the address range!
- the address range may be an area provided for each logical unit specified by the access device power, and the address management table may be a table that collectively manages a plurality of the address ranges.
- the memory control unit stores address range specifying information for specifying the switching destination address range in the nonvolatile memory. You may write.
- the memory control unit may write the address range specifying information in the nonvolatile memory in a form incorporated in the address management table.
- the memory control unit may specify the address range by accessing before initialization based on the address range specifying information.
- Another memory controller of the present invention is a memory controller that writes or reads data to or from a non-volatile memory having a plurality of address ranges configured by one or more physical blocks. Temporarily storing an address management table that includes a first table that manages the write status of physical blocks in the address range and a second table that manages the status of physical blocks in the address range.
- Write data and distributed management information for generating the address management table to the nonvolatile memory update the address management table of the read / write memory, and write data when writing data
- a memory controller that writes the address management table to the nonvolatile memory reads the second table from the nonvolatile memory, and stores it in the read / write memory at the time of initialization;
- the distribution management information is read from within the address range accessed before initialization, the first table is generated based on the read distribution management information, and stored in the read / write memory.
- Address management table raw And a composition part.
- the nonvolatile memory device of the present invention controls the nonvolatile memory having a plurality of address ranges configured by one or more physical blocks, and controls writing or reading of data to or from the nonvolatile memory. And a memory controller.
- a non-volatile storage system of the present invention includes the above non-volatile storage device including a non-volatile memory having a plurality of address ranges configured by one or more physical blocks, and the address range specified above. And an access device that controls writing or reading of data with respect to the nonvolatile memory.
- the memory control method of the present invention temporarily stores a non-volatile memory having a plurality of address ranges composed of one or more physical blocks and an address management table for managing the state of the physical blocks.
- a memory control method for controlling a non-volatile storage device having a read / write memory wherein the memory control method includes data and distributed management information for generating the address management table when data is written.
- the address management table of the read / write memory is updated by writing to a physical block and the data write destination is switched from one address range to another address range, the address management is temporarily stored in the read / write memory.
- FIG. 1 is a block diagram showing a configuration of a nonvolatile memory system according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing an internal configuration of the nonvolatile memory in the first embodiment
- FIG. 3 is a diagram showing a configuration of physical blocks in the first embodiment.
- FIG. 4 is a diagram showing a format of a logical address in the first embodiment.
- FIG. 5 is a diagram showing an address conversion table in the first embodiment.
- FIG. 6 is a diagram showing a physical area management table in the first embodiment.
- FIG. 7 is a circuit diagram showing a configuration of an address range switching unit in the first embodiment.
- FIG. 8 is a diagram showing address range specifying information in the first embodiment.
- FIG. 9 A diagram showing a write sequence when the address range in the first embodiment is not switched.
- FIG. 10 is a diagram showing a write sequence when the address range is switched in the first embodiment.
- FIG. 11 is a block diagram showing a configuration of a nonvolatile memory system according to the second embodiment of the present invention.
- FIG. 12 is a diagram showing an internal configuration of a nonvolatile memory according to a second embodiment
- FIG. 13 is a diagram showing physical blocks in the second embodiment.
- FIG. 14 is a diagram showing a format of a logical address in the second embodiment.
- FIG. 15 is a view showing an address conversion table in the second embodiment.
- FIG. 16 is a diagram showing a physical area management table in the second embodiment.
- FIG. 17 shows a write management table in the second embodiment.
- FIG. 18 is a diagram showing address range specifying information in the second embodiment.
- FIG. 19 is a diagram showing a write sequence when the address range is not switched in the second embodiment.
- FIG. 20 is a diagram showing a write sequence when the address range is switched in the second embodiment.
- FIG. 21 is a diagram showing another write sequence when the address range is switched in the second embodiment.
- FIG. 1 shows the configuration of the nonvolatile memory system in the present embodiment.
- the nonvolatile storage system of this embodiment includes an access device 100 and a nonvolatile storage device that operates based on a read / write command of user data (hereinafter simply referred to as “data”) transmitted from the access device 100. And 123.
- the non-volatile storage device 123 stores the non-volatile memory 115 based on the nonvolatile memory 115 that stores the data transferred from the access device 100 and the read / write command and the logical address transmitted from the access device 100. And a memory controller 114 for controlling.
- the storage area of the nonvolatile memory 115 is divided into a plurality of address ranges.
- the memory controller 114 includes a host interface unit (hereinafter referred to as “host I / F unit”) 101, a work RAM 103, a ROM 104 storing a program, and a program stored in the work RAM 103 and the ROM 104. It has a CPU 102 that controls the entire inside 114.
- host I / F unit a host interface unit
- work RAM 103 a work RAM 103
- ROM 104 storing a program
- program stored in the work RAM 103 and the ROM 104 It has a CPU 102 that controls the entire inside 114.
- the memory controller 114 further includes a memory control unit 122 that controls the nonvolatile memory 115, an address management table generation unit 107 that generates the address management table 112, and a read / write memory that temporarily stores the address management table 112. 113.
- the memory control unit 122 includes an address range control unit 124 that determines switching of the address range of the nonvolatile memory 115, a nonvolatile memory access unit 109 that controls reading and writing of data with respect to the nonvolatile memory 115, and
- the address management table control unit 108 writes the address management table 112 temporarily stored in the read / write memory 113 into the nonvolatile memory 115 via the nonvolatile memory access unit 109.
- FIG. 2 specifically shows the configuration of the storage area of the nonvolatile memory 115 of the present embodiment.
- the nonvolatile memory 115 is 1 GB, and 8 chips of 1 Gbit flash memory are mounted.
- the nonvolatile memory 115 includes a plurality of physical blocks 211.
- the physical block 211 is an erase block of the smallest unit that can be selectively erased. In this embodiment, it has a size of about 4 kB.
- the non-volatile memory 115 is divided into eight address ranges of address ranges 0 to 7 in the vertical direction of FIG. 2, and is divided into four banks of banks 0 to 3 in the horizontal direction.
- Each address range is composed of 4k physical blocks 211.
- Each address range has a user data area 116 for storing data and an address management table area 117 for storing the address management table 112.
- the address management table area 117 provided for each address range stores an address management table 112 corresponding to each address range.
- the address management table area 117 stores address management tables 112 in order from the lower side (upper side in FIG. 2). Thereafter, the old address management table 112 that has become unnecessary is sequentially deleted so that the new address management table 112 can be stored.
- the address management table area 117 is used cyclically. For example, when a write command is issued from the access device 100 and valid data is written in the nonvolatile memory 115, the latest address management table in the address range 1 is written in 2047—a0 to 2047—dO. If it is inserted, the address management tables stored in 2046—a1 to 2046—dl and 2 046—a0 to 2046—dO on the lower side (the upper side in FIG. 2) are erased, Invalid block. And the area made into the invalid block is used later.
- the non-volatile memory 115 further includes a current address range number storage area 118 for storing address range specifying information 801 (details will be described later) shown in FIG.
- the current address range number storage area 118 is provided on the upper side of the address range 7.
- the sum of the sizes of the user data area 116 of the address range 7 and the address management table area 117 is smaller than the sizes of the other address ranges.
- the current address range number storage area 118 stores address range specifying information 801 in order from the lower side (upper side in FIG. 2). Thereafter, the old and old address range specifying information 801 are deleted in order so that new V and address range specifying information 801 can be stored.
- the current address range number storage area 118 is used cyclically.
- nonvolatile memory 115 information related to security, manufacturer code, and the like are written. Description of the so-called system area will be omitted.
- FIG. 3 shows a specific example of the physical block 211 in the present embodiment.
- the physical block 211 has two pages, page 0 and page 1.
- a page is a unit of writing.
- the maximum number of simultaneous writes is one page in each of four banks, that is, a maximum of four pages.
- Each page has a data area 212 of 2048 noise and a management area 213 of 64 noise.
- One sector is 512 bytes, and the data area 212 is composed of four sectors.
- the data area 212 is an area where data transferred from the access device 100 is written.
- distributed management information 214 is stored.
- the distributed management information 214 includes a logical block number designated by the access device 100 and a block status indicating the status of the physical block 211.
- the distributed management information 214 is written to the management area 213 of page 0 when the data transferred also by the access device 100 is written to the data area 212 of page 0.
- FIG. 4 shows a format of the logical address 400 transmitted from the access device 100 to the nonvolatile storage device 123 in the present embodiment.
- bit 0 to bit 1 (bO to bl) force sector number 401 bit 2 to bit 3 (b2 to b3) are bank number 402, bit 4 (b4) Is page number 403.
- the 12 bits including the number 404 and the bank number 402 of bit 5 to bit 14 (b5 to bl4) are the logical block nanno 411, bit 15 to bit 17 (bl5 to bl7), and the address range nanno 405.
- the address range 0 to 7 of the non-volatile memory 115 is designated by the 3-bit address range number 405.
- 12 bits corresponding to logical block number 411 are subject to address conversion to physical block number 412.
- the address management table 112 includes an address conversion table 110 and a physical area management table 111.
- FIG. 5 shows the address conversion table 110 in the present embodiment.
- the address conversion table 110 is a tape that converts the logical block number 411 included in the logical address 400 specified by the access device 100 into the physical block number 412 in the nonvolatile memory 115. It is le.
- the address conversion table 110 indicates the corresponding physical block number 412 for each logical block number 411.
- the address conversion table 110 is generated for each address range, and therefore includes physical block numbers 412 specified by 4096 logical block numbers 411.
- FIG. 6 shows the physical area management table 111 in the present embodiment.
- the physical area management table 111 is a table that stores the block status such as the state of the physical block 211 that is an erasing unit in the nonvolatile memory 115, that is, whether valid data is stored in the physical block 211! It is.
- the physical area management table 111 indicates the state of each physical block for each physical block number 412 of the nonvolatile memory 115.
- the block status indicating the state of the physical block includes valid, invalid, and defective. A binary number of “00” indicates that the valid block has already been written with valid data, and a binary number of “11” indicates that the data that has been erased or written is unnecessary. Indicates a block.
- the binary number “10” indicates a bad block that cannot be used due to a solid error on the memory cell.
- the block status includes at least three states.
- block statuses for 4096 physical block numbers 412 are stored.
- the address management table generation unit 107 shown in FIG. 1 generates the address management table 112 based on the distributed management information 214 stored in the user data area 116 at the time of initialization such as power-on. It is stored on the read / write memory 113. In the present embodiment, only the distribution management information 214 stored in the user data area 116 in the address range read from the current address range number storage area 118 is read out. That is, at the time of initialization, an address management table 112 is generated for any one address range in the address ranges 0 to 7.
- the read / write memory 113 is a volatile memory such as SRAM or a nonvolatile memory such as a ferroelectric memory, and temporarily stores the address management table 112. Data writing or the like according to an instruction from the access device 100 is performed while referring to the address management table 112 stored in the read / write memory 113 and updating.
- the memory control unit 122 writes the data and the distribution management information 214 in the user data area 116 in response to a write instruction from the access device 100.
- the address management table control unit 108 in the memory control unit 122 updates the address management table 112 temporarily stored in the read / write memory 113.
- the address management table control unit 108 stores the address management table 112 temporarily stored in the read / write memory 113 when the write destination address instructed by the access device 100 is switched to another address range. To the address management table area 117 of the current address range via the volatile memory access unit 109.
- the address range specifying information 801 is information for specifying the address range of the switching destination.
- FIG. 8 shows address range specifying information 801 in the present embodiment.
- the address range specifying information 801 includes time information 711 for identifying temporal relations and an address range number 712 after switching at the time of address range switching.
- the lower 27 bits indicate the time information 711, and the upper 3 bits indicate the address range number 712.
- the address range control unit 124 shown in FIG. 1 has an address range switching unit 105 and an address range specifying unit 106.
- the address range specifying unit 106 stores the address range that is currently being accessed in the nonvolatile memory 115, that is, in initialization at power-up, before power-up or reset. In order to be able to identify the address range that has been accessed, immediately after the address range is switched, when starting to write to the address range after switching, the address range is entered via the nonvolatile memory access unit 109.
- the specific information 801 is stored in the current address range number storage area 118 of the nonvolatile memory 115.
- the address range specifying unit 106 reads the address range specifying information 801 having the latest time information 711 from the current address range number storage area 118 of the nonvolatile memory 115 at the time of initialization after the power is turned on. Specify the range number 712. As a result, for example, even when the system is restarted due to a failure such as a power shutdown, the address range specifying unit 106 can specify the address range number 712 that was accessed before the startup.
- FIG. 7 shows a configuration of the address range switching unit 105 in the present embodiment.
- Address range The switching unit 105 includes a counter 701, a register 702, a comparator 703, and a register 704.
- the register 702 temporarily stores the address range number 405 included in the logical address 400 transferred by the access device 100 according to the system clock SCK.
- the comparator 703 compares the address range number 405 transferred by the access device 100 with the address range number 405 stored in the register 702, and activates the address range switching signal if they are different. Output.
- the register 704 temporarily stores the address range number 405 transferred by the access device 100 when the address range switching signal becomes active.
- the output of the register 704 is the address range number 712 after switching when the address range is switched.
- the counter 701 is preset with the time information 711 of the latest address range specifying information 801 stored in the current address range number storage area 118 at the time of activation. Note that the physical block 211 of the non-volatile memory 115 immediately after shipment from the factory is completely erased, so the data of the lowest page of the current address range number storage area 118 is read, and the time information of initial value 0 is stored. Preset to counter 701. Counter 701 increments the value by one when the address range switching signal becomes active.
- the number of bits of the counter 701 of the present embodiment will be described. If the average write data capacity for one write command from the access device 100 is 16 kB for 4 physical blocks (that is, 1 cluster in FAT16), all of the user data area 116 in one address range The number of commands to write the physical block is approximately lk times (2 to the 10th power) according to equation (1).
- the rewrite life of the non-volatile memory 115 that is, the number of rewrites less than the guaranteed good block rate is 100,000 times (2 to the 17th power).
- the number of bits may be increased in consideration of the difference in the rewrite life of the nonvolatile memory 115 and the design margin.
- the address range switching unit 105 configured as described above is transferred by the access device 100. Based on the logical address 400, it is detected whether or not the address range number 405 has been switched. The time information 711 representing the temporal relationship is output so that the command at what time can be understood.
- the address range specifying unit 106 searches the current address range number storage area 118 of the nonvolatile memory 115 via the nonvolatile memory access unit 109 and stores the current address range number storage area 118 in the current address range number storage area 118.
- the address range specifying information 801 the one with the largest value of the time information 711 is read as the latest address range specifying information 801. This identifies the address range number 712 that was accessed before the power was turned on.
- the time information 711 included in the address range specifying information 801 is preset in the counter 701. However, if the value of all bits of the time information 711 is 1, it is determined that it is immediately after shipment from the factory, and a value of 0 is preset in the counter 701.
- the address management table generation unit 107 reads the distributed management information 214 stored in the user data area 116 within the specified address range, and generates the address conversion table 110 and the physical area management table 111. And stored in the read / write memory 113.
- the nonvolatile storage device 123 enters a command reception state such as reading / writing from the access device 100.
- the address range switching unit 105 Determine whether the address range number 405 transferred by is the same as the address range number 712 specified during the initialization process. To do. If they are the same, the logical block number 411 included in the logical address 400 is converted into the physical block number 412 based on the address management table 112, and data is written to the physical block 211 specified by the physical block number 412.
- FIG. 9 shows a normal write sequence when address range switching does not occur in the present embodiment.
- FIG. 9 shows a data write period TA 0 for writing data to page 0 of the physical block 211 and a data write period TA 1 for writing data to page 1 of the physical block 211.
- data is written to the nonvolatile memory 115 by multi-bank write that simultaneously writes page 0 or page 1 of four pages in banks 0 to 3.
- the data write periods TA0 and TA1 include a ride command and address Z data transfer period Tal, an erase busy period Ta2, and a program busy period Ta3.
- the memory controller 114 first transfers the write command, the physical block number 412 in the user data area 116, and the data for four pages of banks 0 to 3 to the nonvolatile memory 115 ( Ride command and address Z data transfer period Tal). At this time, the distributed management information 214 is also transferred to the nonvolatile memory 115 at the same time. Next, the physical block 211 specified by the physical block number 412 is erased (erasure busy period Ta2). Finally, data and distributed management information 214 are written to page 0 of physical block 211 in banks 0 to 3, and address management table 112 on read / write memory 113 is updated (program busy period Ta3).
- data is written to the physical block 211 of logical addresses 0—a 0 to 0—dO and 0—al to 0—dl.
- data is transferred from the logical address 0—a0 to 0—dO to the physical block 211 of 1021—al to 1021—dl.
- one cluster is normally 16 kB, and in many products, the access device 100 issues a write instruction in units of 16 kB in a nonvolatile storage device. Forward to device 123.
- the address management table 112 temporarily stored in the read / write memory 113 is written back to the nonvolatile memory 115, and the temporal overhead increases the processing speed. It was a factor to lower.
- the nonvolatile storage device 123 of the present embodiment does not perform a process of writing back the address management table 112 temporarily stored in the read / write memory 113 to the nonvolatile memory 115, and at the time of data writing In addition, distributed management information 214 is written to streamline the overhead.
- FIG. 10 shows the write sequence when address range switching occurs.
- the address range switching unit 105 detects that the address range is switched by the comparator 703
- the memory control unit 123 reads the address management table write period (hereinafter referred to as “AT write period”) TB, the address management table. Processing is performed in the order of the read period (hereinafter referred to as “AT read period”) TC and the address range specifying information write period TD.
- AT write period the address management table write period
- TD address range specifying information write period
- memory controller 114 receives logical address 400 designating address range 1 from access device 100.
- the address range switching unit 105 detects that the address range is switched from 0 to 1 by the comparator 703. Then, the memory controller 114 first performs processing in the AT write period TB as post-processing of the old address range.
- the memory controller 114 temporarily stores the address management table 112 in the address range 0 stored in the read / write memory 113 in the address management table area 117 in the address range 0 of the nonvolatile memory 115. Write back as the latest address management table.
- the memory controller 114 transfers the write command, the physical block number 412 in the address management table area 117 in the address range 0, and the address management table 112 stored in the read / write memory 113 to the nonvolatile memory 115. (Write command and address ZAT transfer period Tbl).
- Tbl write command and address ZAT transfer period
- the address management table 112 is written into the erased physical block 211 (program busy period Tb3
- the writing process for the address range 0 is completed, and the actual address range switching time TS is between the end time of the AT write period TB and the start time of the AT read period TC.
- processing is performed in the AT read period TC and the address range specification information write period TD.
- the CPU 102 issues an instruction to read the address management table 1 12 in the address range 1 to the nonvolatile memory access unit 109.
- the nonvolatile memory access unit 109 The management table 112 is read from the address management table area 117 in the address range 1, and the address management table control unit 108 stores the read address management table 112 in the read / write memory 113 (read command and address ZAT transfer period Tel) .
- the address management table 112 read here is the latest address management table in the address management table area 117 in the address range 1. Whether or not the address management table 112 is the latest is determined as follows.
- the top address of the page of the physical block in the address management table area 117 specifically, 4 pages (all 8kB) of logical addresses 2047—al to 2047—dl in FIG. 2 are erased as a set. Judge whether it is power or not. If not erased, it is determined that the set of logical addresses 2047-al to 2047-dl is the latest address management table. If it has been erased, the search is performed in the upper direction of FIG. 2, that is, the lower side of the nonvolatile memory 115, and four pages that are not erased, that is, some value is written, are used as the latest address management table. select.
- the memory controller 114 stores the address range specifying information 801 including the address range number 712 after switching shown in FIG. 8 in the current address range number storage area of the nonvolatile memory 115.
- the counter 701 in the address range specifying unit 106 is incremented, and the address range number 712 after switching is stored in the register 704.
- the address range specifying unit 106 generates address range specifying information 801 including the time information 711 of the counter 701 and the address range number 712 stored in the register 704.
- the nonvolatile memory access unit 109 transfers the write command, the physical block number 412 and the address range specifying information 801 in the current address range number storage area 118 of the nonvolatile storage device 115 to the nonvolatile memory 115 (write command and address). Z address range specific information transfer period Tdl).
- the physical block 211 specified by the physical block number 412 is erased (erase busy period Td2).
- address range specifying information 801 is written into the erased physical block 211 (program busy period Td3).
- the address range specifying unit 106 can determine which address range the failure such as the power shutdown occurred during the processing.
- the address management table generation unit 107 performs nonvolatile memory access.
- the distributed management information 214 read via the unit 109 is limited to one address range. For example, if the non-volatile memory 115 has a multi-bank page read function and the time required for each multi-bank page read is 100 ⁇ s, the reading of the distributed management information 214 is completed in about 100 milliseconds according to equation (3). .
- the conventional semiconductor memory device as shown in Patent Document 2 reads the dispersion management information of the entire area, and therefore the read time is about 6400 ms according to the equation (5).
- the value is 8 times. This value is a long waiting time when the user starts up.
- the value of the equation (5) becomes larger as the capacity of the nonvolatile memory becomes larger.
- the time required for the initialization process of this embodiment is 1Z8 of Patent Document 2, and the process can be performed in a short time.
- the data write period TAO and TA1 shown in Fig. 9 and the AT write period TB and data write period TAO shown in Fig. 10 are 1.5 ms each.
- the address range does not change, for example, a logical address
- the writing time of the present embodiment is shorter than the writing time shown in Patent Document 1.
- the present embodiment uses an AT write period TB for post-processing the old address range, an AT read period TC and an address for pre-processing the new address range.
- the range identification information write period TD is required, and processing time is longer than that of Patent Document 1.
- Patent Document 1 is compared based on the rate value at which one entire logical range is rewritten in units of 16 kB.
- the capacity of one address range is about 16MB (for the sake of simplicity, the address management table area is considered an error).
- access Device 100 will command lk writes.
- the conventional semiconductor memory device shown in Patent Document 1 has an average rewrite rate of 3.6 MBZ seconds as shown in Equation (9).
- the average rewrite rate is 5.5 MBZ seconds as shown in the equation (10), which is faster than the nonvolatile memory device 123 of the present embodiment.
- One address range can be rewritten.
- the instantaneous speed degradation at the time of switching the address range is on the order of several milliseconds, so that it can be sufficiently absorbed by using a notor that is normally provided on the access device 100 side. This does not cause the processing to fail.
- the initialization time at startup can be minimized and the address management table 112 can be updated.
- the rewrite rate can be improved. That is, according to the present invention, the address management table 1 during normal operation 1 While avoiding a decrease in access speed due to the 12 write-back processing, it is possible to shorten the time for creating the address management table 112 at initialization after a failure such as a power shutdown.
- the management area 213 in FIG. 3 may store time information 711 in addition to the distributed management information 214.
- the time information 711 is written to the management area 213.
- the address management table area 117 After the address range is specified during initialization processing, only the physical block 211 in which the time information 711 corresponding to the time information 711 of the address range specification information 801 is written is read and stored in the address management table area 117.
- the latest address management table 112 may be revised.
- the address management table 112 in the address management table area 117 can be updated in a short time, which is useful in initialization processing after the processing is interrupted due to power shutdown or the like.
- the read / write memory 113 may use a read / write memory other than RAM as long as it can be accessed at a relatively high speed.
- the nonvolatile memory 115 may incorporate a plurality of nonvolatile memory chips.
- the nonvolatile memory 115 may be a non-volatile memory other than a flash memory.
- nonvolatile memory 115 may be configured by using one flash memory chip, or may be configured by using a plurality of flash memory chips.
- the address management table area 117 is provided in each address range.
- the address management table areas 117 in the address ranges 0 to 7 are grouped into one range, for example, the nonvolatile memory 115. May be provided in the last area.
- the storage position of the address management table 112 may not be physically fixed as in the address management table area 117 of the present embodiment.
- the address management table 112 is stored in the physical block 211 of the user data area 116 without providing the address management table area 117.
- pointer information indicating the physical address of the storage destination of the address management table 112 is stored in the nonvolatile memory 115, and the storage position can be searched according to the pointer information.
- the position of the current address range number storage area 118 is not limited to the upper side of the address range 7.
- the address range specifying information 801 is non-volatile.
- a non-volatile memory other than the force non-volatile memory 115 stored in the current address range number storage area 118 of the generating memory 115 may be provided separately and stored therein.
- the address range specifying information 801 may be written back to the nonvolatile memory 115 in a form incorporated in the address management table 112 corresponding to the address range before switching when the address range is switched. Absent. In that case, in the initialization after the power is turned on, the latest address management table 112 stored in all address ranges 0 to 7 is examined and stored in the address management table 112 including the latest time information 711. It is determined that the address range number 712 is the same as the address range number at the time when the power is shut off.
- FIG. 11 shows a nonvolatile memory system according to the second embodiment of the present invention.
- the nonvolatile storage system of the second embodiment is different from the first embodiment in the size of the address range of the nonvolatile memory 1115 and the generation method at the time of initialization of the address management table 1112.
- the nonvolatile storage system of this embodiment includes an access device 100 and a nonvolatile storage device 123 that operates based on a read / write command for data transmitted from the access device 100.
- the nonvolatile storage device 123 is a nonvolatile memory 1115 that stores data transferred from the access device 100, and a nonvolatile read / write instruction and a logical address of data transmitted from the access device 100.
- the storage area of the nonvolatile memory 1115 has a plurality of address ranges.
- the memory controller 114 includes a host I / F unit 101, a work RAM 103, a ROM 104 that stores a program, and a CPU 102 that controls the entire memory controller 114 using the program stored in the work RAM 103 and the ROM 104.
- the memory controller 114 further includes a memory control unit 122 that controls the nonvolatile memory 1115, an address management table generation unit 107 that generates the address management table 1112, and a read / write memory that temporarily stores the address management table 1112 113.
- the memory control unit 122 determines whether the address range of the nonvolatile memory 1115 is switched, the address range control unit 124, the nonvolatile memory access unit 109 that controls reading and writing of data to the nonvolatile memory 1115, and the reading and writing An address management table control unit 108 for writing the address management table 1112 temporarily stored in the memory 113 to the nonvolatile memory 1115 via the nonvolatile memory access unit 109 is provided.
- the storage area of the nonvolatile memory 1115 includes a user data area 1116 for storing data, an address management table area 1117 for storing the address management table 1112, and the address range specifying information 1801 shown in FIG. Current address range number storage area 118 for storing.
- FIG. 12 specifically shows the configuration of the storage area of the nonvolatile memory 1115 of the present embodiment.
- the non-volatile memory 1115 is 1 GB, and 8 chips of 1 Gbit flash memory are mounted.
- the nonvolatile memory 1115 includes a plurality of physical blocks 211.
- the physical block 211 is an erase block of the smallest unit that can be selectively erased, and has a size of about 4 kB in this embodiment.
- the nonvolatile memory 1115 is divided into four banks 0 to 3 in the horizontal direction.
- the address range 1201 includes a total of four physical blocks 211 selected one by one from each bank in the user data area 1116.
- four physical blocks with logical block number “0” including logical addresses 0—aO, 0—al to 0—dO, and 0—dl form one address range 1201.
- the logical block number is an address range number that specifies the address range 1201.
- logical block number “0” address range number “0”.
- the user data area 1116 has an address range of 0 to 8188.
- the address management table area 1117 is provided in the upper area of the nonvolatile memory 1115 rather than being provided in the address range 1201.
- the address management table area 1117 stores the address management tape 1112 in order from the lower side (upper side in FIG. 12). Thereafter, the old address management table 1112 that has become unnecessary is sequentially deleted so that the new address management table 1112 can be stored. In this way, The less management table area 1117 is used cyclically. For example, assume that a write command is issued from the access device 100, valid data is written in the nonvolatile memory 1115, and stored in the latest address management tape memory 1112 physical addresses 8190_aO to 8190_dO. The address management tables 1112 stored in 8189-al to 8189-dl and 8189-a0 to 8189-d0 lower than that (upper side in FIG. 12) are erased as invalid blocks. This area is made available for later use.
- the storage area of the nonvolatile memory 1115 has a current address range number storage area 118 on the upper side of the address management table area 1117.
- the current address range number storage area 118 is an area for storing information for specifying an address range number, and stores address range specifying information 1801 shown in FIG.
- the current address range number storage area 118 is used cyclically while erasing the physical block 211 storing the old address range specifying information 1801 that is no longer needed.
- nonvolatile memory 1115 the description of the so-called system area in which security-related information, manufacturer code, and the like are written is omitted here.
- FIG. 13 shows a specific example of the physical block 211 in the present embodiment.
- the physical block 211 has two pages, page 0 and page 1.
- a page is a unit of writing.
- the maximum number of simultaneous writes is one page in each of four banks, that is, a maximum of four pages.
- Each page has a data area 212 of 2048 knots and a management area 213 of 64 knots.
- One sector is 512 bytes, and the data area 212 is composed of four sectors.
- the data area 212 is an area where data transferred from the access device 100 is written.
- distributed management information 214 is stored in the management area 213 of page 0, distributed management information 214 is stored.
- the distributed management information 214 includes a logical block number designated by the access device 100 and a block status indicating the status of the physical block 211. When the data transferred from the access device 100 is written to the data area 212 of page 0, the distributed management information 214 is written to the management area 213 of page 0.
- FIG. 14 shows a format of a logical address 1400 transmitted from the access device 100 to the nonvolatile storage device 123 in the present embodiment.
- the logical address 1400 has a sector number 401, a bank number 402, a page number 403, and an address range number 1405 from the lower bit to the river page.
- the address range number 1405 is the logical block number 1411.
- the 13 bits corresponding to logical block number 1411 are subject to address translation to physical block number 1412.
- the address management table 1112 of this embodiment includes an address conversion table 1110, a physical area management table 1111, and a write management table 1121.
- FIG. 15 shows an address conversion table 1110 in the present embodiment.
- the address conversion table 1110 is a table for converting the logical block number 1411 included in the logical address 1400 designated by the access device 100 into the physical block number 1412 in the nonvolatile memory 1115.
- the address conversion table 1110 indicates a physical block number 1412 corresponding to each logical block number 1411.
- the address conversion table 1110 includes physical block numbers 1412 for all logical block numbers 1411 in the nonvolatile memory 1115. Further, the address conversion table 1110 stores a physical block number newly reserved in response to a write instruction from the access device 100 at the end.
- FIG. 16 shows a physical area management table 1111 in the present embodiment.
- the physical area management table 1111 is a table indicating the state of the physical block 2 11 which is an erasure unit in the nonvolatile memory 1115.
- the physical area management table 1111 is a block indicating whether or not valid data is stored. Remember the status.
- the physical area management table 1111 stores block statuses for all physical block numbers 1412 included in the address conversion table 11 10, and the capacity of the physical area management table 1111 of this embodiment is the first capacity. This is different from the capacity of the physical area management table 111 of the embodiment. Except for the capacity, the physical area management table 1111 of this embodiment is the same as the physical area management table 111 of the first embodiment.
- FIG. 17 shows the write management table 1121 in the present embodiment.
- the write management table 1121 is a table that stores the write state of the physical block corresponding to the logical block that is one unit managed by the address conversion table 1110.
- the write management table 1121 indicates, for each bank of page 0 and page 1, whether or not the data has been written by 1 bit, and stores “1” if not written and “0” if written. For example, when four physical blocks are newly reserved in response to a write instruction from the access device 100, all bits of the write management table 1121 are set to binary “1”. The next time data is written, the binary “0” is set in the bit corresponding to the page where the data was written.
- the write management table 1121 determines whether it is necessary to reallocate a new physical block when data is written to a page where “0” is already set.
- the address management table control unit 108 shown in FIG. 11 reads the address conversion table 1110 and the physical area management table 1111 from the address management table area 1117 of the nonvolatile memory 1115 at the time of initialization.
- the address management table generation unit 107 generates the write management table 1121 based on the distributed management information 214 stored in the physical block 211 in the address range accessed before power-on.
- the read / write memory 113 is a volatile memory such as SRAM or a nonvolatile memory such as a ferroelectric memory, and temporarily stores the address management table 1112. Data writing or the like according to an instruction from the access device 100 is performed while referring to the address management table 1112 stored in the read / write memory 113 and updating.
- the memory control unit 122 writes the data and the distribution management information 214 in the user data area 1116 in response to a write instruction from the access device 100.
- the address management table control unit 108 in the memory control unit 122 updates the address management table 1112 temporarily stored in the read / write memory 113.
- the address management table control unit 108 stores the address management table 111 temporarily stored in the read / write memory 113 when the write destination address designated by the access device 100 is switched to another address range. 2 is written in the address management table area 1117 of the nonvolatile memory 1115.
- the address range specifying information 1801 is information for specifying the switching destination address range.
- FIG. 18 shows address range specifying information 1801 in the present embodiment.
- the address range specifying information 1801 includes time information 711 and an address range number 1712 for specifying the address range after switching.
- the number of bits of the address range number 1712 is different from the number of bits of the address range number 712 of the first embodiment.
- the address range control unit 124 shown in FIG. 11 has an address range switching unit 105 and an address range specifying unit 106.
- the internal configuration of the address range switching unit 105 is the same as that in FIG. 7 of the first embodiment.
- the address range switching unit 105 detects whether or not the address range number 1712 has been switched based on the logical address transferred by the access device 100. When switching is detected, the address range number 1712 after switching is output, and the time sequence of each instruction is changed so that the instruction transferred by the access device 100 can be identified. The time information 711 to be output is output.
- the address range specifying unit 106 when starting to write to the address range after switching, sends the address range specifying information 1801 via the nonvolatile memory access unit 109 to the nonvolatile memory. Stored in the current address range number storage area 118 of 1115.
- the address range specifying unit 106 based on the address range specifying information 1801 stored in the current address range number storage area 118, at the time of initialization after the power supply startup, addresses accessed before the power supply startup. Specify range 1 201. As a result, for example, even when the system is restarted due to a failure such as power shutdown, the address range specifying unit 106 can specify the address range number 1712 that was accessed before the startup.
- the initialization process is performed not only when the power is turned on but also when the nonvolatile storage device 123 is reset.
- the nonvolatile memory access unit 109 reads the address management table area 1117 of the nonvolatile memory 1115, the address conversion table 1110, and the physical area management table 1111.
- the address management table control unit 108 writes the address conversion table 1110 and the physical area management table 1111 to the read / write memory 113.
- the address translation table 1110 and the physical area management table 1111 read during the initialization process are stored in the physical block 211 in the address management table area 1117, and the latest address translation table 1110 and the physical area management table. 1111.
- the highest address of the page of the physical block 211 corresponding to the address management table area 1117 specifically, the logical address 8190—al to 8190—dl in FIG.
- the criteria for determining whether or not all four pages (8kB in total) are erased as a set are as follows. Then, the search is performed in the upper direction in FIG. 12, and four pages that are not erased, that is, some values are written are selected as the latest address conversion table 1110 and physical area management table 1111.
- the CPU 102 issues an instruction to read the address range specifying information 1801 to the nonvolatile memory access unit 109.
- the address range specifying unit 106 searches the address range specifying information 1801 having the largest time information 711 from the current address range number storage area 118 of the non-volatile memory 1115 via the non-volatile memory access unit 109.
- the address range number 1712 included in the address range specifying information 1801 is transferred to the address management table generating unit 107.
- the address management table generation unit 107 generates a write management table 1121 based on the distribution management information 214 of the physical block 211 in the address range accessed before power-on, and stores it in the read / write memory 113. However, it is determined that the address range specifying information 1801 has not been written for the time information 711 having all bit values of 1.
- the memory controller 101 After writing the address conversion table 1110, the physical area management table 1111, and the write management table 1121 to the read / write memory 113, the memory controller 101 accepts commands such as read / write from the access device 100. Enter the state.
- Figure 19 shows the writing process when there is no address range switching.
- the access to the nonvolatile memory 115 is in units of 16 kB.
- the access is in units of 2 kB.
- FIG. 19 in the data write period TA0, 2 kB of data is written to page 0 of the physical block 211 indicated by the logical address 0—aO in the address range 0, and in the next data write period TBI, Data of 2 kB is written to page 0 of physical block 211 indicated by logical address 0—bO in 0.
- the write command and address Z data transfer period Tal, erase busy period Ta2, and program busy period Ta3 are the same as in FIG. 9 of the first embodiment.
- Figure 20 shows the write process when the address range is switched.
- FIG. 20 shows an example in which the address range 1201 is switched from “3” to “4”.
- the address range switching unit 105 receives the logical address 1400 designating the address range 4 from the access device 100. It detects that the address range has been switched from “3” to “4”. As a result, the processing for the address range 3 is completed, and the address range switching point TS is reached between the data write period TA3 and the data write period TAO.
- the address conversion table 1110, the physical area management table 1111, and the write management table 1121 temporarily stored in the read / write memory 113 in the AT write period TB are stored in the address management table area 1117 of the nonvolatile memory 1115. Stored.
- address range specifying information 1801 including the address range “4” is written into the current address range number storage area 118 of the nonvolatile memory 1115.
- the address conversion table 1110 for all logical block numbers 1411 and the physical area management table 1111 for all physical block numbers 1412 included in the address conversion table 1110 are read and written. Since it is stored in the memory 113, the AT read period TC of FIG. 10 need not be provided.
- the nonvolatile memory device 123 stores the data every time data is written.
- the dress management table 1112 is not written back to the nonvolatile memory 1115.
- the address management table 1112 on the nonvolatile memory 1115 when a failure such as power interruption occurs may not be the latest address management information. Therefore, when the address range specifying unit 106 starts up immediately after a failure such as a power shutdown, the address range when a failure such as a power shutdown occurs is specified, and the distributed management information 214 stored in the address range. Based on the above, the address management table generation unit 107 generates the write management table 1121 on the read / write memory 113.
- the amount of data read by the address management table generation unit 107 via the nonvolatile memory access unit 109 is limited to the distributed management information 214 within the address range, it can be read in a relatively short time. For example, if the non-volatile memory 1115 has a multi-bank page read function and the required multi-bank page read time for each page is 100 seconds, the read operation is completed in about 0.8 milliseconds according to equation (11).
- the read time of the dispersion management information in all areas is about 6400 ms according to the equation (13).
- this value is a long time as a waiting time when the user starts up. Such a problem becomes fatal as the capacity of the semiconductor memory device increases.
- the initialization process can be performed in a short time.
- the data write periods TA0, TA1 shown in FIG. 19 and the data write periods TA3, TA0, AT write period TB, and address range specific information write period TD shown in FIG. 20 are 1.5 ms each.
- this embodiment and Patent Document 1 are compared based on the rate value at which one address range is rewritten in units of 2 kB.
- the capacity of one address range is 16 kB.
- the rewrite rate of the conventional semiconductor memory device as shown in Patent Document 1 is an average of 444 kBZ seconds as shown in Equation (17).
- the rewrite rate of the nonvolatile memory device 123 of the present embodiment is an average of 593 kBZ seconds as shown in the equation (18).
- the nonvolatile memory device 123 in the present embodiment can be rewritten at a higher speed than the conventional semiconductor memory device.
- the initialization time at startup is minimized.
- the overhead of updating the address management table 1112 can be rationalized, and as a result, the rewrite rate can be improved.
- the address range is switched using the write sequence shown in FIG. 21 instead of FIG. You may perform the process when it changes.
- the AT write period TB is provided after the data write period TA3, and the interval between the AT write period TB and the data write period TAO is used as the address range switching time point TS.
- the management area 213 in FIG. 13 may store time information 711 in addition to the distributed management information 214 and the like.
- the latest address management table stored in the address management table area is based on the information of only the physical block that matches the time information 711 of the address range specifying information 1801 stored in the current address range number storage area 118 of FIG.
- Bulletin 1112 By revising Bulletin 1112, a truly up-to-date address management table 1112 can be generated.
- the read / write memory 113 may use a read / write memory other than RAM as long as it can be accessed at a relatively high speed.
- nonvolatile memory 1115 may be configured using one flash memory chip.
- Non-volatile memory 1115 A plurality of flash memory chips may be used.
- Non-volatile memory 1115 A plurality of flash memory chips may be used.
- Non-volatile memory 1115 A plurality of flash memory chips may be used.
- a non-volatile memory other than the flash memory may be used.
- the storage location of the address management table 1112 is not physically fixed, but pointer information indicating the physical address of the area for address management information is used. Separately, mix the address management table 1112 in the same area as the user data area 1116, and move the storage location according to the pointer information.
- the address range specifying information 1801 for specifying the address range such as the time information 711 is stored in the current address range number storage area 118 of the nonvolatile memory 1115.
- a non-volatile memory may be provided separately and stored there.
- the address range specifying information 1801 may be written back to the nonvolatile memory 1115 in a form incorporated in the address management table 1112 corresponding to the switched address range. Absent. However, in that case, in the initialization after the power is turned on, the latest address management table 1112 corresponding to all the address ranges 0 to 8188 in the address management table area 1117 is checked, and the latest time information 711 is obtained. The address range number 1712 stored in the included address management table 1112 is determined as the address range number 1712 at the time when the power is shut off. The address range number 1712 at the time of switching written there can be identified as the address range number 1712 to which a write instruction or the like from the access device 100 has been transferred when a failure such as a power shutdown occurs.
- the non-volatile storage device of the present invention has a V effect if both high-speed writing and shortening of the initialization time can be achieved using a storage medium such as a memory card using a non-volatile memory such as a flash memory. It is useful as a recording medium for portable AV devices such as still image recording / playback devices and moving image recording / playback devices, or portable communication devices such as mobile phones.
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JP2003296188A (ja) * | 2002-03-18 | 2003-10-17 | Samsung Electro Mech Co Ltd | 高容量フラッシュメモリカードシステムにおけるデータ運営方法 |
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US7139864B2 (en) * | 2003-12-30 | 2006-11-21 | Sandisk Corporation | Non-volatile memory and method with block management system |
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- 2006-05-18 US US11/914,989 patent/US8051270B2/en not_active Expired - Fee Related
- 2006-05-18 WO PCT/JP2006/309933 patent/WO2006126445A1/ja active Application Filing
- 2006-05-18 CN CN200680017750A patent/CN100590608C/zh not_active Expired - Fee Related
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JPH1173379A (ja) * | 1997-06-20 | 1999-03-16 | Sony Corp | データ管理装置及びデータ管理方法並びに記憶媒体 |
JP2001142774A (ja) * | 1999-11-11 | 2001-05-25 | Toshiba Corp | メモリカード及び同カードに適用されるアドレス変換方法 |
JP2003296188A (ja) * | 2002-03-18 | 2003-10-17 | Samsung Electro Mech Co Ltd | 高容量フラッシュメモリカードシステムにおけるデータ運営方法 |
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JP2010152517A (ja) * | 2008-12-24 | 2010-07-08 | Toshiba Corp | 不揮発性半導体メモリドライブ装置および不揮発性半導体メモリドライブ装置のアドレス管理方法 |
JP2012531655A (ja) * | 2009-11-04 | 2012-12-10 | 株式会社日立製作所 | フラッシュメモリモジュール |
CN109032958A (zh) * | 2017-06-12 | 2018-12-18 | 西部数据技术公司 | 用于在控制同步操作期间读取数据的方法和设备 |
JP2020123023A (ja) * | 2019-01-29 | 2020-08-13 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
CN100590608C (zh) | 2010-02-17 |
CN101185067A (zh) | 2008-05-21 |
US8051270B2 (en) | 2011-11-01 |
JPWO2006126445A1 (ja) | 2008-12-25 |
US20080168252A1 (en) | 2008-07-10 |
JP4884382B2 (ja) | 2012-02-29 |
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