WO2006123580A1

WO2006123580A1 - Nitride semiconductor device and method for manufacturing same

Info

Publication number: WO2006123580A1
Application number: PCT/JP2006/309550
Authority: WO
Inventors: Yoshiaki Hasegawa; Akihiko Ishibashi; Toshiya Yokogawa
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2005-05-19
Filing date: 2006-05-12
Publication date: 2006-11-23
Also published as: JP4842827B2; JPWO2006123580A1; CN1957510A; CN100477425C

Abstract

A nitride semiconductor device (100) is provided with an n-GaN substrate (1); a semiconductor multilayer structure which is formed on a main plane of the n-GaN substrate (1) and includes a p-type region and an n-type region; a p-side electrode (32) in contact with a part of the p-type region included in the semiconductor multilayer structure; and an n-side electrode (34) provided on a rear plane of the substrate (1). The rear plane of the substrate (1) includes a rough surface region (40a) and a flat surface region (40b), and the n-side electrode (34) covers at least a part of the rough surface region (40a).

Description

Specification

Nitride semiconductor device and manufacturing method thereof

Technical field

The present invention relates to a nitride semiconductor device and a method for manufacturing the same.

Background art

[0002] III-V nitride semiconductor materials such as gallium nitride (GaN) (Al Ga in N (0

x y Ι-χ-y

≤x≤l, 0≤y≤l)) is a key device for achieving ultra-high-density recording with optical disc devices, and is currently reaching a practical level. is there. Increasing the output of a blue-violet semiconductor laser is an indispensable technology not only for enabling high-speed writing of optical discs but also for developing new technical fields such as application to laser displays.

In recent years, a GaN substrate has been considered promising as a substrate necessary for manufacturing a nitride semiconductor device. The GaN substrate is superior in crystal lattice matching and heat dissipation compared to the sapphire substrate that has been used in the past. Another advantage is that the GaN substrate is conductive while the sapphire substrate is insulative. In other words, it is possible to adopt a structure in which electrodes are also formed on the back side of the GaN substrate and current flows in the direction across the GaN substrate. If an electrode is formed on the back surface of a conductive GaN substrate, it becomes possible to reduce the size (chip area) of each semiconductor device, and if the chip area is reduced, it can be fabricated from a single wafer. Since the total number of chips increases, manufacturing costs can be reduced.

[0004] A semiconductor laser in which an n-side electrode is formed on the back surface of a GaN substrate is disclosed in Patent Documents 1 to 3, for example.

Patent Document 1: Japanese Patent Laid-Open No. 2002-16312

Patent Document 2: JP 2004-71657 A

Patent Document 3: JP 2004-6718

Disclosure of the invention

Problems to be solved by the invention [0005] When the n-side electrode is formed on the back surface of the GaN substrate, there is a problem that the electrical contact characteristic is bad! Even in the prior art described in the above patent documents, contact characteristics are improved by forming irregularities on the back surface of the substrate.

[0006] However, the conventional method is insufficient in improving the contact resistance, and for the reason described in detail later, if a technology for forming irregularities on the back surface of the substrate is adopted at the mass production level, It was also found that there is a problem that it is difficult to manufacture a laser device with a high yield.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nitride semiconductor device that can be manufactured with high yield while improving the electrical contact characteristics on the back side of the substrate, and its It is to provide a manufacturing method.

Means for solving the problem

[0008] The nitride semiconductor device of the present invention includes a nitride-based semiconductor substrate containing an n-type impurity, a semiconductor multilayer structure formed on the main surface of the semiconductor substrate and including a p-type region and an n-type region, A nitride semiconductor device comprising: a p-side electrode that contacts a part of the p-type region included in the semiconductor multilayer structure; and an n-side electrode provided on a back surface of the semiconductor substrate, the semiconductor substrate The back surface includes a flat region and a rough surface region, and the n-side electrode covers at least a part of the rough surface region.

[0009] Preferably, according to the embodiment, the flat region on the back surface of the semiconductor substrate has a band shape having a width of 20 m or more, and is located around the rough surface region. ing.

[0010] Preferably, according to the embodiment, the contour of the contact region between the back surface of the semiconductor substrate and the n-side electrode is aligned with the boundary between the flat region and the rough surface region.

In a preferred embodiment, the rough surface region on the back surface of the semiconductor substrate is a polished surface or a clean surface.

In a preferred embodiment, the main surface of the semiconductor substrate is a + C polar surface.

In a preferred embodiment, the flat region on the back surface of the semiconductor substrate is a C polarity surface.

Preferably, in the embodiment, the rough surface region on the back surface of the semiconductor substrate has a plurality of concave portions or convex portions formed by etching. Preferably, according to the embodiment, a plurality of facets having different plane orientations are formed in the rough surface region on the back surface of the semiconductor substrate.

[0016] Preferably, in the embodiment, the uneven step of the rough surface region on the back surface of the semiconductor substrate is in a range of lOnm or more and the uneven step of the flat region is 10ηm or less. .

[0017] Preferably, in the embodiment, the n-side electrode covers the entire rough surface region on the back surface of the semiconductor substrate.

[0018] Preferably, according to the embodiment, the flat region on the back surface of the semiconductor substrate is disposed so as to contact the cleavage position.

[0019] Preferable! / According to the embodiment, the n-side electrode is made of Ti, Al, Pt, Au, Mo, Sn, In, Ni,

It has a layer formed of at least one metal or alloy selected from the group consisting of Cr, Nb, Ba, Ag, Rh, Ir, Ru, and Hf.

In a preferred embodiment, the n-side electrode has a contact resistivity of 5 × 10 ″ ⁴ Ω-cm ² or less.

[0021] The method for manufacturing a nitride semiconductor device of the present invention includes a step of preparing a nitride semiconductor substrate containing an n-type impurity, and a semiconductor multilayer structure including a p-type region and an n-type region. Forming on the main surface of the substrate; forming a P-side electrode in the p-type region included in the semiconductor multilayer structure; forming an n-side electrode on the back surface of the semiconductor substrate including a nitrogen surface; A method of manufacturing a nitride semiconductor device, comprising: forming a flat region and a rough surface region on the back surface before forming an n-side electrode on the back surface of the semiconductor substrate; and forming the n-side electrode. And cleaving the semiconductor substrate so that a cleavage plane passes through the flat region.

Preferably, according to the embodiment, after forming the flat region and the rough surface region on the back surface of the semiconductor substrate, and before forming the n-side electrode on the back surface of the semiconductor substrate, A step of reducing the carbon concentration on the back surface is performed.

[0023] Preferably, according to the embodiment, the step of reducing the carbon concentration includes a step of forming an insulating film on the back surface of the semiconductor substrate and a step of removing the insulating film.

[0024] Preferably, in the embodiment, the step of reducing the carbon concentration is performed in the semiconductor substrate. The method includes a step of depositing an oxide silicon film on the back surface and a step of removing the acid silicon film.

[0025] Preferably, in the embodiment, the step of forming the rough surface region includes a mask having an opening that exposes a portion of the back surface of the semiconductor substrate where the rough surface region is to be formed. Forming a layer on the back surface of the semiconductor substrate; and performing an etching process on a portion of the back surface of the semiconductor substrate where the rough surface region is to be formed.

[0026] Preferably, in the embodiment, the step of forming the n-side electrode includes a step of depositing a metal electrode layer on the back surface of the semiconductor substrate so as to cover the mask layer, and a step of forming the metal electrode layer. A step of patterning the metal electrode layer on the n-side electrode by removing a portion located on the mask layer together with the mask layer.

The invention's effect

[0027] According to the present invention, the effective area of the contact interface is increased by the rough surface area at the interface between the back surface of the nitride-based semiconductor substrate and the n-side electrode, and the carbon concentration at the contact interface is reduced. This also improves the contact characteristics of the n-side electrode. Furthermore, since the cleavage is facilitated, a semiconductor laser device can be manufactured with a high yield.

Brief Description of Drawings

FIG. 1 is a perspective view schematically showing a GaN crystal structure in a GaN substrate.

FIG. 2 is a cross-sectional view showing a first embodiment of a nitride semiconductor device according to the present invention.

FIG. 3 (a) is a plan view showing a part on the upper surface side of the nitride semiconductor substrate in Embodiment 1, and FIG. 3 (b) is a plan view showing the back surface side of the nitride semiconductor substrate.

FIG. 4 is a cross-sectional view showing the main part of the nitride semiconductor device before cleavage in Embodiment 1.

FIG. 5 (a) and (b) are perspective views schematically showing primary cleavage.

FIG. 6 is a cross-sectional view showing another embodiment of the nitride semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing still another embodiment of a nitride semiconductor device according to the present invention. Explanation of symbols

[0029] 10 n-type GaN substrate 10a no ^ ¹ ~ "

12 n-type GaN layer

14 n-type AlGaN cladding layer

16 GaN light guide layer

18 InGaN multiple quantum well layers

20 InGaN interlayer

22 p-type AlGaN cap layer

24 p-type GaN optical guide layer

26 p-type AlGaN cladding layer

28 p-type GaN contact layer

30 SiO layer

2

32 P side electrode (PdZPt)

34 n-side electrode (TiZPtZAu)

36 SiO layer

2

40a Rough surface area on the back of the substrate

40b Flat area on the back of the substrate

50 cleavage guide

100 Semiconductor laminated structure

BEST MODE FOR CARRYING OUT THE INVENTION

[0030] The inventor of the present application has attributed the cause of the high electrical external resistance of the n-side electrode formed on the bottom surface of the nitride semiconductor substrate to carbon (C) existing on the back surface of the nitride semiconductor substrate. In addition, the present inventors have found out that it is effective to reduce the contact resistance by reducing the carbon concentration at the interface between the back surface of the nitride semiconductor substrate and the n-side electrode. .

[0031] As shown in Fig. 1, the GaN crystal is composed of Ga atoms and N nuclear power, and has a hexagonal crystal structure. The surface (top surface) of the GaN substrate on which epitaxial growth of various semiconductor layers is performed is a surface (Ga surface or + C polar surface) in which Ga atoms are arranged in layers. On the other hand, the back side of the GaN substrate is a surface (nitrogen surface or Is —C polarity plane). The nitrogen surface (hereinafter referred to as the “N surface”) has a property that always appears on the back surface of the GaN substrate even when the GaN substrate is polished from the back surface side and the substrate thickness is reduced to an arbitrary thickness. ing. Note that even in a general nitride semiconductor substrate in which Ga atoms of the GaN substrate are substituted with A1 atoms or In atoms at some sites, the back surface of the substrate is the N plane as described above.

According to the study of the present inventor, the N surface of a nitride semiconductor substrate such as a GaN substrate adsorbs carbon and immediately forms an electrode on the N surface, and then the carbon stabilizes at the interface between the N surface and the electrode. Continue to exist. This carbon exists stably at the interface where it does not diffuse to the surroundings even by heat treatment after electrode formation, and functions as an electrical barrier at the contact interface. If the carbon existing on the backside of the substrate can be properly eliminated before the n-side electrode is formed, the electrical barrier existing at the contact interface can be reduced, and the contact characteristics of the n-side electrode can be significantly improved.

When irregularities are formed on the back surface of the GaN substrate and roughened, the ratio (area ratio) of the N surface occupying the back surface of the substrate can be reduced. However, if irregularities are formed on the back surface of the substrate by the conventional technology, there is a problem that it is difficult to perform “cleavage” of the GaN substrate with a high yield. Hereinafter, this problem will be described.

[0034] Since the GaN substrate has a hexagonal crystal structure, the process of separating the individual semiconductor chips (having a substantially rectangular parallelepiped shape! / Spinning) by “cleavage” of the GaN substrate is performed with a high yield. It is very difficult to do. In order to perform this cleavage with a high yield, a plurality of “concave arrangements (hereinafter referred to as“ cleavage guides ”)” are formed on the cleave line on the upper surface side of the GaN substrate, and “cleave guides” are formed from the back side of the substrate. It is effective to adopt a method of primary cleavage along

[0035] Since the GaN substrate has translucency, the position of the “cleavage guide” formed on the upper surface side of the substrate is originally observed by the force on the back surface side of the substrate, and primary cleavage is performed along the cleavage guide. Is possible. However, if unevenness is formed on the entire back surface of the GaN substrate, irregular reflection occurs on the back surface of the substrate, making it impossible to observe the cleavage guide from the back surface of the substrate. For this reason, when unevenness is formed on the back surface of the GaN substrate according to the conventional technology, the cleavage process cannot be performed with a high yield.

Therefore, in the present invention, instead of forming unevenness on the entire back surface of the nitride semiconductor substrate, unevenness is formed only on a specific region, so that the back surface of the substrate is roughened with a flat region (window region). It is divided into surface areas. The n-side electrode is formed so as to cover at least a part of the rough surface region.

Note that the “flat region” in this specification is a relatively smooth surface as compared to the “rough surface region”. More specifically, the “flat region” is a portion of the back surface of the substrate that is kept smooth by polishing, and means a region that is not intentionally uneven. However, the “flat region” may be subjected to a cleaning process (cleaning process) after polishing polishing. On the other hand, the “rough surface region” is a portion of the back surface of the substrate where irregularities are intentionally formed by a process such as etching. If the etching for roughening is anisotropic etching with different etching rates depending on the crystal plane orientation, facets having a plurality of different plane orientations are formed in the roughened area.

[0038] According to the present invention, irregular reflection does not occur in the flat region on the back surface of the substrate. Therefore, when the "cleavage guide" is formed on the upper surface side of the substrate, the "cleavage guide" is observed from the back surface side of the substrate and appropriately primary. Cleavage can be performed.

Hereinafter, a method for manufacturing a nitride semiconductor device according to the present invention will be described.

First, in the present invention, a semiconductor multilayer structure is formed on the surface (Ga surface) of a nitride semiconductor substrate by a known semiconductor growth method using an epitaxy growth technique. The semiconductor stacked structure includes a p-type region and an n-type region. When a light emitting device such as a semiconductor laser is manufactured, the semiconductor stacked structure includes a double hetero structure and a structure for confining light and current in a certain space.

[0041] After forming the P-side electrode in electrical contact with the p-type region in the semiconductor multilayer structure on the surface side of the nitride substrate, before forming the n-side electrode on the back surface of the nitride semiconductor substrate, In the present invention, a special process, that is, a step of forming a rough surface region in a predetermined region on the back surface of the nitride semiconductor substrate is performed. This step can be performed by covering a part of the back surface of the substrate with a mask layer and then etching a region not covered with the mask layer.

Preferably, according to the embodiment, after the rough surface region and the flat region are formed on the back surface of the substrate, surface treatment for reducing the carbon concentration is performed. This treatment includes a step of covering the back surface of the nitride semiconductor substrate with a layer of deposit, and a step of removing this layer by etching. More preferably, after depositing a silicon dioxide (SiO 2) film on the back side of the nitride semiconductor substrate, this Si o Remove the membrane from the back. According to the experiments of the present inventor, the above treatment is performed on the back surface of the substrate.

2

By performing the process (deposition and removal of SiO film), the concentration of carbon existing on the back of the substrate is greatly increased.

2

Therefore, the effect of reducing the contact resistance can be obtained.

[0043] When the n-side electrode is formed on the back surface of the nitride semiconductor substrate after performing the above steps (back surface treatment), the effective contact area increases at the interface between the substrate back surface and the n-side electrode, and the interface The carbon concentration in can be reduced below the detection limit of the measuring device. As a result, the contact resistance is greatly reduced.

In a preferred embodiment, a plurality of recesses (cleavage guides) that define cleavage lines are formed in the upper part of the semiconductor multilayer structure provided on the substrate main surface side. Such a recess can be easily formed by, for example, a scribe technique and an etching technique.

[0045] After the n-side electrode is formed on the back surface of the substrate, the cleaving guide is observed through the flat region existing at a position not covered by the n-side electrode, and the primary cleavage is performed from the back surface of the substrate along the cleavage guide. Is performed to divide the nitride semiconductor substrate into a plurality of bars. The individual semiconductor laser chips can then be separated from each bar by performing secondary cleavage for each bar.

[Embodiment 1]

Hereinafter, a first embodiment of a nitride semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to the drawings.

[0047] First, reference is made to FIG. FIG. 2 schematically shows a cross section of the nitride semiconductor device of this embodiment, that is, a GaN-based semiconductor laser. The element cross section shown in the figure is a plane parallel to the resonator end face, and the resonator length direction is orthogonal to the cross section.

[0048] The semiconductor laser of this embodiment includes an n-type GaN substrate doped with an n-type impurity (thickness: about

100 μm) 10 and a semiconductor multilayer structure 100 provided on the surface (Ga surface) of the n-type GaN substrate 10.

[0049] The semiconductor multilayer structure 100 includes an n-type GaN layer 12, an n-type AlGaN cladding layer 14, a GaN light guide layer 16, an InGaN multiple quantum well layer 18, an InGaN intermediate layer 20, a p-type AlGaN cap layer 22, and a p-type GaN. Includes light guide layer 24, p-type AlGaN cladding layer 26, and p-type GaN contact layer 28 It is out.

[0050] The impurity concentration (dope concentration) and thickness of each semiconductor layer included in the semiconductor multilayer structure 100 in the present embodiment are as shown in Table 1 below.

[0051] [Table 1]

Note that the impurities, impurity concentration, and thickness of each semiconductor layer shown in Table 1 are merely examples, and do not limit the present invention.

[0053] In the semiconductor multilayer structure 100, the p-type GaN contact layer 28 and the p-type AIGaN cladding layer 26 are processed into a ridge stripe shape extending along the resonator length direction. The width of the ridge stripe is, for example, about 1.5 m, and the resonator length is, for example, 600 m. The chip width (element size in the direction parallel to each semiconductor layer in FIG. 5) is, for example, 200 m.

[0054] Of the upper surface of the semiconductor multilayer structure 100, the portion excluding the upper surface of the ridge stripe is the SiO layer 3

2

The upper surface of the ridge stripe is exposed at the center of the SiO layer 30.

2

A stripe-shaped opening to be formed is formed. SiO

The surface of the p-type GaN contact layer 28 is in contact with the p-side electrode (Pd / Pt) 32 through the opening of the two layers 30.

[0055] The back surface of the n-type GaN substrate 10 is divided into a rough surface region 40a where unevenness is formed and a flat region 40b where unevenness is not formed. The n-side electrode (TiZPtZAu) 34 is provided so as to cover the rough surface region. The uneven step in the rough surface area 40a is, for example, in the range of 10 nm or more (preferably 50 nm or more) and 1 μm or less. The uneven step in the flat region 40b is in the range of, for example, not less than 1 nm and not more than 10 nm. In the present embodiment, the carbon concentration at the interface between the back surface of the n-type GaN substrate 10 and the n-side electrode 34 is reduced to 5 atomic% or less, more specifically to 2 atomic% or less.

Hereinafter, a preferred embodiment of a method for manufacturing a nitride semiconductor device according to this embodiment will be described.

[0058] First, an n-type GaN substrate 10 prepared by a known method is prepared. The n-type GaN substrate 10 has a thickness of about 400 m, for example. The surface of the n-type GaN substrate 10 is planarized by a polishing cage.

Next, the semiconductor multilayer structure 100 is formed on the surface of the n-type GaN substrate 10. The semiconductor stacked structure 100 can be formed by a known epitaxial growth technique. For example, each semiconductor layer is grown as follows.

First, the n-type GaN substrate 10 is inserted into the chamber of a metal organic chemical vapor deposition (MOVPE) apparatus. Thereafter, the surface of the n-type GaN substrate 10 is subjected to a heat treatment (thermal cleaning) of about 500 to L 100 ° C. This heat treatment is performed, for example, at 750 ° C for 1 minute or longer, preferably 5 minutes or longer. During this heat treatment, gases containing nitrogen atoms (N) (N, NH, hydra

2 3 gin) is preferably flowed into the chamber.

[0061] Thereafter, the temperature of the reactor is controlled to about 1000 ° C, and trimethylgallium (TMG) and ammonia (NH3) gases as source gases and carrier gases hydrogen and nitrogen are simultaneously supplied.

Three

In addition, silane (SiH) gas is supplied as an n-type dopant, and the thickness is about 1 μm.

Four

An n-type GaN layer 12 having an object concentration of about 5 × 10 ¹⁷ cm ³ is grown.

Next, while supplying trimethylaluminum (TMA), an n-type AlGaN cladding layer 14 having an Al Ga N force of about 1.5 m in thickness and Si impurity concentration of about 5 × 10 ¹⁷ cm- ³ is formed. Grow

0.05 0.95

. Then, after growing a GaN optical guide layer16 of GaN with a thickness of about 120 nm, the temperature is lowered to about 800 ° C., the carrier gas is changed to nitrogen, and trimethylindium (TMI) and TMG are supplied. A quantum well (3 layers) with an InGaN force of about 3 nm and a thickness of about 9 n

0.10 0.90

A multiple quantum well active layer 18 consisting of m InGaN barrier layers (two layers) is grown. That

0.02 0.98

Thereafter, an InGaN intermediate layer 20 made of InGaN is grown. InGaN intermediate layer 20

0.01 0.99

The p-type dopant (Mg) diffusion from the p-type semiconductor layer formed on the active layer 18 to the active layer 18 is greatly suppressed, and the active layer 18 can be maintained in high quality even after crystal growth. [0063] Next, the temperature in the reactor is again raised to about 1000 ° C, hydrogen is introduced into the carrier gas, and p-type dopant biscyclopentagel magnesium (Cp Mg) Ga

Al Ga N with a film thickness of about 20 nm and an Mg impurity concentration of about l X 10 ¹⁹ cm— ³

P-type AlGaN cap layer 22 with 0.20 0.80 force is grown.

Next, a second GaN optical guide layer 24 having a thickness of about 20 nm and an Mg impurity concentration of about 1 × 10 ¹⁹ cm ^{−3 and having} a p-type GaN force is grown. Thereafter, a p-type AlGaN cladding layer 26 made of AlGaN having a thickness of about 0.5 m and an impurity concentration of about 1 × 10 ¹⁹ cm− ³ is grown. Finally, thick

0.05 0.95

A p-type GaN contact layer 28 having a thickness of about 0.1 μm and an Mg impurity concentration of about 1 × 10 ^2Q cm— ³ is grown.

Next, with reference to FIG. 3A, a process of forming a plurality of recesses (cleavage guides) 50 on the upper surface of the semiconductor multilayer structure will be described. FIG. 3 (a) is a plan view of a part of the semiconductor substrate as seen from the upper surface side. The rows of cleavage guides 50 are periodically arranged on the line to be cleaved, and function so that cleavage occurs along that line. Each recess functioning as the cleavage guide 50 has, for example, a depth of 1 to 20 μm, a width of 1 to 5 μm, and a length of 1 to 40 μm, and is formed by a scribe process and an etching process. obtain. In the example shown in FIG. 3 (a), the arrangement pitch of the recesses corresponds to the arrangement pitch of the semiconductor laser element regions on the substrate, but if the cleavage can be guided in an appropriate direction, the recesses are arranged. The shape and the size of the array pitch are arbitrary. However, it is preferable that the recess has a rhombus shape having an acute angle in the “cleavage direction” when viewed from the upper surface side of the substrate, and a cross-sectional shape perpendicular to the substrate is a weight. This is because, when the row of concave portions having such a shape is used as a cleavage guide, the cleavage of the substrate back side force also proceeds straight along the row of concave portions, and the cleavage yield is improved immediately.

Thereafter, the n-type GaN substrate 10 is polished from the back side, and the thickness of the n-type GaN substrate 10 is reduced to about 100 μm. Next, as shown in FIG. 3 (b), a mask layer 42 having a lattice shape is formed on the back surface of the n-type GaN substrate 10, and the region that should be covered with the mask layer 42 is exposed to an etching solution. As a result, a large number of etch pits or protrusions are formed to roughen the surface. The etch ing liquid, for example, using a Mizusani匕potassium (KOH) or hot phosphoric acid, 10-6 0 minutes at room temperature, by etching the above number density 5 X 10 ⁶ number ZCM ^2, the depth 10 ~: LOO Onm pits can be formed. The formation of the roughened region (rough surface region 40a) may be performed by dry etching instead of the above wet etching or in combination with wet etching.

[0067] The mask layer 42 has a plurality of openings that define the position and shape of the rough surface region 40a, and can be produced, for example, by exposing and developing a resist film. The portion of the back surface of the n-type GaN substrate 10 that is covered with the mask layer 42 corresponds to a portion where primary cleavage or secondary cleavage is performed. Etch pits are not formed in the area of the back surface of the n-type GaN substrate 10 covered with the mask layer 42, and it functions as a flat area 40b.

In the present embodiment, since the rough surface region 40a is formed in the region where the n-side electrode 34 is to be formed on the back surface of the substrate by the above method, the area ratio of the N surface at the contact interface is reduced. , The surface area increases. This has the effect of reducing the carbon concentration at the contact interface, and also increases the effective area of the contact, making it possible to reduce the contact resistance.

[0069] After that, in this embodiment, the thickness of the back surface (polished surface) of the n-type GaN substrate 10 is about 0.5 to 1. by the ECR sputtering method for the purpose of further reducing the contact resistance. SiO

2 Deposit a film. By etching this SiO film, from the back side of the n-type GaN substrate 10

2

The SiO film is removed. The SiO film has at least an n-side current on the back surface of the n-type GaN substrate 10.

twenty two

The pole needs to be completely removed from the area where it is to be formed. In this embodiment, SiO

2 Remove the membrane with hydrofluoric acid. Etchant used to remove the SiO film is hydrofluoric acid.

2

It is not limited and other kinds of etchants may be used. The removal of the SiO film

2

It is not limited to etching, and dry etching or a combination of wet etching and dry etching may be used. Even if irregularities are formed on the back surface of the substrate, a part of the N surface may remain in the rough surface region 42, and carbon may be adsorbed on such an N surface, which may deteriorate the contact characteristics. For this reason, it is preferable to perform the above-mentioned back surface treatment (carbon reduction treatment).

Next, each metal layer of TiZPtZAu is continuously deposited on the back surface of the n-type GaN substrate 10 in this order from the substrate side. After that, by removing the mask layer 42, the position on the mask layer 42 is increased. The lift-off of the metal layer to be placed is performed, and the n-side electrode 34 is also formed on the metal layer force located on the rough surface region 40a. After this, sintering is performed in a nitrogen atmosphere (about 300 ° C). This sintering process has the effect of further reducing the contact resistance of the n-side electrode 34. According to this embodiment, it is possible and child contact resistivity of the n-side electrode 34 below 5 X 10- ⁴ Ω 'cm.

According to the present embodiment, since the n-side electrode 34 is patterned using the mask layer 42 used for forming the rough surface region 40a, the back surface of the n-type GaN substrate 10, the n-side electrode 34, The contour of the contact region is aligned with the boundary between the rough surface region 40a and the flat region 40b.

FIG. 4 is a cross-sectional view showing a part of the n-side GaN substrate 10 at the stage where the n-side electrode 34 is formed. As shown in FIG. 4, the unevenness formed by etching is formed on a part (rough surface region) of the back surface of the substrate. Such irregularities also constitute facet surface forces where crystal planes other than the (000-1) plane are exposed. The rough surface region in this embodiment has a plurality of protrusions formed by etching, and each protrusion (height: 10 to: LOOOnm) is a polygonal pyramid type or a polygonal frustum type, and its surface Consists of facet faces other than the (000-1) face.

Next, primary cleavage is performed along the broken line shown in FIG. FIGS. 5 (a) and 5 (b) schematically show the process of forming the semiconductor substrate force bar 10a by primary cleavage. The semiconductor laser shown in FIG. 2 can be obtained by performing secondary cleavage on the bar 10a obtained by primary cleavage. The direction of secondary cleavage is orthogonal to the direction of primary cleavage.

[0074] According to the present embodiment, since the n-side electrode having the rough surface region 40a as the contact surface is formed, it is possible to increase the effective area of the contact surface and reduce the carbon concentration in the contact surface. Therefore, the contact resistance of the n-side electrode can be reduced. Further, as shown in FIG. 3 (b), the cleavage guide can be observed from the back side of the substrate, so that the cleavage can be performed with a high yield. In addition, the flat region 40b on the back surface of the substrate in each semiconductor laser element in which the substrate force is also divided by cleavage is disposed so as to contact the cleavage position.

[0075] Flatness on the substrate back surface of each semiconductor laser element divided from the substrate by cleavage The region 40b has a band shape having a width of 20 / zm or more, and is located around the rough surface region 40a (see FIG. 3B).

[0076] The layout of the flat region 40b on the back surface of the substrate is not limited to the example shown in FIG. The flat region 40b may be formed at a position where the cleavage guide 50 can be observed from the back side of the substrate.

[0077] (Embodiment 2)

With reference to FIGS. 6 and 7, another embodiment of the nitride semiconductor device according to the present invention will be described.

The embodiment shown in FIG. 6 has the same configuration as the semiconductor laser device in Embodiment 1 except that the flat region on the back surface of the n-type GaN substrate is covered with an insulating layer 36.

[0079] As shown in FIG. 6, an insulating layer 36 such as a SiO film may remain on a part of the back surface of the substrate.

2

V ヽ. The region force where the n-side electrode 34 should be in contact with the backside of the substrate is a force that needs to remove the insulating film. Even if a part of the insulating film remains around the n-side electrode 34 as the insulating layer 36, the contour There is no effect on the tatoo characteristics. Also, leave the insulating layer 34 with strong force such as SiO on the back of the substrate.

2

In this case, the insulating layer 34 absorbs light (stray light) leaking from the active layer 18 to the substrate 10, and an effect of reducing noise can be obtained.

The embodiment shown in FIG. 7 has the same configuration as the semiconductor laser device of Embodiment 1 except that the back surface of the substrate is inclined. As shown in FIG. 7, the entire back surface of the substrate may be inclined from the N surface. This can be realized by inclining and fixing the back surface of the substrate with respect to the polishing board during polishing of the back surface of the substrate.

[0081] According to the present invention, since the contact resistance at the interface between the back surface of the substrate and the n-side electrode is reduced, there is a way to use various kinds of powerful metals as materials for the n-electrode. be opened. That is, metals or alloys such as Ti, Al, Pt, Au, Mo, Sn, In, Ni, Cr, Nb, Ba, Ag, Rh, Ir, Ru, or Hf should be used as the material for the n-side electrode. It becomes possible.

In each of the above embodiments, a GaN substrate is used as the nitride semiconductor substrate. However, the nitride semiconductor substrate is not limited to GaN, and is a substrate formed of AlGaN, InGaN, or the like. May be. Further, the substrate may be an off-substrate.

Industrial applicability

The present invention contributes to mass production of highly reliable nitride semiconductor lasers and the like in order to improve the n-side electrode contact characteristics in nitride semiconductor devices that are expected to be used as short-wavelength light sources and high breakdown voltage devices. it can.

Claims

The scope of the claims

[1] a nitride-based semiconductor substrate containing an n-type impurity;

A semiconductor multilayer structure formed on a main surface of the semiconductor substrate and including a p-type region and an n-type region;

A p-side electrode in contact with a part of the p-type region included in the semiconductor multilayer structure; an n-side electrode provided on the back surface of the semiconductor substrate;

A nitride semiconductor device comprising:

The back surface of the semiconductor substrate includes a flat region and a rough surface region,

The n-side electrode is a nitride semiconductor device that covers at least a part of the rough surface region.

[2] The flat region on the back surface of the semiconductor substrate has a strip shape having a width of 20 μm or more, and is located around the rough surface region. Nitride semiconductor device.

[3] The nitride semiconductor device according to [1], wherein a contour of a contact region between the back surface of the semiconductor substrate and the n-side electrode is aligned with a boundary between the flat region and the rough surface region. .

4. The nitride semiconductor device according to claim 1, wherein the rough surface region on the back surface of the semiconductor substrate is a polished surface or a clean surface.

5. The nitride semiconductor device according to claim 1, wherein the main surface of the semiconductor substrate is a + C polarity surface.

6. The nitride semiconductor device according to claim 1, wherein the flat region on the back surface of the semiconductor substrate is a C polarity surface.

7. The nitride semiconductor device according to claim 1, wherein the rough surface region on the back surface of the semiconductor substrate has a plurality of concave portions or convex portions formed by etching.

8. The nitride semiconductor device according to claim 1, wherein a plurality of facets having different plane orientations are formed in the rough surface region on the back surface of the semiconductor substrate.

9. The nitride semiconductor according to claim 1, wherein the uneven step of the rough surface region on the back surface of the semiconductor substrate is in a range of 1 Onm or more and 1 μm or less, and the uneven step of the flat region is 1Onm or less. apparatus.

[10] The n-side electrode covers the entire rough surface region on the back surface of the semiconductor substrate. The nitride semiconductor device according to claim 1.

11. The nitride semiconductor device according to claim 1, wherein the flat region on the back surface of the semiconductor substrate is disposed so as to be in contact with a cleavage position.

[12] The n-side electrode is selected from the group consisting of Ti, Al, Pt ゝ Au, Mo, Sn ゝ In, Ni ゝ Cr ゝ Nb ゝ Ba ゝ Ag, Rh, Ir, Ru, and Hf. 2. The nitride semiconductor device according to claim 1, further comprising a layer formed of at least one kind of metal or alloy.

13. The nitride semiconductor device according to claim 1, wherein a contact resistivity of the n-side electrode is 5 × 10 ″ ⁴ Ω′cm ² or less.

14. The nitride semiconductor device according to claim 1, wherein the back surface of the semiconductor substrate has a polishing surface force.

[15] providing a nitride semiconductor substrate containing an n-type impurity;

Forming a semiconductor multilayer structure including a P-type region and an n-type region on the main surface of the semiconductor substrate;

Forming a p-side electrode in the p-type region included in the semiconductor multilayer structure; forming an n-side electrode on the back surface of the semiconductor substrate including a nitrogen surface;

A method of manufacturing a nitride semiconductor device comprising:

Forming a flat region and a rough surface region on the back surface before forming the n-side electrode on the back surface of the semiconductor substrate;

Cleaving the semiconductor substrate so that a cleaved surface passes through the flat region after forming the n-side electrode;

A method for manufacturing a nitride semiconductor device, comprising:

[16] After the flat region and the rough surface region are formed on the back surface of the semiconductor substrate, and before the n-side electrode is formed on the back surface of the semiconductor substrate, a step of reducing the carbon concentration on the back surface of the semiconductor substrate is performed. The method for manufacturing a nitride semiconductor device according to claim 15.

[17] The step of reducing the carbon concentration comprises:

Forming an insulating film on the back surface of the semiconductor substrate;

Removing the insulating film;

The method for manufacturing a nitride semiconductor device according to claim 15, comprising:

[18] The step of reducing the carbon concentration comprises:

Depositing a silicon oxide film on the back surface of the semiconductor substrate;

Removing the silicon oxide film;

[19] The step of forming the rough surface region includes:

Forming a mask layer on the back surface of the semiconductor substrate, the mask layer having an opening that exposes a portion of the back surface of the semiconductor substrate where the rough surface region is to be formed;

Etching the portion of the back surface of the semiconductor substrate where the rough surface region is to be formed; and

[20] The step of forming the n-side electrode includes:

Depositing a metal electrode layer on the back surface of the semiconductor substrate so as to cover the mask layer; and removing the portion of the metal electrode layer located on the mask layer together with the mask layer, 20. The method for manufacturing a nitride semiconductor device according to claim 19, comprising: patterning an electrode layer on the n-side electrode.