WO2006114825A1 - Procede de fabrication d’un dispositif semi-conducteur - Google Patents

Procede de fabrication d’un dispositif semi-conducteur Download PDF

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Publication number
WO2006114825A1
WO2006114825A1 PCT/JP2005/006741 JP2005006741W WO2006114825A1 WO 2006114825 A1 WO2006114825 A1 WO 2006114825A1 JP 2005006741 W JP2005006741 W JP 2005006741W WO 2006114825 A1 WO2006114825 A1 WO 2006114825A1
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WO
WIPO (PCT)
Prior art keywords
conductor
semiconductor chip
solder
sealing resin
semiconductor device
Prior art date
Application number
PCT/JP2005/006741
Other languages
English (en)
Japanese (ja)
Inventor
Katsuo Arai
Takuya Nakajo
Keiichi Okawa
Akiko Matsuyama
Hidemasa Kagii
Hiroshi Sato
Hiroyuki Nakamura
Hiroi Oka
Akira Muto
Ichio Shimizu
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2005/006741 priority Critical patent/WO2006114825A1/fr
Publication of WO2006114825A1 publication Critical patent/WO2006114825A1/fr

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01075—Rhenium [Re]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a manufacturing technique for a semiconductor device in the form of a resin-sealed semiconductor package.
  • Various semiconductor packages are used, and there is a resin-encapsulated semiconductor package in which a high-power semiconductor chip is encapsulated with an encapsulated resin portion.
  • the semiconductor chip is sealed in the encapsulated resin part, so that the reliability of the semiconductor chip can be improved. Further, by exposing the terminals on the back surface of the sealing resin portion, high density surface mounting of the resin sealing type semiconductor package becomes possible.
  • Patent Document 1 discloses a surface-mount type semiconductor device having a mounting surface bonded to a mounting substrate, and includes a lead frame, a semiconductor chip, and a semiconductor chip.
  • the mounting surface has a tip surface of an electrode terminal drawn from the semiconductor chip through a lead frame and a surface of two or more electrodes provided on the semiconductor chip.
  • a technique for providing a semiconductor device exposed in a planar shape is described.
  • Patent Document 2 In Japanese Patent Application Laid-Open No. 2000-243880 (Patent Document 2), a semiconductor pellet is fixed on an island, a first post electrode is bonded to an electrode pad of the semiconductor pellet, and a second portion is attached to an extended portion of the island. A technique is described in which the post electrodes of the first and second post electrodes are exposed on the surface of the resin layer and are used as external connection terminals by adhering the post electrode and covering the whole with a resin layer. ing.
  • Patent Document 3 In Japanese Patent Application Laid-Open No. 2000-243887 (Patent Document 3), a semiconductor pellet is fixed on an island, a post electrode is bonded to an electrode pad of the semiconductor pellet, and the extended portion of the island is the same as the post electrode. Describes technology to bend to a certain height and cover the entire surface with a resin layer, so that the head of the post electrode and the head of the extension are exposed on the surface of the resin layer and become a terminal for external connection. Has been. Patent Document 1: Japanese Unexamined Patent Publication No. 2003-86737
  • Patent Document 2 Japanese Patent Laid-Open No. 2000-243880
  • Patent Document 3 Japanese Patent Laid-Open No. 2000-243887
  • the surface of the resin-encapsulated semiconductor package can be mounted by exposing the terminals on the lower surface (back surface) of the encapsulated resin portion. Furthermore, by exposing the terminals on both the upper and lower surfaces of the sealing resin portion only on the lower surface of the sealing resin portion, the heat dissipation of the resin-sealed semiconductor package can be improved. Also, the sealing resin part is
  • It can be formed by injecting a sealing resin material into the cavity of the upper mold and the lower mold in the molding step and hardening.
  • the upper and lower molds of the upper and lower molds may be There is a possibility that strong pressure is applied to the semiconductor chip from above and below via the lower terminal. If vertical force pressure is applied to the semiconductor chip, the semiconductor chip may crack. This reduces the manufacturing yield of the semiconductor device in the form of a resin-encapsulated semiconductor package.
  • the present invention provides first and second conductor portions on the first and second main surfaces of a semiconductor chip when manufacturing a semiconductor device in the form of a resin-sealed semiconductor package having exposed conductors on both upper and lower surfaces.
  • the first and second conductor portions and the semiconductor chip are placed in the cavity formed by the first mold and the second mold, and the solder is melted.
  • the first mold is fixed to the second mold, and a sealing resin material is introduced into the cavity to seal the semiconductor chip and a part of the first and second conductor portions. It forms the anti-grease part.
  • the first and second main surfaces of the semiconductor chip are provided with the first and second main surfaces.
  • the first and second conductor portions of the conductor member are joined via solder, respectively, and the first and second conductor portions and the semiconductor chip are disposed in the mold cavity.
  • the second conductor member is disposed, the first and second conductor members are fixed to the mold in a state where the solder is melted, and a sealing resin material is introduced into the cavity to thereby form the semiconductor A sealing resin portion for sealing the chip and a part of the first and second conductor portions is formed.
  • the present invention provides a first and second conductor on the first and second main surfaces of a semiconductor chip when manufacturing a semiconductor device in the form of a resin-encapsulated semiconductor package having exposed conductors on both upper and lower surfaces.
  • Each part is disposed via solder, and solder reflow processing is performed while fixing the first conductor part and the second conductor part, and the solder is applied to the first and second main surfaces of the semiconductor chip.
  • the first and second conductor portions are joined to each other, the first and second conductor portions and the semiconductor chip are arranged in a mold cavity, and a sealing resin material is placed in the cavity. To form a sealing resin portion that seals the semiconductor chip and a part of the first and second conductor portions.
  • the first and second main surfaces of the semiconductor chip are provided with the first and second main surfaces.
  • the first and second conductor portions of the conductor member are arranged via solder, and a solder reflow process is performed while fixing the first conductor member and the second conductor member.
  • the first and second conductor portions of the first and second conductor members are joined to the first and second main surfaces of the first and second main surfaces via the solder, and the first and second conductor portions and the semiconductor
  • the first and second conductor members are fixed to the mold so that the chip is disposed in the mold cavity, and a sealing resin material is introduced into the cavity to introduce the semiconductor chip. And a sealing resin portion for sealing the first and second conductor portions To do.
  • the first and second conductors are provided on the first and second main surfaces of the semiconductor chip. Parts are joined to each other, the second conductor part is fixed to the first member, a frame body is disposed on the first member so as to surround the semiconductor chip, and a sealing resin material is placed in the frame body. It is introduced and cured to form a sealing resin portion that seals the semiconductor chip and part of the first and second conductor portions.
  • the first and second main surfaces of the semiconductor chip are provided with the first and second main surfaces.
  • the first and second conductor portions of the conductor member are joined to each other, the second conductor member is fixed to the first member, and a frame body is disposed on the first member so as to surround the periphery of the semiconductor chip.
  • a sealing resin material is introduced into the frame body and cured to form a sealing resin part that seals the semiconductor chip and a part of the first and second conductor parts. .
  • the manufacturing yield of the semiconductor device can be improved.
  • the heat dissipation characteristics of the semiconductor device can be improved.
  • FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a bottom view of the semiconductor device of FIG.
  • FIG. 3 is a side view of the semiconductor device of FIG. 1.
  • FIG. 4 is a cross-sectional view of the semiconductor device of FIG.
  • FIG. 5 is a cross-sectional view of the semiconductor device of FIG.
  • FIG. 6 is a plan view showing an example of a chip layout of a semiconductor chip used in the semiconductor device of FIG.
  • FIG. 7 is a plan view showing an example of a chip layout of a semiconductor chip used in the semiconductor device of FIG.
  • FIG. 8 is a process flow diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
  • FIG. 9 is a process flow diagram showing a molding process.
  • FIG. 10 is a graph showing mold temperature and mold pressure in a molding process.
  • FIG. 11 is a fragmentary cross-sectional view of the semiconductor chip during its manufacturing step.
  • FIG. 12 is a fragmentary cross-sectional view of the semiconductor chip during a manufacturing step following that of FIG. 11;
  • FIG. 13 is a plan view of relevant parts in the process of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 14 is an essential part cross sectional view of the same semiconductor device as in FIG. 13 during a manufacturing step
  • FIG. 15 is a substantial part plan view of the semiconductor device in manufacturing process, following FIG. 13;
  • FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step
  • FIG. 17 is a substantial part plan view of the semiconductor device in manufacturing process, following FIG. 15;
  • FIG. 18 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 17 during the manufacturing step;
  • FIG. 19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;
  • FIG. 20 is a fragmentary cross-sectional view of the semiconductor device during the manufacturing step following that of FIG. 19;
  • FIG. 21 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 20;
  • FIG. 22 is a fragmentary cross-sectional view of the semiconductor device during the manufacturing step following that of FIG. 21; 23] FIG. 23 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 22;
  • FIG. 24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23;
  • FIG. 25 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 24;
  • FIG. 26 is a fragmentary plan view of the same semiconductor device as in FIG. 25 in manufacturing process.
  • FIG. 26 is a fragmentary plan view of the same semiconductor device as in FIG. 25 in manufacturing process.
  • FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 25;
  • FIG. 29 is a cross-sectional view showing a state where a plurality of semiconductor devices are mounted on a mounting substrate.
  • FIG. 30 is a top view of FIG. 29.
  • FIG. 31 is an explanatory diagram of a molding process of a comparative example.
  • FIG. 32 A perspective view showing the appearance of a mold used in the manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 33 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process thereof.
  • FIG. 34 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 33;
  • FIG. 35 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 34;
  • FIG. 36 is a process flow diagram showing a manufacturing process for a semiconductor device in another embodiment of the invention.
  • FIG. 37 is a plan view of the essential part in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 38 is an essential part cross sectional view of the same semiconductor device as in FIG. 37 during a manufacturing step
  • FIG. 39 is a plan view of a principal part in the semiconductor device manufacturing process subsequent to FIG. 37;
  • FIG. 40 is an essential part cross-sectional view of the same semiconductor device as in FIG. 39 during a manufacturing step
  • FIG. 40 is a plan view of a principal part in the semiconductor device manufacturing process subsequent to FIG. 39;
  • FIG. 42 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 41 during the manufacturing step;
  • FIG. 43 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 42;
  • FIG. 44 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 43;
  • FIG. 45 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 44;
  • FIG. 46 is an essential part cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 45;
  • FIG. 47 A plan view of the essential part in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 48 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 47 during the manufacturing step;
  • FIG. 48 is a substantial part plan view of the semiconductor device during a manufacturing step following that of FIG. 47;
  • FIG. 50 is an essential part cross sectional view of the same semiconductor device as in FIG. 49 during a manufacturing step
  • FIG. 50 is a substantial part plan view of the semiconductor device during a manufacturing step following that of FIG. 49;
  • FIG. 52 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 51 during the manufacturing step;
  • FIG. 53 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 52;
  • FIG. 54 is an essential part cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 53;
  • FIG. 55 is a plan view of relevant parts showing one example of a state in which lead frames are fitted together.
  • FIG. 56 is a plan view of relevant parts showing another example of the fitting portion of the lead frame.
  • FIG. 57 is a plan view of relevant parts showing another example of a state in which the lead frames are fitted together.
  • FIG. 58 is a cross-sectional view of FIG.
  • FIG. 59 is another cross-sectional view of FIG. 57.
  • FIG. 60 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process thereof.
  • FIG. 61 is an essential part cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 60;
  • FIG. 62 is a process flow diagram showing a manufacturing process of a semiconductor device in another embodiment of the invention.
  • FIG. 63 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process thereof.
  • FIG. 64 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 63;
  • FIG. 65 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 64;
  • FIG. 66 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 65;
  • FIG. 67 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 66;
  • FIG. 68 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 67;
  • FIG. 69 is a plan view of the essential part in the manufacturing process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 70 is a substantial part plan view of the semiconductor device in manufacturing process, following FIG. 69;
  • FIG. 71 is an essential part cross sectional view of the same semiconductor device as in FIG. 70 during a manufacturing step;
  • FIG. 72 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 71.
  • FIG. 72 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 71.
  • hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Even a plan view may be hatched to make the drawing easier to see.
  • FIG. 1 is a top view (plan view) of a semiconductor device 1 according to an embodiment of the present invention
  • FIG. 2 is a bottom view (bottom view, back view, plan view)
  • FIG. Side view, Figure 4 and Figure 5 It is sectional drawing (side sectional drawing).
  • the cross section taken along line A—A in FIG. 1 ie, the cross section taken along line A—A in FIG. 2) substantially corresponds to FIG. 4, and the cross section taken along line B—B in FIG. Almost corresponds to Fig. 5.
  • 3 substantially corresponds to a side view of the semiconductor device 1 when viewed from the direction of the arrow 10 in FIG.
  • the semiconductor device (semiconductor package) 1 of the present embodiment is a grease-sealed, surface-mount type semiconductor package. That is, the semiconductor device 1 is a semiconductor device in the form of a resin-sealed semiconductor package.
  • a semiconductor device 1 of the present embodiment shown in FIGS. 1 to 5 includes a semiconductor chip 2 and source terminals (source terminals, source connection conductors, conductors) 3 formed of a conductor, Gate terminals (gate terminals, gate connecting conductors, conductor parts) 4 and drain terminals (drain terminals, drain connecting conductor parts, conductor parts) 5 and a sealing resin part for sealing them (Sealing part, sealing resin) 6.
  • the sealing resin portion 6 is made of a resin material such as a thermosetting resin material, and may contain a filler.
  • the sealing resin portion 6 can be formed using an epoxy resin containing a filler.
  • the sealing resin portion 6 has two main surfaces located opposite to each other, an upper surface (front surface, first surface) 6a and a rear surface (bottom surface, lower surface, second surface) 6b.
  • the back surface 6 b of the resin part 6, that is, the back surface (bottom surface, bottom surface) lb of the semiconductor device 1 is the mounting surface of the semiconductor device 1.
  • the semiconductor chip 2 is formed after various semiconductor elements or semiconductor integrated circuits are formed on a semiconductor substrate (semiconductor wafer) that has strength such as single crystal silicon, and then the back surface of the semiconductor substrate is ground as necessary.
  • the semiconductor substrate is separated into each semiconductor chip 2 by dicing or the like.
  • the semiconductor chip 2 is sealed in the sealing resin part 6.
  • the semiconductor chip 2 for example, a semiconductor chip formed with a vertical power MISFET (Metal Insulator Semiconductor Field Effect Transistor) force S having a trench type gate structure can be used.
  • the semiconductor chip 2 has two main surfaces located on opposite sides, the front surface (the main surface on the semiconductor element forming side, the second main surface) 2a and the back surface (the main surface on the side opposite to the front surface 2a, the first Main surface) 2b, semiconductor chip 2 table Source pad electrode (surface electrode) 2s and gate pad electrode (surface electrode) 2g formed on surface 2a, and back surface drain electrode (back surface electrode) 2d formed on the entire back surface 2b of semiconductor chip 2 ing.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the source pad electrode 2s is electrically connected to the source of the MISFET formed in the semiconductor chip 2, and the gate pad electrode 2g is electrically connected to the gate electrode of the MISFET formed in the semiconductor chip 2.
  • the back surface drain electrode 2d is electrically connected to the drain of the MISFET formed in the semiconductor chip 2.
  • FIG. 6 is a plan view (top view) showing an example of the chip layout of the semiconductor chip 2
  • FIG. 7 is a plan view (top view) showing another example of the chip layout of the semiconductor chip 2.
  • the semiconductor chip 2 according to the present embodiment has a force in which the source pad electrode 2s and the gate pad electrode 2g are formed on the surface 2a of the semiconductor chip 2.
  • the gate pad electrode 2g can be formed near the center of the edge of the surface 2a of the semiconductor chip 2 as shown in FIG. 6, for example, or as shown in FIG. As described above, the gate pad electrode 2g can be formed in the vicinity of the corner of the surface 2a of the semiconductor chip 2.
  • the source terminal 3, the gate terminal 4 and the drain terminal 5 have a conductor force, for example, a metal material force such as copper (Cu) or a copper alloy.
  • a conductor force for example, a metal material force such as copper (Cu) or a copper alloy.
  • the surface 2a side of the semiconductor chip 2 faces downward between the source terminal 3 and gate terminal 4 located on the lower side of the semiconductor chip 2 and the drain terminal 5 located on the upper side of the semiconductor chip 2.
  • the source terminal 3 is bonded (adhered or connected) to the source pad electrode 2s on the surface 2a of the semiconductor chip 2 through the solder 11 which is a conductive bonding material, and the gate terminal 4 is connected to the semiconductor chip.
  • the source terminal 3 is electrically connected to the source pad electrode 2s of the semiconductor chip 2 via the solder 11
  • the gate terminal 4 is electrically connected to the gate pad electrode 2g of the semiconductor chip 2 via the solder 11.
  • the drain terminal 5 is electrically connected to the back surface drain electrode 2d of the semiconductor chip 2 via the solder 11.
  • the lower surface 3a (front surface) of the source terminal 3 (second conductor portion) is exposed on the rear surface 6b (second surface) of the sealing resin portion 6.
  • Side surface (end surface, end portion) 3b of source terminal 3 is exposed on the side surface of sealing resin portion 6.
  • the other side surface (end portion) of the source terminal 3 is covered and sealed with the sealing resin portion 6.
  • the exposed side surface 3b of the source terminal 3 is a side surface (end surface) generated by a cutting process when the semiconductor device 1 is manufactured.
  • a part of the upper surface 3c of the source terminal 3 is joined to the source pad electrode 2s of the semiconductor chip 2 via the solder 11, and the other part of the upper surface 3c of the source terminal 3 is connected to the sealing resin part 6. Covered and sealed.
  • the lower surface 4a (front surface) of the gate terminal 4 (second conductor portion) is exposed on the rear surface 6b (second surface) of the sealing resin portion 6.
  • the side surface (end surface, end portion) 4b of the gate terminal 4 is exposed on the side surface of the sealing resin portion 6, and the other side surface (end portion) of the gate terminal 4 is covered with the sealing resin portion 6. It is sealed.
  • the exposed side surface 4b of the gate terminal 4 is a side surface (end surface) generated by a cutting process when the semiconductor device 1 is manufactured.
  • a part of the upper surface 4c of the gate terminal 4 is bonded to the gate pad electrode 2g of the semiconductor chip 2 via the solder 11, and the other part of the upper surface 4c of the gate terminal 4 is connected to the sealing resin portion 6. Covered and sealed.
  • the drain terminal 5 includes a first part (chip connection part, conductor part) 5a, a second part (external terminal component part, conductor part) 5b, a first part 5a, and a second part 5b. And a step portion (bending portion, connecting portion, conductor portion) 5c for connecting between them.
  • the first portion 5a, the second portion 5b, and the step portion 5c are integrally formed of the same conductor material, and the first portion 5a and the second portion 5b having different height positions are stepped. Part 5c is connected.
  • a part of the lower surface 5d of the first portion 5a of the drain terminal 5 is joined to the back surface drain electrode 2d of the semiconductor chip 2 via the solder 11, and the lower surface 5d of the first portion 5a of the drain terminal 5
  • the other part is covered and sealed with the sealing resin part 6.
  • the upper surface 5e (front surface) of the first portion 5a (first conductor portion) of the drain terminal 5 (first conductor portion) is exposed on the upper surface 6a (first surface) of the sealing resin portion 6.
  • the step portion 5 c of the drain terminal 5 is covered with the sealing resin portion 6 and sealed in the sealing resin portion 6.
  • the bottom surface 5f (surface different from the top surface 5e of the first portion 5a) of the second portion 5b of the drain terminal 5 (first conductor portion) is exposed at the back surface 6b (second surface) of the sealing resin portion 6. It has been done.
  • the side surface (end surface, end portion) 5g of the second portion 5b of the drain terminal 5 (that is, the end side surface 5g opposite to the side connected to the stepped portion 5c) is the side surface of the sealing resin portion 6.
  • the other side surface (end portion) of the second portion 5b of the drain terminal 5 that is exposed is covered and sealed with the sealing resin portion 6.
  • the exposed side surface 5g of the drain terminal 5 is cut when the semiconductor device 1 is manufactured. It is a side surface (end surface) generated by the process.
  • the bottom surface 3a of the source terminal 3 exposed on the back surface 6b of the sealing resin portion 6, the bottom surface 4a of the gate terminal 4 (second conductor portion), and the bottom surface 5f of the second portion 5b of the drain terminal 5 are substantially More preferably, they are formed on the same plane.
  • the back surface (bottom surface) lb of the semiconductor device 1 corresponding to the back surface 6b of the sealing resin portion 6 is the bottom surface 3a of the source terminal 3, the bottom surface 4a of the gate terminal 4, and the drain terminal 5
  • the lower surface 5f of the second portion 5b is exposed, and these exposed portions (that is, the lower surface 3a of the source terminal 3, the lower surface 4a of the gate terminal 4, and the lower surface 5f of the second portion 5b of the drain terminal 5) are the semiconductor device 1 It functions as an external terminal (terminal, external connection terminal, external connection terminal).
  • the semiconductor device 1 Since the source terminal 3, the gate terminal 4, and the drain terminal 5 as external terminals are exposed on the back surface lb of the semiconductor device 1 (the back surface 6b of the encapsulating grease part 6), the semiconductor device 1 can be surface mounted.
  • the back surface lb of the semiconductor device 1 (the back surface 6b of the sealing resin portion 6) is the mounting surface of the semiconductor device 1.
  • the drain terminal 5 of the semiconductor device 1 is on the upper surface (main surface opposite to the rear surface lb) la, that is, on the upper surface 6a of the sealing resin portion 6.
  • the upper surface 5e of the first portion 5a is exposed.
  • the semiconductor device 1 of the present embodiment is a semiconductor device in the form of a resin-encapsulated semiconductor package having exposed conductors on the upper and lower surfaces, and the first portion 5a of the drain terminal 5 is formed on the upper surface la.
  • the exposed conductor on the (upper surface 6a) side, and the second portion 5b of the source terminal 3, the gate terminal 4 or the drain terminal 5 becomes the exposed conductor on the rear surface lb (back surface 6b) side.
  • the upper surface (front surface) la (upper surface 6a of the sealing resin part 6) connected only to the back surface lb (the back surface 6b of the sealing resin part 6) of the semiconductor device 1 is connected to the semiconductor chip 2 ( By exposing the joined conductor portion (the first portion 5a of the drain terminal 5), the heat dissipation characteristics of the semiconductor device 1 can be improved, and the performance of the semiconductor device 1 can be improved.
  • FIG. 8 is a process flow diagram showing a manufacturing process of the semiconductor device 1 of the present embodiment.
  • FIG. 9 is a process flow diagram showing a molding process in the manufacturing process of the semiconductor device 1 of the present embodiment.
  • FIG. 10 is a graph (an explanatory diagram) showing the mold temperature and the mold pressure in the molding process of the present embodiment.
  • 11 and 12 show the semiconductor chip 2 used in the present embodiment. It is principal part sectional drawing in a manufacturing process.
  • FIGS. 13 to 28 are principal part plan views or principal part sectional views showing the manufacturing process of the semiconductor device 1 of the present embodiment. 11 to 28, FIG. 13, FIG. 15, FIG. 17, FIG. 26, and FIG. 27 are plan views (plan views of main parts), and FIG.
  • FIG. 16, FIG. 18 to FIG. It is sectional drawing (main part sectional drawing). 13 and 14 correspond to the same process step, FIGS. 15 and 16 correspond to the same process step, FIGS. 17 and 18 correspond to the same process step, and FIGS. Corresponds to the same process step.
  • the cross-sectional views of FIGS. 14, 16, 18 to 25, and 28 substantially correspond to the cross sections along the line C-C shown in FIGS. 13, 15, and 17, and FIG.
  • the horizontal axis in FIG. 10 corresponds to time (arbitrary unit)
  • the vertical axis corresponds to mold temperature or mold pressure (arbitrary unit: arbitrary unit).
  • 32, and the mold pressure corresponds to the pressure pressing the mold 3 1 against the mold 32).
  • step Sl To manufacture the semiconductor device 1, first, the semiconductor chip 2 and the lead frames (conductor members) 21 and 22 are prepared (step Sl).
  • the semiconductor chip 2 In order to manufacture the semiconductor chip 2, first, as shown in FIG. 11, for example, the main surface of a semiconductor substrate (semiconductor wafer) 101a that has strength such as n + type single crystal silicon into which arsenic (As) is introduced Further, an epitaxial layer 101b having n_type single crystal silicon force is grown to form a semiconductor substrate (semiconductor wafer, so-called epitaxial wafer) 101. Then, after forming an insulating film (oxide silicon film) on the main surface of the semiconductor substrate 101, this insulating film is patterned to form an insulating film 102 (SiO plate).
  • insulating film oxide silicon film
  • the p-type well 103 is formed by ion-implanting a p-type impurity (for example, boron (B)) into the main surface of the semiconductor substrate 101.
  • a p-type impurity for example, boron (B)
  • a trench for forming a trench gate that is, a gate trench 104 is formed by dry etching the semiconductor substrate 101 using a photoresist pattern (not shown) as an etching mask.
  • the depth of the gate trench 104 is deeper than that of the p-type well 103, but shallower than the bottom of the epitaxial layer 101b.
  • the inner wall surface (side surface and bottom surface) of the gate trench 4 using, for example, a thermal oxidation method or the like.
  • a relatively thin gate insulating film (oxide silicon film) 105 is formed on the surface.
  • a conductive film (gate electrode material film) having a force such as a low resistance polycrystalline silicon film is formed on the main surface of the semiconductor substrate 101.
  • a photoresist pattern (not shown) that covers the gate wiring formation region and exposes other regions is formed on the conductive film, and the conductive film is formed using the photoresist pattern as an etching mask.
  • a gate portion 106 having a force such as low-resistance polycrystalline silicon embedded in the gate trench 104 and a gate wiring portion 106a formed integrally with the gate portion 106 are formed.
  • a channel region 107 is formed by ion implantation of a p-type impurity (for example, boron (B)) into the main surface of the semiconductor substrate 101.
  • a p-type impurity for example, boron (B)
  • the source region 108 is formed by ion-implanting n-type impurities (for example, arsenic (As)) into the main surface of the semiconductor wafer 1.
  • an insulating film 112 is formed on the main surface of the semiconductor substrate 101, and is patterned using a photolithography technique and an etching technique. At this time, a contact hole 113 exposing the main surface of the semiconductor substrate 101 and a through hole 114 exposing a part of the gate wiring portion 106a are formed in the insulating film 112.
  • the hole 115 is formed by etching the semiconductor substrate 101 exposed from the contact hole 113. Then, a p + type semiconductor region is formed by ion-implanting, for example, a p-type impurity (for example, boron (B)) into the semiconductor substrate 101 exposed from the contact hole 113 and the hole 115.
  • a p + type semiconductor region is formed by ion-implanting, for example, a p-type impurity (for example, boron (B)) into the semiconductor substrate 101 exposed from the contact hole 113 and the hole 115.
  • a titanium tungsten film (not shown) is formed on the main surface of the semiconductor substrate 101 as necessary, and then an aluminum film (or aluminum alloy film) 116 is formed thereon by a sputtering method or the like. Formed by. Then, the laminated film of the titanium tungsten film and the aluminum-alloy film 116 is patterned using a photolithography technique and an etching technique. As a result, surface electrodes such as the gate electrode 116a and the source wiring 116b are formed.
  • the drain electrode 118 is formed by depositing, for example, nickel, titanium, nickel and gold on the back surface of the semiconductor substrate 101 by vapor deposition.
  • the drain electrode 118 serves as the back surface drain electrode 2d of the semiconductor chip 2.
  • a semiconductor element such as a vertical power MISFET having a trench gate structure is formed on the semiconductor substrate 101.
  • the semiconductor substrate 101 is cut or diced using a dicing saw or the like, and separated into individual semiconductor chips 2.
  • the semiconductor chip 2 in which the vertical power MISFET having the trench type gate structure is formed is manufactured.
  • the vertical MISFET corresponds to a MISFET that flows in the thickness direction of the semiconductor substrate (direction substantially perpendicular to the main surface of the semiconductor substrate) between the source and the drain.
  • the lead frames 21 and 22 used for manufacturing the semiconductor device 1 are conductor members made of a conductor, and are formed of a metal material such as copper (Cu) or a copper alloy, for example.
  • the lead frame 21 (first conductor member) has a drain terminal portion 25 (first conductor portion) to be the drain terminal 5. That is, the lead frame 21 includes the first portion 25a of the drain terminal portion 25 that becomes the first portion 5a of the drain terminal 5 and the second portion of the drain terminal portion 25 that becomes the second portion 5b of the drain terminal 5.
  • a portion 25b and a stepped portion (folded portion) 25c of the drain terminal portion 25 to be a stepped portion (folded portion) 5c of the drain terminal 5 are formed integrally.
  • the lead frame 22 (second conductor member) has a source terminal portion 23 (second conductor portion) to be the source terminal 3 and a gate terminal portion 24 (second conductor portion) to be the gate terminal 4. These are integrally formed.
  • the lead frames 21 and 22 have openings 20a and 20b (the opening 20a of the lead frame 21 and the lead frame 21) along the planned cutting positions in order to facilitate cutting of the lead frames 21 and 22, which will be described later. 22 openings 20b) are provided.
  • Lead frames 21, 22 are gold
  • a metal plate (such as a copper plate) can be manufactured by processing it into a predetermined shape by molding (pressing) or etching, for example.
  • the semiconductor chip 2 is soldered (solder, solder material) 11a, etc. on the lead frame 21, as shown in FIG. 15 and FIG. (Step S2).
  • the front surface 2a side of the semiconductor chip 2 faces upward
  • the back surface 2b side (back surface drain electrode 2d side) of the semiconductor chip 2 faces the first portion 25a of the lead frame 21 so that The semiconductor chip 2 is arranged on the part 25a of 1. That is, the semiconductor chip 2 is placed on the lead frame 21 so that the semiconductor chip 2 (back surface drain electrode 2d) is disposed on the first portion 25a of the drain terminal portion 25 of the lead frame 21 via the solder paste 11a. Place.
  • the semiconductor chip 2 is temporarily fixed to the lead frame 21 by the adhesiveness (adhesiveness) of the solder paste 11a.
  • the lead frame 22 is arranged on the surface 2a of the semiconductor chip 2 via a solder paste (solder, solder material) ib (step S3). . That is, the source terminal portion 23 of the lead frame 22 is disposed on the source pad electrode 2s of the semiconductor chip 2 via the solder paste l ib, and the solder paste l ib is disposed on the gate pad electrode 2g of the semiconductor chip 2.
  • the lead frame 22 is disposed on the lead frame 21 and the semiconductor chip 2 so that the gate terminal portion 24 of the lead frame 22 is disposed therebetween.
  • the lead frame 22 is temporarily fixed to the semiconductor chip 2 by the adhesiveness (adhesiveness) of the solder paste l ib. In FIG. 17, the lead frame 22 is hatched to make it easy to see the force diagram as a plan view.
  • solder reflow is performed (step S4).
  • the solder paste 11a, ib is melted and solidified, and the source terminal portion 23 of the lead frame 22 and the source pad electrode 2s of the semiconductor chip 2 are connected as shown in FIG. Bonded via the solder 11, the gate terminal portion 24 of the lead frame 22 and the gate pad electrode 2g of the semiconductor chip 2 are bonded via the solder 11, and the back surface drain electrode 2d of the semiconductor chip 2 and the lead frame 21 drain The rain terminal 25 is joined with the solder 11.
  • Solder paste 11a, ib force solder 11 is melted and solidified by solder reflow.
  • step S4 cleaning can be performed as necessary to remove soot and flux.
  • the source terminal portion 23 of the lead frame 22 is connected to the source pad electrode 2s of the surface 2a of the semiconductor chip 2 via the solder 11, and the lead frame is connected to the gate pad electrode 2g of the surface 2a of the semiconductor chip 2.
  • the drain terminal portion 25 of the lead frame 21 is bonded to the gate terminal portion 24 of 22 and the back surface drain electrode 2d of the back surface 2b of the semiconductor chip 2.
  • the lead frames 21 and 22 and the assembly (work) 30 having the semiconductor chip force bonded between them can be obtained.
  • a molding process (a resin sealing process, for example, a transfer molding process) is performed to form a sealing resin part 6, and the semiconductor chip 2 is sealed with the sealing resin part 6 (step S 5).
  • step S5 the molding process of step S5 is performed as follows.
  • molds 31, 32 (upper mold 31 and lower mold 32) for forming the sealed resin part 6 are prepared.
  • the dies 31, 32 used in the present embodiment are configured to be heatable.
  • a heater 33a is built in each mold 31, 32, and the molds 31, 32 can be heated by the heater 33a.
  • cooling oil 33b and the like can be circulated in the molds 31, 32, and the molds 31, 32 can be cooled by the cooling oil 33b.
  • the molds 31 and 32 can be controlled to a desired temperature.
  • step S 5a the assembly 30 is placed on the lower mold 32 (step S 5a).
  • step S5b the upper mold 31 is lowered so as to approach the mold 32 and is brought into contact with the assembly 30. Is temporarily fixed (step S5b).
  • the lead frames 21 and 22 of the assembly 30 are sandwiched between the molds 31 and 32, and the lower surface 31a of the mold 31 and the upper surface 32a of the mold 32.
  • the source terminal portion 23 and the gate terminal portion 24 of the lead frame 22, the drain terminal portion 25 of the lead frame 21, and the semiconductor chip 2 therebetween are arranged in the cavity 34 formed by the above.
  • the mold pressure pressure between molds 31 and 32, or pressure to press one of molds 31 and 32 against the other
  • Low Prevent the mold 31 from being pressed strongly against the mold 32. That is, the force that the lower surface 31a of the upper mold 31 is lightly in contact with the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 of the assembly 30 Assembly 30 (i.e., the semiconductor chip between 2 so that the lead frames 21 and 22) sandwiching the 2 are not clamped by the dies 31 and 32, the first portion 25a of the drain terminal portion 25 on the upper side of the semiconductor chip 2 and the source terminal portion 23 on the lower side of the semiconductor chip 2 Also, a large pressure is not applied to the upper and lower sides of the dies 31 and 32 from the dies 31 and 32 to the semiconductor chip 2 through the gate terminal portion 24.
  • step S5c the temperature of the molds 31, 32 is raised, and thereby the solder 11 of the assembly 30 is melted (remelted) (step S5c).
  • the solid state (solidified) solder 11 becomes a molten solder 11c.
  • FIG. 22 the solid state (solidified) solder 11 becomes a molten solder 11c.
  • the solder 11 by heating the molds 31 and 32 to a temperature equal to or higher than the melting point T of the solder 11 (for example, about 320 to 350 ° C.) by the heaters 33a in the molds 31 and 32, The solder 11 can be heated to a temperature equal to or higher than the melting point T of the solder 11 via the lead frames 21 and 22 in contact with the molds 31 and 32, and the solder 11 can be melted to obtain a molten solder 11c.
  • the melting point T of the solder 11 for example, about 320 to 350 ° C.
  • the assembly 30 (that is, the lead frames 21, 22 with the semiconductor chip 2 sandwiched therebetween) is placed in the mold 31, Clamp at 32 (step S5d). That is, as shown in FIG. 10, the mold 31 is pressed against the mold 32 (or the mold 32 is pressed against the mold 31) with a relatively large pressure (clamping pressure). 3D 30 lead frames 21, 22 are clamped by molds 31, 32 and fixed. For example, press the mold 31 against the mold 32 with a pressure (clamping pressure) of about 100 kg weight Zcm 2 . As a result, the mold 31 is fixed to the mold 32 with tension, and the lead frames 21 and 22 force sandwiched between the molds 31 and 32 are fixed to the mold 31 and 32 with tension.
  • the lower surface 31a of the mold 31 is in close contact with the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21, and the upper surface 32a of the mold 32 is the gate terminal portion 24 of the lead frame 22.
  • the force that is in close contact with the lower surface 35b of the source terminal portion 23 and the lower surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 Since the solder 11c is in a molten state and can be deformed as described above. Even if the mold 31 is pressed against the mold 32 with a relatively large pressure (clamping pressure), the pressure is absorbed by the shape change of the molten solder 11c and half Almost no addition to conductor chip 2.
  • the cavity 34 is formed by the lower surface 31 a of the mold 31 and the upper surface 32 a of the mold 32.
  • the upper surface 35a (front surface) of the first portion 25a of the drain terminal portion 25 of the lead frame 21 is a surface opposite to the side facing the back surface 2b of the semiconductor chip 2, that is, the semiconductor chip 2 is joined. It is the surface on the opposite side to the finished surface.
  • the upper surface 35a of the first portion 25a of the drain terminal portion 25 becomes the upper surface 5e of the first portion 5a of the drain terminal 5 after the semiconductor device 1 is manufactured.
  • the lower surface 35c of the second portion 25a of the drain terminal portion 25 of the lead frame 21 becomes the upper surface 5f of the second portion 5b of the drain terminal 5 after the semiconductor device 1 is manufactured.
  • the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 is the surface opposite to the surface facing the surface 2a of the semiconductor chip 2, that is, the surface opposite to the surface where the semiconductor chip 2 is bonded. And the lower surfaces 4a and 3a of the gate terminal 4 and the source terminal 3 after the semiconductor device 1 is manufactured.
  • step S5e the temperature of the molds 31 and 32 is lowered, thereby lowering the solder 11c to a temperature below the melting point T of the solder 11 (cooling).
  • step S5e the molten solder 11c is solidified and becomes solid state (solidified) solder 11 again.
  • the temperature of the dies 31, 32 is reduced to a temperature below the melting point T of the solder 11 (eg, about 180 ° C.).
  • the temperature of the solder 11c is lowered (cooled) to a temperature lower than the melting point T of the solder 11 through the lead frames 21 and 22 that are in contact with the molds 31 and 32, so that the solder 11c is solidified and solidified.
  • the solder 11 can be in the state.
  • a sealing resin material 36 that is a material for forming the sealing resin portion 6 is injected (introduced and filled) into the cavity 34 of the molds 31 and 32.
  • the injected sealing resin material 36 is cured to form the sealing resin part 6 (Step S5g).
  • the sealing resin material 36 for forming the sealing resin part 6 is made of, for example, a resin material such as a thermosetting resin material, and may contain a filler, for example, an epoxy resin containing a filler. Such as fat Can be used.
  • the sealing resin material 36 also has a thermosetting resin material strength
  • the temperature of the molds 31 and 32 is set to a predetermined temperature. By heating to (for example, about 180 ° C.), the sealing resin material 36 can be heated and cured. It is preferable that the temperature at the time of curing of the sealing resin material 36 is lower than the melting point T of the solder 11, thereby preventing the solder 11 from being melted during the curing of the sealing resin material 36. In this way, the sealed resin part 6 is formed.
  • step S5 the lead frames 21 and 22 and the semiconductor chip 2 are molded so that the back surface drain electrode 2d side of the semiconductor chip 2 faces downward with FIGS. 21 to 24 turned upside down. It can also be set to 31, 32.
  • the mold 31 is a lower mold and the mold 32 is an upper mold.
  • the assembly 30 (the lead frames 21 and 22 on which the sealing resin part 6 is formed) is attached to the mold 31, Release from 32 (step S5h).
  • step S5h the molding process of step S5 is performed (as in steps S5a to S5h).
  • the sealing resin 6 is removed.
  • an assembly (work) 30a as shown in FIGS. 25 to 27 is obtained.
  • the assembly 30a is obtained by forming the sealing resin portion 6 on the assembly 30.
  • the formed sealing resin part 6 has an upper surface 6a and a back surface 6b, which are two main surfaces located on opposite sides.
  • the sealing resin portion 6 seals the semiconductor chip 2, the source terminal portion 23, the gate terminal portion 24, and the drain terminal portion 25.
  • step S5 In the molding process of step S5, as described above, the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 and the lower surface 31a of the die 31 are in close contact, and the gate terminal of the lead frame 22 In a state where the lower surface 35b of the part 24 and the source terminal part 23 and the upper surface 32a of the mold 32 are in close contact with each other, a sealing resin material 36 is injected into the cavity 34 of the molds 31, 32, and the semiconductor chip 2 A sealing resin portion 6 for sealing the is formed. For this reason, since there is no gap between the upper surface 35 of the first portion 25a of the drain terminal portion 25 of the lead frame 21 and the lower surface 31a of the mold 31, the sealing resin material 36 is not filled.
  • the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the lower surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 and the upper surface 32a of the mold 32 are not provided. Sealed because there is no gap The resin material 36 is not filled. Therefore, the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 is not formed with the sealing resin portion 6 thereon, and is exposed from the upper surface 6a of the sealing resin portion 6. The bottom surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the bottom surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 are sealed on the top.
  • the resin seal portion 6 is not formed, and is exposed from the back surface 6b of the sealing resin portion 6.
  • the sealing resin portion 6 is formed on the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 on the upper surface 6a of the sealing resin portion 6, and the sealing resin portion On the back surface 6b of the lead frame 22, the bottom surface 35b of the source terminal portion 23 and the bottom surface 35b of the drain terminal portion 25 of the lead frame 21 and the bottom surface 35c of the second portion 25b of the lead frame 21 Even if the resist is formed, it can be removed in the process of removing the paste after the molding process. Thus, the sealing resin portion 6 is in a state where the conductor portions (the source terminal portion 23, the gate terminal portion 24, and the drain terminal portion 25) are exposed on both the upper surface 6a and the rear surface 6b. .
  • Step S6 a plating process is performed as necessary, and a plating layer (not shown) is formed on the portions exposed from the sealing resin portions 6 of the lead frames 21 and 22 (portions made of a conductor). Form (Step S6).
  • a soldering process such as lead-free soldering can be performed.
  • the lead frames 21 and 22 are cut at predetermined positions (step S7).
  • the lead frames 21 and 22 are cut along a cutting line 45 indicated by a dotted line, and the lead frames 21 and 22 protruding from the sealing resin portion 6 are removed.
  • the semiconductor device 1 divided into pieces is obtained (manufactured).
  • the semiconductor device 1 shown in FIG. 28 corresponds to the semiconductor device 1 shown in FIGS.
  • the source terminal portion 23 cut and separated from the lead frame 22 becomes the source terminal 3 of the semiconductor device 1, and the gate terminal portion 24 cut and separated from the lead frame 22 is the gate of the semiconductor device 1.
  • the drain terminal portion 25 which is the terminal 4 and is cut and separated from the lead frame 21 becomes the drain terminal 5 of the semiconductor device 1.
  • the first portion 25a of the drain terminal portion 25 becomes the first portion 5a of the drain terminal 5
  • the second portion 25b of the drain terminal portion 25 becomes the second portion 5b of the drain terminal 5
  • the 25 step portions 25 c become the step portions 5 c of the drain terminal 5.
  • the upper surface 35a of the first portion 25a of the drain terminal portion 25 is not sealed.
  • the lower surface 35b of the source terminal portion 23 becomes the lower surface 3a of the source terminal 3 exposed from the rear surface 6b of the sealing resin 6, and the lower surface of the gate terminal portion 24 extends from the rear surface 6b of the sealing resin portion 6.
  • the exposed lower surface 4a of the gate terminal 4 becomes the lower surface 4a of the drain terminal portion 25, and the lower surface 35c of the second portion 25b of the drain terminal portion 25 is exposed from the rear surface 6b of the sealing resin portion 6. It becomes.
  • FIG. 29 is a cross-sectional view (main part cross-sectional view) showing a state where a plurality of semiconductor devices 1 are mounted on a mounting substrate 51
  • FIG. 30 is a top view (plan view) thereof.
  • a plurality of semiconductor devices 1 are mounted on a mounting substrate (wiring substrate) 51.
  • the back surface (bottom surface) lb side of the semiconductor device 1 is the mounting surface to the mounting substrate 51, and external connection terminals exposed at the back surface lb of the semiconductor device 1, that is, the source terminal 3, the gate terminal 4 and the drain terminal 5 (each of The lower surfaces 3a, 4a, 5f) are joined and electrically connected to the terminals 52 of the mounting substrate 51 via the solder (conductive bonding material) 53.
  • the source terminal 3 (the lower surface 3a) and the gate terminal 4 (the lower surface 4a) exposed at the rear surface lb of the semiconductor device 1 are joined to the terminal 52 of the mounting substrate 51 via the solder 53.
  • the second portion 5b (the lower surface 5f) of the drain terminal 5 exposed at the rear surface lb of the semiconductor device 1 is connected to the terminal 52 of the mounting substrate 51 via the solder 53 in the other cross section.
  • heat radiating fins (heat radiating components, heat sinks) 55 are arranged (mounted) via heat conductive sheets (heat radiating sheets) 54.
  • the radiating fin 55 also has a metal material force such as aluminum (A1) or aluminum alloy.
  • the heat conduction sheet 54 is an insulating sheet having elasticity and has a relatively high heat conductivity.
  • the heat conductive sheet 54 is made of a silicon-based, acrylic-based, or ethylene-propylene-based material, and is made of a rubber-like or gel-like sheet.
  • the heat conductive sheet 54 can also be formed by mixing the above materials with a glass cloth as a base material.
  • the heat conductive sheet 54 can be sandwiched between the semiconductor device 1 that is a heating element and the heat radiating fins 55 that are heat radiating components, and can function to enhance the heat radiating effect.
  • the radiating fins 55 are fixed to the mounting board 51 by, for example, screwing or fixing metal fittings (not shown). Further, the heat radiating fins 55 can be bonded and fixed to the upper surfaces la of the plurality of semiconductor devices 1 using a heat radiating resin adhesive or the like instead of the heat conductive sheet 54.
  • the semiconductor chip 2 is connected to the source terminal 3, the gate terminal 4 and the drain terminal 5, and the source terminal 3, the gate terminal 4 and the drain terminal 5 have a thermal conductivity higher than that of the sealed resin part 6. It is made of high-potential conductor (metal such as copper alloy). Therefore, heat generated in the semiconductor chip 2 in the semiconductor device 1 is radiated to the outside of the semiconductor device 1 through the source terminal 3, the gate terminal 4, and the drain terminal 5. At this time, the heat generated in the semiconductor chip 2 is radiated to the mounting substrate 51 side through the source terminal 3, the gate terminal 4 and the drain terminal 5, and the radiating fin 55 through the drain terminal 5 and the heat conduction sheet 54. Heat is dissipated. A plurality of fins are formed in the radiating fins 55, and the heat conducted from the semiconductor device 1 to the radiating fins 55 is further dissipated into the outside air.
  • the source terminal 3, the gate terminal 4, and the drain terminal 5 (second portion 5b thereof) are exposed as external connection terminals on the back surface lb of the semiconductor device 1.
  • the upper surface 5e of the first portion 5a of the drain terminal 5 is exposed on the upper surface la of the semiconductor device 1 (upper surface 6a of the sealing resin portion 6).
  • the heat generated by the semiconductor chip 2 in the semiconductor device 1 is transferred to the back surface lb side of the semiconductor device 1 (second portion 5b of the source terminal 3, the gate terminal 4 and the drain terminal 5) and the upper surface la side (of the drain terminal 5).
  • Both sides (both sides) force of the first part 5a) can dissipate heat.
  • the heat dissipation characteristic (heat dissipation) of the semiconductor device in the form of a resin-encapsulated semiconductor package can be improved, and the performance can be improved.
  • FIG. 31 shows a state in which the lead frames 21 and 22 with the semiconductor chip 2 interposed therebetween are fixed to the molds 131 and 132 in the molding process of the comparative example examined by the present inventors. .
  • the semiconductor is interposed between the source terminal portion 23 and gate terminal portion 24 of the lead frame 22 and the first portion 25a of the drain terminal portion 25 of the lead frame 21 via the solder 11.
  • the assembly 30 in a state where the chip 2 is sandwiched is clamped by the molds 131 and 132 while the solder 11 is solidified without remelting the solder 11.
  • the sealing resin material is injected into the cavities 134 of the molds 131 and 132 and cured to form the sealing resin portion 6.
  • the lower surface 35b of the source terminal portion 23 and the gate terminal portion 24 is exposed on the back surface 6b side of the sealing resin portion 6, and the drain terminal portion 25 on the upper surface 6a side of the sealing resin portion 6. It is possible to expose the upper surface 35a of the first portion 25a.
  • the molds 131, 132 Via the first portion 25a of the drain terminal portion 25 on the upper side of the semiconductor chip 2 and the source terminal portion 23 and the gate terminal portion 24 on the lower side of the semiconductor chip 2, pressure on both sides of the semiconductor chip 2 can be applied. There is a potential.
  • the assembly 30 immediately before the molding process is caused by variations in the bonding state between the semiconductor chip 2 and the lead frames 21 and 22, the variation in the amount of the bonding material 11, and the like.
  • the height dimension h varies, or the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the upper surface 35a of the first portion 25a of the drain terminal portion 25a of the lead frame 21 Parallelism etc. may vary.
  • the height h of the assembly just before the molding process is slightly larger than the height h of the cavity 134 (h
  • the mold 131 becomes the first part of the drain terminal part 25 of the lead frame 21.
  • the upper surface 35a of 25a is pressurized, and the mold 132 pressurizes the gate terminal portion 24 of the lead frame 22 and the lower surface 35b of the source terminal portion 23, thereby the first portion 25a of the drain terminal portion 25 and the source terminal
  • the semiconductor chip 2 sandwiched between the part 23 and the gate terminal part 24 may be subjected to strong pressure from above and below. If pressure is applied to the semiconductor chip 2 from above and below, cracks and the like may occur in the semiconductor chip 2, which may reduce the manufacturing yield of the semiconductor device 1.
  • FIG. 31 when manufacturing a resin-sealed semiconductor package with exposed terminals on both the upper and lower surfaces such as the semiconductor device 1, when forming the sealed resin part, the above-described FIG. 31 is used. As explained, pressure may be applied to the semiconductor chip to be sealed in the sealing resin portion from the upper and lower sides, and cracks may occur in the semiconductor chip, which is a factor in the production yield of semiconductor devices. It will cause a decline.
  • the solder 11 is melted before the molds 31 and 32 for forming the sealing resin 6 are clamped, and the solder 11 is melted.
  • the semiconductor chip 2 is prevented from being pressed by the upper and lower side forces when the dies 31 and 32 are clamped.
  • the molds 31, 32 Since the molten solder 11 can change its shape in the clamped assembly 30, the height h of the assembly 30 just before the molding process varies, or the gate terminal portion 24 and the source terminal of the lead frame 22 Even if the parallelism between the lower surface 35b of the portion 23 and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 varies, the clamping pressure of the dies 31, 32 is It is absorbed by the shape change and hardly added to the semiconductor chip 2. Thereby, when the assembly 30 (lead frames 21 and 22) is clamped by the dies 31 and 32, the semiconductor chip 2 can be prevented from being pressed from above and below via the terminal portions.
  • the semiconductor chip 2 it is possible to prevent cracks and the like from occurring in the semiconductor chip 2 and to improve the manufacturing yield of the semiconductor device (semiconductor package) 1. In addition, the cost of the semiconductor device 1 can be reduced. After the molds 31 and 32 are clamped, the solder 11 is solidified again.
  • the lower surface 31a of the mold 31 is in close contact with the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21, and the upper surface of the mold 32 is The cavities of the dies 31 and 32 with 32a closely attached to the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the lower surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 34
  • the sealing resin material 36 is injected into the sealing resin part 6 to form the sealing resin part 6, so that the conductor parts (source terminal part 23, gate terminal part 24, both sides of the upper surface 6 a and the back surface 6 b of the sealing resin part 6 are formed. And the drain terminal part 25) can be exposed.
  • a resin-encapsulated semiconductor package in which terminals are exposed on both the upper and lower surfaces such as the semiconductor device 1 can be obtained.
  • the semiconductor chip 2 is sandwiched between a plurality of terminals (source terminal 3, gate terminal 4 and drain terminal 5), and the terminals are exposed on both the upper and lower surfaces.
  • a semiconductor chip having an electrode only on one of the front surface 2a and the back surface 2b that is, a semiconductor chip having an electrode on the front surface 2a and no electrode on the back surface 2a
  • the semiconductor chip having electrodes on both the front surface 2a and the back surface 2b as described above that is, the semiconductor chip having the front electrode and the back electrode
  • the present embodiment and the following embodiments are performed. If the form is applied, the effect is great.
  • the semiconductor chip 2 used in this embodiment and the following embodiments a semiconductor chip on which various semiconductor elements are formed can be used, and the trench type gate as described above can be used.
  • the semiconductor chip is not limited to a vertical power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate structure, and various other semiconductor chips can also be used.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the semiconductor chip 2 has a large heat generation amount, a semiconductor chip,
  • a semiconductor chip in which a power transistor such as a power MISFET is formed (a semiconductor chip in which a semiconductor amplifying element for power amplification is formed)
  • this embodiment and the following embodiments are applied.
  • the effect is great.
  • a semiconductor chip on which a vertical power Ml SFET having a trench gate structure as described above is formed has a relatively large amount of heat generated during operation. Therefore, a vertical power MISFET having a trench gate structure is formed.
  • this semiconductor chip is used as the semiconductor chip 2 and this embodiment and the following embodiments are applied, the effect is greater.
  • FIG. 32 is a perspective view showing the appearance of the dies 31, 32 used in the present embodiment.
  • FIGS. 33 to 35 are cross-sectional views of relevant parts during the manufacturing process of the semiconductor device of the present embodiment, and correspond to FIGS. 21, 22 and 24 of the first embodiment, respectively.
  • the heater 33a is built in the molds 31, 32 as a heating mechanism, and the cooling oil 33b, etc., can be circulated in the molds 31, 32 as a cooling mechanism.
  • the molds 31, 32 can be controlled to a desired temperature.
  • a heating block 61 is provided as a heating mechanism in the dies 31, 32
  • cooling oil 33b is provided as a cooling mechanism in the dies 31, 32.
  • the molds 31 and 32 can be controlled to a desired temperature. That is, in the first embodiment, when the molds 31 and 32 are heated, the force that is used to heat the entire molds 31 and 32 by the heater 33a.
  • the heating blocks 61 of the dies 31, 32 are partially heated.
  • a spring (panel mechanism) 62 is connected to the heating block 61 and is fitted in the molds 31 and 32.
  • the heating block 61 is configured to be movable relative to the portions of the molds 31 and 32 other than the heating block 61.
  • the heating block 61 can also be a metal material, for example, The same metal material force as the molds 31 and 32 (other parts) is also obtained.
  • Other configurations and manufacturing processes are substantially the same as those in the first embodiment.
  • step S5a the assembly 30 is placed on the lower mold 32 (step S5a).
  • step S5a the upper die 31 is lowered so as to approach the die 32 and is brought into contact with the assembly 30, and the assembly 30 is temporarily fixed by the die 31, 32 (step S 5 b).
  • the heating block 61 of the upper die 31 is in contact with the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 of the assembly 30 (the above embodiment).
  • the lower surface 31a of the mold 31 is in contact).
  • the heating block 61 of the lower mold 32 is in contact with the lower surface 35b of the source terminal 23 and the gate terminal 24 of the lead frame 22 of the assembly 30 (in the first embodiment, the mold 32 Of the upper surface 32a of the contact).
  • the temperature of the molds 31, 32 is raised, thereby melting (remelting) the solder 11 of the assembly 30 (step S5c).
  • the solid state (solidified) solder 11 becomes a molten solder 11c.
  • the heating block 61 of the molds 31 and 32 is heated to a temperature equal to or higher than the melting point T of the solder 11 (for example, about 320 to 350 ° C.).
  • the solder 11 can be heated to a temperature equal to or higher than the melting point T of the solder 11 through the lead frames 21 and 22 that are in contact with each other, and the solder 11 can be melted to obtain a solid state solder 11c.
  • the assembly 30 is clamped by the dies 31 and 32 in a state where the solder 11 is melted and becomes the molten solder 11c (step S5d). Then, with the molds 31 and 32 still clamped, the temperature of the molds 31 and 32 is lowered, and thereby the solder 11c is lowered (cooled) to a temperature below the melting point T of the solder 11 and solidified. (Step S5e). As a result, as shown in FIG. 35, the molten solder 11c is solidified and becomes solid state (solidified) solder 11 again.
  • the temperature of the heating blocks 61 of the dies 31 and 32 is lowered to a temperature lower than the melting point T of the solder 11 (for example, about 180 ° C.), thereby heating the dies 31 and 32.
  • the temperature of the solder 11c can be lowered (cooled) to a temperature lower than the melting point T of the solder 11 via the lead frames 21 and 22 in contact with the block 61, and the solder 11c can be solidified.
  • the sealing resin material 36 which is a material for forming the sealing resin portion 6, is injected into the cavity 34 of the molds 31, 32 (step S5f).
  • the injected sealing resin material 36 is cured to form the sealing resin part 6 (step S5g).
  • the assembly 30 is released from the molds 31, 32 as in the first embodiment (step S5h).
  • a manufacturing process of a semiconductor device according to another embodiment of the present invention will be described. Since the structure of the manufactured semiconductor device 1 is the same as that of the first embodiment, the description thereof is omitted here.
  • FIG. 36 is a process flowchart showing the manufacturing process of the semiconductor device of the present embodiment.
  • FIGS. 37 to 46 are principal part plan views or principal part sectional views showing the manufacturing steps of the semiconductor device of the present embodiment.
  • 37, FIG. 39 and FIG. 41 are plan views (main part plan views)
  • FIG. 38, FIG. 40, and FIG. 42 to FIG. 46 are sectional views (main part sectional views).
  • 37 and 38 correspond to the same process step
  • FIGS. 39 and 40 correspond to the same process step
  • FIGS. 41 and 42 correspond to the same process step.
  • the cross-sectional views of FIGS. 38, 40, 42, and 43 substantially correspond to the cross-section along the line DD shown in FIG.
  • FIGS. 44 to 46 show cross sections of regions corresponding to FIGS. 19 to 24, etc., of the first embodiment, and are taken along lines E—E shown in FIG. 39 (CC lines in FIG. 17). Substantially corresponds to the cross-section along
  • the semiconductor chip 2 and the lead frames (conductor members) 21a and 22a are prepared in the same manner as the lead frames 21 and 22 in the first embodiment (steps). Sl).
  • the lead frames 21, 22 are not the entirety of the lead frames 21, 22 for easy understanding. Of these, a region where a single semiconductor device 1 is formed is illustrated. In the plan views of FIGS. 37, 39, and 41 of this embodiment, the lead frames 21a and 22a are wider than those of FIGS. 13, 15, 17, 17, 26, and 27 of the first embodiment. Regions are shown, and the regions shown in FIG. 37, FIG. 39 and FIG. The entire frame 21a, 22a is constructed. A region 71 surrounded by a dotted line in FIG. 37 of the present embodiment substantially corresponds to the region illustrated in the plan views of FIGS. 13, 15, 17, 17, 26, and 27 of the first embodiment. .
  • the lead frames 21a and 22a used in the present embodiment also have the same material force as the lead frames 21 and 22 of the first embodiment, and can be manufactured in substantially the same manner.
  • the lead frames 21a and 22a have substantially the same structure as the lead frames 21 and 22 used in the first embodiment. Therefore, like the lead frame 21 of the first embodiment, the lead frame 21a has the drain terminal portion 25 that becomes the drain terminal 5, as shown in FIGS. That is, the lead frame 21a includes the first portion 25a of the drain terminal portion 25 that becomes the first portion 5a of the drain terminal 5 and the second portion of the drain terminal portion 25 that becomes the second portion 5b of the drain terminal 5. A portion 25b and a stepped portion (folded portion) 25c of the drain terminal portion 25 to be a stepped portion (folded portion) 5c of the drain terminal 5 are formed integrally.
  • the lead frame 22a has a source terminal portion 23 that becomes the source terminal 3 and a gate terminal portion 24 that becomes the gate terminal 4. Are integrally formed. As with the lead frames 21 and 22, the lead frames 21a and 22a are also provided with openings 20a and 20b along the planned cutting positions in order to facilitate the cutting of the lead frames 21a and 22a. .
  • the lead frame 21a is connected to the frame portion 76 to which the drain terminal portion 25 (the second portion 25b) is connected, and to the frame portion 76 through a step portion (folded portion) 77. And an overlapping portion 78, which are integrally formed.
  • the main surface 76a of the frame portion 76 is on the same plane as the lower surface 35c of the second portion 25b of the drain terminal portion 25.
  • the stepped portion 77 connects the frame portion 76 and the overlapping portion 78 having different height positions.
  • the overlapping portion 78 of the lead frame 21a is a portion on which a part of the lead frame 22a is overlapped when the lead frames 21a and 22a are disposed on the semiconductor chip 2 via the solder paste 11a and ib. .
  • the semiconductor chip 2 is soldered on the lead frame 21a as shown in FIGS. (Solder, solder material) 11a etc. are arranged (Step S2). At this time, the front surface 2a side of the semiconductor chip 2 faces upward, and the back surface 2b side of the semiconductor chip 2 (back surface drain The semiconductor chip 2 is disposed on the first portion 25a of the lead frame 2la so that the electrode 2d side) faces the first portion 25a of the lead frame 21a.
  • the semiconductor chip 2 is disposed on the lead frame 21a so that the semiconductor chip 2 (the back surface drain electrode 2d) is disposed on the first portion 25a of the drain terminal portion 25 of the lead frame 21a via the solder paste 11a. Place.
  • the semiconductor chip 2 is temporarily fixed to the lead frame 21a by the adhesiveness (adhesiveness) of the solder paste 11a.
  • the lead frame 22a is disposed on the surface 2a of the semiconductor chip 2 via a solder paste (solder, solder material) ib (step S3).
  • the source terminal portion 23 of the lead frame 22a is disposed on the source pad electrode 2s of the semiconductor chip 2 via the solder paste l ib, and the solder paste l ib is disposed on the gate pad electrode 2g of the semiconductor chip 2.
  • the lead frame 22a is arranged on the lead frame 21a and the semiconductor chip 2 so that the gate terminal portion 24 of the lead frame 22a is arranged.
  • the lead frame 22a is temporarily fixed to the semiconductor chip 2 by the adhesiveness (adhesiveness) of the solder paste l ib. At this time, a part of the lead frame 22a is placed on the overlapping part 78 of the lead frame 21a.
  • the lead frames 21a and 22a are leveled and fixed (step Sll). That is, the lead frame 2 la, 22a is pressed and fixed by using a holding jig (pressing jig) 72, 73. At this time, the upper surface of the lead frames 21a and 22a is pressed by the holding jig 72, and the lower surface of the lead frame 21a is also pressed by the holding jig 73. As a result, the lead frame 21a is in a state where the main surface 76a of the frame portion 76 of the lead frame 21a that contacts (opposes) the holding jig 72 and the main surface 79a of the lead frame 22a are flush with each other (same plane). , 22a is fixed.
  • the holding jigs 72 and 73 are provided with openings 72a and 73a (the opening 72a of the holding jig 72 and the opening 73a of the holding jig 73), and the semiconductor chip 2 and the lead frame 21a
  • the first portion 25a and the source terminal portion 23 and the gate terminal portion 24 of the lead frame 22a are positioned in the openings 72a and 72b of the holding jigs 72 and 73 in plan view. That is, it is more preferable that the holding jigs 72 and 73 have the openings 72a and 73a at positions where they overlap with the semiconductor chip 2 in a plan view.
  • the lead frames 21a, 22a It is possible to prevent the pressure of the semiconductor chip 2 from being applied when pressing and fixing, and the solder pastes 11a and l ib are easily melted in the solder reflow process described later.
  • solder reflow is performed (step S4).
  • the solder reflow process 74 is performed in a state where the lead frames 21a and 22a are pressed and fixed by the holding jigs 72 and 73.
  • the solder reflow process 74 is schematically shown by arrows. This solder reflow process 74 melts and solidifies the solder paste 11a, 1 lb, and connects the source terminal portion 23 of the lead frame 22a and the source pad electrode 2s of the semiconductor chip 2 via the solder 11, as shown in FIG.
  • the gate terminal portion 24 of the lead frame 22a and the gate pad electrode 2g of the semiconductor chip 2 are joined via the solder 11, and the back surface drain electrode 2d of the semiconductor chip 2 and the drain terminal portion 25 of the lead frame 21a are joined. Join through solder 11.
  • Solder paste 11a, l ib melted and solidified by solder reflow becomes solder 11.
  • the lead frames 21 and 22 are pressed and leveled by the holding jigs 72 and 73, fixed, and the solder reflow process is performed in this state. Therefore, the lead frames 21a and 22a move during the solder reflow. Can be prevented.
  • the holding jigs 72 and 73 are removed. Thereafter, washing may be performed as necessary to remove flux and the like.
  • the source terminal portion 23 of the lead frame 22a is read to the gate pad electrode 2g of the surface 2a of the semiconductor chip 2 through the solder 11 to the source pad electrode 2s of the surface 2a of the semiconductor chip 2.
  • the drain terminal portion 25 of the lead frame 2 la is joined to the gate terminal portion 24 of the frame 22 a and the back surface drain electrode 2 d of the back surface 2 b of the semiconductor chip 2.
  • an assembly (work) 30 including the lead frames 21a and 22a and the semiconductor chip bonded between them is obtained.
  • the lead frames 21a and 22a are leveled and fixed by the holding jigs 72 and 73 in step S11, and the solder reflow process in step S4 is performed in this state. Go. Even if the surface tension of the molten solder acts while the solder paste 11a, l ib is melted and solidified by solder reflow and becomes the solder 11, the lead frames 21a, 22a are fixed by the holding jigs 72, 73. Does not move. This prevents the lead frames 21a, 22a from moving during solder reflow (ie, the lead frame 22a from moving relative to the lead frame 21a). Can be stopped.
  • the variation in the height dimension h of the assembly 30 can be suppressed or prevented, and the gate terminal portion 24 of the lead frame 22a and the lower surface 35b of the source terminal portion 23 and the lead frame 21a It is possible to suppress or prevent the parallelism between the first portion 25a of the drain terminal portion 25 and the upper surface 35a of the first portion 25a from varying. That is, in the assembly 30 after solder reflow, the height h of the assembly 30 can be accurately formed according to the standard value (target value), and the gate terminal portion 24 and the source of the lead frame 22a can be formed. The parallelism between the lower surface 35b of the terminal portion 23 and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21a can be increased.
  • a molding process (a resin sealing process, such as a transfer molding process) is performed to form the sealing resin part 6 (step S5).
  • step S5 the molding process of step S5 is performed as follows.
  • the molds 31, 32 (upper mold 31 and lower mold 32) for forming the sealing resin portion 6 are prepared.
  • an elastic sheet (elastic tape) 75a is disposed or attached to the lower surface 31a of the mold 31, and an elastic sheet (elastic tape) 75b is disposed on the upper surface 32a of the mold 32. I prefer to stick it.
  • the elastic sheets 75a and 75b are thin-film members having a thickness of, for example, about 100 ⁇ m.
  • the elastic sheets 75a and 75b are formed of an elastic material and have heat resistance at a temperature during the molding process.
  • the bottom surface 31a of the mold 31 and the top surface of the mold 32 so that the elastic sheets 75a, 75b are arranged on the top and bottom surfaces of the cavities 34 of the molds 31, 32 (that is, the entire inner surface of the cavity 34).
  • the assembly 30 is placed between the molds 31, 32, and the assembly 30 (that is, the lead frames 21, 22 with the semiconductor chip 2 sandwiched between the molds 31, 32) is placed. Clamp and fix with tension.
  • the source terminal portion 23 and gate terminal portion 24 of the lead frame 22, the drain terminal portion 25 of the lead frame 21, and the semiconductor chip 2 between them are arranged in the cavity 34 of the molds 31, 32, Fixed.
  • the elastic sheets 75a and 75b are disposed (attached) on the upper and lower surfaces of the cavities 34 of the molds 31 and 32 as described above, the first of the drain terminal portions 25 of the lead frame 21 is attached.
  • the upper surface 35a of the portion 25a is in close contact with the elastic sheet 75a attached to the lower surface 31a of the mold 31, and the gate terminal portion 2 of the lead frame 22 4 and the lower surface 35b of the source terminal portion 23 and the lower surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 are in close contact with the elastic sheet 75b attached to the upper surface 32a of the mold 32.
  • a sealing resin material 36 which is a material for forming the sealing resin portion 6, is injected into the cavity 34 of the mold 31, 32, and the injected sealing is performed.
  • the resin material 36 is cured to form the sealed resin part 6.
  • the lead frames 21, 22 and the semiconductor chip 2 are made of gold so that the back surface drain electrode 2d side of the semiconductor chip 2 faces downward with FIGS. 45 and 46 turned upside down.
  • the mold 31 is the lower mold and the mold 32 is the upper mold.
  • the assembly 30 (the lead frames 21, 22 with the sealing resin part 6 formed) is formed into a mold 31, Release from 32.
  • the manufacturing process after the formation of the sealing resin portion 6 can be performed in substantially the same manner as in the first embodiment. That is, after the sealing resin part 6 is formed as described above, the slurry or the like of the sealing resin part 6 is removed as necessary. Next, a plating process is performed as necessary to form a plating layer (not shown) on a portion exposed from the sealing resin portion 6 of the lead frames 21a and 22a (portion having a conductor force) (Ste S6). Next, the lead frames 21a and 22a are cut at predetermined positions (step S7). Thereby, the semiconductor device 1 divided into pieces is obtained (manufactured). The structure of the manufactured semiconductor device 1 is the same as that of the semiconductor device 1 shown in FIGS. 1 to 5 of the first embodiment.
  • the solder paste 11a and ib are melted during the solder reflow, and the lead due to the surface tension of the molten solder.
  • the frame 22 may move relative to the lead frame 21. If the lead frame 22 moves relative to the lead frame 21 during solder reflow, the height h of the assembly 30 varies in the assembly 30 after solder reflow, or the gate terminal portion of the lead frame 22 24 and the parallelism between the lower surface 35b of the source terminal portion 23 and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 may vary, and also in FIG. 31 of the first embodiment.
  • the mall When the mold is clamped in the process of forming (sealing resin part 6 forming step), there is a possibility that strong pressure is applied to the semiconductor chip 2 from both the upper and lower sides. If pressure is applied to the semiconductor chip 2 from above and below, cracks or the like may occur in the semiconductor chip 2 and the manufacturing yield of the semiconductor device 1 may decrease.
  • the lead frames 21a and 22a are leveled and fixed by the holding jigs 72 and 73, and the solder reflow process is performed in this state. Even if the surface tension of the molten solder is applied while the solder base 1 la, 1 lb is melted and solidified by solder reflow and becomes the solder 11, the lead frames 21a, 22a are held by the holding jigs 72, 73. Fixed and does not move. Therefore, it is possible to prevent the lead frames 21a and 22a from moving during solder reflow (that is, the lead frame 22a from moving relative to the lead frame 21a).
  • the variation in the height h of the assembly 30 can be suppressed or prevented, and the lead terminal 22 of the lead frame 22a and the lower surface 35b of the source terminal part 23 and the leads can be prevented. It is possible to suppress or prevent variations in parallelism between the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the frame 21a. That is, in the assembly 30 after solder reflow, the height h of the assembly 30 can be accurately formed according to the standard value (target value), and the bottom surfaces of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22a. The parallelism between 35b and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21a can be increased.
  • the problem described in FIG. 31 of the first embodiment (a phenomenon in which the upper and lower side forces are applied to the semiconductor chip 2 when the mold is clamped in the molding process) occurs. It can be suppressed or prevented, the occurrence of cracks in the semiconductor chip 2 can be prevented, and the manufacturing yield of the semiconductor device 1 can be improved.
  • the sheet mold in the molding process for forming the sealing resin portion 6, the sheet mold is performed, and the lower surface 3 la of the upper mold (mold 31) and the lower mold (mold 32).
  • the elastic sheets 75a and 75b are pasted on the upper surface 32a. Therefore, the elastic sheets 75a and 75b are disposed on the upper and lower surfaces of the cavities 34 of the molds 31 and 32 (that is, the entire inner surface of the cavities 34), and the assembly 30 is clamped by the dies 31 and 32.
  • the elastic sheet 7 has the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 attached to the lower surface 31a of the mold 31.
  • the lower surface 35b of the gate terminal 24 and source terminal 23 of the lead frame 22 and the lower surface 35c of the second portion 25b of the drain terminal 25 of the lead frame 21 are attached to the upper surface 32a of the mold 32.
  • the elastic sheet 75b is brought into close contact with the elastic sheet 75b. That is, the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21, the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22, and the drain terminal portion 25 of the lead frame 21.
  • Elastic surfaces 75a and 75b having elasticity are interposed between the lower surfaces 35c of the second portion 25b and the dies 31 and 32 without directly contacting the dies 31 and 32.
  • the clamping pressures of the dies 31 and 32 can be absorbed or alleviated by the elastic sheets 75a and 75b, and the problem described with reference to FIG. 31 of the first embodiment (when the dies are clamped in the molding process) In addition, it is possible to suppress or prevent the occurrence of a strong pressure on the semiconductor chip 2 from above and below.
  • the sealing resin part 6 should be formed by the molding process (sheet molding) using the elastic sheets 75a and 75b as described above.
  • the lead frames 21b and 22b are pressed. Perform solder reflow in step S4 with the tool fixed.
  • 47 to 54 are principal part plan views or principal part sectional views showing the manufacturing steps of the semiconductor device of the present embodiment.
  • 47 to 54, FIG. 47, FIG. 49, and FIG. 48, FIG. 50, and FIGS. 52 to 54 are cross-sectional views (main-part cross-sectional views).
  • 47 and 48 correspond to the same process step
  • FIGS. 49 and 50 correspond to the same process step
  • FIGS. 51 and 52 correspond to the same process step.
  • 48, FIG. 50, FIG. 52, and FIG. 53 substantially correspond to the cross section taken along the line FF shown in FIG.
  • FIG. 54 is a cross-sectional view corresponding to FIG. 44 of the third embodiment, and substantially corresponds to the cross section taken along the line GG (corresponding to the CC line in FIG. 17) shown in FIG.
  • the semiconductor chip 2 and the lead frames (conductor members) 21b and 22b are prepared in the same manner as the lead frames 21a and 22a of the third embodiment (step S). l).
  • the lead frames 21b and 22b used in the present embodiment also have the same material force as the lead frames 21a and 22a of the third embodiment, and can be manufactured in substantially the same manner.
  • the lead frames 21b and 22b have substantially the same structure as the lead frames 21a and 22a used in the third embodiment.
  • the lead frames 21b and 22b lead on the overlapping portion 78 of the lead frame 21a.
  • the lead frames 21b and 22b of the present embodiment have fitting parts 81a and 81b that can be fitted, and these fitting parts 81a and 81b is fitted.
  • the lead frame 21b and the lead frame 22b can be fixed by fitting one of the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b to the other. Since the configurations of the lead frames 21b and 22b other than the vicinity of the fitting portions 81a and 81b are substantially the same as those of the lead frames 21a and 22a of the third embodiment, the description thereof is omitted here.
  • the semiconductor chip 2 is soldered on the lead frame 21b and the solder paste 11a.
  • Step S2 the semiconductor chip 2 is placed on the first portion 25a of the lead frame 21b so that the front surface 2a side of the semiconductor chip 2 faces upward and the back surface 2b side of the semiconductor chip 2 faces the first portion 25a of the lead frame 21b.
  • the lead frame 21b on which the semiconductor chip 2 is mounted is placed on the mounting table 83, the first portion 25a of the lead frame 21b and the semiconductor in the concave portion (recessed portion) 83a of the mounting table 83.
  • the mounting process of the semiconductor chip 2 in step S2 can be performed.
  • the mounting table 83 is not shown for easy viewing of the drawing.
  • the lead frame 22b is disposed on the surface 2a of the semiconductor chip 2 via the solder paste ib (step S3). That is, the source terminal portion 23 of the lead frame 22b is disposed on the source pad electrode 2s of the semiconductor chip 2 via the solder paste l ib and the like, and the solder paste l ib is disposed on the gate pad electrode 2g of the semiconductor chip 2 and the like. Then, the lead frame 22b is disposed on the lead frame 2 lb and the semiconductor chip 2 so that the gate terminal portion 24 of the lead frame 22b is disposed.
  • the lead frame 22b is placed on the surface 2a of the semiconductor chip 2 via the solder paste l ib using a tool (lead frame mounting tool, suction tool) 84 ( Mount.
  • the tool 84 is configured to hold the lead frame 22b by, for example, suction from the suction hole 84a and move to a predetermined position.
  • the suction hole 84a is provided at the position shown in FIG. If the suction hole 84a is provided at the position shown in FIG. 49, the suction hole 84a does not appear in the cross section of FIG.
  • FIG. 50 (appears in the other cross sections), but in order to simplify the understanding,
  • the cross-sectional view of FIG. 50 also shows the suction hole 84a.
  • 51 and 52 show a state in which the mounting table 83 and the tool 84 are not shown in the state after the mounting process of the lead frame 22b in step S3.
  • the lead frames 21b and 22b have the fitting portions 81a and 81b that can be fitted. For this reason, in the mounting process of the lead frame 22 in step S3 of the present embodiment, one of the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b is fitted to the other to lead the lead frame 21b. And lead frame 22b are fixed.
  • the lead frame 21b and the lead frame 22b are sandwiched between the tool 84 and the mounting table 83, and the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b are fitted to fix the lead frame 21b and the lead frame 22b. Therefore, the lead frames 21b and 22b are fixed in a leveled state.
  • the lead frames 21b and 22b are fixed by fitting the fitting portions 81a and 81b in a state where they are flush with (a same plane) 79a. Therefore, in the present embodiment, the mounting of the lead frame 22b in step S3 and the leveling and fixing of the lead frames 21b and 22b in step S4 are performed in the same process.
  • step S4 After taking out the lead frames 21b and 22b from the mounting table 83, as shown in FIG. 53, a solder reflow process 74 is performed (step S4).
  • step S4 In the present embodiment, as described above, in the state where the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b are fitted and the lead frame 21b and the lead frame 22b are fixed, The solder reflow process in step S4 is performed. This solder reflow melts and solidifies the solder paste 11a, ib, and joins the source terminal part 23 of the lead frame 22a and the source pad electrode 2s of the semiconductor chip 2 via the solder 11, as shown in FIG. Then, the gate terminal part 24 of the lead frame 22a and the gate pad electrode 2g of the semiconductor chip 2 are joined via the solder 11, and the back surface drain electrode 2d of the semiconductor chip 2 and the drain terminal part 25 of the lead frame 21a are soldered. Join through 11.
  • solder paste 11a, l ib force solder 11 is melted and solidified by solder reflow.
  • the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b are fitted and the lead frames 21b and 22b are leveled and fixed, and the solder reflow process is performed in this state. Therefore, it is possible to prevent the lead frames 21b and 22b from moving during solder reflow.
  • the flux or the like can be removed by washing as necessary.
  • the lead terminal 22 of the lead frame 22a is read to the source pad electrode 2s of the surface 2a of the semiconductor chip 2 via the solder 11, and the gate pad electrode 2g of the surface 2a of the semiconductor chip 2 is read.
  • the drain terminal portion 25 of the lead frame 21a is joined to the gate terminal portion 24 of the frame 22a and the back surface drain electrode 2d of the back surface 2b of the semiconductor chip 2.
  • an assembly (work) 30 including the lead frames 21a and 22a and the semiconductor chip bonded between them is obtained.
  • FIG. 5 A semiconductor device similar to the semiconductor device 1 shown in FIG. 5 is manufactured.
  • the fitting portion 81a of the lead frame 21b and the fitting portion 81b of the lead frame 22b are fitted and the lead frames 21b and 22b are leveled and fixed in this state.
  • a solder reflow process is performed. For this reason, it is possible to obtain substantially the same effect as in the third embodiment. In other words, even if the surface tension of the molten solder acts while the solder paste 11a, l ib is melted and solidified by solder reflow and becomes the solder 11, the lead frames 21b, 22b are fitted to each other at the fitting portions 81a, 81b.
  • the lead frames 21b and 22b from moving during solder reflow (ie, the lead frame 22b from moving relative to the lead frame 21b). it can. Therefore, in the assembly 30 after the solder reflow, the variation in the height h of the assembly 30 can be suppressed or prevented, and the gate terminal portion 24 of the lead frame 22b and the lower surface 35b of the source terminal portion 23 and the lead frame It is possible to suppress or prevent variations in the parallelism between the upper surface 35a and the first portion 25a of the drain terminal portion 25 of 21b. That is, in the assembly 30 after the solder reflow, the height h of the assembly 30 can be accurately formed according to the standard value (target value), and the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22b.
  • target value the standard value
  • the parallelism between the lower surface 35b of the lead frame 21b and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21b can be increased. As a result, it is possible to suppress the occurrence of the problem described in FIG. 31 of the first embodiment (a phenomenon in which a strong pressure is applied to the semiconductor chip 2 when the mold is clamped in the molding process). It is possible to prevent the occurrence of cracks in the semiconductor chip 2 and to improve the manufacturing yield of the semiconductor device 1.
  • the shapes of the fitting portions 81a and 81b of the lead frames 21b and 22b can be variously changed.
  • FIG. 55 is a plan view of a principal part showing an example of a state in which the fitting portions 81a and 81b of the lead frames 21b and 22b are fitted together.
  • the fitting portions 81a and 81b that are fitted to each other are disengaged by providing irregularities on the fitting portion 81b (that is, at least one of the fitting portions 81a and 81b) of the lead frame 22b. become. For this reason After fixing the lead frames 21b and 22b by fitting the mating portions 81a and 81b, it is possible to more accurately prevent the lead frames 21b and 22b from being displaced due to a load or the like.
  • FIG. 56 to 59 are principal part plan views or principal part sectional views showing other examples of the fitting parts 81a, 81b of the lead frames 21b, 22b.
  • FIG. 56 shows a plan view of the main part of the fitting portion 81a of the lead frame 21b.
  • FIG. 57 shows the fitting portion 81a of the lead frame 21b of FIG.
  • FIG. 58 shows a cross-sectional view (cross-sectional view of the main part) taken along line H—H in FIG.
  • FIG. 59 shows a cross-sectional view (essential cross-sectional view) taken along line JJ in FIG.
  • FIG. 56 is a plan view of the force, and the lead frame 2 lb is hatched to make it easy to see.
  • 60 and 61 are fragmentary cross-sectional views showing the manufacturing steps of the semiconductor device of the present embodiment.
  • the solder reflow in step S4 is performed in a state where the lead frame (21a, 22a or 21b, 22b) is fixed, thereby increasing the height in the assembly 30 after the solder reflow.
  • the dimension h is accurately formed according to the standard value (target value), and the lower surface 35b of the gate terminal 24 and the source terminal 23 23 and the first portion 25a of the drain terminal 25 in the assembly 30 The degree of parallelism with the upper surface 35a was increased.
  • step S4 the solder reflow of step S4 is performed with the lead frames 21c, 22c (corresponding to the lead frames 21a, 22a or 21b, 22b) fixed as in the third and fourth embodiments. Even if it is performed, as shown in FIG. 60, the lower surface 35 5b of the lead terminal 22 and the source terminal 23 of the lead frame 22c (corresponding to the lead frame 22a or 22b) in the assembly 30 and the lead frame 21c (lead If the parallelism between the drain terminal part 25 of the first part 25a of the frame 21a or 21b) and the upper surface 35a of the first part 25a is low, the following process may be performed before the molding process. .
  • the lead frame 22c is arranged on the mounting table 86 so that the lower surfaces 35b of the gate terminal portion 24 and the source terminal portion 23 are in contact with (being opposed to) the mounting table 86, and the drain terminal of the lead frame 21c of this assembly 30
  • the holding member 87 is arranged on the assembly 30 so as to contact (oppose) the upper surface 35a of the first portion 25a of the part 25, and reheating (for example, about 350 ° C.) is performed to remelt the solder 11. .
  • step S5 can be performed in the same manner as in the third and fourth embodiments.
  • the gate terminal portion 24 of the lead frame 22c and the lower surface 35b of the source terminal portion 23 in the assembly 30 and the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21c Even if the parallelism between the two is low, the solder 11 is remelted after the solder reflow process in step S4 and before the molding process in step S5, and the lead frames 21c and 22c are leveled. The parallelism between the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 and the upper surface 35a of the first portion 25a of the drain terminal portion 25 can be further increased.
  • FIG. 62 is a process flow diagram showing a manufacturing process of the semiconductor device la of the present embodiment.
  • 63 to 68 are cross-sectional views of relevant parts showing the manufacturing steps of the semiconductor device la of the present embodiment.
  • the semiconductor device la of the present embodiment can be manufactured as follows, for example.
  • step S 1 to S4 the same steps (steps S 1 to S4) as in the first embodiment are performed to obtain an assembly (workpiece) 30 having the structure in FIG. 63 similar to that in FIG. 19 in the first embodiment.
  • Step 21 Since the process of forming the assembly 30 is the same as that in the first embodiment (steps S1 to S4), the description thereof is omitted here.
  • the assembly 30 is composed of the lead frames 21 and 22 and the semiconductor chip 2 bonded between them, and leads to the source pad electrode 2 s on the surface 2a of the semiconductor chip 2.
  • the source terminal portion 23 of the frame 22 is joined via the solder 11
  • the gate terminal portion 24 of the lead frame 22 is joined via the solder 11 to the gate pad electrode 2g of the front surface 2a of the semiconductor chip 2, and the back surface of the semiconductor chip 2
  • the drain terminal portion 25 of the lead frame 21 is joined to the back surface drain electrode 2d of 2b via the solder 11.
  • the assembly 30 is attached (adhered) to an adhesive sheet (adhesive tape, adhesive film, adhesive sheet, adhesive tape, adhesive film) 91 and fixed (steps).
  • the adhesive sheet 91 has an adhesive layer (adhesive layer, adhesive layer) having adhesiveness (adhesiveness) on one main surface 91a, and the adhesive surface (adhesiveness) has an adhesive layer (adhesiveness) on the main surface 91a.
  • Assembly 30 is affixed.
  • the pressure-sensitive adhesive sheet 91 is coated with an adhesive (adhesive) on one main surface of a plastic film (for example, a plastic film having a heat resistance of about 180 ° C.
  • the assembly 30 is affixed to the adhesive sheet 91, the lower surface 35c of the second portion 25b of the drain terminal portion 25 of the lead frame 21 is adhered (contacted, contacted) to the main surface 91a of the adhesive sheet 91, and The gate terminal portion 24 of the lead frame 22 and the lower surface 35b of the source terminal portion 23 are bonded (adhered to, or in contact with) the main surface 91a of the adhesive sheet 91.
  • a frame (dam, frame) 92 is formed on the main surface 91a of the adhesive sheet 91.
  • the main part of the pressure-sensitive adhesive sheet 91 is arranged so that the semiconductor chip 2 and the source terminal part 23, the gate terminal part 24, and the drain terminal part 25 bonded to the semiconductor chip 2 are disposed (accommodated) in the opening 92a of the frame 92.
  • a frame 92 is mounted on the surface 91a. For this reason, the periphery of each semiconductor chip 2 in the assembly 30 is surrounded by the frame 92.
  • the frame 92 also has a plastic material force, for example.
  • a sealing resin material 93 that is a material for forming the sealing resin portion 6 is dropped into each opening 92a of the frame 92 by potting or the like.
  • Fill (step S24) At this time, the second portion 25b and stepped portion 25c of the drain terminal portion 25 of the lead frame 21 and the gate terminal portion 24 and source terminal portion 23 of the lead frame 22 and the semiconductor chip 2 are embedded in the sealing resin material 93.
  • the sealing is performed to fill each opening 92a of the frame 92 so that the upper surface 35a of the first portion 25a of the drain terminal portion 25a of the lead frame 21 is exposed without being filled with the sealing resin material 93. Adjust the amount of grease material 93.
  • the sealing resin material 93 is made of a resin material such as a thermosetting resin material and can contain a filler.
  • a filler for example, an epoxy resin containing a filler can be used.
  • the sealing resin material 93 filled in each opening 92a of the frame 92 is cured by heat treatment or the like to form the sealing resin part 6 (step S25).
  • the pressure-sensitive adhesive sheet 91 and the frame body 92 preferably have heat resistance equal to or higher than the curing temperature (for example, about 180 ° C) of the sealing resin material 93.
  • the heat resistance temperature of the pressure-sensitive adhesive sheet 91 and the frame 92 is 180 ° C or higher, and more preferable if it is 200 ° C or higher.
  • steps S24 and S25 as described above, the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the upper surface 32a of the mold 32 are adhered to the main surface 91a of the adhesive sheet 91.
  • the sealing resin material 93 is filled in the opening 92 a of the frame 92 and cured to form the sealing resin part 6. Therefore, on the back surface 6b of the formed sealing resin portion 6, the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the second portion 25b of the drain terminal portion 25 of the lead frame 21 35c is exposed.
  • the sealing resin part 6 is formed in this way, the adhesive sheet 91 and the frame body 92 are removed from the assembly 30 in which the sealing resin part 6 is formed (step S26). Thereafter, the dust or the like in the sealing resin portion 6 can be removed as necessary. As a result, an assembly 30a as shown in FIG. 67 is obtained.
  • the assembly 30 a is obtained by forming the sealing resin portion 6 on the assembly 30.
  • the formed sealing resin portion 6 has an upper surface 6a and a rear surface 6b, which are two main surfaces located on opposite sides of each other. In the assembly 30a, the sealing resin portion 6 seals the semiconductor chip 2, the source terminal portion 23, the gate terminal portion 24, and the drain terminal portion 25.
  • the steps after the formation of the sealing resin portion 6 can be performed in substantially the same manner as in the first embodiment. That is, a plating process is performed as necessary to form a plating layer (not shown) on the portions exposed from the sealing resin portions 6 of the lead frames 21 and 22 (portions made of a conductor) (step S27). ). For example, soldering treatment such as lead-free soldering can be performed.
  • the lead frames 21 and 22 are cut at predetermined positions (step S28). That is, the lead frames 21 and 22 protruding from the sealing resin portion 6 are removed.
  • FIG. 68 corresponds to FIG. 28 (that is, FIG. 4) of the first embodiment.
  • the sealing resin portion 6 has a substantially rectangular parallelepiped shape. Except for the outer shape of the sealing resin portion 6, the semiconductor device la of the present embodiment has substantially the same structure as the semiconductor device 1 of the first embodiment (semiconductor device 1 of FIGS. 1 to 5). Therefore, the explanation is omitted here.
  • FIGS. 69 to 72 are principal part plan views (FIGS. 69 and 70) or principal part sectional views showing the manufacturing steps of the semiconductor device of the present embodiment in the case of using the lead frames 21 and 22 of the multiple structure.
  • Fig. 71 and Fig. 72 Fig. 69 (Principal part plan) corresponds to the same process step as Fig. 64, and Fig. 70 (Principal part plan view) and Fig. 71 (Principal part sectional view) It corresponds to the same process step as in Fig. 65, and Fig.
  • FIG. 72 (sectional view of the main part) corresponds to the same process step as in Fig. 66 above. 71 corresponds to the cross-sectional view taken along the line K-K of FIG. 70, and FIG. 72 shows a cross-section of the same region as FIG.
  • the overall structure of the lead frames 21 and 22 shown in FIGS. 69 to 72 is almost the same as the lead frames 21a and 22a described in the third embodiment and the lead frames 21b and 22b described in the fourth embodiment. Since it is the same, the explanation is omitted here.
  • step S22 After forming the assembly 30 using the lead frames 21 and 22 having the multiple structure, in step S22, the assembly 30 is pasted on the main surface 91a of the adhesive sheet 91 as shown in FIG. Then, in step S23, as shown in FIG. 70 and FIG. 71, the frame body 92 is pasted and fixed on the main surface 91a of the adhesive sheet 91. As shown in FIG. 69 and FIG. 70, the lower surface of the frame body 92 is bonded and fixed onto the main surface 91a of the adhesive sheet 91 in a region other than the region where the lead frames 21 and 22 are bonded.
  • the opening 92b that accommodates the other protrusions of the lead frames 21 and 22 is formed only by the opening 92a that accommodates the semiconductor chip 2 and the source terminal 23, the gate terminal 24, and the drain terminal 25 that are joined to the semiconductor chip 2. If the frame body 92 is provided, it is possible to prevent the lead frames 21 and 22 from being deformed when the frame body 93 is attached to the adhesive sheet 91. Thereafter, in step S24, as shown in FIG. 72, the sealing resin material 93 is dropped into each opening 92a of the frame 92, and in step S25, the sealing resin material 93 is hardened and sealed. Formation of the greave part 6. In step S24, the force of dropping the sealing resin material 93 into each opening 92a of the frame 92. The sealing resin material 93 is not dropped into the opening 92b. Thereafter, by performing steps S26 to S28, the semiconductor device la is manufactured.
  • the frame body 92 in a state where the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the upper surface 32a of the mold 32 are in close contact with the main surface 91a of the adhesive sheet 91.
  • the sealing resin material 93 is filled in the opening 92a of the resin and cured to form the sealing resin part 6. Yes. Therefore, on the back surface 6b of the formed sealing resin portion 6, the lower surface 35b of the gate terminal portion 24 and the source terminal portion 23 of the lead frame 22 and the lower surface of the second portion 25b of the drain terminal portion 25 of the lead frame 21 35c is exposed.
  • the sealing resin material 93 when the sealing resin material 93 is filled in the opening 92 a of the frame 92, the upper surface 35 a of the first portion 25 a of the drain terminal portion 25 of the lead frame 21 is embedded in the sealing resin material 93. In this state, the sealing resin material 93 is cured to form the sealing resin part 6. Therefore, the upper surface 35a of the first portion 25a of the drain terminal portion 25 of the lead frame 21 is exposed on the upper surface 6a of the formed sealing resin portion 6. Thereby, the conductor portions (source terminal portion 23, gate terminal portion 24 and drain terminal portion 25) can be exposed on both the upper surface 6a and the back surface 6b of the sealing resin portion 6.
  • the semiconductor device la of the present embodiment is similar to the semiconductor device 1 of the first embodiment, and the source terminal 3, the gate terminal 4, and the drain terminal 5 (of the back surface lb of the semiconductor device 1)
  • the second portion 5b) is exposed as an external connection terminal
  • the upper surface 5e of the first portion 5a of the drain terminal 5 is exposed at the upper surface la of the semiconductor device la (upper surface 6a of the sealing resin portion 6). Accordingly, the heat generated by the semiconductor chip 2 in the semiconductor device la is transferred to the back surface lb side of the semiconductor device la (the second portion 5b of the source terminal 3, the gate terminal 4, and the drain terminal 5) and the upper surface la side (the drain terminal).
  • Heat can be radiated from both sides (both sides) of the first part 5a).
  • the heat dissipation characteristics (heat dissipation) of the semiconductor device in the form of a resin-encapsulated semiconductor package can be improved, and the performance can be improved.
  • the sealing resin part 6 is formed without using a mold, and the sealing resin material 93 is placed in each opening 92a of the frame 92 by potting or the like. By filling and curing, the sealing resin portion 6 is formed. For this reason, strong pressure is not applied to the semiconductor chip 2 from the upper and lower sides during the formation process of the sealing resin part 6 (filling and curing process of the sealing resin material 93). This suppresses or prevents the occurrence of the problem described in FIG. 31 of the first embodiment (a phenomenon in which strong pressure is applied to the semiconductor chip 2 when the mold is clamped in the molding process). Therefore, the generation of cracks in the semiconductor chip 2 can be prevented, and the manufacturing yield of the semiconductor device la can be improved.
  • sealing is performed in each opening 92a of frame 92 by potting or the like.
  • the resin material 93 is dropped, and the sealing resin material 93 is cured to form the sealing resin part 6. Therefore, the upper surface 35a of the first portion 25a of the drain terminal portion 25 can be slightly protruded from the upper surface 6a of the sealing resin portion 6. That is, the upper surface 5e of the first portion 5a of the drain terminal 5 of the manufactured semiconductor device la can be slightly protruded from the upper surface 6a of the sealing resin portion 6.
  • the first portion 5a (upper surface 5e) of the drain terminal 5 slightly protrudes from the upper surface 6a of the sealing resin portion 6 on the upper surface of the semiconductor device la.
  • the first portion 5a of the drain terminal 5 of the semiconductor device la and the heat conducting sheet 54 Can be further improved.
  • the thermal conductivity between the first portion 5a of the drain terminal 5 of the semiconductor device la and the heat conductive sheet 54 can be improved, and the heat generated in the semiconductor chip 2 is transferred to the drain terminal 5 and the heat conductive sheet 54.
  • the heat can be accurately radiated by a heat radiating component such as the heat radiating fin 55 through the heat sink. Therefore, the heat dissipation efficiency of the semiconductor device la can be further improved.
  • the present invention is suitable for application to a manufacturing technique of a semiconductor device in the form of a resin-sealed semiconductor package.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne une électrode de grille raccordée à une électrode de pastille de grille sur un plan avant d'une puce semi-conductrice (2) et une électrode de source (3) raccordée à une électrode de pastille de source (2s) qui sont exposées à partir d'un plan arrière (6b) d'une partie de résine de scellement (6). Une première partie (5a) d'une borne de drain (5) raccordée à une électrode de drain de plan arrière (2d) de la puce semi-conductrice (2) est exposée à partir d'un plan supérieur (6a) de la partie de résine de scellement (6) et une seconde partie (5b) de la borne de drain (5) faisant partie intégrante avec la première partie (5a) est exposée à partir du plan arrière (6b) de la partie de résine de scellement (6). Au moment de la fabrication d'un tel dispositif semi-conducteur (1), la première partie (5a) de la borne de drain (5), la borne de grille et la borne de sources (3) sont liées sur la puce semi-conductrice (2) au moyen d'une soudure (11), puis la puce semi-conductrice est disposée dans une cavité d'une matrice métallique, la matrice métallique est fixée dans un état où la soudure (11) est fondue, un matériau de résine de scellement est introduit dans la cavité de la matrice métallique après que la soudure (11) s’est solidifiée et une partie de résine de scellement est formée.
PCT/JP2005/006741 2005-04-06 2005-04-06 Procede de fabrication d’un dispositif semi-conducteur WO2006114825A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/006741 WO2006114825A1 (fr) 2005-04-06 2005-04-06 Procede de fabrication d’un dispositif semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/006741 WO2006114825A1 (fr) 2005-04-06 2005-04-06 Procede de fabrication d’un dispositif semi-conducteur

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WO2006114825A1 true WO2006114825A1 (fr) 2006-11-02

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082323A (ja) * 2009-10-07 2011-04-21 Renesas Electronics Corp 半導体装置の製造方法
CN105489508A (zh) * 2015-12-24 2016-04-13 江苏长电科技股份有限公司 一种防止芯片偏移的夹芯封装工艺方法

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JPH10189626A (ja) * 1996-12-24 1998-07-21 Nippon Retsuku Kk 電子部品の製造方法
JP2000294580A (ja) * 1999-04-12 2000-10-20 Nitto Denko Corp 半導体チップの樹脂封止方法及びリ−ドフレ−ム等貼着用粘着テ−プ
JP2000294673A (ja) * 1999-04-01 2000-10-20 Miyazaki Oki Electric Co Ltd 半導体装置の製造方法
JP2003508832A (ja) * 1999-08-26 2003-03-04 インフィネオン テクノロジーズ アクチェンゲゼルシャフト スマートカードモジュールおよびスマートカードモジュールを含むスマートカード、ならびにスマートカードモジュールを製造するための方法
JP2004266096A (ja) * 2003-02-28 2004-09-24 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
JP2005051130A (ja) * 2003-07-31 2005-02-24 Nec Electronics Corp リードレスパッケージ型半導体装置とその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189626A (ja) * 1996-12-24 1998-07-21 Nippon Retsuku Kk 電子部品の製造方法
JP2000294673A (ja) * 1999-04-01 2000-10-20 Miyazaki Oki Electric Co Ltd 半導体装置の製造方法
JP2000294580A (ja) * 1999-04-12 2000-10-20 Nitto Denko Corp 半導体チップの樹脂封止方法及びリ−ドフレ−ム等貼着用粘着テ−プ
JP2003508832A (ja) * 1999-08-26 2003-03-04 インフィネオン テクノロジーズ アクチェンゲゼルシャフト スマートカードモジュールおよびスマートカードモジュールを含むスマートカード、ならびにスマートカードモジュールを製造するための方法
JP2004266096A (ja) * 2003-02-28 2004-09-24 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
JP2005051130A (ja) * 2003-07-31 2005-02-24 Nec Electronics Corp リードレスパッケージ型半導体装置とその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082323A (ja) * 2009-10-07 2011-04-21 Renesas Electronics Corp 半導体装置の製造方法
CN105489508A (zh) * 2015-12-24 2016-04-13 江苏长电科技股份有限公司 一种防止芯片偏移的夹芯封装工艺方法

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