WO2006112968A1 - Appareil destine a ameliorer la largeur de bande pour des circuits possedant des dispositifs de commande a memoire multiple - Google Patents

Appareil destine a ameliorer la largeur de bande pour des circuits possedant des dispositifs de commande a memoire multiple Download PDF

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Publication number
WO2006112968A1
WO2006112968A1 PCT/US2006/008447 US2006008447W WO2006112968A1 WO 2006112968 A1 WO2006112968 A1 WO 2006112968A1 US 2006008447 W US2006008447 W US 2006008447W WO 2006112968 A1 WO2006112968 A1 WO 2006112968A1
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WIPO (PCT)
Prior art keywords
memory controller
access
external
memory
data bus
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PCT/US2006/008447
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English (en)
Inventor
Eric Matulik
Original Assignee
Atmel Corporation
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Publication date
Priority claimed from FR0503811A external-priority patent/FR2884629B1/fr
Application filed by Atmel Corporation filed Critical Atmel Corporation
Priority to GB0721911A priority Critical patent/GB2441668A/en
Priority to DE112006000758T priority patent/DE112006000758T5/de
Publication of WO2006112968A1 publication Critical patent/WO2006112968A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Definitions

  • the present invention relates to memory controllers. More specifically, the present invention relates to control circuits for multiple memory controllers.
  • An integrated micro-controller device includes a microprocessor, on-chip memories, an interface with external memories including an external bus interface (EBI) used to run application software, a number of standard peripheral modules configured to communicate with the external devices such as an universal asynchronous receiver/transmitter (UART) , a serial peripheral interface (SPI) , a parallel I/O chip (PIO) , or a universal serial bus (USB) , and modules to generate interruptions like an interrupt controller, or a timer.
  • EBI external bus interface
  • UART universal asynchronous receiver/transmitter
  • SPI serial peripheral interface
  • PIO parallel I/O chip
  • USB universal serial bus
  • the EBI generates signals required to drive external memories such as a static RAM (SRAM) memory controller; a flash memory controller; a burst flash memory controller; a synchronous dynamic RAM (SD-SDRAM) memory controller; a double date rate synchronous memory controller (DDR-SDRAM) ; a reduced latency dynamic RAM memory controller, an EEPROM, or a read only memory (ROM) .
  • SRAM static RAM
  • SD-SDRAM synchronous dynamic RAM
  • DDR-SDRAM double date rate synchronous memory controller
  • ROM read only memory
  • these signals like chip select signals, and/or control signals (read/write, enable, strobe) are transmitted using a control bus, an address bus, and/or a data bus.
  • a micro-controller utilizes an external bus interface (EBI) . If this is the case, an EBI may drive several memory devices of different types, like SDRAM, SRAM, and flash, at the same time by generating the corresponding signals for each memory it targets.
  • EBI external bus interface
  • the EBI module is often connected on the internal system bus as a slave executing the actions required by the microprocessor which acts as a master in a simplified architecture.
  • the master is able to read/write data from/into the internal memory (RAM) or external memories .
  • Internal memories are often faster than external memory but smaller.
  • a set of data that requires fast access time (such as interrupt handler software, or any set of data which size is small enough) resides at on-chip memories.
  • the address decoder asserts the internal selection signal .
  • the EBI is not selected in this case.
  • a large set of data that can be processed at a slower access time resides at the external memory.
  • the address decoder asserts the internal selection signal .
  • the EBI modules translate the system bus waveforms protocol into the targeted memory waveform protocol .
  • the EBI asserts the "wait" signal to indicate the master that no other access is possible.
  • the master postpones its next access whatever the destination of the new access is. For example, if the next access target is the external memory, it will postponed because of the wait state which has been asserted to prevent an access to the external bus.
  • This architecture becomes especially burdensome when several masters are connected on a single system bus to a plurality of slave devices because all of the masters will be put in wait states.
  • the master having initiated the transfer of data, will not be allowed to process any transfer of data to or from other slaves.
  • FIG. 1 depicts a prior art system architecture 10 with a micro-controller 12 connected to different types of external memories, such as a static RAM (SRAM) memory 14 and a synchronous dynamic RAM (SDRAM) memory by utilizing an external bus interface (EBI) (not shown) .
  • SRAM static RAM
  • SDRAM synchronous dynamic RAM
  • EBI external bus interface
  • the EBI may drive several memory devices of different types, like SRAM 14 and SDRAM 16 by generating the corresponding signals for each memory it targets.
  • a common port mapping for the EBI includes a single address bus 18, a bi-directional data bus and different control signals.
  • the "chip selects" signals are unique for each memory device. For instance, the chipsel_sram signal 22 is used to select the SRAM memory device 14, whereas the chipsel_sdram signal 24 is utilized to select the SDRAM memory device 16.
  • Each type of memory device requires other specific control signals, like a byte enable signal (not shown) for SRAM 14, and a bank addressing signal (not shown) for SDRAM 16. As it is well known to those skillful in the art, the data transfer cannot occur at the same time on more than one external memory device. Therefore, each control signal output of the micro-controller should have multiple functions to accommodate the needs of different memory devices .
  • FIG. 2 illustrates a basic prior art microcontroller architecture 40 in more details.
  • the EBI module 42 is often connected on the internal system bus (including an internal address bus 46, an internal data bus 50, an internal read data bus 48, and an internal write data bus 44) as a slave, that is EBI executes the actions required by the microprocessor 52 which acts as a master in a simplified architecture.
  • the master-slave model the master
  • microprocessor 52 is able to read/write data from/into the internal memory, like ROM, or SRAM on-chip memories 54, or to read/write data from/to the External memories (not shown) .
  • An internal memory is in most cases faster than an external memory, but has a lesser data capacity. Therefore, the data that requires a fast access time, such as an interrupt handler software, or any data which size is small enough, is targeted into on-chip memories.
  • the master sets the internal address bus 46 to a value targeting an on-chip memory 54 (for example, the SRAM memory)
  • the address decoder 56 asserts the internal "sel_intram" internal selection signal 58.
  • the EBI 42 is not selected in this case .
  • a large set of data that accepts a slower access time can be stored in the external memory. If this is the case, when the master (microprocessor 52) starts an access to/from an external memory, the address decoder 56 asserts the internal "sel_ebi" selection signal 60 via the EBI module 42 that translates the system bus waveforms protocol into the targeted external memory waveform protocol . When an external memory (not shown) requires more than one system bus clock cycle to be accessed, the EBI 42 asserts the "wait" signal (not shown) to indicate the master
  • microprocessor 52 that no other access to any kind of destination device is possible. If this is the case, the master (microprocessor 52) postpones its next access to any other device.
  • the master that initiated the transfer to any type of device that requires more than one system bus clock cycle to be accessed will not be allowed to process any transfer to any other device until the first transfer is completed.
  • FIG. 3 illustrates a prior art architecture 70 wherein the EBI has several sub-modules, including a SRAM memory controller 72, and a SDRAM memory controller 74.
  • the "Sel_ebi" signal 60 of FIG. 2 includes a plurality of selection signals, whereas each memory controller is assigned its own selection signal.
  • the SDRAM memory controller 74 is assigned the selection signal "sel_extsdram" 78, and the SRAM memory controller 72 is assigned the selection signal "sel_extsram" 76.
  • the multiplexers MUXl 80 and MUX2 82 are required to share the external address bus 84 and the external data bus 86. If the SRAM memory (not shown) is selected, the "external address bus" 84 is driven by the SRAM controller 72.
  • the multiplexer MUX3 88 allows the SRAM memory controller 72 and the SDRAM memory controller 74 to share the internal read data bus 90.
  • "wait" signal 92 is performed at each memory controller level, taking into account the specific characteristics of the memory being driven and at the EBI level where it is necessary to collect all the - S -
  • memory controllers wait information and report a single signal. This is the function of 2_input OR gate 94.
  • FIG. 4 depicts prior art waveforms for a system including a read access to an external memory requiring one wait state and requiring roughly one clock cycle to release the data bus after the external memory has been de-selected.
  • time data float The time required to completely release the data bus after the external memory de-selection is called "time data float" (TDF) .
  • the EBI asserts the wait signal 116 for three wait cycles 122, though Dl Data value 120 on the EBI data bus 112 is available after only one wait cycle. This is done to prevent any other transfer on EBI until the EBI data bus 112 is released, i.e. until time T2 126 on the system bus clock 102.
  • the wait signal is asserted for the wait period 122 equal to the time data float period TDF. Therefore the next access to external memory cannot start before T2 126.
  • the present invention provides an apparatus for improving a bandwidth for circuits having multiple memory controllers by generating a plurality of busy signals that are configured to indicate when the next external access to the data bus is allowed, thus improving the data throughput .
  • One aspect of the present invention is directed to an apparatus featuring a data bus, a memory controller, a first output signal circuit, and a second output signal circuit .
  • the first output signal is configured to indicate when the memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the memory controller
  • the second output signal is configured to indicate when the memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the memory controller.
  • the apparatus of the present invention employs a first input signal circuit and a second input signal circuit.
  • the first input signal is configured to indicate when the data bus is released by an external memory controller for a read access by the memory controller
  • the second input signal is configured to indicate when the external bus is released by the external memory controller for a write access by the memory controller.
  • the memory controller delays all external accesses to the data bus subsequent to an initial write access to the data bus.
  • the memory controller anticipates a next external access to the address bus subsequent to an initial read access to the data bus by performing a next access command using the address bus .
  • Another aspect of the present invention is directed to an apparatus for improving bandwidth for circuits having a plurality of memory controllers.
  • This architecture includes a first memory controller, a second memory controller, a first first_memory_controller _output signal circuit, a second first_memory__controller _output signal circuit, a first second_memory_controller _output signal circuit, and a second second_memory _controller_output signal circuit.
  • the first first_memory_controller_output signal is configured to indicate when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller.
  • the second_first_memory_controller__output signal is configured to indicate when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller.
  • the first second_memory _controller_output signal is configured to indicate when the second memory controller releases the address bus for an external access subsequent to a read access to the data bus by the second memory controller.
  • the second second_memory_controller_output signal is configured to indicate when the second memory controller releases the data bus for an external access subsequent to a write access to the data bus by the second memory controller.
  • FIG. 1 depicts a prior art system architecture with a micro-controller connected to external memories, like a Static RAM (SRAM) memory and a synchronized dynamic RAM (SDRAM) memory.
  • SRAM Static RAM
  • SDRAM synchronized dynamic RAM
  • FIG. 2 illustrates a basic prior art microcontroller architecture.
  • FIG. 3 shows the prior art architecture of the external bus interface (EBI) having several sub-modules, including a SRAM memory controller, and a SDRAM memory controller.
  • EBI external bus interface
  • FIG. 4 illustrates prior art waveforms for a system including a read access to an external memory requiring one wait state and requiring roughly one clock cycle to release the data bus after the external memory has been de-selected.
  • FIG. 5 depicts the apparatus of the present invention for improving bandwidth for circuits having a plurality of memory controllers and a plurality of busy signal circuits.
  • FIG. 6 illustrates timing diagrams for the apparatus of FIG. 5 having two clocks gain in throughput.
  • FIG. 7 illustrates timing diagrams with a gain in throughput for the apparatus of FIG. 5 when an external read access is followed by an external access.
  • FIG. 8 illustrates timing diagrams with a gain in the throughput of the apparatus of FIG. 5 when an external write access is followed by an external access.
  • the EBI apparatus 140 of the present invention for improving bandwidth for circuits 140 has a first (SRAM) memory controller 142 in parallel to a second (SDRAM ) memory controller 144.
  • a first first_memory__controller_output signal circuit 146 asserts a busy_read_out sram controller output signal 8.
  • a second first_memory_controller_output signal circuit 148 asserts a busy_write_out sram controller output signal 7.
  • a first second_memory_controller__output signal circuit 156 asserts a busy_read_out sdram controller output signal 2.
  • a second second_memory_controller _output signal circuit 154 asserts a busy_write_out sdram controller output signal 1.
  • a first first_memory_controller_input signal circuit 150 receives a busy_read__in_sram signal 6.
  • a second first_memory_controller_input signal circuit 152 receives a busy_write_in_sram signal 5.
  • a first second_memory_controller_input signal circuit 160 receives a busy_read_in_sdram signal 4, and a second second_memory_controller_input signal circuit 158 receives a busy_write_in_sdram signal 3.
  • the first memory controller 142 can be selected from various memory controllers including a static RAM (SRAM) memory controller; a flash memory controller; a burst flash memory controller; a synchronous dynamic RAM (SDRAM) memory controller; a double date rate synchronous dynamic RAM controller; and a reduced latency dynamic RAM memory controller.
  • SRAM static RAM
  • SDRAM synchronous dynamic RAM
  • the busy_read_in_sram signal 6 indicates when the external data bus 162 is released for a read access by the SRAM memory controller 142.
  • the busy_write_in_sram signal 5 indicates when the external data bus 162 is released for a write access by the SRAM memory controller 142.
  • the busy_read_in_sdram signal 4 indicates when the external address bus 166 is released for a read access by the SDRAM memory controller 144.
  • the busy_write_in_sdram signal 3 indicates when the external data bus 162 is released for a write access by the SDRAM memory controller 144.
  • the busy_read_in _sram signal 6 and the busy_write_in_sram signal 5 are internally combined with the selection signal sel_extsram
  • the busy_read_in_sdram signal 4 and the busy_write_in_sdram signal 3 are internally combined with the selection signal sel_extsdram 170 to allow the SDRAM controller 144 access to the external bus 162.
  • the busy_read__out sram controller output signal 8 indicates when the SRAM memory controller 142 releases the external address bus 166 for a next external access subsequent to a read access to the data bus by the SRAM memory controller 142.
  • the busy_write_out sram controller output signal 7 indicates when the SRAM memory controller 142 releases the external data bus 162 for a next external access subsequent to a write access to the data bus by the SRAM memory controller.
  • the busy_read_out sdram controller output signal 2 indicates when the SDRAM memory- controller 144 releases the external address bus 166 for an external access subsequent to a read access to the data bus by the SDRAM memory controller.
  • the busy_write_out sdram controller output signal 1 is configured to indicate when the SDRAM memory controller 144 releases the external data bus 162 for an external access subsequent to a write access to the data bus by the SDRAM memory controller.
  • the "busy_read_out/busy_write_out” signals are asserted when some conditions are met.
  • the timing condition to assert a "busy_read__out” signal is the time where a read access on an external memory ends (time data float also known as TDF) . During this period the
  • busy_read_out is asserted to indicate the memory controller 142 (or 144) which drives the next access to the address bus 166 that certain command (active or precharge command) can be performed because the external address bus 166 is not busy.
  • the memory controller 142 anticipates the next access to the address bus, but it will not perform the read command as long as "busy_read_out” signal is asserted because the residual data can be present on the EBI data bus .
  • the wait signal 172 is asserted to indicate the master (microprocessor, or direct memory access controller) (not shown) that the data is not ready. No other access can be anticipated in this situation.
  • bus_write_out signal is a write access to the data bus 162 by the memory controller 142 "(or 144) where the data bus 162 is driven by the microcontroller (not shown) .
  • the memory for instance, SRAM, or SDRAM
  • Memory controller 142 (or 144) includes a store element (not shown) to hold the data until the write transfer is completed. If this is the case, there is no need to assert the "wait” signal. Instead, the master (microcontroller) should be informed that the current write access to the data bus needs several clock cycles to be completed. This is done by asserting the "busy_write_out” signal to prevent any other access on
  • the apparatus 140 of the present invention optimizes the EBI architecture efficiency for multiple memory type. Indeed, for a given clock frequency, an application software will run faster with the invention rather than without invention.
  • the efficiency of the EBI architecture for multiple memory type of the present invention is illustrated in the discussion below.
  • the output circuits including the first first_memory_controller_output signal circuit 146, the second first__memory_controller_output signal circuit 148, the first second_memory_controller
  • the second second_memory _controller_output signal circuit 156, and the second second_memory _controller_output signal circuit 154 are all electrically communicating with the input circuits including the first first_memory_controller_input signal circuit 150, the second first_memory_controller__input signal circuit 152, the first second_memory_controller _input signal circuit 160, and the second second__memory _controller_input signal circuit 158.
  • the "busy_write_out” signal 7 of memory controller 142 drives the "busy__write_in” signal 3 of memory controller 144.
  • the "busy_write_out” output signal 1 of memory controller 144 drives the “busy_write_in” signal 5 of memory controller 142.
  • the "busy_read_out” signal 8 of memory controller 142 drives the “busy_read_in” signal 4 of memory controller 144.
  • the "busy_read_out” output signal 2 of memory controller 144 drives the "busy_read_in” signal 6 of memory controller 142.
  • FIG. 6 illustrates a signal output drawing for the apparatus of FIG. 5 that has dual clock gain in throughput as compared with the throughput of the prior art apparatus of FIG. 4, when an external read access is followed by an external access, whereas the memory requires only one clock cycle of TDF.
  • the read transfer command 220 sent by the master on the internal system bus 205 starts the read transfer to an external memory followed by the external memory transfer to an another device access to the external bus .
  • a read access is required on EBI (the read value Dl 228 at the address location Al 224) .
  • the wait signal 226 from memory controller is asserted during the first clock period Tl 228 (on a system bus clock 202) , and de- asserted afterwards.
  • the master starts the new write access D2 230 at address location A2 232 which corresponds to the external memory without wait signals.
  • the memory controller samples the internal address bus value A2 229 into internal storage elements and holds this value on the external address bus until the memory has completed the read of data bus (value Dl 228) at time T3 240.
  • This time is exactly the same as the time T3 of FIG. 4.
  • the master can initiate the next transfer command using the control bus and the address bus then can perform the next transfer command to an external device at time T3 240 which is equal to (Tl + 2) clock cycles.
  • the gain is 2 clock cycles. The gain is higher if the wait signal used in the prior art apparatus to complete a single read is longer than 3 clock cycles .
  • FIG. 7 illustrates further signal output drawings for the apparatus of FIG. 5.
  • the memory requires more than 2 clock cycles of TDF 252, whereas in the example shown in FIG. 6 the memory requires only one clock cycle of TDF 242.
  • the time of data floating (TDF) is not part of the wait time 254.
  • the gain is 2 clock cycle for the given example The gain is higher if the external memory requires more cycles to release the data bus after being de-selected. More specifically, on the first access the "wait" signal 254 is asserted to prevent the master from reading the data prematurely at cycle T2 256 after the first cycle Tl 258. On the second cycle T2 256 the "wait" signal 254 is released to inform master that the data is ready on the internal bus.
  • FIG. 8 illustrates further signal output drawings of the apparatus of FIG. 5.
  • the memory may require several clock cycles to be correctly written, for instance two clock periods. If the memory controller includes a store element to hold the data until the write transfer is completed, there is no need to assert the wait signal 284. Instead, there is a need to inform the system (master) that the current write access needs several clock cycles to be completed. This is done by asserting a busy_write signal 282 to prevent any other access on EBI. If this is the case, it is not possible to anticipate the next access, no matter what the next access is, because the external address bus is busy by the write access. In this embodiment, the gain is dependent on the number of clock cycles required for a write command to be completed.
  • the following output circuits: the first first_memory_controller_output signal circuit 146, the second first_memory_controller_output signal circuit 148, the first second_memory_controller _output signal circuit 156, and the second second_ memory_controller_output signal circuit 154 are all electrically disconnected from the following input circuits : the first first_memory_controller_input signal circuit 150, the second first_memory__controller_input signal circuit 152, the first second_memory_controller _input signal circuit 160, and the second second_memory _controller_input signal circuit 158.
  • the simplified architecture features a data bus 162, a single memory controller 142, a first output signal circuit 146, a second output signal circuit 148, a first input signal circuit 150, and a second input signal circuit 152.
  • the first output signal 8 indicates when the memory controller 142 releases the address bus 166 for a next external access subsequent to a read access to the data bus by the memory controller 142
  • the second output signal 7 indicates when the memory controller 142 releases the data bus 162 for a next external access subsequent to a write access to the data bus 162 by the memory controller 142.
  • the first input signal 6 indicates when the address bus 166 is released by an external memory controller for a read access by the memory controller 142
  • the second input signal 5 indicates when the external bus is released by the external memory controller for a write access by the memory controller 142.
  • the method for improving bandwidth for circuits having a plurality of memory controllers employs the following steps: (A) asserting a first first_memory _controller_output signal to indicate when a first memory controller releases an address bus for a next external access subsequent to a read access to the data bus by the first memory controller; (B) asserting a second first_memory_controller_output signal to indicate when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller; (C) asserting a first second_memory_controller_output signal to indicate when a second memory controller releases the address bus for an external access subsequent to a read access to the data bus by the second memory controller; and
  • the step (A) of asserting the first first__memory_controller _output signal further includes the step of: (Al) asserting a first_busy_read_out signal by using the address bus to anticipate a next external access to the data bus subsequent to an initial read access to the external data bus by the first memory controller.
  • the step (B) of asserting the second first_memory__controller__output signal further includes the step of: (Bl) asserting a first_busy_write_out signal to delay all external accesses to the external data bus subsequent to an initial write access to the external data bus by the first memory controller.
  • the step (C) of asserting the first second_memory_controller_output signal further includes the step of: (Cl) asserting a second_busy_read_out signal by using the address bus to anticipate a next external access to the data bus subsequent to an initial read access to the external data bus by the second memory controller.
  • the step (D) of asserting the second second_memory_controller_output signal further includes the step of: (Dl) asserting a second_busy_write_out signal to delay all external accesses to the external data bus subsequent to an initial write access to the external data bus by the second memory controller.
  • Further steps can include the following: (E) asserting a first first_memory_controller_input signal to indicate when the external address' bus is released for a read access by the first memory controller; (F) asserting a second first_memory_controller_input signal to indicate when the external data bus is released for a write access by the first memory controller; (G) asserting a first second__memory_controller_input signal to indicate when the external address bus is released for a read access by the second memory controller; and (H) asserting a second second_memory_controller_input signal to indicate when the external data bus is released for a write access by the second memory controller.

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Abstract

L'invention concerne un appareil (140) destiné à améliorer la largeur de bande pour des circuits possédant des dispositifs de commande à plusieurs mémoires utilisant un premier dispositif de commande à mémoire (142), un second dispositif de mémoire (144), un premier circuit de signal de sortie de lecture occupé (146), un premier circuit de signal de sortie d'écriture occupé (148), un second circuit de signal de sortie de lecture occupé (156) et un second circuit de signal de sortie d'écriture occupé (154). Le premier signal de sortie de lecture occupé (8) indique lorsque le premier dispositif de commande de mémoire (142) libère le bus d'adresse (166) pour un accès externe suivant ultérieur à un accès de lecture au bus de données par le premier dispositif de commande de mémoire (142). Le premier signal de sortie de lecture occupé (7) indique lorsque le premier dispositif de commande de mémoire (142) libère le bus de données (162) pour un accès externe suivant ultérieur à l'accès de lecture au bus de données par le premier dispositif de commande de mémoire (142). Le second signal de sortie de lecture occupé indique que le second dispositif de mémoire (144) libère le bus d'adresse (166) pour un accès externe suivant ultérieur à un accès de lecture du bus de données par le second dispositif de commande de mémoire (144). Le second signal de sortie de lecture occupé (1) indique lorsque le second dispositif de commande de mémoire (144) libère le bus de données (162) pour un accès externe suivant ultérieur à un accès de lecture au bus de données par le second dispositif de commande de mémoire (144).
PCT/US2006/008447 2005-04-15 2006-03-08 Appareil destine a ameliorer la largeur de bande pour des circuits possedant des dispositifs de commande a memoire multiple WO2006112968A1 (fr)

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GB0721911A GB2441668A (en) 2005-04-15 2006-03-08 Apparatus to improve bandwidth for circuits having multiple memory controllers
DE112006000758T DE112006000758T5 (de) 2005-04-15 2006-03-08 Vorrichtung zum Verbessern der Bandbreite für Schaltungen mit mehreren Speichersteuereinheiten

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FR05/03811 2005-04-15
FR0503811A FR2884629B1 (fr) 2005-04-15 2005-04-15 Dispositif d'amelioration de la bande passante pour des circuits munis de controleurs memoires multiples
US11/183,052 US20060236007A1 (en) 2005-04-15 2005-07-15 Apparatus to improve bandwidth for circuits having multiple memory controllers
US11/183,052 2005-07-15

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US5893158A (en) * 1996-05-09 1999-04-06 Furuta; Minoru Multibank dram system controlled by multiple dram controllers with an active bank detector
US20010052060A1 (en) * 1999-07-12 2001-12-13 Liewei Bao Buffering system bus for external-memory access

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