WO2016053146A1 - Système informatique - Google Patents

Système informatique Download PDF

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Publication number
WO2016053146A1
WO2016053146A1 PCT/RU2015/000626 RU2015000626W WO2016053146A1 WO 2016053146 A1 WO2016053146 A1 WO 2016053146A1 RU 2015000626 W RU2015000626 W RU 2015000626W WO 2016053146 A1 WO2016053146 A1 WO 2016053146A1
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WO
WIPO (PCT)
Prior art keywords
computer system
microprocessor
external serial
data
controller
Prior art date
Application number
PCT/RU2015/000626
Other languages
English (en)
Russian (ru)
Other versions
WO2016053146A8 (fr
Inventor
Павел Николаевич ОСИПЕНКО
Дмитрий Сергеевич КОРОЛЕВ
Константин КРАСИК
Константин Львович ГУРИН
Григорий Юрьевич ХРЕНОВ
Original Assignee
Открытое Акционерное Общество "Байкал Электроникс"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Открытое Акционерное Общество "Байкал Электроникс" filed Critical Открытое Акционерное Общество "Байкал Электроникс"
Priority to EA201700120A priority Critical patent/EA038978B1/ru
Publication of WO2016053146A1 publication Critical patent/WO2016053146A1/fr
Publication of WO2016053146A8 publication Critical patent/WO2016053146A8/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Definitions

  • the claimed solution relates to computer technology, in particular to computer systems using external memory to boot the system as applied to low-cost computer systems with advanced functionality.
  • a solution is known according to US patent 6,601,167 B 1 (priority from 01/14/2000), which includes a method for initializing a computer system, including a processor and sequential access memory with a download program stored in it, and a corresponding computer system for implementing the method.
  • the bootloader in response to the initialization of the computer system, first controls the serial storage device to read the boot program, and then controls the processor to switch to the boot program in the sequential access memory.
  • the first page of the boot program memory calls boot code, which must be transferred to random access memory (RAM).
  • the processor switches to the code in RAM, forcing the remaining part of the boot code from the serial access memory to be transferred to RAM and executing it.
  • the disadvantage of this solution is the need to use internal RAM, even for small computer systems.
  • boot devices using NAND flash memory for example, US patent 7849302 (priority of 04/10/2006), and a method of obtaining boot instructions from non-volatile memory, for example, the technical solution of US patent 20068533448 (priority of 12/06/2010), which can be implemented by detecting a reset signal related to the device, and receiving a predetermined data page from the non-volatile memory region into a register associated with the non-volatile memory, by paginating the data from the non-volatile memory, wherein the data page itself includes device loading commands.
  • the address included in it is used to identify the location of one or more commands in the register.
  • NAND flash data lines provide input lines for transferring data to the processor core.
  • the processor core at boot time, receives new boot instructions at the point in time when they exit the NAND flash memory.
  • the disadvantages of this solution is that the claimed boot method involves the use of exclusively NAND Flash memory, and for the boot method that it uses a multi-signal interface between the microprocessor and the NAND Flash chip, which, firstly, requires a large number of pins of the system chip on a chip (SoC), and, secondly, it requires a specialized microprocessor device interface.
  • SoC system chip on a chip
  • this approach may require the availability of internal RAM.
  • US patent 2004/0230738 A1 (priority 29.10.2003), in the form of a device that allows you to control the execution of commands directly from serial flash memory, and a flash memory chip using this device, while the ROM controller with with a certain amount of data storage has access to ROM for reading entire pages of memory in which the required data is stored, and can transfer the necessary data to the main control module or execute them.
  • the device includes a cache module for accessing the indicated ROM memory address in response to a command received from the control module, and reading or writing data to the main control module, and a ROM controller with a bootloader that allows loading by reading data from the ROM with the storage boot codes in the buffer and immediate transfer of boot codes to the main control module upon request.
  • the main disadvantage is the mandatory availability of internal RAM.
  • the SoC chip containing the microprocessor starts the initialization procedure, for which the microprocessor core starts reading and executing the initialization program instructions from a certain starting address in its own address space.
  • the initial initialization program is located in a bootable non-volatile read-only memory (ROM), made, for example, using Flash technology, or boot ROM is implemented as a part of a microcircuit, which requires a special technological process, making the process of manufacturing a microcircuit more expensive.
  • ROM bootable non-volatile read-only memory
  • boot ROM is implemented as a part of a microcircuit, which requires a special technological process, making the process of manufacturing a microcircuit more expensive.
  • serial ROMs for example, SPI format (serial peripheral interface) for storing initial initialization programs that transmit read and write data, control and status information over a single-bit serial channel.
  • SPI type ROM chips use three lines for receiving and transmitting data:
  • the microprocessor core reads and executes instructions from the micro ROM, the result of which will be the copying of the initial initialization program from the serial ROM to the internal boot RAM, after which the control is transferred to the internal boot RAM command, which affects the speed and design complexity and therefore the cost of the system.
  • a computer system which includes a system on a chip (SoC) and an external serial ROM; SoK, in turn, includes a microprocessor, which includes at least one microprocessor core, an external serial ROM controller for parallel transmission of data words read from an external serial ROM, located between them and connected to each other, a device for directly displaying data addresses located in an external serial ROM, in the address space of the microprocessor and the internal switching device.
  • SoC system on a chip
  • SoK includes a microprocessor, which includes at least one microprocessor core, an external serial ROM controller for parallel transmission of data words read from an external serial ROM, located between them and connected to each other, a device for directly displaying data addresses located in an external serial ROM, in the address space of the microprocessor and the internal switching device.
  • the internal switching device located between the microprocessor and the device for the direct mapping of data addresses located in an external serial ROM into the address space of the microprocessor.
  • the internal switching device allows you to include in the composition of the SoC, at least one interface device, and at least one internal memory device.
  • Interface devices allow SoCs to interact with peripheral devices external to the system on the chip, including high-speed ones, for example, use external microcircuits with built-in dynamic memory as RAM, as well as perform the second stage of loading from them using the widespread high-speed and / or low-speed data transfer / reception protocols.
  • Internal memory devices can further increase the processing power of the system.
  • the device for direct mapping of data addresses located in an external serial ROM into the address space of the microprocessor operates according to the algorithm depicted in FIG. 2. It includes a register of read data, an address register, and a state machine of a device for direct mapping of addresses, which makes automatic calls to the registers of an external serial ROM controller. Located between the switching device and the controller of the external serial ROM, it converts the read requests from the microprocessor through the internal switching device into a sequence of calls to the controller of the external serial ROM. As a result of the operation of the controller, a set of data words read from external serial ROM.
  • the resulting set of words is transmitted via the data bus to the microprocessor through an internal switching device, which allows the microprocessor to carry out high-speed interaction with other devices of the system on a chip.
  • This interaction is carried out using an intra-system interface supported by an internal switching unit using sets of buses, where each of them in turn contains three buses: an address bus, a control bus, and a data bus.
  • the interaction between the device for direct display of data addresses located in the external serial ROM and the controller of the external serial ROM is carried out through a set of interface buses supported by the controller of the external serial ROM, in accordance with the above algorithm (Fig. 2).
  • Data exchange between the controller of the external serial ROM and the ROM itself is carried out through the signals of the serial interface.
  • a processor that includes at least one core, and the internal switching device allows the inclusion of at least one interface device and at least one internal memory device.
  • interface devices functionally ensure the interaction of the system with external peripheral devices, including high-speed, and can, for example, use external microcircuits with integrated dynamic memory as RAM, as well as perform the second stage of loading from them through widely common high-speed and / or low-speed data transmission / reception protocols.
  • the inclusion of internal memory devices also affects the increase in computing power of SoCs.
  • a device for directly mapping data addresses located in an external serial ROM to the microprocessor address space allows executing commands located in an external serial ROM (and, in the best case, executing the initial boot code of a computer system), due to the fact that at the time the readiness for operation of an external serial ROM from a computer system, remove the reset signal, automatically initialize one or more control registers of the controller of the external serial ROM using the state machine of the direct mapping into the microprocessor address space of the data addresses located in the external serial ROM containing the initial boot code, and wait for the microprocessor to receive read requests, and upon receipt of the read request, the addresses from the microprocessor on the control bus and on the address bus, respectively, using the state machine of the device for direct mapping of data addresses, located in the external serial ROM, in the address space of the microprocessor, make a corresponding entry in the data register and, possibly, in the control register of the controller of the external serial ROM, then using the finite state machine of the device for direct mapping of data addresses
  • the technical result of the claimed invention is the creation of a computer system with the optimized ability to run the initialization program from an external serial ROM by mapping the data addresses located in the external serial ROM to the address space of the microprocessor reduces the number of contacts required to connect an external boot ROM to the SoC, and makes it possible to refuse the use of internal boot RAM and ROM, which saves space on the chip while providing high computing power and advanced functionality.
  • the creation of this computer system expands the arsenal of modern computer systems.
  • FIG. 1 A computer system with a chip system containing a microprocessor including one or more microprocessor cores, a device for directly mapping data addresses located in an external serial ROM into the microprocessor address space, 'internal switching device, interface devices, internal memory devices and controller external serial ROM.
  • FIG. 2 The algorithm of the device for the direct mapping of data addresses located in an external serial ROM into the address space of the microprocessor.
  • a computer system consisting of SoC (1) and an external sequential ROM (2), can be implemented using a chip system containing a microprocessor (3), including at least one microprocessor core; an internal switching device (4) located between the microprocessor (3) and the device (5) for direct mapping of data addresses located in an external serial ROM (2) into the address space of the microprocessor (3), including at least one microprocessor core (t ie, microprocessor (3) can be both consisting of one core, and can be multi-core).
  • Device (5) operates according to the algorithm depicted in FIG. 2.
  • the device (5) includes a read data register (6), an address register (7) and a state machine (8) of a direct address mapping device (5) that automatically accesses the registers of the controller (9) of an external serial ROM (2) .
  • a direct address mapping device (5) that automatically accesses the registers of the controller (9) of an external serial ROM (2) .
  • it converts the read requests of the ROM (2) coming from the side of the internal switching device (4) from the microprocessor (3), containing at least , one microprocessor core, in a sequence of calls to the controller (9) of the external serial ROM (2), resulting in a set of data words read from the external serial ROM (2).
  • the resulting set of words is transmitted to the microprocessor (3) containing at least one microprocessor core through an internal switching device (4), while the internal switching device (4) allows the microprocessor (3) containing at least one microprocessor core, to carry out high-speed interaction with other devices of the system on a chip.
  • Data is transmitted from the device (5) for direct address mapping to the internal switching device (4) and the controller (9) using the intrasystem interface supported by the internal switching device (4) containing sets of buses (11) and (12), where each of which, in turn, contains at least three buses, for example, in the set (11) they contain an address bus (13), a control bus (14) and a data bus (15).
  • the device (5) interacts with the controller (9) of the external serial ROM (2) through a set of buses the interface (16) supported by the controller (9) of the external serial ROM (2), in accordance with the algorithm describing the operation of the direct address mapping unit (Fig. 2).
  • the interface (16) the AMBA interface or any specialized interface can be used.
  • the controller (9) of the external serial ROM (2) includes a state machine (17) of the controller of the serial ROM (2) and a set of registers, among which at least one status register (18), at least one register can be distinguished control (19) at least one data register (20). Data is exchanged between the controller (9) of the external serial ROM (2) and the ROM itself (2) by means of the signals of the serial interface (protocol) of the ROM controller via single-bit serial channels (10).
  • the initial boot code of the computer system located in the external serial ROM (2) is transmitted, due to the fact that when the external serial ROM (2) is ready for operation, the reset signal is removed from the computer system, one automatically or several control registers of the controller (9) of the external serial ROM (2) using the state machine of the device (8) of direct mapping into the address space of the microprocess litter (3) containing at least one microprocessor core, data addresses located in an external serial ROM (2) containing the initial boot code, and expected from microprocessor (3) containing at least one microprocessor core, income read requests, and upon receipt of a read request and addresses from a microprocessor (3) containing at least one microprocessor core, via the control bus and address bus, respectively, using an internal switching device (4) and a state machine ( 8) devices (5) for direct mapping of data addresses located in an external serial ROM (2) into the address space of a microprocessor (3) containing at least one microprocessor core, make a corresponding record in the data register (20) and, possibly ,
  • Data words read from an external serial ROM (2) are transmitted via a data bus (15) to a switching device (4) and then to a microprocessor (3), including at least one microprocessor core.
  • the microprocessor (3) including at least one microprocessor core, is capable of reading data from a serial ROM external to the SoC (2) using an external serial ROM controller (9), (2) device (5) and internal switching unit (4).
  • the interaction of the device (5) with the internal switching device (4) can be performed using any internal system of the SoC, supported by the internal switching unit, for example, AMBA / OCP / etc.
  • Data exchange between the device (5) for direct mapping of data addresses located in an external serial ROM into the address space of a microprocessor (3), including at least one microprocessor core, and the controller (9) of an external serial ROM (2) can be carried out in in accordance with any protocol supported by the controller (9) of the external serial ROM (2).
  • the data exchange of the controller (9) with an external serial ROM (2) is carried out via single-bit serial channels (10).
  • SoC includes interface devices (21) and internal memory devices (22).
  • an internal switching device (4) allows the microprocessor (3), which includes at least one microprocessor core, to use interface devices (22) when connecting high-speed and low-speed peripheral devices using the intra-system interface (12) supported by the internal switching device, for example AMBA / OCP, etc.
  • an internal switching device supporting the DMA (Direct Memory Access) mode can be used, while additional external peripheral devices can be connected to the computer system through interface devices, which can expand the functionality and computing power of this system.
  • External peripherals for example, can be used to carry out the second stage of loading, after the end of the first stage, which is performed using the device (5) for direct mapping of addresses from external ROM (2).
  • the second stage can be carried out using a high-speed protocol for receiving / transmitting data (for example, SATA), while the boot code of the first stage must necessarily include the initialization code of all devices involved in the second stage of loading.
  • interface devices in a system on a chip where the controller devices are interface devices, i.e., part of the SoC), the following can be used:
  • PCI controller device Peripheral component interconnect
  • PCI Express PCI Express
  • USB controller device Universal Serial Bus
  • interface devices such as:
  • the AMBA, OCP, etc. interface can be used as an intra-system interface.
  • the units that make up the peripheral device controllers can interact with each other via another interface, i.e. different from the interface of the switching unit.
  • At least one microprocessor core due to the use of an internal switching device (4) when connecting interface devices (21) (at least one) and internal memory devices (22) (at least one), will provide the following advantages:

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne des équipements informatiques. Le système informatique comprend un système monopuce et une mémoire ROM externe séquentielle, le système monopuce comprenant un microprocesseur contenant au moins un noyau de microprocesseur; un contrôleur de la mémoire ROM externe séquentielle; un système d'affichage direct des adresses de données se trouvant dans la mémoire ROM externe séquentielle dans l'espace d'adressage du microprocesseur; au moins un dispositif d'interface; au moins un dispositif de mémoire interne; et au moins un dispositif de commutation interne assurant l'interaction entre le microproceseur et les autres dispositifs du système sur puce; le dispositif d'affichage direct des adresses de données se trouvant dans la mémoire ROM externe séquentielle, dans l'espace d'adressage du microprocesseur, comprend un registre de données lues, un registre d'adresse et un automate d'états finis du dispositif d'affichage direct des adresses.
PCT/RU2015/000626 2014-09-30 2015-09-30 Système informatique WO2016053146A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EA201700120A EA038978B1 (ru) 2014-09-30 2015-09-30 Устройство прямого отображения адресов данных, располагающихся во внешнем последовательном пзу, в адресное пространство микропроцессорного ядра, компьютерная система и способ передачи данных

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2014139279/08A RU2579949C2 (ru) 2014-09-30 2014-09-30 Компьютерная система
RU2014139279 2014-09-30

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WO2016053146A1 true WO2016053146A1 (fr) 2016-04-07
WO2016053146A8 WO2016053146A8 (fr) 2016-07-28

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PCT/RU2015/000626 WO2016053146A1 (fr) 2014-09-30 2015-09-30 Système informatique

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EA (1) EA038978B1 (fr)
RU (1) RU2579949C2 (fr)
WO (1) WO2016053146A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108228392A (zh) * 2016-12-12 2018-06-29 罗伯特·博世有限公司 控制设备

Citations (2)

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Publication number Priority date Publication date Assignee Title
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US20060174100A1 (en) * 2005-01-31 2006-08-03 Samsung Electronics Co., Ltd System and method of booting an operating system for a computer

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US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US6601167B1 (en) * 2000-01-14 2003-07-29 Advanced Micro Devices, Inc. Computer system initialization with boot program stored in sequential access memory, controlled by a boot loader to control and execute the boot program
JP2004334486A (ja) * 2003-05-07 2004-11-25 Internatl Business Mach Corp <Ibm> ブートコードを用いた起動システム、及び起動方法

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US20060174100A1 (en) * 2005-01-31 2006-08-03 Samsung Electronics Co., Ltd System and method of booting an operating system for a computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108228392A (zh) * 2016-12-12 2018-06-29 罗伯特·博世有限公司 控制设备
CN108228392B (zh) * 2016-12-12 2024-01-02 罗伯特·博世有限公司 控制设备

Also Published As

Publication number Publication date
RU2579949C2 (ru) 2016-04-10
WO2016053146A8 (fr) 2016-07-28
RU2014139279A (ru) 2015-05-27
EA201700120A1 (ru) 2017-10-31
EA038978B1 (ru) 2021-11-17

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