WO2007116485A1 - Dispositif mémoire, circuit interface correspondant, système et carte mémoire, carte de circuits imprimés et dispositif électronique - Google Patents

Dispositif mémoire, circuit interface correspondant, système et carte mémoire, carte de circuits imprimés et dispositif électronique Download PDF

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Publication number
WO2007116485A1
WO2007116485A1 PCT/JP2006/306891 JP2006306891W WO2007116485A1 WO 2007116485 A1 WO2007116485 A1 WO 2007116485A1 JP 2006306891 W JP2006306891 W JP 2006306891W WO 2007116485 A1 WO2007116485 A1 WO 2007116485A1
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WO
WIPO (PCT)
Prior art keywords
memory
information
memory device
transmission
identification information
Prior art date
Application number
PCT/JP2006/306891
Other languages
English (en)
Japanese (ja)
Inventor
Toshihiro Miyamoto
Akio Takigami
Masaya Inoko
Takayoshi Suzuki
Hiroyuki Ono
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/306891 priority Critical patent/WO2007116485A1/fr
Publication of WO2007116485A1 publication Critical patent/WO2007116485A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits

Definitions

  • Memory device its interface circuit, memory 'system, memory' card, circuit board and electronic equipment
  • the present invention relates to a memory used for information storage in an electronic device such as a personal computer (PC), and in particular, a memory device including a plurality of banks, an interface circuit thereof, a memory 'system, a memory' card, and a circuit board And electronic devices.
  • PC personal computer
  • PCs use memories such as JEDEC (Joint Electron Device Engineering Council) specifications such as SDRAM (Synchronous Dynamic Random Access Memory) and DDR-SDRAM (Double Data Rat-SDRAM).
  • JEDEC Joint Electron Device Engineering Council
  • SDRAM Serial Dynamic Random Access Memory
  • DDR-SDRAM Double Data Rat-SDRAM
  • Patent Document 1 describes a memory controller including a plurality of programmable timing registers that can be programmed to store timing information suitable for a memory device.
  • Patent Document 2 includes a microprocessor 'chip and a nonvolatile memory' chip, which are connected by an internal card bus, and the microprocessor chip contains key information, usage information, and program instruction information. The memory card is listed.
  • Patent Document 3 describes a computer system that includes an embedded processor coupled to an input / output processor and a local memory.
  • Patent Document 4 describes a memory having an internal storage means together with an SPI driver.
  • Patent Document 5 describes a data processing system including a CPU linked to a data memory via a unidirectional read bus, a unidirectional write bus, and an address bus.
  • Patent Document 6 describes a memory system in which a bus for transferring write data and a bus for transferring read data are separately provided and a memory controller and a memory are connected.
  • Patent Document 7 the data transfer operation to the random access memory is controlled in response to the first transition of the periodic signal, and the data transfer operation of the random access memory array is in response to the second transition of the periodic signal.
  • a random access memory configured to control is described.
  • Patent Document 8 describes a CD that includes a DRAM unit and a DRAM control and cache Z refresh control unit.
  • a semiconductor memory device including a RAM is described.
  • Patent Document 9 describes a synchronous DRAM having a control unit with a memory array, in which the contents of the data bus and the operation status confirmation information are the same, and the mode register can be set only in this case. Is described.
  • Patent Document 10 describes a mode register control circuit such as SDRAM.
  • Patent Document 1 Japanese Patent Laid-Open No. 2004-110785 (Summary, Fig. 1 etc.)
  • Patent Document 2 JP-A-6-208515 (Summary, Fig. 1 etc.)
  • Patent Document 3 JP-A-9 6722 (Summary, Fig. 2 etc.)
  • Patent Document 4 Japanese Unexamined Patent Publication No. 2005-196486 (paragraph number 0029, FIG. 6 etc.)
  • Patent Document 5 Japanese National Patent Publication No. 9 507325 (Summary, Fig. 1 etc.)
  • Patent Document 6 Japanese Unexamined Patent Application Publication No. 2002-63791 (Summary, Fig. 1 etc.)
  • Patent Document 7 Japanese Patent Laid-Open No. 11 328975 (Summary, Fig. 2 etc.)
  • Patent Document 8 Japanese Patent Laid-Open No. 7-169271 (paragraph number 0038, FIG. 1, etc.)
  • Patent Document 9 JP-A-8-124380 (paragraph number 0020, FIG. 2 etc.)
  • Patent Document 10 Japanese Patent Laid-Open No. 9259582 (paragraph number 0028, FIG. 1, etc.)
  • Full duplexing of the bus for simultaneously transferring data and reading / writing data is effective for high-speed data processing. Since full-duplex bus uses separate buses for read and write, data can be transferred at high speed and without gaps without complicated control for switching the bus direction. In this full-duplex bus, the address and write data can be combined to reduce the number of signal lines. In this case, if the address information is given first as the memory access order, the data is read or written next, so that time overlap is avoided. It will be awkward.
  • a bank is a memory matrix.
  • the size of the memory matrix is limited by the capacity of the memory cells. To increase the memory capacity, it is only necessary to install multiple memory matrices as multiple banks. Even if many banks are installed, if each bank is accessing one bank, it is necessary to deassert the bank being accessed to move to another bank. If there is no such restriction, each bank can be operated at the same time.
  • the command transmitted to the bus 6 between the chip 'set 2 and the memory' module 4 has a problem of overlapping timing as shown in FIG. Figure 2 A is RAS # 1 for the bank of memory module 4, ta is the access time of RAS # 1, and the falling edge of RAS # 1 represents the command.
  • RAS # 1 for the bank of memory module 4
  • ta is the access time of RAS # 1
  • the falling edge of RAS # 1 represents the command.
  • C AS # shown in C occurs corresponding to 1 3 # 1
  • RAS # 2 falls, In other words, the RAS # 2 command and CAS # command overlap.
  • a in Fig. 3 shows RAS # 1
  • B in Fig. 3 shows CAS # 1
  • a certain additional time from the fall of CAS # 1 Is set and as shown in Fig. 3C, the command position of CAS # 1 is delayed by an additional time tc, and data DATA1 shown in Fig. 3G is transferred correspondingly.
  • RAS # 2 occurs as shown in Fig. 3D
  • CAS # 2 occurs as shown in Fig.3E.
  • F of 3 CAS # 2 occurs after an additional time tc
  • Patent Documents 1 to 10 do not suggest or disclose the means for solving the problem.
  • an object of the present invention relates to a memory device including a single or a plurality of memory chips having a plurality of banks, and avoids duplication of commands and speeds up data reading and writing.
  • Another object of the present invention is to enable CAS latency to be dynamically specified.
  • Another object of the present invention is to simultaneously transmit and receive data without increasing the number of pins, thereby enabling high-speed access to a memory.
  • the present invention has a bus configuration in which a memory 'module interface circuit and a memory' module are distinguished in the signal transmission direction, and identifies transmission information on the bus.
  • the memory device and the memory system corresponding to the bus configuration and the signal line are configured with a signal line for transmitting the identification information.
  • the signal from the interface circuit such as a chip set to the memory module is distinguished in the transmission direction, and the data transmission and reception are physically independent, and the signal is sent by data, address information, and control signal. Without distinguishing the lines, the data signal transmission direction can be unidirectional to eliminate the bus turn-around period, thereby increasing the speed of memory access.
  • a first aspect of the present invention is a memory device including a single or a plurality of memory chips, and is connected to a node distinguished in a transmission direction of transmission information, It is configured to be connected to a signal line for transmitting identification information for identifying the transmission information.
  • the identification information may be information representing write data power address information power, or even by such a structure, The objective is achieved.
  • the transmission information is received from the bus, the identification information is received from the signal line, and the identification information is received from the transmission information card.
  • the above object can be achieved by a configuration including an information identification unit for identifying information.
  • a second aspect of the present invention is an interface circuit of a memory device including a single or a plurality of memory chips, and includes a bus that is distinguished in a transmission direction of transmission information. And a signal line for transmitting identification information for identifying the transmission information.
  • the identification information may be configured to be information representing a write data power address information power.
  • the configuration is also achieved by the configuration.
  • the information processing apparatus may include a mixing unit that mixes information and write data for the memory device, and an identification information transmitting unit that generates and transmits the identification information by the output of the holding unit.
  • a third aspect of the present invention is a memory system including a memory device including a single or a plurality of memory chips, wherein the bus is distinguished in the transmission direction of transmission information. And a signal line for transmitting identification information for identifying the transmission information.
  • the transmission information is sent in correspondence with the bus, and identification information for identifying the transmission information is sent to the signal line.
  • the above object can also be achieved by a configuration including an information processing section to be transmitted.
  • the information is The information processing unit includes a holding unit that holds command information and address information received from an external force, a mixing unit that mixes information output from the holding unit and write data for the memory device, and the holding unit
  • the above object can also be achieved by a configuration including an identification information transmitting section that generates and transmits the identification information by the output of the above.
  • a fourth aspect of the present invention is a memory card including a single or a plurality of memory chips, and is connected to a bus distinguished in the transmission direction of transmission information, It is configured to be connected to a signal line for transmitting identification information for identifying the transmission information.
  • the identification information may be information indicating write data power address information power, or by such a structure, the above objective is achieved.
  • the memory card preferably receives the transmission information from the bus and the identification information from the signal line, and receives the identification information from the transmission information card.
  • the above object can be achieved by a configuration including an information identification unit for identifying information by information or by such a configuration.
  • a fifth aspect of the present invention is a circuit board on which a memory device including a single memory chip or a plurality of memory chips is installed, wherein the transmission direction of transmission information of the memory device is And a signal line for transmitting identification information for identifying the transmission information.
  • a sixth aspect of the present invention is a circuit board on which a memory device including a single or a plurality of memory chips is installed, and the transmission direction of transmission information of the memory device And an information processing unit connected to a signal line for transmitting identification information for identifying the transmission information.
  • the information processing unit sends the transmission information corresponding to the bus, and provides identification information for identifying the transmission information.
  • the above object can also be achieved by a configuration including a configuration for sending to the signal line.
  • a seventh aspect of the present invention is an electronic apparatus having a configuration using the above memory device.
  • the electronic device may be any device that stores information using a memory device such as a computer device. Such a configuration also achieves the above object.
  • an eighth aspect of the present invention is an electronic apparatus having a configuration using the interface circuit of the memory device.
  • This electronic device is as described above, and the above object can also be achieved by such a configuration.
  • a ninth aspect of the present invention is an electronic apparatus having a configuration using the memory system.
  • This electronic device is as described above, and the above object can also be achieved by such a configuration.
  • a tenth aspect of the present invention is an electronic apparatus having a configuration using the memory card.
  • This electronic device is as described above, and the above object can also be achieved by such a configuration.
  • an eleventh aspect of the present invention is an electronic apparatus having a configuration using the circuit board.
  • This electronic apparatus is as described above, and the above object can be achieved by such a configuration.
  • FIG. 1 is a diagram showing a memory module and a chip set.
  • FIG. 2 is a diagram illustrating command duplication avoidance processing.
  • FIG. 3 is a diagram illustrating command duplication avoidance processing.
  • FIG. 4 is a diagram showing a memory system according to the first embodiment.
  • FIG. 5 is a diagram showing a configuration example of a memory module.
  • FIG. 6 is a diagram showing a configuration example of a memory chip.
  • FIG. 7 is a diagram showing a configuration example of a chip set.
  • FIG. 8 is a diagram showing data transfer processing.
  • FIG. 9 is a diagram showing the relationship between commands and data buses.
  • FIG. 10 is a diagram showing processing by a command.
  • FIG. 11 is a diagram showing a configuration example of a command.
  • FIG. 12 is a diagram showing command assignment.
  • FIG. 13 is a diagram illustrating a configuration example of a personal computer according to a second embodiment.
  • FIG. 14 A diagram showing a configuration example of a memory card according to the third embodiment.
  • FIG. 15 is a diagram illustrating a configuration example of a circuit board according to a fourth embodiment.
  • FIG. 4 is a diagram showing a configuration example of the memory system according to the first embodiment.
  • FIG. 4 shows an example of the memory device and its interface circuit of the present invention, and the present invention is not limited to the configuration shown in FIG.
  • the memory system 100 includes a memory module 200 as a memory device including a single or a plurality of memory chips, and a chip set 300 as an interface circuit of the memory device.
  • Chip 'set 300' and memory 'module 200 are in the relationship of chip' set 300 force S master and memory module 200 as slave.
  • a bus 400 is connected between the chip set 300 and the memory module 200.
  • the bus 400 includes a first bus 402 and a second bus which are distinguished in the transmission direction of transmission information. 4 04 and signal line 406 are installed.
  • the write data and address information of the memory module 200 are transmitted to the bus 402, and the transmission direction is the direction from the chip set 300 to the memory module 200.
  • the read data of the memory module 200 is transmitted to the nose 404, and the transmission direction is the direction of force from the memory module 200 to the chip set 300.
  • identification information for identifying the transmission information of the bus 402 is transmitted to the signal line 406.
  • the control signal CZD # is used as an identification signal for identifying whether the write data and address information transmitted to the bus 402 are also the write data address information. Is transmitted.
  • a CPU (Central Processing Unit) 500 power S is connected to the chip set 300 via the host bus 102!
  • the memory module 200 is an example of a memory device according to the present invention, and includes a plurality of memory chips 201 to 20N as shown in FIG. Each of the memory chips 201 to 20N is a constituent unit that constitutes a memory, and does not have to be a minimum constituent unit, and may have a different configuration. In this embodiment, the memory 'module 200 includes multiple memories' Although the chips 201 to 20N are configured, a single memory module may be used.
  • each of the memory 'chips 201, 202 ⁇ 20 ⁇ includes, as a plurality of banks, for example, four sets of memory' matrix 211, 212, 213, 214, timing as an information identification unit and a data separation unit
  • a control unit 210 is installed. That is, as described above, data including part or all of the address information of the memory module 200 and the write data is transmitted to the memory chips 201 to 20 through the bus 402.
  • a control signal C / D # is applied by a signal line 406. Therefore, the memory control chips 210, 202,... 20N are provided with a timing control unit 210 for identifying and separating the write data and the address information from the data input described above.
  • the address information includes a bank address of the memory module 200, a row address, a column address, etc., and a part of the address information is selected, for example, a bank address And Row address.
  • the control signal CZD # includes identification information for identifying write data and address information in data input transmitted through the node 402.
  • the timing control unit 210 receives the data input and the control signal CZD #, and separates the address information and the write data from the data input at a predetermined timing using the control signal CZD # as identification information. Data can be read from and written to the memory chips 201 to 20N specified by the address information.
  • Each memory 'chip 201 to 20N is connected to a bus 400 that is individually connected to the aforementioned chip set 300.
  • the chip' set 300 includes a data transmission unit 310 as an information processing unit,
  • the data sending unit 310 mixes part or all of the address information and the write data, generates a data output as a result of the processing and sends it to the bus 402, and also outputs the data output power to the write data and address.
  • the control signal CZD # is sent to the signal line 406 as identification information or identification signal for use in information identification.
  • the bus 400 for transmitting data or the like has the data transmission direction set to a single direction by the bus 402 in the write direction and the bus 404 in the read direction.
  • the data to be transmitted is data including part or all of write data and address information, and the transmission data is multiplexed.
  • the signal lines 406 are provided in the additional U to the nodes 402 and 404 for transmitting the address information and data.
  • a unidirectional control signal CZD # directed to Joule 200 is transmitted.
  • the signal line 406 for transmitting the control signal CZD # since the signal line 406 for transmitting the control signal CZD # is provided independently, the signal line 406 includes a chip 'set 300 to a memory' module even during data transfer. Commands can be sent to 200, and if the banks of the memory chip 201 to 20N are different, data can be written and read in parallel. As a result, high-speed data transfer is achieved.
  • FIG. 6 is a block diagram showing a configuration example of a memory chip.
  • the same parts as those in FIGS. 4 and 5 are denoted by the same reference numerals.
  • Each of the memory chips 201 to 20N is provided with a plurality of memory matrices 211 to 214, a timing control unit 210, and an input / output circuit 220.
  • Row decoders 241, 242, 243, 244 and sense ZColumn decoders 251, 252, 253, 254 are installed corresponding to each of the memories' matrices 211-214.
  • a plurality of memory cells are arranged in a matrix, that is, in a plurality of rows and a plurality of columns.
  • the address signal for N bits passes through the row buffer for N bits and enters the row decoders 241 to 244 by the row address selection signal RAS to select memory cells for one row.
  • the column address selection signal CAS enters the sense ZColumn decoders 251 to 254, and the column is selected so that data can be read and written. This is possible for each operation memory matrix 211-214.
  • the address information and write data included in the data input are separated using the control signal CZD #. This processing is synchronized with the CPU 500 (Fig. 4) by the clock, and the separated write data is stored in the memory 'matrix 211-214 selected according to the command, the row decoders 241-244 and the column decoder 25 1 Written through ⁇ 254.
  • the data in the memory matrixes 211 to 214 is also read out from the memory matrixes 211 to 214 specified by the command, and the memory module 20 through the input / output circuit 220.
  • the zero side force is sent to nose 404 and received by chip 'set 300.
  • FIG. 7 is a block diagram showing a configuration example of a chip'set.
  • the same parts as those in FIG. 4 are denoted by the same reference numerals.
  • the chip set 300 includes a data transmission unit 310 and a bidirectional buffer 320.
  • the data transmission unit 310 includes a command buffer 312, a control circuit 314, and a multiplexer 316 as a mixing unit. It is included.
  • the command 'buffer 312 is a storage unit as a holding unit that temporarily holds command and / or address information, and the command and / or address information from the CPU 500 or the like is sequentially held in the command' buffer 312.
  • the control circuit 314 is an identification information transmission unit that transmits identification information. The control circuit 314 receives an output from the command buffer 312 and outputs a control signal CZD #.
  • the bidirectional buffer 320 receives the read data RD from the memory module 200 or the data D ATA from the CPU 500, sends the read data RD from the memory module 200 to the CPU 500, or receives the data DATA from the CPU 500. Add to multiplexer 316.
  • write data and part or all of address information are mixed and used as data output, so if it is necessary to send address information, data transfer is performed. This can be done by temporarily stopping. Since the memory module 200 does not directly write data at the write data reception timing, the temporary stop of the data transfer does not affect the data writing process. In other words, the dynamic latency setting has no effect on the write timing of write data.
  • control line is independent by the signal line 406, CAS latency can be dynamically specified, and data can be efficiently written to the memory module 200. Even if a bank is provided to increase the memory capacity, the memory capacity can be utilized efficiently.
  • FIG. 9 is a time chart showing processing of commands and data buses
  • Fig. 10 is a diagram showing processing by commands
  • Fig. 11 is a diagram showing commands
  • Fig. 12 is a diagram showing command allocation of data buses. is there.
  • A is the control signal CZD #, and tcm represents the command period.
  • B is command and write data transmitted to the memory module 200 through the bus 402
  • C is read data read from the memory module 200 through the bus 404. If the banks are different, data can be read and written in parallel, and data can be transmitted between the memory module 200 and the chip set 300 in parallel.
  • FIG. 10 shows the details of the command and write data of B in FIG. 9, where A in FIG. 10 shows the clock, and B shows the command and write data on the bus 402. Specify the bank at the falling edge, then specify the row of the memory matrix 211-214 at the rising edge of the clock, specify the operation at the falling edge of the next clock, and specify the operation of the memory matrix 211-214 at the rising edge of the next clock. Indicates that a column is specified! /
  • a, b, c, and d in B of FIG. 10 include banks, rows, and operations as shown in FIG. Yong and row are set. Also, commands are assigned as shown in Fig. 12, and for example, 8 bits from bit 0 to bit 7 are set to latency, bit 8 to bit 11 are operated, and bit 12 to bit 15 are set to reserved. ing.
  • the number of clocks of 2, 3, 4, and 5 is selectively set in the latency.
  • precharge is set to “0001”
  • active is set to “0010”
  • write is set to “0011”
  • read is set to “0100”.
  • precharge indicates RAS or CAS deassertion
  • active indicates RAS assertion.
  • the command power is applied to the memory chips 201 to 20N by the rising and falling edges of each of the two clocks.
  • a part of an 8-bit parallel command is sent at each edge, and a 32-bit command is sent as a whole.
  • the command includes a row address (Rowl ⁇ 15), a column address (Column0 ⁇ 15), and a specific operation (Op0 ⁇ 15).
  • the city is specified as part of Op0-15.
  • Op0 to 15 mainly consist of latency and operations. In the example, the latency is specified by the lower 8 bits of Op0 to 7.
  • the memory chips 201 to 20N operate to assert CAS by delaying the clock by the latency for the command. Therefore, inconvenience due to duplication of commands is solved, and continuous data transfer becomes possible.
  • FIG. 13 is a diagram illustrating a configuration example of a personal computer (PC) according to the second embodiment.
  • PC personal computer
  • the PC 600 is an example of an electronic device including the memory module 200, and includes the memory chips 201 to 20 N of the memory module 200.
  • the PC 600 is provided with a CPU 500, and the CPU 500 is connected to the chip 'set (north bridge) 300 via the bus 102.
  • the chip' set 300 has the memory module 200 described above.
  • an input / output (IZO) interface unit 504 is connected via a south bridge 502.
  • the south bridge 502 is a means for transferring data between the CPU 500 and the IZO interface unit 504.
  • the configurations of the memory module 200 and the bus 400 are the same as those already described (FIG. 4, FIG. 5, or FIG. 6).
  • the IZO interface unit 504 is connected with, for example, a keyboard 506 or an unillustrated display device as an input / output device.
  • write data that does not cause duplication of commands is continuously transmitted to a memory module 200 having memory chips 201 to 20 including a plurality of memories 'matrix 211 to 214'.
  • the data can be transmitted to and stored in the memory module 200, and the read data can be read from the memory module 200 to the chip set 300, thereby speeding up the memory access.
  • FIG. 14 is a diagram showing a configuration example of a memory card according to the third embodiment.
  • FIG. 14 the same parts as those in FIG. 4, FIG. 5, or FIG.
  • the memory card 700 is a specific example of the memory module 200 described above, and is a connector that is inserted into a socket on the mother board side of the circuit board 702 to be electrically connected.
  • Part 704, 706 force formed, connector part 704 ⁇ J has four threads and memory'chip 711,712,713,714, connector part 706 ⁇ J has four threads and memory'chip 721,722,723 724 power ⁇ is installed.
  • Each of the memory chips 711 to 714 and 721 to 724 is mounted with the memory matrices 211 to 214 and the timing controller 210 as described above.
  • the timing control unit 210 is provided, and the chip 'set 300 Receives data input including part or all of the address information and write data, and the data input force also separates the address information and write data and writes the data to the memory chips 711 to 714, 721-7 24 Or it can be read out.
  • the pin configuration can be simplified.
  • FIG. Figure 15 shows the fourth It is a figure which shows the structural example of the circuit board which concerns on embodiment.
  • Figure 4 or Figure 1
  • a memory slot 802 for mounting a memory card 700 on which the memory module 200 described above is mounted is mounted, and a chip set 300 is mounted.
  • Chip 'set 300' and memory 'slot 802 are connected by a bus and can exchange data.
  • write data including address information is sent from the memory module 200 to the memory card 700, and the memory card 700 separates the address information from the write data.
  • Data writing or reading processing can be performed at high speed.
  • the PC 600 is shown as an example of an electronic device that is an application example of the memory device.
  • the present invention is widely used in television devices, server devices, telephone devices, and the like having a PC function. It can be done.
  • the signal line 406 is exemplified by a single line. However, it may be constituted by a bus having the same number as the nodes 402 and 404, which may be a plurality of lines. .
  • the present invention physically separates the sending and receiving of data, as well as data, addresses,
  • the signal line is not distinguished by control, and the signal is distinguished by the transmission direction, and the signal transmission direction is unidirectional, so even if the memory capacity is increased without increasing the number of pins, memory access and Data transmission can be accelerated and useful.

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Abstract

L'invention concerne un dispositif mémoire (module mémoire (200)) comprenant une seule ou plusieurs puces mémoire, connecté à des bus (402, 404) distingué par le sens de transmission des informations de transmission et connecté à une ligne de signaux (406) pour transmettre des informations d'identification afin d'identifier les informations de transmission. Ces informations de transmission représentent des données d'écriture ou des informations d'adresse. Le dispositif mémoire comprend également une section d'identification d'informations (unité de commande de temporisation (210)) pour recevoir les informations d'identification (signal de commande (C/D#)) provenant de la ligne de signaux et identifier les informations provenant des informations de transmission.
PCT/JP2006/306891 2006-03-31 2006-03-31 Dispositif mémoire, circuit interface correspondant, système et carte mémoire, carte de circuits imprimés et dispositif électronique WO2007116485A1 (fr)

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PCT/JP2006/306891 WO2007116485A1 (fr) 2006-03-31 2006-03-31 Dispositif mémoire, circuit interface correspondant, système et carte mémoire, carte de circuits imprimés et dispositif électronique

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PCT/JP2006/306891 WO2007116485A1 (fr) 2006-03-31 2006-03-31 Dispositif mémoire, circuit interface correspondant, système et carte mémoire, carte de circuits imprimés et dispositif électronique

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WO2007116485A1 true WO2007116485A1 (fr) 2007-10-18

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US9524764B2 (en) 2012-10-11 2016-12-20 Kabushiki Kaisha Toshiba Semiconductor device having stacked chips

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JPH09500751A (ja) * 1993-06-02 1997-01-21 ランバス・インコーポレーテッド ダイナミック・ランダム・アクセス・メモリ・システム
JPH09330156A (ja) * 1996-06-13 1997-12-22 Hitachi Ltd バスシステム及び回路基板
JP2001092771A (ja) * 1999-09-24 2001-04-06 Toshiba Corp 記憶装置、記憶装置用の制御装置及びこれらを用いた記憶システム
JP2004127305A (ja) * 2002-10-04 2004-04-22 Samsung Electronics Co Ltd メモリ制御装置

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JPH09500751A (ja) * 1993-06-02 1997-01-21 ランバス・インコーポレーテッド ダイナミック・ランダム・アクセス・メモリ・システム
JPH09330156A (ja) * 1996-06-13 1997-12-22 Hitachi Ltd バスシステム及び回路基板
JP2001092771A (ja) * 1999-09-24 2001-04-06 Toshiba Corp 記憶装置、記憶装置用の制御装置及びこれらを用いた記憶システム
JP2004127305A (ja) * 2002-10-04 2004-04-22 Samsung Electronics Co Ltd メモリ制御装置

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US9524764B2 (en) 2012-10-11 2016-12-20 Kabushiki Kaisha Toshiba Semiconductor device having stacked chips

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