Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/10—Decoders
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
  • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Definitions

• the present invention relates to a semiconductor integrated circuit device, and more particularly to a memory circuit incorporating multiple column decoder connections.
• a prior art bit-select circuit comprises multiple address bytes organized into eight bits each.
• Semiconductor memory chips usually organize a memory array into rows and columns. Each row of memory array elements shares a connection commonly known as a wordline. Each column of memory array elements shares a connection commonly known as a bitline (B7, B6, ..., BO) .
• B7, B6, ..., BO bitline
• the specific intersection of a wordline and a bitline at a memory cell is used to provide a read and write capability for the cell.
• eight bitlines are organized as a byte, providing a conveniently sized grouping for handling data within the memory array.
• Fig. 1 Every bitline from the memory array is connected to peripheral logic outside the array by a passgate transistor.
• Fig. 1 includes eight passgate transistors (only three shown) contained within a bit- select multiplexer ("mux") .
• a y- decoder output signal e.g., decoder signal YO enables BYTE 0
• decoder signal Yl enables BYTE 1
• the passgate transistors coupled to the decoder signals (YO, Yl, ..., Y127) are collectively known as the y-multiplexer or y- mux.
• bitline signals passed by the y-mux are connected in an organized fashion before being passed to a bit-select multiplexer. All BO bits from bytes 0 ... 127 are connected to a global bitline GBLO. Similarly, all Bl bits from bytes 0 ... 127 are connected to a global bitline GBLl. Analogous connections are replicated with the remaining bitlines.
• the bit-select multiplexer selects one global bitline at a time during sensing, and couples the selected bitline to a sense amplifier SA.
• the prior art bit-select multiplexer suffers from a deficiency as the memory size increases. Specifically, as the number of bytes in the memory page (also referred to as the memory page size) increases, the number of passgates connected to the global bitlines increases. This increases the electrical loading on the global bitlines, thus slowing down the sensing speed of the sense amplifier SA. Therefore, what is needed is a way to continually increase a number of bytes in a memory page while not increasing electrical loading on the bitlines, thereby maintaining the sensing speed of the sense amplifier.
• the present invention divides the memory array into portions, in an exemplary embodiment, a lower page portion and an upper page portion. Each memory page addresses half of a total number of memory bytes, thereby reducing a length of global bitlines within the memory page.
• Separate memory page multiplexers are employed for the lower and upper memory pages with each multiplexer coupled to a common sense amplifier.
• bit select mux for each page portion. For example, only one of either a lower bit select mux or an upper bit select mux operates to select and couple a bitline to a sense amplifier at a given time. By operating in this way and allowing only one multiplexer to couple a bitline signal at any given time, read operations associated with the lower memory page do not interfere with read operations associated with the upper memory page.
• lower and upper global bitlines are half as long as the global bitlines in the prior art of Fig. 1. Consequently the global bitlines exhibit half as much electrical loading as the global bitlines of the prior art .
• a reduced global bitline length and loading of the present invention results in a commensurately higher speed operation.
• Fig. 1 is a schematic diagram of a bit-select circuit as known in the prior art.
• Fig. 2 is a schematic diagram of a bit-select circuit according to an exemplary embodiment of the present invention.
• an exemplary embodiment of a bit-select circuit 200 comprises a lower memory page portion 210 and an upper memory page portion 250.
• a lower page y-mux portion 212 comprises address bytes BYTEO through BYTE63 of the lower memory page portion 210 providing a total of 64 bytes addressed.
• An upper page y-mux portion 252 comprises address bytes BYTE64 through BYTE127 of the upper memory page portion 250 providing a total of 64 address bytes in the upper page, and a total of 128 address bytes considering the lower and upper memory pages in combination.
• Each of the address bytes BYTEO through BYTE127 comprises eight bitlines BO through B7. Skilled artisans will appreciate that the notation used in Fig. 2 is commonly employed and will further recognize that, for example, bitline BO of address BYTEO is distinct and separate from bitline BO of address BYTEl.
• Passgate transistors in the lower page y-mux portion 212 couple the bitlines comprising address bytes BYTEO through BYTE63 to a lower global bitlines group 214, comprising lower global bitlines LGBLO through
• the BO bitlines comprising BYTEO through BYTE63 are coupled to the lower global bitlines LGBLO .
• the Bl bitlines comprising BYTEO through BYTE63 are coupled to the lower global bitline LGBLl. Analogous couplings are replicated with the remaining bitlines in BYTEO through BYTE63.
• Passgate transistors in the upper page y-mux portion 252 couple the bitlines comprising address bytes BYTE64 through BYTE127 to an upper global bitlines group 254, comprising upper global bitlines UGBLO through UGBL7.
• the BO bitlines comprising BYTE64 through BYTE127 are coupled to the upper global bitline UGBLO.
• the Bl bitlines comprising BYTE64 through BYTE127 are coupled to the upper global bitline UGBLl. Analogous couplings are replicated with the remaining bitlines in BYTE64 through BYTE127.
• the lower global bitlines group 214 is coupled to a sense amplifier 201 by a lower bit-select mux 216.
• the lower bit-select mux 216 is comprised of eight mux transistors, each transistor having one of eight lower bit-select control signals coupled to a gate terminal of the transistor.
• the lower global bitline LGBLO is coupled to the sense amplifier 201 by the transistor associated with a lower bit-select control signal LBSO.
• the lower global bitline LGBLl is coupled to the sense amplifier 201 by the transistor associated with a lower bit-select control signal LBSl.
• the remaining lower global bitlines LGBL2 ... LGBL7 are coupled in an analogous manner .
• the upper global bitlines group 254 is coupled to a sense amplifier 201 by an upper bit-select mux 256.
• the upper bit-select mux 256 is comprised of eight mux transistors, each transistor having one of eight upper bit-select control signals coupled to a gate terminal of the transistor.
• the upper global bitline UGBLO is coupled to the sense amplifier 201 by the transistor associated with an upper bit-select control signal UBSO.
• the upper global bitline UGBLl is coupled to the sense amplifier 201 by the transistor associated with an upper bit-select control signal UBSl.
• the remaining upper global bitlines UGBL2 ... UGBL7 are coupled in an analogous manner .
• only one of the lower bit select mux 216 and the upper bit select mux 256 operates to select and couple a bitline to the sense amplifier 201 at a given time.
• read operations associated with the lower memory page portion 210 do not interfere with read operations associated with the upper memory page portion 250.
• the lower and upper global bitlines as described supra are half as long as the global bitlines in the prior art of Fig. 1, and consequently exhibit only half as much electrical loading as the global bitlines of the prior art.
• the reduced global bitline length and loading of the present invention results in higher speed operation of the sense amplifier 201.
• the present invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present invention as set forth in the appended claims.
• the memory page division is presented in terms of an upper and a lower memory page having a combined total of 128 bytes of addressing.
• the global bitline loading can be maintained under a constant value by repeating the splitting scheme as described supra to limit the number of bytes associated with a specific bit-select mux.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Read Only Memory (AREA)
• Static Random-Access Memory (AREA)

Priority Applications (3)

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Publications (1)

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Family Applications (1)

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Citations (6)

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• 2005
  • 2005-04-08 US US11/102,906 patent/US7099202B1/en active Active
• 2006
  • 2006-03-08 WO PCT/US2006/008448 patent/WO2006110239A1/en active Application Filing
  • 2006-03-08 EP EP06737609A patent/EP1866927A4/en not_active Withdrawn
  • 2006-03-08 JP JP2008505314A patent/JP2008536250A/ja not_active Withdrawn
  • 2006-03-08 CN CN2006800105172A patent/CN101151676B/zh not_active Expired - Fee Related
  • 2006-03-08 KR KR1020077024167A patent/KR20070116896A/ko not_active Application Discontinuation
  • 2006-04-03 TW TW095111733A patent/TW200643975A/zh unknown

Patent Citations (6)

Non-Patent Citations (1)

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