WO2006103762A1 - Matrice de tubes plasma - Google Patents

Matrice de tubes plasma Download PDF

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Publication number
WO2006103762A1
WO2006103762A1 PCT/JP2005/006093 JP2005006093W WO2006103762A1 WO 2006103762 A1 WO2006103762 A1 WO 2006103762A1 JP 2005006093 W JP2005006093 W JP 2005006093W WO 2006103762 A1 WO2006103762 A1 WO 2006103762A1
Authority
WO
WIPO (PCT)
Prior art keywords
display
electrodes
support substrate
display electrodes
arc tubes
Prior art date
Application number
PCT/JP2005/006093
Other languages
English (en)
Japanese (ja)
Inventor
Hitoshi Hirakawa
Manabu Ishimoto
Kenji Awamoto
Original Assignee
Shinoda Plasma Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinoda Plasma Corporation filed Critical Shinoda Plasma Corporation
Priority to JP2007510287A priority Critical patent/JPWO2006103762A1/ja
Priority to PCT/JP2005/006093 priority patent/WO2006103762A1/fr
Publication of WO2006103762A1 publication Critical patent/WO2006103762A1/fr
Priority to US11/905,138 priority patent/US20080024049A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/20—Constructional details
    • H01J11/22—Electrodes, e.g. special shape, material or configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
    • H01J11/18—AC-PDPs with at least one main electrode being out of contact with the plasma containing a plurality of independent closed structures for containing the gas, e.g. plasma tube array [PTA] display panels

Definitions

  • the present invention relates to an image obtained by arranging a plurality of arc tubes each having a phosphor layer therein, causing discharge within the plurality of arc tubes, and causing the phosphor layer inside the arc tube to emit light. Is related to the plasma tube array.
  • Each luminescent yarn is formed by forming a MgO layer and a phosphor layer inside a glass tube and enclosing a discharge gas such as Ne and Xe.
  • the phosphor layer is formed on a support member, which is a mounting component called a boat, having a cross-sectional shape close to a semicircle, and the support member (boat) is inserted into the glass tube. Thereafter, the glass tube is evacuated while being heated in a vacuum chamber, and after filling with a discharge gas, both ends are melt-sealed.
  • a number of light emitting yarns manufactured in this way are aligned and fixed in parallel, electrodes are provided above and below the light emitting yarns, and voltage is applied to these electrodes to cause discharge inside the light emitting yarns. Makes the phosphor emit light.
  • FIG. 1 is a perspective view showing a basic structure of a plasma tube array.
  • phosphor layers that emit red (R), green (G), and blue (B) fluorescence are respectively arranged inside, and each light emitting yarn in which a discharge gas is sealed.
  • 10 R, 10G, 10B, 10R, 10G, 10B, ... forces are parallel to each other and are arranged in a planar shape as a whole, and a large number of light-emitting yarns arranged with them 10R, 10G, 10B , 10R, 10G, 10B, ... are transparent front support substrate 20 and rear support substrate 30 arranged on the front and back, respectively, and a large number of these light emitting yarns 10R, 10G, 10B, 10R, 10 G arranged , 10B,... Sandwiched between front support substrate 20 and rear support substrate 30 have.
  • a plurality of the display electrode pairs 21 are arranged in the longitudinal direction of the light emitting yarns 1 OR, 10G, 10B, 10R, 10G, 10B,.
  • the two display electrodes 211 and 212 constituting one display electrode pair 2 1 are respectively formed on metal (for example, 0: 7 1 0 :) bus electrodes 211 &, 212a and transparent electrodes 21 lb and 212b made of ITO thin films formed on the sides close to each other.
  • the nose electrodes 21 la and 212a are for lowering the electric resistance of the display electrodes 211 and 212
  • the transparent electrodes 211b and 212b are for emitting light with the light emitting yarns 10R, 10G, 10B, 10R, 10G, 10B, ...
  • the display electrode pair 21 may be configured by an electrode having a high aperture ratio, such as a mesh electrode formed only by a transparent electrode.
  • the intersection between the signal electrode 31 and the display electrode pair 21 is a unit light emitting region (unit discharge region).
  • one of the display electrodes 211 and 212 is used as a scanning electrode, and a selective discharge is generated at the intersection between the scanning electrode and the signal electrode 31 to select a light emitting region.
  • display discharge is generated between the display electrodes 211 and 212 by using wall charges formed on the inner surface of the light emitting yarn in the region.
  • the selective discharge is a counter discharge generated in the light emitting yarn between the scanning electrode and the signal electrode 31 facing vertically.
  • the display discharge is between the display electrodes 211 and 212 arranged in parallel on the plane. Is a surface discharge generated in the light emitting yarn. With such an electrode arrangement, a plurality of light emitting regions are formed in the longitudinal direction inside the light emitting yarn.
  • the electrode structure shown in the figure has a configuration in which three electrodes are arranged in one light emitting region, and a force that is a structure in which a display discharge is generated by the display electrodes 211 and 212 is not limited to this.
  • a display discharge may be generated between the display electrodes 211 and 212 and the signal electrode 31. That is, the display electrode 211, 212 is a single electrode, and this single display electrode is used as a scanning electrode to generate a selective discharge and a display discharge (opposite discharge) between the data electrode 3. May be.
  • the front support substrate 20 and the back support substrate 30 may be a glass substrate or a substrate made of a transparent polymer material or the like.
  • FIG. 2 is a schematic diagram showing the structure of one pixel of the plasma tube array 100 shown in FIG.
  • each of the light emitting yarns 10R, 10G, and 10B has a protective film 12 such as MgO formed on the inner surface of the glass tube 11, and each phosphor layer 14R that emits fluorescence of each color R, G, B in the glass tube 11
  • the boat 13 which is a support member on which 14G and 14B are formed is inserted (see Patent Document 2).
  • FIG. 3 is a view showing a boat on which a phosphor layer is formed.
  • the boat 13 has a semicircular cross section or a shape similar to the cross section, and has a glass tube 11
  • Each of the light emitting yarns 10R, 10G, and 10B shown in FIG. 2 is configured by inserting a boat 13 having the shape shown in FIG. In FIG. 2, it is shown that the display electrode pair 21 including the two display electrodes 211 and 212 is arranged on the light emitting yarns 10R, 10G, and 10B. As described above, these two display electrodes 211 and 212 are composed of metal bus electrodes 21 la and 212a and transparent electrodes 21 lb and 212b.
  • Luminescent yarn 10R, 10G, 10B The diameter of each piece is typically about lmm. In the case of the structure shown in FIG. 2, the size of the area D1 of 1 pixel is 3 mm. X 3mm.
  • FIG. 4 is a diagram showing the front support substrate 20 and the display electrodes 211 and 212 formed on the front support substrate 20.
  • two display electrodes 211 and 212 extending in parallel to each other on the inner surface of the front support substrate 20 so that a surface discharge gap G is formed between them.
  • a display electrode pair 21 is formed.
  • a large number of display electrode pairs 21 are formed, and reverse slits S are formed between adjacent display electrode pairs 21 to prevent discharge.
  • the two display electrodes 211 and 212 constituting the display electrode pair 21 are formed of transparent electrodes 212b and 21 lb made of an ITO thin film on the side close to the surface discharge gap G, and are separated from the surface discharge gap G.
  • the side (reverse slit S side) is formed of bus electrodes 21 la and 212a made of a metal material.
  • the transparent electrodes 212b and 21 lb are for facilitating emission light of the phosphor layer in the discharge space corresponding to the surface discharge gap G through the glass substrate 11 and being emitted to the front surface.
  • the nose electrodes 211a and 212a are for lowering the resistance value of the display electrodes 211 and 212.
  • the widths of the nose electrodes 211a and 212a which decreases the resistance value of the display electrodes 211 and 212.
  • the emitted light from the phosphor layer is easily blocked, the light emission is reduced.
  • the width of the bus electrodes 21 la and 212a is narrowed so as not to block the emitted light of the phosphor layer force, the light use efficiency will be reduced and it will be difficult to obtain a bright display screen.
  • the resistance values of the display electrodes 211 and 212 increase.
  • the reverse slit S is a non-light emitting portion.
  • the bus electrodes 211a and 212a are widened to the reverse slit S side. This may not be possible, but this may not be possible because a discharge may occur in the reverse slit S.
  • Patent Document 1 Japanese Patent Laid-Open No. 61-103187
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-86141
  • An object of the present invention is to provide a display device that satisfies both requirements at a high level. Means for solving the problem
  • the first plasma tube array of the plasma tube array of the present invention that achieves the above object includes a plurality of arc tubes each having a phosphor layer and arranged in parallel to each other, and A front support substrate and a rear support substrate that sandwich the arc tube, a plurality of display electrodes formed on a plurality of arc tube facing surfaces of the front support substrate in a direction straddling the plurality of arc tubes, and a rear support substrate A plurality of signal electrodes formed in a direction along the arc tube in association with each of the arc tubes, and a plurality of display electrode forming surfaces of the front support substrate. Is provided with a plurality of wirings formed on the opposite display surface in the extending direction of the plurality of display electrodes and connected to each of the plurality of display electrodes.
  • the second plasma tube array of the plasma tube array of the present invention includes a plurality of arc tubes having a phosphor layer therein and arranged in parallel to each other, and the plurality of arc tubes.
  • Front support substrate and rear support substrate to be sandwiched, a plurality of display electrodes formed on a plurality of arc tube facing surfaces of the front support substrate in a direction straddling the plurality of arc tubes, and a plurality of back support substrates
  • a plurality of signal electrodes formed in a direction along the arc tube, and an inner surface on which a pair of display electrodes on the front substrate is arranged on the surface facing the arc tube.
  • a plurality of unit panels having a plurality of wirings formed on the outer surface of the back side corresponding to the display electrodes and extending in parallel with the display electrodes and connected to the corresponding display electrodes, respectively.
  • the wiring is characterized by comprising the connection extend over units adjacent panels connected.
  • each of the display electrodes may be an electrode force formed of a light transmissive material, or each of the display electrodes. At least part of it may consist of mesh electrodes made of metallic materials! /.
  • the display electrode and the wiring are connected to each of both ends of the front substrate by a metal wire straddling the end surface of the front substrate. It is preferable.
  • the wiring is preferably formed at a position facing the reverse slit with a gap narrower than the width of the reverse slit.
  • the display electrodes 211 and 212 are formed in place of the bus electrodes 21 la and 212a in the conventional example shown in FIG. 4 or wiring for assisting the bus electrodes 21 la and 212a. Since it is provided on the outer surface opposite to the inner surface, the resistance values of the display electrodes 211 and 212 are equivalently reduced, so that the width of the bus electrodes 21 la and 212a can be reduced, for example, and the emission in the phosphor layer is increased. It can be used efficiently.
  • FIG. 1 is a perspective view showing a basic structure of a plasma tube array.
  • FIG. 2 is a schematic diagram showing the structure of one pixel of the plasma tube array.
  • FIG. 3 is a view showing a board on which a phosphor layer is formed.
  • FIG. 4 is a diagram showing a front support substrate and display electrodes formed on the front support substrate.
  • FIG. 5 is a diagram showing a front support substrate and display electrodes formed on the front support substrate of the plasma display panel according to the first embodiment of the present invention.
  • FIG. 6 is a diagram showing a connection method between display electrodes formed on the inner surface of the front support substrate and wirings formed on the outer surface in the first embodiment shown in FIG. 5.
  • FIG. 7 is a view showing a front support substrate and display electrodes formed on the front support substrate of the plasma display panel according to the second embodiment of the present invention.
  • FIG. 8 shows a connection method between display electrodes and wiring in the second embodiment shown in FIG. FIG.
  • FIG. 9 is a plan view showing a state in which a plurality of basic panels according to the present invention are connected as in the second embodiment shown in FIGS. 7 and 8.
  • FIG. 10 is a perspective view showing a state in which a plurality of basic panels according to the present invention are connected as in the second embodiment shown in FIGS. 7 and 8.
  • FIG. 5 is a diagram showing the front support substrate 20 and the display electrodes 211 and 212 formed on the front support substrate 20 of the plasma tube array according to the first embodiment of the present invention.
  • a display electrode 2 consisting only of transparent electrodes 21 lb and 212b is provided.
  • wiring 43 corresponding to the bus electrodes 211a and 212a is formed on the outer surface of the front support substrate 20.
  • FIG. 6 is a diagram showing a connection method between the display electrodes 211 and 212 formed on the inner surface of the front support substrate 20 and the wiring 43 formed on the outer surface in the first embodiment shown in FIG. is there.
  • the display electrodes 211 and 212 formed on the inner surface of the front support substrate 20 and the wiring 43 formed on the outer surface of the front support substrate 20 are connected by metal wires 45 on both sides of the front support substrate 20. Has been.
  • the wiring 43 is made of a CrZCuZCr metal thin film and is black with low reflectance. These wirings 43 are formed at a position facing the reverse slit S at intervals T narrower than the reverse slit S so as to cover the reverse slit S, and the reflectance of the entire panel is reduced, and the bright room contrast is reduced. Improvements are being made.
  • the wiring 43 is in contact with the atmosphere and has such a narrow interval T where the withstand voltage is high. Even discharge can be avoided sufficiently.
  • the wiring 43 can be formed with a sufficient width, the reflectance can be lowered only by, for example, providing an oxide film on the surface of the wiring 43.
  • the display electrodes 211 and 212 may be formed of a mesh-like metal thin film having an opening sufficient to transmit emitted light instead of the transparent electrodes 212b and 21 lb.
  • FIG. 7 is a diagram showing the front support substrate 20 and the display electrodes 211 and 212 formed on the front support substrate 20 of the plasma tube array according to the second embodiment of the present invention. Differences from the first embodiment shown in FIG. 5 will be described.
  • the surface electrodes 211 and 212 are formed by only the transparent electrodes 212b and 212b.
  • the transparent electrode alone has a sufficiently low resistance value even if the wiring 43 is included. In some cases, it cannot be obtained, and there is a drawback that disconnection is likely to occur. Therefore, in the second embodiment shown in FIG. 7, the display electrodes 211 and 212 are composed of transparent electrodes 211b and 212b and bus electrodes 21la and 212a having a metal thin film force, as in the conventional example shown in FIG. Yes.
  • the wiring 43 is provided on the outer surface of the front support substrate 20, and the self electrode 43 is connected to the display electrodes 211 and 212 by both sides J of the front support substrate 20.
  • the width of la, 212a is sufficiently narrower than that of the conventional example shown in FIG. 4, and the utilization efficiency of emitted light in the phosphor layer can be improved.
  • FIG. 8 is a diagram showing a connection method between the display electrodes 211 and 212 and the wiring 43 in the second embodiment shown in FIG. Although only one display electrode 211 is shown here, it is common to all the display electrodes 211 and 212.
  • the wiring 43 is connected to the bus electrode 21 la made of a metal thin film among the display electrodes 211 by a wire 45. This is because when the wire 45 is connected by a soldering technique, the bus electrode 21 la made of a metal thin film can be soldered more strongly than the transparent electrode 21 lb.
  • FIG. 9 and FIG. 10 are the same as the second embodiment shown in FIG. 7 and FIG.
  • FIG. 3 is a plan view and a perspective view, respectively, showing a state in which a plurality of basic panels (here, two panels, A panel and B panel) are connected. Again, only the full support substrate on the front side of the display device is shown.
  • a plurality of basic panels here, two panels, A panel and B panel
  • the A panel and the B panel are arranged in a direction in which the wiring 43 extends linearly across the two panels, and the wiring 43 of the two panels is adjacent to the panel by the wire 46. Connected across
  • the electrode structure in which the wiring 43 is formed on the outer surface of the glass substrate is employed, it is possible to connect a plurality of panels as shown in FIGS. 9 and 10 to constitute an ultra-large display system.
  • a plurality of panels can be driven by a single drive circuit.
  • the advantages are as follows. First, the circuit cost is reduced. The second is the power of image continuity between panels.
  • the sustain electrodes are connected even if there are multiple panels, they can be regarded as one electrode, so there is no variation in luminance due to the difference in display load. For this reason, even if an ultra-large display system is configured, the display quality is good because the continuity of the video is good.
  • each panel is driven by an independent drive circuit, so each panel can be displayed even if one image is displayed on each panel.
  • the load of the video that is in charge of is different and the expression of brightness and gradation is inconsistent.
  • the panel load is different, so the APC point that adjusts the panel power 'brightness' is shifted, which causes the drive frequency to be different.
  • the result is that the continuity of line brightness cannot be maintained.
  • a low-cost, low-resistance display electrode, a low-reflectance panel, and a super-large panel can be realized.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Gas-Filled Discharge Tubes (AREA)

Abstract

La présente invention concerne une matrice de tubes plasma comportant un substrat supportant le plan avant (11) et un substrat supportant le plan arrière, placés l’un au-dessus de l'autre en formant entre eux un espace de décharge ; une pluralité d’électrodes compteuses d’affichage (21) placées sur un plan interne du substrat de support (11) ; et une pluralité d’électrodes de signal placées sur le substrat arrière. La matrice de tubes plasma affiche une image en émettant de la lumière par application d’une tension aux électrodes de signal et aux électrodes compteuses d’affichage (21). Les besoins conflictuels de blocage de lumière par les électrodes d’affichage (211, 212) et de résistance des électrodes d’affichage sont tous deux satisfaits à haut niveau. Sur un plan extérieur du substrat supportant le plan avant (11) sont disposées une pluralité de câblages (43) correspondant aux électrodes d’affichage (211,212) s’étendant parallèlement aux électrodes d’affichage (211, 212) et connectés à chacune des électrodes d’affichage (211, 212).
PCT/JP2005/006093 2005-03-30 2005-03-30 Matrice de tubes plasma WO2006103762A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007510287A JPWO2006103762A1 (ja) 2005-03-30 2005-03-30 プラズマチューブアレイ
PCT/JP2005/006093 WO2006103762A1 (fr) 2005-03-30 2005-03-30 Matrice de tubes plasma
US11/905,138 US20080024049A1 (en) 2005-03-30 2007-09-27 Plasma tube array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/006093 WO2006103762A1 (fr) 2005-03-30 2005-03-30 Matrice de tubes plasma

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/905,138 Continuation US20080024049A1 (en) 2005-03-30 2007-09-27 Plasma tube array

Publications (1)

Publication Number Publication Date
WO2006103762A1 true WO2006103762A1 (fr) 2006-10-05

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PCT/JP2005/006093 WO2006103762A1 (fr) 2005-03-30 2005-03-30 Matrice de tubes plasma

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US (1) US20080024049A1 (fr)
JP (1) JPWO2006103762A1 (fr)
WO (1) WO2006103762A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8327395B2 (en) * 2007-10-02 2012-12-04 The Nielsen Company (Us), Llc System providing actionable insights based on physiological responses from viewers of media
JP5047872B2 (ja) * 2008-04-30 2012-10-10 篠田プラズマ株式会社 ガス放電管および表示装置
JP5047071B2 (ja) * 2008-06-18 2012-10-10 篠田プラズマ株式会社 発光管アレイ型表示サブモジュール及び表示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11162358A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Ind Co Ltd 画像表示装置及びその製造方法
JP2001265256A (ja) * 2000-03-17 2001-09-28 Fujitsu Ltd 表示装置
JP2002196685A (ja) * 2000-12-26 2002-07-12 Sumitomo Chem Co Ltd 透明電極付き基板、その製造方法及び用途
JP2003338244A (ja) * 2002-05-17 2003-11-28 Fujitsu Ltd 発光管アレイ型表示装置
JP2004288492A (ja) * 2003-03-24 2004-10-14 Fujitsu Ltd 表示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532578B2 (ja) * 1991-05-31 2004-05-31 三菱電機株式会社 放電ランプおよびこれを用いる画像表示装置
JP2003045337A (ja) * 2001-07-31 2003-02-14 Fujitsu Ltd 表示管および表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11162358A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Ind Co Ltd 画像表示装置及びその製造方法
JP2001265256A (ja) * 2000-03-17 2001-09-28 Fujitsu Ltd 表示装置
JP2002196685A (ja) * 2000-12-26 2002-07-12 Sumitomo Chem Co Ltd 透明電極付き基板、その製造方法及び用途
JP2003338244A (ja) * 2002-05-17 2003-11-28 Fujitsu Ltd 発光管アレイ型表示装置
JP2004288492A (ja) * 2003-03-24 2004-10-14 Fujitsu Ltd 表示装置

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US20080024049A1 (en) 2008-01-31
JPWO2006103762A1 (ja) 2008-09-04

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