WO2006090444A1 - Appareil de charge/decharge, appareil d'affichage, ecran plasma et procede de charge/decharge - Google Patents

Appareil de charge/decharge, appareil d'affichage, ecran plasma et procede de charge/decharge Download PDF

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Publication number
WO2006090444A1
WO2006090444A1 PCT/JP2005/002900 JP2005002900W WO2006090444A1 WO 2006090444 A1 WO2006090444 A1 WO 2006090444A1 JP 2005002900 W JP2005002900 W JP 2005002900W WO 2006090444 A1 WO2006090444 A1 WO 2006090444A1
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WO
WIPO (PCT)
Prior art keywords
groups
electrodes
voltage
pulse
charging
Prior art date
Application number
PCT/JP2005/002900
Other languages
English (en)
Japanese (ja)
Inventor
Koichi Sakita
Tadayoshi Kosaka
Hajime Inoue
Kazushige Takagi
Yoshiho Seo
Original Assignee
Hitachi Plasma Patent Licensing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Plasma Patent Licensing Co., Ltd. filed Critical Hitachi Plasma Patent Licensing Co., Ltd.
Priority to JP2007504579A priority Critical patent/JP4372191B2/ja
Priority to PCT/JP2005/002900 priority patent/WO2006090444A1/fr
Publication of WO2006090444A1 publication Critical patent/WO2006090444A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • Charge / discharge device display device, plasma display panel, and charge / discharge method
  • the present invention relates to recovery of electrical energy stored in a capacitance, and in particular, by applying a pulse voltage to a capacitor formed in a cell constituting a screen of a plasma display panel (PDP).
  • PDP plasma display panel
  • the present invention relates to a charge / discharge device for recovering accumulated charges, a plasma 'display' panel, and a charge / discharge method.
  • Japanese Patent Laid-Open No. 11-338416 (A) published on December 10, 1999 describes a method of driving a plasma 'display' panel.
  • the potential of the electrode is changed at high speed without using an inductor, and stable power recovery is performed regardless of the voltage application pattern to a plurality of cells to reduce power consumption.
  • the first terminal of the capacitive element for power recovery is connected to the electrode, and the second terminal of the capacitive element is set to be lower than the second potential line GND and the potential difference from the second potential line is the first potential.
  • Power is recovered by temporarily fixing it to a potential higher than the potential difference between the line Vs and the second potential line GND (12Vs).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 11-338416
  • Japanese Laid-Open Patent Publication No. 11-338418 (A) published on December 10, 1999 describes a plasma display panel driving method and a plasma display panel device.
  • a low-cost reactive power recovery circuit is installed in the PDP divided into multiple blocks.
  • Two X electrodes are connected via FET and coil
  • two Y electrodes are connected via FET and coil
  • the first X electrode and second Y electrode force are connected via SFET and coil.
  • the second Y electrode and the first X electrode are connected to the FET via a coil.
  • the energy stored in the capacitance between the first X electrode and the first Y electrode paired with the second X of another pair Release into the capacitance between the electrode and the second Y electrode.
  • the potential of the second X electrode reaches the potential Vs.
  • the first X electrode is grounded.
  • Patent Document 2 Japanese Patent Laid-Open No. 11-338418
  • Japanese Unexamined Patent Publication No. 2000-338934 (A) published on December 8, 2000 describes a method for driving a capacitive load.
  • this driving method in driving a capacitive load that binaryly controls each electrode potential of the electrode pair, one electrode of the electrode pair is connected to the bias potential line via the primary winding of the transformer, and the transformer The secondary electrode is connected to the ground potential line, and the other electrode of the electrode pair is connected to the ground potential line to charge the capacitance between the electrodes of the electrode pair.
  • Patent Document 3 Japanese Patent Laid-Open No. 2000-338934
  • Japanese Patent Laid-Open No. 2003-76321 (A) published on March 14, 2003 includes plasma.
  • 'Display panel display device in the pair of display electrodes, in the sustain period, a driving waveform process is performed in which the rising period of one electrode is temporally overlapped with the falling period of the other electrode.
  • the interval between sustain pulses applied to the pair of display electrodes is shortened without making the slope of the rise and fall of the pulse waveform steep.
  • Patent Document 4 Japanese Patent Laid-Open No. 2003-76321
  • the sustaining panel When the sustaining panel is applied to the display electrode of the PDP via the inductor by the recovery capacitor that stores the recovered electrical energy, the sustaining power rise time S tends to be longer. is there.
  • the inductor requires an inductance having a required magnitude in order to supply electrical energy to the display electrode in a resonant manner. If the inductance of the inductor is reduced, the recovery efficiency of electrical energy decreases.
  • An object of the present invention is to realize a circuit that applies a pulse having a short rise time to an electrode.
  • Another object of the present invention is to shorten the delay from the start of pulse application to the electrode until discharge.
  • Yet another object of the present invention is to reduce the width of a pulse applied to an electrode.
  • Still another object of the present invention is to increase the recovery efficiency of electrical energy accumulated in the charge / discharge capacitance.
  • the charge / discharge device charges and discharges a plurality of capacitances divided into a plurality of g gnoles by applying a voltage, and further, one terminal is coupled to the common conductor potential.
  • One terminal of each of the plurality of resonant inductors is coupled to the capacitance of each of the g groups, and the other terminal of each of the plurality of resonant inductors is coupled to the other terminal of the recovery capacitor. .
  • the charging / discharging device further includes a first path forming means for charging the capacitance of each of the g groups from the recovery capacitor through the g resonant inductors, and the capacitance of the g gnorapes.
  • a first path forming means for charging the capacitance of each of the g groups from the recovery capacitor through the g resonant inductors, and the capacitance of the g gnorapes.
  • a second path forming means for recovering electrical energy to the recovery capacitor via each resonance inductance; and a control means for controlling the first and second path forming means.
  • the present invention also relates to a display device and a plasma “display” panel including the above-described charge / discharge device.
  • the present invention also relates to a charge / discharge method for realizing the functions of the above-described charge / discharge device.
  • the rise time of the pulse applied to the electrode can be shortened, the width of the pulse applied to the electrode can be reduced, and a larger number of pulse positions can be secured within a predetermined period.
  • the display quality of the display device can be improved, and the recovery efficiency of the electrical energy accumulated in the charge / discharge capacitance can be increased.
  • FIG. 1 shows a configuration of a typical display device 60 according to an embodiment of the present invention.
  • the display device 60 includes a three-electrode surface discharge type PD P10 having a display surface with an array power of n X m cells, and a drive unit 50 for selectively emitting an array of cells.
  • PD P10 having a display surface with an array power of n X m cells
  • drive unit 50 for selectively emitting an array of cells.
  • it is used for a television receiver, a computer system monitor, and the like.
  • the display electrode X is a sustain electrode
  • the display electrode Y is a scan electrode.
  • the display electrodes X and Y typically extend in the row or horizontal direction of the screen, and the address electrode A extends in the column or vertical direction.
  • the drive unit 50 includes a driver control circuit 51, a data conversion circuit 52, a power supply circuit 53, an X electrode driver circuit or X driver circuit 61, a Y electrode driver circuit or Y driver circuit 64, and an address electrode driver circuit or A.
  • the drive unit 50 receives field data Df indicating the emission intensity of the three primary colors R, G, and B together with various sync signals from an external device such as a TV tuner or a computer.
  • the finale data Df is temporarily stored in the field memory in the data conversion circuit 52.
  • the data conversion circuit 52 converts the field “data Df” into the subfield “data Dsf for gradation display” and supplies it to the A driver circuit 68.
  • the subfield 'data Dsf is a set of display data of 1 bit per cell, and the value of each bit represents whether or not light emission of each cell in the corresponding subfield SF is required.
  • the X driver circuit 61 includes a reset circuit 62 that applies a voltage for initialization to the display electrode X in order to equalize the wall voltages of a plurality of cells constituting the PDP display surface, and a display release to the cells. And a sustain circuit 63 for applying a sustain pulse to the display electrode X to generate electricity.
  • the Y driver circuit 64 includes a reset circuit 65 that applies a voltage for initialization to the display electrode Y, a scan circuit 66 that applies a scan pulse to the display electrode Y in addressing, and a display discharge in the cell. And a sustain circuit 67 for applying a sustain panorace to the display electrode Y.
  • the A driver circuit 68 applies an address pulse to the address electrode A designated by the subfield “data Dsf” according to the display data.
  • the driver control circuit 51 controls the application of the pulse voltage and the transfer of the subfield “data Dsf”.
  • the power supply circuit 53 supplies driving power to a required part in the unit.
  • a picture is typically composed of one frame period. In interlaced scanning, one frame consists of two fields, and in progressive scanning, one frame consists of one field. It is configured.
  • one field F in the time series of the input image of such one field period is divided into a predetermined number q of subfields SF. .
  • each field F is replaced with a set of q subfields SF.
  • the field period Tf which is a field transfer period, is divided into q subfield periods Tsf in accordance with such a field configuration, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission.
  • the length of the reset period TR and the address period TA is constant regardless of the weight, while the number of displays in the display period TS increases as the weight increases. The longer the weight, the longer. In this case, the length of the subfield period Tsf is longer as the weight of the corresponding subfield SF is larger.
  • FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of the X driver circuit 61, the Y driver circuit 64, and the A driver circuit 68 according to an embodiment of the present invention.
  • the illustrated waveform is an example, and the amplitude, polarity, and timing can be changed variously.
  • the order of the reset period TR, the address period TA, and the sustain period TS is the same in the q subfields SF, and the drive sequence is repeated for each subfield SF.
  • a negative polarity pulse Prxl and a positive polarity pulse Prx2 are sequentially applied to all the display electrodes X, and a positive polarity pulse Pry is applied to all the display electrodes Y. 1 and negative polarity pulse Pry2 are applied in order.
  • Panores Prxl, Pryl, and Pry2 are ramp waveforms or blunt pulses that gradually increase in amplitude at the rate of change at which a microdischarge occurs.
  • the first applied pulses Prxl and Pry 1 are applied to generate an appropriate wall voltage of the same polarity in all cells regardless of whether light is emitted or not in the previous subfield SF.
  • the wall voltage can be adjusted to a value corresponding to the difference between the discharge start voltage and the pulse amplitude.
  • the drive voltage applied to the cell is a composite voltage representing the difference in the amplitude of the panel applied to the display electrodes X and Y.
  • a negative scan pulse Vy is applied to display electrode Y corresponding to the selected row for each row selection period (scanning time for one row). Apply.
  • the address discharge should occur at the same time as this row selection. Apply the address pulse Va only to the address electrode A corresponding to the selected cell. That is, the potential of the address electrode A1—Am is binary-controlled based on the subfield 'data Dsf for m columns of the selected row j.
  • a discharge occurs between the display electrode Y and the address electrode A.
  • the address discharge is a trigger, and the subsequent surface discharge between the display electrodes XY occurs.
  • sustain “Panores Ps having a predetermined polarity (positive polarity in the example in the figure) is first applied to all the display electrodes Y. Thereafter, sustain “Panores Ps” is alternately applied to the display electrode X and the display electrode Y.
  • the amplitude of the sustain pulse Ps is the sustain voltage Vs.
  • Sustain 'Panores Ps surface discharge occurs in the cell where the predetermined wall charge remains.
  • the number of times the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above.
  • the address electrode A is biased to a voltage Vas having the same polarity as the sustaining panorless Ps in order to prevent unnecessary counter discharge throughout the sustain period TS.
  • a capacitance C formed by each pair of display electrodes Xj and Yj has a capacitance C.
  • the sustain circuits 63 and 67 in FIG. 1 apply the voltages Vs of the two series of sustain pulses Ps in FIG. 2 between the pair of display electrodes Xj and Yj, respectively.
  • FIG. 3 shows a normal pulse power supply and recovery circuit 11 having an electrical energy recovery or power recovery function and a clamp circuit 14 used in the sustain circuits 63 and 67 for the PDP 10.
  • a pulse power supply and recovery circuit 11 has a capacity Cr (for example, 100 times or more of Cpa) sufficiently larger than the total panel capacity Cpa between n pairs of display electrodes X and Y, and one terminal.
  • a capacity Cr for example, 100 times or more of Cpa
  • a common resonance in which one terminal is coupled to the connection point between D2 and the other terminals of diodes D1 and D2, and the other terminal is coupled to one of the n pairs of display electrodes (X or Y) of capacitance Cpa.
  • an inductor L1 for example, 100 times or more of Cpa
  • the inductance L of the resonant inductor L1 is typically 200-500nH.
  • the clamp circuit 14 includes a constant voltage source Vs of a predetermined voltage Vs coupled via a switch SW2 to a connection point between the other terminal of the resonant inductor L1 and one display electrode (X or Y). The connection point is connected to the ground point GND via the switch SW4.
  • the charge capacitor Cr generally accumulates electric charge of voltage Vs / 2, and the total panel capacitance Cpa of the n pairs of display electrodes does not accumulate electric charge. To do. Therefore, the panel capacitance Cpa, that is, the value of the voltage V at each capacitance C is
  • Switch SW4 is turned on. Its peak voltage Vpmin is slightly higher than the ground potential GND or 0 V. Thereafter, switch SW3 is turned off. The ground point GND of the clamp circuit 14 clamps the voltage V of the panel capacitance Cpa to the ground potential GND or 0V.
  • switch SW4 is turned off. In this way, most of the electric charge supplied from the recovery capacitor Cr to the total panel capacitance Cpa, that is, electric power is recovered.
  • the resistance R represents the resistance inherent in the display electrode. It can be seen that the quantities are coupled in series between Cpa. Panel capacity Cpa value Cpa
  • Vp max —— (1 + e
  • the rise time Tr is proportional to the square root of the product LCp.
  • the rise time and fall time Tr are short.
  • the power recovery efficiency ⁇ is expressed by the following equation.
  • FIG. 4 shows a pulse voltage application circuit 602 used in the sustain circuits 63 and 67 for the PDP 10 according to the embodiment of the present invention.
  • the n pairs of display electrodes X and Y of the PDP 10 are divided into a plurality of g groups Gl, G2,... Gg (2 ⁇ g ⁇ n).
  • the number of each display electrode pair in the groups Gl, G2,... Gg is approximately equal to each other, but may not be exactly equal to each other.
  • the pulse voltage application circuit 602 includes a pulse power supply and recovery circuit 110 having an electrical energy recovery function, that is, a power recovery function, and clamp circuits 141, 142, ⁇ provided in the respective groups G1 to Gg. ⁇ 148 and control signal generation circuit 160.
  • the pulse power supply and recovery circuit 110 supplies power to the electrodes X and Y of the nZg pair of each group G1 Gg at the rise of the pulse Ps and collects power at the fall force S of the pulse Ps.
  • Each of the clamp circuits 141 1 to 148 applies a voltage V between a corresponding pair of nZg display electrodes X and Y connected in parallel to each other.
  • the pulse power supply and recovery circuit 110 has a power recovery capacitor Cr having one terminal coupled to a common conductor potential or a ground point GND, and forms a path 1 connected in series to the recovery capacitor Cr. Recovering capacitor Cr to other terminal via switch SW1
  • the diode D1 to which the cathode (anode) is coupled and the power sword (cathode) via the switch SW2 are connected to the other terminal of the recovery capacitor Cr so as to form a path 2 in series with the capacitor Cr and in parallel with the diode D1.
  • Common resonant inductors L21 to L28 are provided for the electrodes Z and Y of the nZg pair of each group G1 Gg. Resonant inductors L21-L28 have equal inductances L. Inductance L is the inductance of inductor L1 in Figure 3.
  • g 'L (g' ⁇ g) that is somewhat smaller than g times the case L, for example 400nH 5mH.
  • g ′ may be 7.
  • Each of the power clamp circuits 141 1 to 148 has a switch SW21 corresponding to the connection point of one display electrode X or Y of the display electrode pair X and Y of the corresponding group Gl, G2,. SW22,... Constant voltage source Vs of a predetermined voltage Vs coupled through SW28 and switch SW41, SW42,... SW48 corresponding to the connection point.
  • the point GND is included.
  • the clamp circuits 141, 142,..., 148 have the same configuration.
  • the control signal generation circuit 160 controls the on / off operation of the switches SW1, SW21, H * SW28, SW3, SW41, "-SW4 8 in the pulse power supply and recovery circuit 110 and the clamp circuit 141-148.
  • Signal C
  • SW4 is generated.
  • the switches SW1, SW21—SW28, SW3, and SW41—SW48 are generated.
  • FIG. 5 shows a control signal C of the control signal generation circuit 160 of FIG. 4 for controlling the switch SW1 SW48 according to the embodiment of the present invention.
  • Each group display electrode capacitance Cpb voltage V is peak voltage Vpm
  • switch SW21 SW28 is turned on. Note that no current flows in the direction opposite to the supply current due to the diode D1. Therefore, switch SW1 must be turned off at any timing between the time when the peak voltage is reached and the time when switch SW21—SW28 turns off. Its peak voltage Vpmax is slightly lower than voltage Vs. In this case, the rise time Tr is shorter than in the case of the conventional pulse power supply and recovery circuit 11 of FIG.
  • the voltage source Vs of the clamp circuit 141 1 148 clamps the voltage V of each group display electrode capacitance Cpb to the voltage Vs, and each group display electrode capacitance
  • Cpb voltage V is maintained at voltage Vs.
  • Cpb 1 148 compensates the voltage V of the panel capacitance Cpb so that it becomes a predetermined voltage Vs. After that, sustain discharge occurs,
  • SW21—SW28 are turned off according to control signal C 1 C.
  • Switch SW41-SW48 is turned on according to control signal C
  • the switch SW3 may be turned off at any timing before the turn-off timing of the force switch SW41—SW48 after reaching the peak voltage.
  • Its peak voltage Vpmin is slightly higher than the ground potential GND or 0V.
  • the fall time Tr is shorter than that of the conventional pulse power supply and recovery circuit 11 of FIG. Clamp circuit 141 1 148 grounding point GND is connected to the voltage V of each group display electrode capacitance Cpb.
  • 6A and 6B show a comparison of the pulse Ps waveforms by the pulse power supply and recovery circuit 11 of FIG. 3 and the pulse power supply and recovery circuit 110 of FIG.
  • the rise time and fall time Tr of the pulse Ps are shorter than the pulse Ps of the pulse power supply and recovery circuit 11 in FIG.
  • FIGS. 7A and 7B show a comparison of waveforms of another pulse Ps by the pulse power supply and recovery circuit 11 of FIG. 3 and the pulse power supply and recovery circuit 110 of FIG.
  • the rise time and fall time Tr of the pulse Ps is the same force as the pulse Ps of the pulse power supply and recovery circuit 11 in Fig. 3
  • the peak voltage Vpmax is higher than the pulse Ps of the pulse power supply and recovery circuit 11 in Fig. 3
  • the power supply efficiency and the power recovery efficiency are higher when the peak voltage Vpmin is lower.
  • FIG. 8 shows a pulse voltage application circuit 604 according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit 602 of FIG.
  • the inductors L21-L28 coupled to the power sword of diode 1 are the same as those in FIG. 4
  • the inductance L of the inductor is larger than the inductance L of the inductor L21—L28 (L> L). In this case, Panole
  • the rise time Tr of the pulse Ps is shortened, and the negative peak V at the fall of the pulse Ps V
  • the power recovery efficiency ⁇ can be increased by lowering pmin.
  • switch SW1 and diode D1 in FIGS. 4 and 8 may be interchanged.
  • the arrangement of the switch SW3 and the diode D2 may be switched.
  • FIG. 9 is a circuit diagram of the pulse voltage application circuit 602 of FIG. 4 used in the sustain circuits 63 and 67 for the PDP 10 and another pulse voltage marking circuit of the same configuration according to another embodiment of the present invention.
  • 603 is shown.
  • the display electrodes X and ⁇ of the ⁇ pair are divided into a plurality of 2g gnorapes Gl, G2... G2g (2 ⁇ g ⁇ nZ4).
  • a pulse voltage application circuit 602 is provided for the display electrode pair X and Y of the first g group G 1-1 Gg, and the display electrode pair X and Y of the second g group Gg + 1—G2g
  • a pulse voltage application circuit 603 is provided.
  • n pairs of display electrodes X and Y are divided into 3 g or more groups, and three or more pulse voltage application circuits having the same configuration as the pulse voltage application circuit 602 are provided.
  • One pulse voltage application circuit may be associated with each group.
  • n pairs of display electrodes X and Y are divided into 2g or more groups, and two or more pulse voltage application circuits having the same configuration are provided, as shown in FIG. Each g group may be associated with one pulse voltage application circuit.
  • the present invention is not limited to this, for example, organic and inorganic EL, and electronic paper that displays characters by storing charges by applying voltage. Is also applicable.
  • FIG. 1 shows a configuration of a typical display device according to an embodiment of the present invention.
  • FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of an X driver circuit, a Y driver circuit, and an A driver circuit according to an embodiment of the present invention.
  • Fig. 3 shows the electrical energy recovery, ie, used in the sustain circuit for PDP.
  • a normal pulse power supply and recovery circuit having a power recovery function and a clamp circuit are shown.
  • FIG. 4 shows a panoramic voltage application circuit used in a sustain circuit for a PDP according to an embodiment of the present invention.
  • FIG. 5 shows the ON / OFF state of the control signal of the control signal generation circuit of FIG. 4 for controlling the switch, the display electrode capacitor and the recovery during pulse application according to the embodiment of the present invention. A schematic waveform of the voltage across the capacitor is shown.
  • FIGS. 6A and 6B show a comparison of the waveforms of the pulse power supply and recovery circuit of FIG. 3 and the pulse power supply and recovery circuit of FIG.
  • FIGS. 7A and 7B show a comparison of the waveforms of different pulses by the pulse power supply and recovery circuit of FIG. 3 and the pulse power supply and recovery circuit of FIG.
  • FIG. 8 shows a pulse voltage application circuit according to another embodiment of the present invention in which the pulse voltage application circuit of FIG. 4 is modified.
  • FIG. 9 shows the pulse voltage application circuit of FIG. 4 and another Nores voltage application circuit of the same configuration used in the sustain circuit for the PDP according to another embodiment of the present invention. ing.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

La présente invention décrit un appareil de charge/décharge (602) comprenant un condensateur de récupération d'énergie électrique (Cr) dont l'une des bornes est couplée à un potentiel de conducteur commun pour la charge/décharge des groupes g de condensateurs ainsi qu'une pluralité de bobines d'inductance résonnantes associées à l'un des groupes g respectifs. Pour chacune des bobines d'induction résonnantes, l'une des bornes est couplée à une borne respective du groupe g de capacitance et l'autre borne est couplée à l'autre borne du condensateur de récupération. L'appareil de charge/décharge (602) comprend de plus un premier moyen de formation de chemin (SW1, D1) permettant de charger les groupes g de capacitance à partir du condensateur de récupération via les bobines d'inductance résonnantes g (L21-L28), un second moyen de formation de chemin (SW3, D2) permettant de décharger les groupes g de capacitance afin de restaurer l'énergie électrique du condensateur de récupération par les bobines d'inductance résonnantes g, enfin un moyen de contrôle qui permet de contrôler les premiers et seconds moyens de formation de chemin.
PCT/JP2005/002900 2005-02-23 2005-02-23 Appareil de charge/decharge, appareil d'affichage, ecran plasma et procede de charge/decharge WO2006090444A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007504579A JP4372191B2 (ja) 2005-02-23 2005-02-23 充放電装置、表示装置、プラズマ・ディスプレイ・パネル、および充放電の方法
PCT/JP2005/002900 WO2006090444A1 (fr) 2005-02-23 2005-02-23 Appareil de charge/decharge, appareil d'affichage, ecran plasma et procede de charge/decharge

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PCT/JP2005/002900 WO2006090444A1 (fr) 2005-02-23 2005-02-23 Appareil de charge/decharge, appareil d'affichage, ecran plasma et procede de charge/decharge

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JPH09146490A (ja) * 1995-11-24 1997-06-06 Nec Corp 表示パネル駆動回路
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