WO2006059641A1 - Memoire magnetique - Google Patents

Memoire magnetique Download PDF

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Publication number
WO2006059641A1
WO2006059641A1 PCT/JP2005/021985 JP2005021985W WO2006059641A1 WO 2006059641 A1 WO2006059641 A1 WO 2006059641A1 JP 2005021985 W JP2005021985 W JP 2005021985W WO 2006059641 A1 WO2006059641 A1 WO 2006059641A1
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WO
WIPO (PCT)
Prior art keywords
wiring
magnetic
layer
electrically connected
storage areas
Prior art date
Application number
PCT/JP2005/021985
Other languages
English (en)
Japanese (ja)
Inventor
Keiji Koga
Original Assignee
Tdk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corporation filed Critical Tdk Corporation
Publication of WO2006059641A1 publication Critical patent/WO2006059641A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • the present invention relates to a magnetic memory that stores data in a magnetoresistive effect element.
  • MRAM Magnetic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SRAM Static RAM
  • An example of such an MRAM is a magnetic memory described in Patent Document 1, for example.
  • This magnetic memory is connected to a tunnel magnetoresistive (TMR) element, a wiring (cell bit line) for passing a write current to the TMR element, and a cell bit line for each storage area (memory cell). And a transistor.
  • the TMR element includes a first magnetic layer (magnetic layer) whose magnetization direction is changed by an external magnetic field, a second magnetic layer whose magnetization direction is fixed, a first magnetic layer, and a second magnetic layer. And a non-magnetic insulating layer sandwiched between them, and the binary magnetic data is obtained by controlling the magnetic field direction of the first magnetic layer in parallel or anti-parallel to the magnetic field direction of the second magnetic layer. It is an element to memorize.
  • TMR elements are arranged along the wiring (cell bit line) branched from the bit line to each storage area in order to prevent erroneous writing to the storage area that is not the target of writing.
  • a write current is selectively supplied to the cell bit line. This configuration eliminates the so-called half selection state of the TMR element and prevents erroneous writing to a non-selected storage area. Also, by arranging the TMR element so that one end of the TMR element is in contact with the cell bit line, a read current is supplied to the TMR element through the cell bit line.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-153182
  • the magnetic memory disclosed in Patent Document 1 has two write selection transistors: a write selection transistor for controlling the write current flowing through the cell bit line, and a read selection transistor for controlling the read current flowing through the TMR element.
  • a transistor is provided for each storage area. As described above, if two transistors for reading selection and writing selection are arranged for each storage area, a large space is required for each storage area, which is one factor that hinders the miniaturization of the MRAM.
  • Patent Document 1 describes a configuration for selectively supplying a read current to a TMR element as a wiring in the column direction (bit line) and a wiring in the row direction (word line) passing through the selected storage area.
  • a so-called cross-point configuration is also disclosed in which a read current is passed between the two.
  • a transistor for selecting a bit line and a transistor for selecting a word line are required for each column and each row, respectively. This will hinder downsizing.
  • the present invention has been made in view of the above-described problems, and an object thereof is to provide a magnetic memory that can prevent erroneous writing and can be miniaturized.
  • a magnetic memory includes a plurality of storage areas, and each of the plurality of storage areas includes a magnetosensitive layer whose magnetization direction is changed by an external magnetic field. It has an effect element and a wiring portion extending along the magnetosensitive layer. In-region wiring that provides an external magnetic field to the magnetosensitive layer by a write current that is electrically connected to one end of the intra-region wiring and one end of the magnetoresistive effect element. And switch means for controlling the conduction of the read current to the magnetoresistive element.
  • the switching means of the storage area when data is written to a certain storage area, the switching means of the storage area is preferably turned on, and a write current is supplied so as to flow between both ends of the wiring in the area.
  • a write current flows through a wiring portion extending along the magnetosensitive layer of the magnetoresistive element, and an external magnetic field is provided to the magnetosensitive layer to write data.
  • the magnetoresistive effect element since the magnetoresistive effect element has a higher resistance than the in-region wiring, the write current does not branch to the magnetoresistive effect element.
  • the switch means of the storage area is turned on, for example, the other end side of the wiring in the area is put in a high resistance state, and the current is supplied from the switch means. It is preferable to supply the read current to the magnetoresistive element. Data can be read by detecting the magnitude of the read current or the voltage across the magnetoresistive element.
  • the write current and the read current are controlled by one switch means, a conventional MRAM that requires two transistors in one storage area, or each column and Compared to a cross-point MRAM that requires a read transistor for each row, the storage area can be made smaller. Therefore, the MRAM can be further downsized.
  • intra-area wiring is provided for each storage area, and the write current flowing through the intra-area wiring can be controlled by the switch means provided in each storage area.
  • the effect element has no half-selected state and can prevent erroneous writing to a storage area that is not a write target.
  • the in-region wiring is electrically connected to one end of the magnetoresistive effect element at the wiring portion, and the read current is supplied to the magnetoresistive effect element from the switch means.
  • a plurality of storage areas are arranged in a two-dimensional shape with m rows and n columns (m and n are integers of 2 or more) force, and correspond to each column of the plurality of storage areas.
  • each of the storage areas a first wiring electrically connected to one end of the in-area wiring and one end of the magnetoresistive effect element via the switch means, and each column of the plurality of storage areas A second wiring electrically connected to the other end of the in-area wiring and a corresponding storage area in each of the storage areas of the corresponding column;
  • a third wiring connected to the control terminal of the switch means is provided corresponding to each row of the plurality of storage areas, and the other end of the magnetoresistive effect element is electrically connected to each storage area of the corresponding row.
  • a fourth wiring connected to the terminal.
  • a write current is supplied between the first wiring and the second wiring corresponding to the column including the storage area to be written, and the line including the storage area is connected to the row.
  • a control voltage for controlling the switch means to the conductive state By applying a control voltage for controlling the switch means to the conductive state to the corresponding third wiring, a write current can be suitably applied to the internal wiring in the storage area.
  • a read current is supplied between the first wiring corresponding to the column including the storage area to be read and the fourth wiring corresponding to the row including the storage area, and the row including the storage area is included.
  • a control voltage for controlling the switch means can be suitably passed to the magnetoresistive effect element in the storage area.
  • the magnetic memory is preferably electrically connected to the first and fourth wirings, and preferably further includes a read current supply means for supplying a read current to the magnetoresistive element.
  • the magnetic memory preferably further includes a write current supply unit that is electrically connected to the first and second wirings and supplies a write current to the in-region wiring.
  • the magnetic memory further includes a magnetic yoke provided so that each of the plurality of storage areas continuously surrounds the wiring portion of the intra-area wiring, and the magnetosensitive layer of the magnetoresistive effect element includes
  • the magnetic yoke may be constituted by a part of the magnetic yoke.
  • the wiring portion along the magnetosensitive layer is surrounded by the magnetic yoke, so that the magnetic field emitted in the direction in which the magnetosensitive layer force is deviated can be reduced.
  • the magnetosensitive layer is constituted by a part of the magnetic yoke surrounding the wiring portion, an external magnetic field can be efficiently provided to the magnetosensitive layer.
  • an external magnetic field due to a write current can be efficiently provided to the magnetosensitive layer of the magnetoresistive element, so that the magnetic direction of the magnetosensitive layer can be reversed with a small write current.
  • each of the plurality of storage areas includes at least a pair of open end portions facing each other through a gap of a predetermined length and surrounds a wiring portion of the intra-area wiring.
  • the magnetoresistive effect element may be arranged such that the pair of side surfaces of the magnetoresistive effect element are opposed to or in contact with the pair of open ends of the magnetic yoke, respectively.
  • the magnetic yoke has a pair of open ends facing or in contact with each of the pair of side surfaces of the magnetoresistive element, so that a magnetic field (magnetic An external magnetic field as viewed from the resistive element can be efficiently provided to the magnetosensitive layer of the magnetoresistive element.
  • a magnetic field magnetic An external magnetic field as viewed from the resistive element
  • the external magnetic field caused by the write current can be efficiently provided to the magnetosensitive layer of the magnetoresistive effect element, so that the magnetic field direction of the magnetosensitive layer is reversed with a small write current. be able to.
  • FIG. 1 is a conceptual diagram showing an overall configuration of a magnetic memory according to an embodiment.
  • FIG. 2 is an enlarged cross-sectional view showing a cross-sectional configuration when the storage section is cut along the row direction.
  • FIG. 3 is an enlarged cross-sectional view of the storage section taken along line II in FIG.
  • FIG. 4 is an enlarged cross-sectional view of the storage section taken along line II-II in FIG.
  • FIG. 5 is an enlarged cross-sectional view of a TMR element.
  • FIG. 6 is an enlarged sectional view of the magnetic yoke.
  • FIG. 7 shows the operation around the TMR element in the storage area.
  • Fig. 7 (a) shows the state during writing
  • Fig. 7 (b) shows the state during reading.
  • FIG. [Fig. 8] Fig. 8 shows the operation around the TMR element in the storage area.
  • Fig. 8- (a) shows the state during writing
  • Fig. 8- (b) shows the state during reading.
  • FIG. 9 is a diagram showing the manufacturing process of the TMR element and its peripheral structure
  • FIG. 9A is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. b) is a side cross-sectional view along line III-III shown in Fig. 9- (a).
  • FIG. 10 is a diagram showing the manufacturing process of the TMR element and its peripheral structure
  • FIG. 10- (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. b) is a side cross-sectional view along the IV-IV line shown in Figure 10- (a).
  • FIG. 11 is a diagram showing the manufacturing process of the TMR element and its peripheral structure
  • FIG. 11 (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. b) is a side cross-sectional view along the line V-V shown in Fig. 11 (a).
  • FIG. 12 is a diagram showing the manufacturing process of the TMR element and its peripheral structure
  • FIG. 12- (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. b) is a side cross-sectional view along the VI-VI line shown in Figure 12- (a).
  • FIG. 13 is a diagram showing a manufacturing process of a TMR element and its peripheral structure.
  • FIG. 14 is a diagram showing a manufacturing process of a TMR element and its peripheral structure.
  • FIG. 15 is a diagram showing the manufacturing process of the TMR element and its peripheral structure
  • FIG. 15- (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. b) is a side cross-sectional view along the line VII-VII shown in Figure 15- (a).
  • FIG. 16 is a diagram showing a manufacturing process of a TMR element and its peripheral structure.
  • FIG. 17 is a view showing the shape of a magnetic yoke according to a modification.
  • FIG. 18 is a view showing the shape of a magnetic yoke according to a modification.
  • FIG. 1 is a conceptual diagram showing the overall configuration of the magnetic memory 1 according to the present embodiment.
  • the magnetic memory 1 includes a storage unit 2, a bit selection circuit 11, a word selection circuit 12, bit lines 13 and 14, and word lines 15 and 19.
  • the storage unit 2 includes a plurality of storage areas 3.
  • the plurality of storage areas 3 are arranged in a two-dimensional form having m rows and n columns (m and n are integers of 2 or more).
  • Each of the plurality of storage areas 3 includes a TMR element 4, an intra-area wiring 31, a read / write transistor 32, and a read wiring 35.
  • the TMR element 4, the in-region wiring 31, and the readout wiring 35 are formed in the magnetic material layer 8 (described later) of the storage unit 2.
  • the TMR element 4 is a magnetoresistive effect element including a magnetosensitive layer whose magnetic field direction is changed by an external magnetic field.
  • the TMR element 4 includes a first magnetic layer which is a magnetosensitive layer, a second magnetic layer whose magnetization direction is fixed, and a nonmagnetic insulating layer sandwiched between the first magnetic layer and the second magnetic layer. Consists of and.
  • the TMR element 4 is arranged along one wiring portion of the in-region wiring 31 so that the magnetization direction of the first magnetic layer is changed by receiving an external magnetic field generated by a write current flowing through the in-region wiring 31.
  • the first magnetic layer and the second magnetic layer are in accordance with the relationship between the magnetic direction of the first magnetic layer and the magnetic direction of the second magnetic layer.
  • the resistance value between the magnetic layer changes. In this way, binary data is written to the TMR element 4.
  • one end of the TMR element 4 on the first magnetic layer side or the second magnetic layer side is electrically connected to one wiring portion of the in-region wiring 31, thereby electrically connecting to the read / write transistor 32. It is connected.
  • the read current is supplied from the bit wiring 13 described later to the TMR element 4 via the read / write transistor 32 and the intra-region wiring 31, the resistance value between the first magnetic layer and the second magnetic layer is increased.
  • the voltage value or current value across the TMR element 4 changes. By measuring the voltage value or current value between both ends, binary data written in the TMR element 4 is read.
  • the first magnetic layer side of the TMR element 4 (The second magnetic layer side) means either the first magnetic layer side or the second magnetic layer side with respect to the nonmagnetic insulating layer, and another layer on the first magnetic layer (second magnetic layer). This includes the case where there is intervening.
  • the intra-region wiring 31 is a wiring that provides an external magnetic field to the first magnetic layer of the TMR element 4 by a write current flowing through the intra-region wiring 31 and supplies a read current to the TMR element 4.
  • One end of the intra-region wiring 31 is electrically connected to the bit wiring 13 via the read / write transistor 32.
  • the other end of the intra-region wiring 31 is electrically connected to the bit wiring 14.
  • the read / write transistor 32 is switch means for controlling the conduction of the write current and the read current in the in-region wiring 31.
  • one of the drain and the source is electrically connected to the intra-region wiring 31 and one end of the TMR element 4, and the other is electrically connected to the bit wiring 13.
  • the gate of the read / write transistor 32 is electrically connected to the word line 15.
  • the read wiring 35 is a wiring that connects the TMR element 4 and the word wiring 19 in order to supply a read current to the TMR element 4. Specifically, one end of the read wiring 35 is electrically connected to the other end of the TMR element 4, and the other end of the read wiring 35 is electrically connected to the word wiring 19.
  • the bit wirings 13 and 14 are arranged corresponding to each column of the storage area 3.
  • the bit wiring 13 is the first wiring in this embodiment. That is, the bit wiring 13 is electrically connected to one end of the intra-area wiring 31 included in each storage area 3 in the corresponding column via the read / write transistor 32.
  • the bit wiring 13 supplies a positive write current to the intra-region wiring 31 and supplies a read current to the TMR element 4 via the intra-region wiring 31.
  • the bit wiring 14 is a second wiring in the present embodiment.
  • the bit wiring 14 is electrically connected to the other end of the in-area wiring 31 included in each storage area 3 of the corresponding column.
  • the bit wiring 14 supplies a negative write current to the in-region wiring 31.
  • the word wiring 15 is a third wiring in the present embodiment.
  • the word wiring 15 is disposed corresponding to each row of the storage area 3 and is electrically connected to a gate which is a control terminal of the read / write transistor 32 included in each storage area 3 of the corresponding row.
  • the word wiring 19 is the fourth wiring in the present embodiment. Word wiring 19 Is arranged corresponding to each row of the storage area 3, and is electrically connected to the other end of the TMR element 4 included in each storage area 3 of the corresponding row via a read wiring 35. .
  • the write current supply means in the present embodiment is configured by the bit selection circuit 11. That is, the bit selection circuit 11 has a function of providing a positive or negative write current to the in-area wiring 31 of each storage area 3. Specifically, the bit selection circuit 11 is electrically connected to the bit wirings 13 and 14, and corresponds to the address according to the address instructed at the time of data writing from the inside or the outside of the magnetic memory 1. An address decoder circuit for selecting a column and a current drive circuit for supplying a positive or negative write current between the bit line 13 and the bit line 14 corresponding to the selected column are configured.
  • the read current supply means in the present embodiment is constituted by a bit selection circuit 11 and a word selection circuit 12. That is, the bit selection circuit 11 and the word selection circuit 12 have a function of providing a read current to the TMR element 4 in each storage region 3 via the intra-region wiring 31.
  • the bit selection circuit 11 is configured to include an address decoder circuit that selects a column corresponding to the address in accordance with an address instructed when data is read from the internal or external power data of the magnetic memory 1.
  • the word selection circuit 12 is configured to include an address decoder circuit that is electrically connected to the word line 19 and selects a row corresponding to the address according to the designated address. At least one of the bit selection circuit 11 and the word selection circuit 12 is supplied with a read current between the bit wiring 13 corresponding to the selected column and the word wiring 19 corresponding to the selected row.
  • a current drive circuit is included.
  • the word selection circuit 12 is electrically connected to the word wiring 15.
  • the word selection circuit 12 applies a control voltage for turning on the read / write transistor 32 to the word line 15 corresponding to the selected row at the time of data writing or data reading.
  • the magnetic memory 1 having the above configuration operates as follows. That is, when an address (i row j column Zl ⁇ i ⁇ m, l ⁇ j ⁇ n) for writing data from the inside or outside of the magnetic memory 1 is specified, the bit selection circuit 11 and the word selection circuit 12 are respectively Applicable j column and i Select a row. In the read / write shared transistor 32 of the storage area 3 included in the i row selected by the word selection circuit 12, a control voltage is applied to the gate via the word wiring 15, and the write current becomes conductive. Further, in the storage area 3 included in the j column selected by the bit selection circuit 11, a positive or negative voltage corresponding to data is applied between the bit wiring 13 and the bit wiring 14.
  • a write current is generated in the internal wiring 31 via the read / write transistor 32.
  • the magnetization direction of the first magnetic layer of the TMR element 4 is reversed by the magnetic field generated by the write current. In this way, binary data is written into the storage area 3 of the designated address (i row j column).
  • the bit selection circuit 11 and the word selection circuit 12 select the corresponding one column and k row, respectively.
  • a control voltage is applied to the gate via the word wiring 15, and the read current becomes conductive.
  • the bit selection circuit 11 or the word Read current is supplied from the selection circuit 12.
  • a read current flows through the TMR element 4 in the storage region 3 included in both the one column selected by the bit selection circuit 11 and the k row selected by the word selection circuit 12 . Then, for example, by determining the voltage drop amount in the TMR element 4, the binary data stored in the storage area 3 of the instructed address (k rows and 1 column) is read out.
  • FIG. 2 is an enlarged cross-sectional view showing a cross-sectional configuration when the storage unit 2 is cut along the column direction.
  • FIG. 3 is an enlarged cross-sectional view of the storage unit 2 taken along the line II in FIG.
  • FIG. 4 is an enlarged cross-sectional view of the storage unit 2 taken along line II-II in FIG.
  • the storage unit 2 includes a semiconductor layer 6, a wiring layer 7, and a magnetic material layer 8.
  • the semiconductor layer 6 is a layer in which a semiconductor device such as a transistor is formed while maintaining the mechanical strength of the entire storage unit 2 including the semiconductor substrate 21.
  • Magnetic material layer 8 is T This is a layer on which a component made of a magnetic material such as the MR element 4 and the magnetic yoke 5 for efficiently applying a magnetic field to the TMR element 4 is formed.
  • the wiring layer 7 is provided between the semiconductor layer 6 and the magnetic material layer 8.
  • the wiring layer 7 includes a magnetic device such as a TMR element 4 formed in the magnetic material layer 8, a semiconductor device such as a transistor formed in the semiconductor layer 6, a bit wiring 13 and 14, and a word wiring 15 and 19. This is a layer in which wirings for electrically connecting the wirings penetrating each storage area 3 to each other V are formed.
  • the semiconductor layer 6 includes a semiconductor substrate 21, an insulating region 22, and a read / write transistor 32.
  • the semiconductor substrate 21 is made of, for example, a Si substrate and is doped with p-type or n-type impurities.
  • the insulating region 22 is formed in a region other than the read / write transistor 32 on the semiconductor substrate 21 and electrically isolates the read / write transistor 32 of each storage region 3 from each other.
  • the insulating region 22 is made of an insulating material such as SiO.
  • the read / write transistor 32 includes a drain region 32 a and a source region 32 c having a conductivity type opposite to that of the semiconductor substrate 21, a gate electrode 32 b serving as a control terminal, and a part of the semiconductor substrate 21.
  • the drain region 32a and the source region 32c are formed, for example, by doping an impurity having a conductivity type opposite to that of the semiconductor substrate 21 in the vicinity of the surface of the Si substrate.
  • a semiconductor substrate 21 is interposed between the drain region 32a and the source region 32c, and a gate electrode 32b is disposed on the semiconductor substrate 21.
  • the magnetic material layer 8 includes a TMR element 4, a magnetic yoke 5, an insulating region 24, an in-region wiring 31, and a readout wiring 35.
  • TMR element 4 magnetic yoke 5, in-region wiring 31, and readout wiring 35
  • FIG. 5 is an enlarged cross-sectional view of the TMR element 4.
  • FIG. 5 shows a cross section of the storage area 3 along the row direction.
  • the TMR element 4 includes a first magnetic layer 41, a nonmagnetic insulating layer 42, a second magnetic layer 43, and an antiferromagnetic layer 44 that are stacked in this order.
  • the first magnetic layer 41 is a magnetosensitive layer in this embodiment, and an external magnetic field from the in-region wiring 31. The magnetic field direction changes depending on the field, and binary data can be recorded.
  • the first magnetic layer 41 is constituted by a part of a magnetic yoke 5 (beam yoke 5b) described later.
  • a ferromagnetic material such as Co, CoFe, NiFe, NiFeCo, and CoPt can be used.
  • the magnetic field direction is fixed by the antiferromagnetic layer 44.
  • the magnetic field direction of the second magnetic layer 43 is stabilized by exchange coupling at the joint surface between the antiferromagnetic layer 44 and the second magnetic layer 43.
  • the magnetic axis easy axis direction of the second magnetic layer 43 is set along the magnetic axis easy axis direction of the first magnetic layer 41.
  • a ferromagnetic material such as Co, CoFe, NiFe, NiFeCo, CoPt can be used.
  • IrMn, PtMn, FeMn, PtPdMn, NiO, or any combination of these materials can be used.
  • the nonmagnetic insulating layer 42 is a layer made of a nonmagnetic and insulating material. Since the nonmagnetic insulating layer 42 is interposed between the first magnetic layer 41 and the second magnetic layer 43, a tunnel magnetoresistive effect (TMR) is generated between the first magnetic layer 41 and the second magnetic layer 43. Occurs. That is, between the first magnetic layer 41 and the second magnetic layer 43, the relative relationship between the magnetic field direction of the first magnetic layer 41 and the magnetic field direction of the second magnetic layer 43 (parallel or antiparallel). An electrical resistance corresponding to is generated.
  • the material of the nonmagnetic insulating layer 42 is preferably a metal oxide or nitride such as Al, Zn, or Mg.
  • a third layer is provided via a nonmagnetic metal layer or a synthetic AF (antiferromagnetic) layer instead of the antiferromagnetic layer 44.
  • a magnetic layer may be provided.
  • the third magnetic layer forms antiferromagnetic coupling with the second magnetic layer 43, so that the magnetic field direction of the second magnetic layer 43 can be further stabilized.
  • the influence of the static magnetic field from the second magnetic layer 43 to the first magnetic layer 41 can be prevented, the magnetic reversal of the first magnetic layer 41 can be facilitated.
  • the material of the third magnetic layer is not particularly limited, but it is preferable to use a ferromagnetic material such as Co, CoFe, NiFe, NiFeCo, CoPt alone or in combination. Further, as the material of the nonmagnetic metal layer provided between the second magnetic layer 43 and the third magnetic layer, Ru, Rh, Ir, Cu, Ag and the like are suitable. The thickness of the nonmagnetic metal layer is 2n in order to obtain strong antiferromagnetic coupling between the second magnetic layer 43 and the third magnetic layer. U, which is preferably less than m.
  • the in-region wiring 31 also has a conductive metal force and extends in the column direction of the storage region 3.
  • One end of the in-region wiring 31 is electrically connected to the electrode 17a through the vertical wiring 16a (see FIG. 2). Further, the other end of the in-region wiring 31 is electrically connected to the bit wiring 14 (see FIGS. 3 and 4) by a wiring (not shown).
  • a wiring portion 31 a of the intra-region wiring 31 extends along the first magnetic layer 41 of the TMR element 4. Then, when a write current flows through the intra-region wiring 31, an external magnetic field is provided from the wiring portion 3 la to the first magnetic layer 41 of the TMR element 4.
  • the magnetic axis easy axis direction of the first magnetic layer 41 of the TMR element 4 is set to be along the direction intersecting with the longitudinal direction of the in-region wiring 31 (that is, the direction intersecting with the write current direction).
  • the first magnetic layer 41 of the TMR element 4 is provided on the read wiring 35.
  • the read wiring 35 is made of a conductive metal and extends in the column direction of the storage area 3. One end of the read wiring 35 is electrically connected to the first magnetic layer 41. The other end of the read wiring 35 is electrically connected to the word wiring 19 (see FIG. 2) via a wiring (described later) inside the wiring layer 7. Further, the antiferromagnetic layer 44 of the TMR element 4 is electrically connected to the wiring portion 31a of the in-region wiring 31. With this configuration, it is possible to allow the read current to flow suitably from the in-region wiring 31 to the TMR element 4 (or from the read wiring 35 to the TMR element 4).
  • the magnetic yoke 5 is a ferromagnetic member that covers the periphery of the in-region wiring 31 and efficiently provides a magnetic field generated by a write current to the TMR element 4.
  • FIG. 6 is an enlarged cross-sectional view of the magnetic yoke 5.
  • FIG. 6 is a cross section along the row direction of the storage area 3.
  • the magnetic yoke 5 includes a first beam yoke 5b, a pair of pillar yokes 5c, and a second beam yoke 5d.
  • the first beam yoke 5 b is disposed between the read wiring 35 and the nonmagnetic insulating layer 42 so as to serve also as the first magnetic layer 41 of the TMR element 4.
  • the first beam yoke 5b is connected to one of the pair of pillar yokes 5c, and the other end of the first beam yoke 5b is connected to the other of the pair of pillar yokes 5c.
  • the second beam yoke 5d is provided along the surface of the in-region wiring 31 opposite to the TMR element 4.
  • the pair of pillar yokes 5c are provided along the side surface of the in-region wiring 31, and both ends of the first beam yoke 5b and the second beam yoke are provided. Connecting both ends of the 5d.
  • the first beam yoke 5b, the pair of pillar yokes 5c, and the second beam yoke 5d are arranged in part of the extension direction of the in-region wiring 31 (wiring portion 3 la on the TMR element 4).
  • the outer periphery of the intra-region wiring 31 is completely (continuously) surrounded.
  • the first magnetic layer 41 of the TMR element 4 is constituted by a part of the magnetic yoke 5 (first beam yoke 5b).
  • the magnetic yoke 5 As a material constituting the magnetic yoke 5, for example, a metal containing at least one element among Ni, Fe, and Co is preferable.
  • the magnetic yoke 5 is preferably formed so that its easy axis direction is along the easy axis direction of the first magnetic layer 41 of the TMR element 4.
  • the material of the insulating region 24 is SiO, like the insulating region 22 of the semiconductor layer 6.
  • Two insulating materials can be used.
  • the wiring layer 7 includes an insulating region 23, bit wirings 13 and 14, word wirings 15 and 19, and a plurality of vertical wirings and horizontal wirings. Note that, in the wiring layer 7, all regions other than each wiring are occupied by the insulating region 23.
  • the material of the insulating region 23 is SiO, like the insulating region 22 of the semiconductor layer 6.
  • Insulating materials can be used.
  • w can be used as the material for the vertical wiring
  • A1 can be used as the material for the horizontal wiring.
  • the electrode 17a to which one end of the in-region wiring 31 of the magnetic material layer 8 is connected is electrically connected to the vertical wirings 16b to 16d and the horizontal wirings 18a and 18b.
  • the vertical wiring 16d is in ohmic contact with the drain region 32a of the read / write transistor 32.
  • the horizontal wiring 18c is electrically connected to the vertical wiring 16e, and the vertical wiring 16e is in ohmic contact with the source region 32c of the read / write transistor 32.
  • the horizontal wiring 18c is electrically connected to the bit wiring 13 through the vertical wiring 16h.
  • the readout wiring 35 of the magnetic material layer 8 is electrically connected to the vertical wirings 16f and 16g and the horizontal wiring 18d of the wiring layer 7, and the vertical wiring 16g is electrically connected to the word wiring 19! Speak.
  • the bit wiring 14 is electrically connected to the end of the in-region wiring 31 opposite to the side where the electrode 17a is provided by a wiring (not shown).
  • the gate electrode 32b is configured by a part of the word line 15 extending in the row direction of the storage region 3. With this configuration, the word line 15 is connected to the read / write transistor 3. 2 is electrically connected to the control terminal (gate electrode 32b).
  • Fig. 7 (a) when a negative write current I flows in the intra-region wiring 31, the wl of the wiring portion 31a is placed around the wiring portion 31a of the intra-region wiring 31.
  • Magnetic field ⁇ is generated in the circumferential direction.
  • the magnetic field ⁇ forms a closed path that goes around the inside of the magnetic yoke 5 provided around the wiring portion 3 la.
  • the magnetic field ⁇ is generated around the wiring portion 3 la
  • the magnetic field ⁇ (external magnetic field) is applied to the first magnetic layer 41 (first beam yoke 5b) of the TMR element 4 by the magnetic field confinement action of the magnetic yoke 5. ) Is provided efficiently. Due to this magnetic field ⁇ , the magnetic field direction A of the first magnetic layer 41 is directed in the same circumferential direction as the magnetic field ⁇ .
  • the magnetic field direction B of the second magnetic layer 43 is oriented in the same circumferential direction as the magnetic field ⁇ in advance by exchange coupling with the antiferromagnetic layer 44, the magnetic field of the first magnetic layer 41 is The direction A and the magnetic direction B of the second magnetic layer 43 are in the same direction, that is, in a parallel state.
  • one of the binary data (for example, 0) is written into the TMR element 4.
  • a read current I is passed between the wiring portion 31a and the read wiring 35, and the current value Change or change in potential difference between the wiring portion 31a and the readout wiring 35 is detected.
  • the force at which the TMR element 4 records any binary data that is, the magnetic field direction A of the first magnetic layer 41 is parallel to the magnetic field direction B of the second magnetic layer 43.
  • the first magnetic layer 41 is not affected by the tunnel magnetoresistance effect (TMR) in the nonmagnetic insulating layer 42.
  • TMR tunnel magnetoresistance effect
  • the resistance value between the layer 41 and the second magnetic layer 43 is relatively small. Therefore, for example, when the read current I is constant, the potential difference between the wiring portion 31a and the read wiring 35 becomes relatively small, and therefore 0 may be written to the TMR element 4 as binary data. Wow.
  • a magnetic field ⁇ that is opposite to the magnetic field ⁇ is generated around the wiring part 31a of the internal wiring 31.
  • the magnetic field ⁇ forms a closed path that goes around the inside of the magnetic yoke 5.
  • the magnetic field ⁇ (external magnetic field) is effective on the first magnetic layer 41 (first beam yoke 5b) of the TMR element 4. Provided well. Due to this magnetic field ⁇ , the magnetic field direction A of the first magnetic layer 41 is the same as the magnetic field ⁇ .
  • the magnetic field direction B of the second magnetic layer 43 is directed in the circumferential direction opposite to the magnetic field ⁇ .
  • the magnetic field direction A of the first magnetic layer 41 and the magnetic field direction B of the second magnetic layer 43 are opposite to each other, that is, in an antiparallel state.
  • the other binary data (for example, 1) is written in the TMR element 4.
  • the first magnetic layer 41 causes the first magnetoresistance effect (TMR) in the nonmagnetic insulating layer 42 to
  • TMR first magnetoresistance effect
  • the resistance value between the magnetic layer 41 and the second magnetic layer 43 becomes relatively large. Therefore, for example, as shown in FIG. 8 (b), when a constant read current I is passed between the wiring portion 31a and the readout wiring 35, the potential difference between the wiring portion 31a and the readout wiring 35 becomes relatively large. . From this, it can be seen that 1 is written in the TMR element 4 as binary data.
  • the write currents I and 1 and the read current I are controlled by one switch means (read / write transistor 32).
  • the transistor for controlling the read current and the space required to define the size of the storage area is required. Therefore, in a conventional magnetic memory that requires two transistors per storage area, or in a cross-point type magnetic memory that requires a reading transistor for each column and each row, the storage section becomes large. , Favorable force.
  • a read / write transistor 32 that can control both the write currents I and 1 and the read current I is provided.
  • the magnetic memory 1 (storage unit 2) can be downsized.
  • the intra-area wiring 31 is provided for each storage area 3, and the write current flowing through the intra-area wiring 31 by the read / write transistor 32 provided in each storage area 3 Since I and I can be controlled, there is no half-selected state of TMR element 4 wl w2
  • the storage area to be written is stored.
  • a write current I, I wl w2 is supplied between the bit wiring 13 corresponding to the column including the area 3 and the bit wiring 14, and the word wiring 15 corresponding to the row including the storage area 3 is read / written.
  • the write current I, 1 can be suitably supplied to the internal wiring 31 of the storage area 3 wl w2
  • a read current I is supplied between the bit wiring 13 corresponding to the column including the storage area 3 to be read and the word wiring 19 corresponding to the row including the storage area 3, and the storage area 3 is By applying a control voltage for controlling the read / write transistor 32 to the conductive state to the word line 15 corresponding to the included row, it is possible to allow a read current to flow through the TMR element 4 in the storage region 3 appropriately.
  • the magnetic memory 1 is electrically connected to the word wirings 15 and 19, and is read current supply means (bit selection circuit 11) for supplying the read current I to the TMR element 4. And a word selection circuit 12).
  • the read current I can be suitably supplied to the TMR element 4 in the storage area 3 to be read.
  • the magnetic memory 1 is electrically connected to the bit wirings 13 and 14, and write current supply means (wl w2
  • a bit selection circuit 11 is preferably provided. Thereby, the write currents I and 1 can be suitably supplied to the in-area wiring 31 of the storage area 3 to be written.
  • each of the plurality of storage areas 3 preferably has a magnetic yoke 5 provided so as to continuously surround the wiring portion 31a of the in-area wiring 31.
  • the first magnetic layer 41 of the TMR element 4 is preferably constituted by a part of the magnetic yoke 5 (first beam yoke 5b).
  • first beam yoke 5b the magnetic yoke 5
  • the external magnetic fields ⁇ and ⁇ by the write currents I and I wl can be efficiently provided to the first magnetic layer 41 of the TMR element 4, so that w2 1 2
  • each storage region 3 has such a magnetic yoke 5
  • the magnetization direction A of the first magnetic layer 41 can be reversed with small write currents I and I, so that the write current I
  • the read / write transistor 32 that controls the conduction of I can be made small. Therefore, each memory w2
  • the magnetic memory 1 (storage unit 2) can be further reduced in size.
  • FIG. 9- (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1, and FIG. 9- (b) is taken along the line III-III shown in FIG. 9- (a). It is side surface sectional drawing.
  • the readout wiring 35 is formed on the wiring layer 7.
  • the readout wiring 35 is formed so that one end of the readout wiring 35 is in contact with the vertical wiring 16 f of the wiring layer 7.
  • the vertical wiring 16i shown in the figure is a vertical wiring electrically connected to the bit wiring 14 (see FIGS. 3 and 4) in the wiring layer 7.
  • Fig. 10 (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • Fig. 10 (b) is a side cross-sectional view along the IV-IV line shown in Fig. 10 (a). It is.
  • a layer 61 having a Ta layer underlayer, a NiFe layer, and a CoFe layer force is formed by a high vacuum (UHV) DC sputtering device.
  • This layer 61 is a layer to be a first beam yoke (first magnetic layer).
  • the A1 layer is formed on the layer 61, and the A1 layer is oxidized by oxygen plasma to form a tunnel insulating layer 62 that becomes a nonmagnetic insulating layer. Then, a CoFe layer 63 serving as a second magnetic layer, an IrMn layer 64 serving as an antiferromagnetic layer, and a Ta protective layer (not shown) are sequentially formed on the tunnel insulating layer 62.
  • FIG. 11— (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1, and FIG. 11— (b) is taken along the line V—V shown in FIG. 11— (a). It is side surface sectional drawing.
  • the layer 61, the tunnel insulating layer 62, the CoFe layer 63, and the IrMn layer 64 are formed by ion milling.
  • the first beam yoke 5b (first magnetic layer 41) is formed.
  • the tunnel insulating layer 62, the CoFe layer 63, and the IrMn layer 64 are ion milled.
  • the TMR element 4 including the nonmagnetic insulating layer 42, the second magnetic layer 43, and the antiferromagnetic layer 44 is formed by molding.
  • the TMR element 4 is formed by using, for example, Si (OC H) using a CVD apparatus.
  • a SiO insulating layer 24a is formed in the entire region except the top. Thereafter, the second resist mask is removed.
  • Fig. 12 (a) is a plan view showing a part of the manufacturing process of magnetic memory 1
  • Fig. 12 (b) is a side cross-sectional view along the VI-VI line shown in Fig. 12 (a).
  • a third resist mask is formed so as to be continuous over the wiring 16b, the TMR element 4, and the vertical wiring 16i. Then, after depositing T and Cu layers sequentially by sputtering, the third resist mask is removed. Thus, the intra-region wiring 31 is formed on the TMR element 4.
  • the intra-region wiring 31 has one end connected to the vertical wiring 16b and the other end connected to the vertical wiring 16i.
  • a SiO insulating layer 24b is formed so as to cover it. At this time, for example, Si (OC
  • the SiO insulating layer 24b may be formed by H).
  • a fourth resist mask (not shown) is formed on the SiO 2 insulating layer 24b formed on the in-region wiring 31. And SiO
  • the part (that is, the part excluding the periphery of the in-region wiring 31) is removed by, for example, CF gas.
  • FIG. 15- (a) is a plan view showing a part of the manufacturing process of the magnetic memory 1
  • FIG. 15- (b) is a side sectional view taken along line VII-VII shown in FIG. 15- (a). It is.
  • a fifth resist mask (not shown) having an opening corresponding to the planar shape of the magnetic yoke 5 is formed. At this time, the opening of the fifth resist mask is exposed to the SiO insulating layer 24b and the first beam yoke 5b.
  • NiFe layer is formed by sputtering. At this time, NiFe layer The NiFe layer is formed so as to completely cover the SiO insulating layer 24b. And the fifth resister
  • the magnetic yoke 5 having the first beam yoke 5b, the pair of pillar yokes 5c, and the second beam yoke 5d and surrounding the in-region wiring 31 is formed.
  • the SiO insulating layer 24 c made of the material
  • the insulating region 24 composed of the SiO insulating layers 24a to 24c is formed.
  • 17 and 18 are cross-sectional views showing the shapes of the magnetic yokes 51 and 52 according to this modification, respectively.
  • the magnetic yoke 51 has a substantially annular physical force having at least a pair of open ends opposed to each other through a gap having a predetermined length, so that one wiring portion of the in-region wiring 31 It is arranged so as to surround the outer periphery of 31a.
  • the magnetic yoke 51 of this modification is configured by a pair of opposing yokes 51b, a pair of pillar yokes 51c, and a beam yoke 51d.
  • the pair of opposing yokes 51b has a pair of end surfaces 51a as a pair of open ends.
  • the pair of end faces 51a are opposed to each other via a gap having a predetermined length along the magnetic axis easy axis direction of the first magnetic layer 45 of the TMR element 4a.
  • the first magnetic layer 45 does not also serve as a part of the magnetic yoke 51, and other layers (nonmagnetic insulating layer 46).
  • the second magnetic layer 47 and the antiferromagnetic layer 48) are formed in the same planar shape.
  • the TMR element 4a is implemented as described above so that the first magnetic layer 45 is electrically connected to the wiring portion 31a of the in-region wiring 31, and the antiferromagnetic layer 48 is electrically connected to the readout wiring 35.
  • the TMR element 4 is formed upside down.
  • the TMR element 4a and the magnetic yoke 51 are arranged so that the pair of side surfaces 4b of the TMR element 4a face the pair of end faces 51a of the magnetic yoke 51, respectively, and the easy magnetization axis of the first magnetic layer 45 They are arranged so that the directions are along the direction in which the pair of end faces 51a are arranged. Also magnetic The beam yoke 51d of the yoke 51 is provided along the surface of the in-region wiring 31 opposite to the TMR element 4a.
  • the pair of pillar yokes 51c is provided along the side surface of the in-region wiring 31, and connects one end of each of the pair of opposed yokes 51b on the side different from the end surface 51a and both ends of the beam yoke 5Id.
  • the opposing yoke 51b, the pillar yoke 51c, and the beam yoke 51d surround the outer periphery of a portion (wiring portion 31a) of the intra-region wiring 31 along the TMR element 4a.
  • the magnetic yoke 51 may have a shape having a pair of end surfaces 5 la facing each of the pair of side surfaces 4b of the TMR element 4a. Thereby, a path closed in the outer peripheral direction of the wiring portion 31a of the magnetic field force internal wiring 31 inside the magnetic yoke 51 generated by the write current can be configured. Then, an external magnetic field can be efficiently provided to the first magnetic layer 45 of the TMR element 4a disposed between the pair of end faces 51a.
  • the area of the cross section perpendicular to the circumferential direction of the magnetic yoke 51 is preferably the smallest on the pair of end faces 51a. Thereby, the magnetic field inside the magnetic yoke 51 can be more efficiently applied to the first magnetic layer 45 of the TMR element 4a.
  • the magnetic yoke 52 includes a pair of opposing yokes 52b, a pair of pillar yokes 52c, and a beam yoke 52d.
  • the configuration and shape of the pair of pillar yokes 52c and beam yoke 52d are the same as the configuration and shape of the pair of pillar yokes 51c and beam yoke 51d of the magnetic yoke 51 described above (see FIG. 17).
  • the end faces 52a of the pair of opposing yokes 52b are in contact with the side surfaces of the first magnetic layer 45 among the side surfaces 4b of the TMR element 4a.
  • the magnetic field generated in the magnetic yoke 52 by the write current can be provided to the first magnetic layer 45 more efficiently.
  • a read current flowing between the first magnetic layer 45 and the second magnetic layer 47 is suitably passed through the nonmagnetic insulating layer 46. Therefore, the pair of end faces 52a of the magnetic yoke 52 should be in contact with the second magnetic layer 47, which is preferably in contact with the nonmagnetic insulating layer 46.
  • the magnetic memory according to the present invention is not limited to the above-described embodiments, but various other types. Deformation is possible.
  • the TMR element is used as the magnetoresistive effect element in the above embodiment, a GMR element using a giant magneto-resistive (GMR) effect may be used.
  • the GMR effect is a phenomenon in which the resistance value of the ferromagnetic layer in the direction perpendicular to the stacking direction changes depending on the angle formed by the magnetization directions of the two ferromagnetic layers sandwiching the nonmagnetic layer.
  • the TMR element and GMR element have a pseudo spin valve type that writes and reads Z using the difference in coercive force of the two ferromagnetic layers, and the magnetic field direction of one ferromagnetic layer is strong. There is a spin valve type that is fixed by exchange coupling with the magnetic layer.
  • Data reading in the GMR element is performed by detecting a change in the resistance value of the ferromagnetic layer in a direction orthogonal to the stacking direction.
  • Data writing in the GMR element is performed by reversing the magnetic field direction of one ferromagnetic layer by a magnetic field generated by a write current.
  • a transistor read / write transistor
  • the current is interrupted as necessary.
  • Various means having a function of conducting can be applied.
  • the switch means and the magnetoresistive effect element are electrically connected to each other by connecting the wiring portion of the in-region wiring and one end of the magnetoresistive effect element.
  • the switch means and the magnetoresistive element may be connected to each other by, for example, a wiring different from the in-region wiring.
  • the present invention can be used in a magnetic memory that stores data in a magnetoresistive element.

Abstract

L'invention concerne une mémoire magnétique (1) qui inclut une pluralité de zones de mémorisation (3), dont chacune comporte : un élément de type TMR (4) contenant une première couche magnétique (41) dont le sens de magnétisation (A) est modifié par des champs extérieurs Φ1, Φ2, un câblage de zone (31) comportant une partie de câblage (31a) s'étendant le long de la première couche magnétique (41) fournissant les champs magnétiques extérieurs Φ1, Φ2 à la première couche magnétique (41) grâce à des courants d'écriture Iw1, Iw2 circulant dans la partie de câblage (31a) qui est reliée électriquement à une extrémité de l'élément TMR (4) et à partir de laquelle circule un courant de lecture Ir dans l'élément TMR (4), ainsi qu'un transistor de lecture/écriture (32) relié électriquement à une extrémité du câblage de zone (31) et commandant la liaison électrique des courants d'écriture Iw1, Iw2 et du courant de lecture Ir dans le câblage de zone (31).
PCT/JP2005/021985 2004-12-01 2005-11-30 Memoire magnetique WO2006059641A1 (fr)

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JP5092384B2 (ja) * 2006-12-15 2012-12-05 Ｔｄｋ株式会社 磁気記憶装置、磁気記憶方法
JP2008306169A (ja) * 2007-05-07 2008-12-18 Canon Anelva Corp 磁気抵抗素子、磁気抵抗素子の製造方法及び磁性多層膜作成装置
US8174800B2 (en) 2007-05-07 2012-05-08 Canon Anelva Corporation Magnetoresistive element, method of manufacturing the same, and magnetic multilayered film manufacturing apparatus
CN107091996B (zh) * 2017-04-28 2023-06-06 黑龙江大学 一种复合磁场传感器及其制作工艺

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WO2004021357A1 (fr) * 2002-08-27 2004-03-11 Freescale Semiconductor, Inc. Memoire d'acces aleatoire magnetique ayant une ligne d'ecriture verticale
JP2004128430A (ja) * 2002-07-30 2004-04-22 Toshiba Corp 磁気記憶装置及びその製造方法
US20040100835A1 (en) * 2002-11-27 2004-05-27 Nec Corporation Magnetic memory cell and magnetic random access memory using the same
JP2004153070A (ja) * 2002-10-31 2004-05-27 Nec Corp 磁気ランダムアクセスメモリ，及びその製造方法
JP2004281599A (ja) * 2003-03-14 2004-10-07 Tdk Corp 磁気抵抗効果素子および磁気メモリデバイス

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JP2004006729A (ja) * 2002-03-29 2004-01-08 Toshiba Corp 磁気記憶装置の製造方法
JP2004128430A (ja) * 2002-07-30 2004-04-22 Toshiba Corp 磁気記憶装置及びその製造方法
WO2004021357A1 (fr) * 2002-08-27 2004-03-11 Freescale Semiconductor, Inc. Memoire d'acces aleatoire magnetique ayant une ligne d'ecriture verticale
JP2004153070A (ja) * 2002-10-31 2004-05-27 Nec Corp 磁気ランダムアクセスメモリ，及びその製造方法
US20040100835A1 (en) * 2002-11-27 2004-05-27 Nec Corporation Magnetic memory cell and magnetic random access memory using the same
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