WO2006059543A1 - スケジューリング方法、スケジューリング装置およびマルチプロセッサシステム - Google Patents
スケジューリング方法、スケジューリング装置およびマルチプロセッサシステム Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
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- the present invention relates to a scheduling method and scheduling apparatus for execution units of parallel processing in a multiprocessor system, and a multiprocessor system.
- Recent operating systems that support multitasking realize a multiprocess environment in which multiple processes can be executed simultaneously, and these processes generate multiple threads within the process and perform parallel processing. Equipped with multi-threading technology that can do this. Processes are assigned unique resources and address space at runtime, and cannot access areas of other processes. On the other hand, a thread is a unit of execution created inside a process, and each thread can freely access areas in the process. A thread is the basic unit by which the operating system allocates CPU execution time.
- a simple round-robin method that selects and executes threads that enter the queue in order at regular intervals, and a priority that executes in order of thread priority.
- threads in the queue are allocated to the CPU and executed at regular intervals.
- threads of each priority are queued in a queue provided for each priority, and in order of priority, threads are selected in order from the queue and assigned to the CPU for execution.
- processing can be executed in parallel to increase the overall speed of processing.
- threads are assigned to one of the processors.
- the performance of the process execution speed and memory consumption varies depending on the execution order of the threads.
- thread scheduling in a multiprocessor system it is necessary to consider the efficiency of the use of processor resources, the exchange of data between threads and the efficiency of communication, etc., and thread scheduling in a single processor system. Different ideas are required.
- the present invention has been made in view of these problems, and an object of the present invention is to control the order in which execution units of parallel processing in a multiprocessor system are allocated to processors, thereby increasing processing efficiency and improving processor utilization efficiency. It is to provide a scheduling technology that can improve the performance.
- a scheduling method is a method for scheduling an order in which execution units to be scheduled to be processed in parallel are allocated to a plurality of processors in a multiprocessor system. Wherein one or more execution units to be scheduled are grouped and each execution unit refers to each other so that resources in the processor occupied by each of the execution units belonging to the same group can be referred to each other. If the resources are mapped to the address space and all execution units belonging to the same group are simultaneously assigned to any processor, the assignment of the group to the processor is controlled under the restriction.
- Another aspect of the present invention is also a scheduling method.
- This method is a method of scheduling an order in which execution units to be scheduled that are processed in parallel are allocated to a plurality of processor in a multiprocessor system, and the execution unit is one or more of the execution units to be scheduled.
- the allocation to the processor is managed in units of groups, and the priority of the group is determined in the order of priority set for each group and within the same priority, the order in which the group arrives in the queue.
- a group that is in the waiting state and in the execution state is assigned to the processor according to the priority order.
- all execution units belonging to the same group according to the priority order can be assigned to processors simultaneously. Since the priority is determined in the order of arrival in the queue within the same priority, the arrival order can be maintained between groups having the same priority. In addition to waiting for execution, including groups that are already in execution, priorities are determined and assigned to processors, so it is possible to easily assign the group to be assigned to the processor in a batch.
- Yet another embodiment of the present invention is also a scheduling method.
- This method is a method for scheduling the order in which execution units to be scheduled to be processed in parallel are assigned to a plurality of processors in a multiprocessor system, and includes a group including one or more execution units to be scheduled.
- the groups that are in the waiting state and in the executing state are taken out in the order of priority set for each group and, in the same priority, in the order of arrival in the waiting queue stored in the order of arrival, the groups are taken out. All execution units belonging to the group are assigned to the processor only if all execution units belonging to the issued group can be assigned to any processor at the same time. Priority is given to the allocation of groups from which waiting queue power is also extracted.
- the execution unit belonging to the group to be sequentially taken out is already assigned to any processor and executing, the execution unit being executed is assigned to another processor. May be allocated to the processor so that the execution unit being executed is not relocated. As a result, for each execution unit belonging to the group that is already assigned to the processor and is being executed, the assignment to the already assigned processor can be maintained, and the cost involved in the assignment process can be reduced.
- Yet another aspect of the present invention is a scheduling apparatus.
- This device allows multiple execution units to be scheduled to be processed in parallel in a multiprocessor system.
- a device that schedules the order of allocation to processors so that one or more execution units to be scheduled can be grouped so that resources in the processors occupied by each of the execution units belonging to the same group can be referred to each other.
- the memory control unit that maps and manages the resource to the address space referred to by each execution unit, the execution queue that stores the group that is waiting and executing, and the leading power of the execution queue Includes an assigner that takes a group and assigns all execution units belonging to the loop to multiple processors only if all execution units belonging to the fetched group can be assigned to any processor at the same time. .
- Yet another embodiment of the present invention is also a scheduling apparatus.
- This device is a device that schedules the order in which execution units to be scheduled to be processed in parallel are assigned to a plurality of processors in a multiprocessor system, and includes a group including one or more execution units to be scheduled Among them, the waiting queue that stores the waiting and executing groups in the order of priority set for each group and in the order of arrival within the same priority, and the order of the leading power of the waiting queue.
- the allocation list generator that adds a group to the allocation list and the allocation list generator only if the group is extracted and all execution units belonging to the extracted group can be allocated to any processor at the same time. A group belonging to the group stored in the generated allocation list. And an allocation unit that allocates all execution units to multiple processors.
- Yet another embodiment of the present invention is a multiprocessor system.
- This system is a multiprocessor system in which execution units to be scheduled to be processed in parallel are assigned to a plurality of processors and executed in parallel, and one processor uses the execution units to be scheduled as other processors.
- Contains a scheduler to assign to The scheduler is configured to group one or more execution units to be scheduled so that resources in the processor occupied by each of the execution units belonging to the same group can be referred to each other.
- a memory control unit that maps and manages the resource in an address space that is referenced by and a group that is in a waiting state and in an executing state are stored.
- the waiting queue and the leading force of the waiting queue are also taken out in order, and only if all execution units belonging to the removed group can be assigned to any processor at the same time.
- an allocator that assigns all execution units to multiple processors.
- Yet another embodiment of the present invention is also a multiprocessor system.
- This system is a multiprocessor system in which execution units to be scheduled to be processed in parallel are assigned to a plurality of processors and executed in parallel, and one processor uses the execution units to be scheduled as other processors.
- the scheduler includes, in a priority order set for each group and within the same priority, a group that is in a state of waiting for execution and executing in a loop including one or more execution units to be scheduled.
- An execution queue stored in the order of arrival and a group are extracted in the order of the leading power of the execution queue, and only when all execution units belonging to the extracted group can be assigned to any processor at the same time
- Yet another embodiment of the present invention is also a scheduling method.
- This method is a method of scheduling the order in which execution units to be scheduled to be processed in parallel are allocated to a plurality of processors in a multiprocessor system, and at least one processor among the plurality of processors is parallelized.
- the resources in the processor that are exclusively occupied by non-scheduled execution units that run on non-allocated processors are excluded from the scheduling target execution unit to be processed.
- the resource is mapped to the address space referred to by each execution unit so that the execution unit can be referred to, and then the allocation of the execution unit to the processor to be allocated is controlled.
- Yet another embodiment of the present invention is also a scheduling apparatus.
- this apparatus is a device that schedules the order in which execution units to be scheduled to be processed in parallel are assigned to a plurality of processors. At least one processor is excluded from the allocation target of the execution unit scheduled for parallel processing, and is exclusively occupied by the non-scheduled execution unit operating on the non-allocation target processor.
- a memory control unit that maps and manages the resources in the address space referred to by each execution target for scheduling so that the resources in the processor can also refer to the execution unit power for the scheduling target, and a state of waiting for execution and executing
- an assigning unit that takes out the execution units to be scheduled and allocates them to any one of the processors in the order of the leading power of the execution queue.
- FIG. 1 is a configuration diagram of a multiprocessor system according to a first embodiment.
- FIG. 2 is a diagram for explaining an address space seen from a thread assigned to the processor of FIG. 1.
- FIG. 3 is a diagram for explaining a thread operating on the processor of FIG. 1 and a thread group to which the thread belongs.
- FIG. 4 is a diagram for explaining how threads are allocated to processors in units of thread groups shown in FIG.
- FIG. 5 is a diagram illustrating thread state transitions
- FIG. 6 is a configuration diagram of a scheduling device according to the first embodiment.
- FIG. 7 is a diagram for explaining the thread state table in FIG. 6.
- FIG. 8 is a diagram for explaining the execution waiting queue of FIG. 6.
- FIG. 9 is a diagram for explaining the scheduling arrangement of FIG. 6.
- FIG. 10 illustrates a scheduling procedure by the scheduling device according to the first embodiment. It is a flowchart.
- FIG. 11 is a diagram illustrating a procedure for assigning threads at a certain time.
- FIG. 12 is a diagram illustrating a procedure for assigning threads at different times.
- FIG. 13 is a diagram showing a time change of a thread assignment state by the thread scheduling of FIGS. 11 and 12.
- FIG. 14 is a diagram for explaining another example of the thread state table of FIG. 6.
- FIG. 15 is a diagram illustrating a procedure for assigning threads at a certain time.
- FIG. 16 is a diagram showing the time change of the thread assignment state by the thread scheduling of FIG.
- FIG. 17 is a diagram for explaining yet another example of the thread state table in FIG. 6.
- FIG. 18 is a diagram illustrating a procedure for assigning threads at a certain time.
- FIG. 19 is a diagram illustrating a procedure for assigning threads at another time.
- FIG. 20 is a diagram illustrating a procedure for assigning threads at yet another time.
- FIG. 21 is a diagram illustrating a procedure for assigning threads at yet another time.
- FIG. 22 is a diagram showing a time change of a thread allocation state by the thread scheduling of FIGS. 18 to 21.
- FIG. 23 is a diagram for explaining an address space viewed from a thread assigned to a processor of the multiprocessor system according to the second embodiment.
- FIG. 24 is a diagram for explaining an address space as seen from a thread assigned to a processor of a multiprocessor system according to a third embodiment.
- FIG. 25 is a diagram showing a time change of a thread allocation state by thread scheduling in the multiprocessor system according to the third embodiment.
- FIG. 1 is a configuration diagram of a multiprocessor system according to the first embodiment.
- the multiprocessor system includes a plurality of processing elements (PE) 100 and a main memory 120, which are connected to the main bus 110.
- Each processing element 100 includes a processor 130, a local memory 140, and a memory control unit 150.
- the processor 130 can read and write data to the oral memory 140.
- the memory control unit 150 provides an interface for referring to data in the local memory 140 from the processors 130 of the other processing elements 100, and provides a function of memory synchronization and exclusive control.
- One of the processing elements 100 is an execution unit of parallel processing, and has a function of scheduling an execution entity (hereinafter referred to as a thread) to be scheduled.
- This scheduling function operates at the privilege level. At the privilege level, it has the right to access all resources of the multiprocessor system.
- programs that operate on other processing elements 100 that do not have a scheduling function operate at the user level. At the user level, the resources that can be accessed are limited compared to the privilege level.
- thread scheduling With thread scheduling, one thread is assigned to each processor 130 at a certain time, and a plurality of threads are executed in parallel in the entire multiprocessor system.
- the thread allocated to each processor 130 can occupy and use all resources such as the low-power memory 140 in the processing element 100 and the registers in the memory control unit 150.
- the thread context is saved in the main memory 120.
- the context of a thread is the state of all resources that the thread occupies in the processing element 100 to which it is assigned (hereinafter referred to as the assigned PE).
- a thread group including one or more threads as elements is defined, scheduling is performed in units of thread groups, and all threads belonging to the thread group are simultaneously selected by any processor 130. Assigned to. Some threads in the thread group are assigned to the processor 130, and the remaining threads do not remain in the main memory 120. Therefore, all threads in the same thread group share a transition state such as waiting for execution or executing. Threads belonging to the same thread loop can directly reference each other's address space without using the kernel system call.
- FIG. 2 is a diagram for explaining the address space 170 as seen from the thread assigned to the processor 130.
- the address space 170 includes a main memory area 172 to which main memory including shared data is mapped, and a thread map area 174 to which occupied resources of each thread in the same group are mapped.
- thread maps # 1 to #n are arranged corresponding to the threads in the same group. If the number of processors is n, a maximum of n threads can be provided in the same group, so n areas are reserved in the thread map.
- Each thread map #l to #n is a memory map of a part of resources that each corresponding thread occupies in the assigned PE.
- the local memory and the memory control unit 150 are allocated. Forces including a group of registers for controlling external force The memory group for controlling the memory controller 150 from the outside is not all accessible, but only the communication registers described later are accessible. This register cannot be accessed.
- the size of the thread map related to the types of accessible registers can be made constant.
- the offset value for the top address of the map becomes a fixed value, which makes management difficult for programmers.
- a part of the resources occupied in the assigned PE by each thread is mapped to the address space.
- each thread in the same group can access and operate a part of resources occupied by other threads without using a system call.
- registers for controlling the memory control unit 150 from the outside it is possible to place certain restrictions on external operations by mapping to the address space only the registers that permit the operation.
- the start address of the second thread map # 2 is the address obtained by adding the offset value corresponding to the size of the thread map to the thread base address.
- the scheduling device 200 described later stores, in the memory, which thread map is used by each thread in the same group as thread map setting information, and controls the memory of the PE to which the thread is allocated at the time of thread allocation.
- the memory control unit 150 of each processing element 100 can grasp to which thread map the resource of each thread in the same group is mapped by the thread map setting information. Based on the thread map of the address space 170, access requests for resources of other threads can be processed by the DMA.
- the thread state management unit 32 of the scheduling apparatus 200 described later manages thread group thread map setting information, and stores the thread map setting information in the thread state table 34 as an example. Hold.
- the thread allocation unit 14 of the scheduling apparatus 200 performs a process of allocating the thread to the processor, and performs a process of setting the thread group thread map setting information in the memory control unit 150.
- the thread assigned to the processor is started after the thread group thread map setting information is set in the memory control unit 150.
- the first thread A1 is assigned to the first area EA1 of the address space of group A.
- the resource memory is mapped and the resource capacity S memory map of the second thread A2 is mapped to the second area EA2 of the address space.
- thread Al, A2 in group A is scheduled, thread A1 is assigned to the first processor, and thread A2 is assigned to the second processor.
- the resource of the second processor is referred to as the resource of the second thread A2.
- the allocation and execution of the first thread Al and the second thread A2 to the processor are performed after the resources are prepared, so the first thread A1 to the second area EA2 that is the thread map of the second thread A2 This access is guaranteed to be an access to the resource of the second thread A2, regardless of which processor the second thread A2 is assigned to.
- the second thread A2 accesses the first area EA1, which is the thread map of the first thread A1.
- a thread allocated to any processor 130 accesses a thread map address set in the address space 170, so that resources occupied by other threads in the same group can be obtained. Can be accessed directly by DMA.
- the other threads in the same group are assigned to any of the processors 130. Which processor 130 is assigned to is different for each scheduling. However, the thread map is set to the same address in address space 170 that is related to which processor the thread is assigned to. Therefore, each thread in the same group is guaranteed to have consistent access to the resources of other threads by accessing a thread map in address space 170 that is independent of the thread's assignment to the processor.
- a communication register that can be used for synchronous communication between threads is provided.
- the value of the communication register can be read by a special instruction from the processor 130 of the processing element 100. If the value has not yet been written to the communication register, the processor 130 stores the value in the communication register. Wait until is written.
- this communication register controls the memory of the processing element 100 other than itself. Can be written from part 150.
- the communication register in the memory control unit 150 is memory-mapped as a thread map in the address space 170 as an occupied resource of the thread. Therefore, a thread can access a communication register of the memory control unit 150 of another processing element 100 by referring to a thread map in its address space 170, and can write a value. .
- the memory control unit 150 has a mechanism in which the processor stalls like a heart until another thread writes a value in the communication register of its own thread. It can be realized, and synchronous communication between threads becomes possible.
- FIGS. 3A to 3D are diagrams for explaining thread groups.
- FIG. 3 (a) shows the first thread group including three threads t hla, thlb and thlc.
- FIG. 3 (b) shows the second thread group including one thread th2a. If there is only one such thread, it is treated as a thread group.
- FIG. 3 (c) shows a third thread group including two threads th3a and th3b.
- FIG. 3 (d) shows the fourth thread group including one thread th4a.
- one thread is designated as the primary thread and represents the thread group.
- all threads belonging to that thread group can be operated together by operating the primary thread.
- FIG. 4 illustrates how threads are allocated to the processor 130 in units of thread groups.
- FIG. This figure shows an assignment state of threads belonging to the four thread groups shown in FIG. 3 to the processors 130 in a multiprocessor system having a total of four processors.
- the three threads thla, thlb, and thlc belonging to the first thread group are assigned to the first processor, the second processor, and the third processor, respectively, and one thread th2a belonging to the second thread group is Assigned to the 4th processor.
- the other two threads th3a and th3b belonging to the third thread group and the one thread th4a belonging to the fourth thread group are saved in the main memory 120.
- Thread scheduling is performed on condition that all threads belonging to the same thread group are allocated to any processor 130 at the same time.
- the first thread loop is assigned to the processor 130 only when the three threads thla, thlb, and thlc belonging to the first thread group can be assigned to any one of the processors 130 at the same time. If one or two of the three threads thla, thlb, thlc are assigned to processor 1 30 and the rest are evacuated to main memory 120, no situation is created!
- FIG. 5 is a diagram illustrating thread state transition.
- the thread is created by the create command and enters the not configured state 42.
- a configuration command is executed for a thread in the unconfigured state 42
- the state transitions to the configured state 44.
- the thread can belong to the same thread group as the primary thread.
- a delete command is executed for a thread in the construction state 44, the thread is deleted and the memory area used for the thread is released.
- the unconstructed state 42 and the built state 44 are combined into a dormant state 40.
- the start command is executed for the primary thread in the construction state 4 4, all threads belonging to the thread group including the primary thread transition to the ready state 52. Thereafter, all the threads belonging to the thread group make a state transition together in the operation (operationa 1) state 50.
- operationa 1 the operation (operationa 1) state 50.
- the command for the thread group is the primary thread. Execute on all threads that belong to the thread group.
- the thread in the execution waiting state 52 transitions to the synchronization waiting (waiting) state 56 by a wait command, and the thread in the synchronization waiting state 56 receives the signal and returns to the execution waiting state 52.
- a thread that is in the execution wait state 52 transitions to a running state 54 by a dispatch command, and a thread that is in the execution state 54 waits for execution by a yield command 52. Return to SYNC state 56 by the wait command, and enter suspend state 60 by the suspend command.
- the thread in the synchronization wait state 56 is changed to the waiting and suspended state 58 by the suspend command, and the thread in the synchronization wait suspension state 58 is synchronized by the resume command. Return to wait state 56.
- a thread in the synchronization wait suspended state 58 transitions to the suspended state 60 in response to a signal.
- a thread in the suspended state 60 transitions to the execution waiting state 52 by the resume command, and a thread in the execution waiting state 52 transitions to the suspended state 60 by the suspend command.
- a thread in the running state 54 transitions to a stopped state 62 when exception handling occurs, and a thread in the stopped state 62 transitions to the running state 54 or the waiting for execution state 52 by a restart command. To do.
- threads in the running state 54 are assigned to the processor 130, and threads in other states are retreated to the main memory 120.
- FIG. 6 is a configuration diagram of scheduling apparatus 200 according to Embodiment 1. This figure is a block diagram focusing on the functions, and these functional blocks can be realized in various forms by hardware only, software only, or their combination. .
- the scheduling device 200 is provided in any one of the processing elements 100 in FIG. 1 and is realized using the processor 130, the local memory 140, and the memory control unit 150. Further, the main memory 120 may be used. In the following description of the configuration of FIG. 6, FIGS. 7 to 9 will be referred to as appropriate.
- the thread state management unit 32 manages thread generation and deletion, thread group setting, thread group priority, and thread group unit state transition using the thread state table 34.
- FIG. 7 is a diagram for explaining the thread state table 34.
- the thread state table 34 stores a thread group ID 70, the number of threads 72 belonging to the thread group, a thread group transition state 74, a thread 76 belonging to the thread group, and a thread group priority 78 in association with each other.
- the thread state management unit 32 updates the thread state table 34 when there is a thread creation and deletion, a thread group setting and state change, a priority setting, or the like.
- the first thread group with group ID 1 has three threads, includes three threads thla, thlb, thlc, and the priority is set to 1.
- the current transition state Is running.
- the second thread group with group ID 2 has one thread, includes one thread th2a, has a priority set to 2, and the current transition state is being executed.
- the third thread group of group ID3 has two threads, includes two threads th3a and th3b, has a priority set to 2, and the current transition state is waiting for execution.
- the fourth thread group of group ID4 has one thread, includes one thread th4a, has a priority set to 4, and is currently waiting for execution. It is assumed that the lower the priority, the higher the priority.
- the priority is 16 levels, but there is a degree of design freedom such as 256 levels.
- the thread state management unit 32 queues the thread group in the execution waiting state or the executing state in the execution waiting queue 30 among the thread dulls managed in the thread state table 34.
- the execution queue 30 is a FIFO (First FIFO) in which thread groups that are in the execution waiting state or in the executing state are fetched first in the order of priority set for each thread group and within the same priority. In First Out) This is a queue that is queued with a priority.
- FIG. 8 is a diagram for explaining the execution waiting queue 30. For each entry in the list of priorities 1-16, the primary thread of the thread group with that priority is queued in FIFO order.
- the primary thread pt hi of the first thread group is queued to the priority 1 entry, and the primary thread pth2 and the second thread group of the second thread group are queued to the priority 2 entry.
- the primary thread pth3 of the 3 thread group is queued in this order, and the primary thread pth4 of the 4th thread group is queued in the priority 4 entry. Since the second thread group is queued before the third thread group, the primary thread pth2 of the second thread group is queued before the primary thread pth3 of the third thread group.
- the primary thread pth2 queued at the head of the priority 2 entry is linked from the priority 1 primary thread pthl at the head position of the waiting queue 30. Further, a link is made from the first primary thread pth2 of the priority 2 entry to the next primary thread pth3 queued within the same priority, and from the primary thread pth3 to the primary thread pth4 of priority 4 It is turned on. As a result, an execution waiting queue 30 with a priority determined so that the primary threads pthl, pth2, pth3, and pth4 can be extracted in this order is generated.
- the thread state management unit 32 deletes the primary thread of the thread group from the waiting queue 30.
- the primary thread of the thread group that has been newly created and is waiting to be executed by the start command, or the primary thread of the thread group that has been waiting for execution after returning from the synchronization waiting state, etc. is entered as an entry of the corresponding priority. Insert in FIF O order and update the waiting queue 30.
- the scheduler 10 controls to take out the thread group queued in the waiting queue 30 from the head and assign it to the processor, and includes an assignment list generation unit 12 and a thread assignment unit 14.
- the thread state management unit 32 restarts when the thread group state transitions to a state such as waiting for synchronization or suspended, or when the thread is terminated.
- the allocation list generator 12 is notified.
- the allocation list generation unit 12 receives a rescheduling instruction from the thread state management unit 32 and performs “marking processing” or “allocation list generation processing” to be described.
- the allocation list generation unit 12 includes an allocation thread number counter 16 and a thread allocation list 18.
- And scheduling array 20 is used to perform thread scheduling.
- the allocated thread number counter 16 counts the number of threads allocated to the processor 130 and is simply referred to as “counter” hereinafter.
- the thread allocation list 18 stores primary threads of a thread group to be allocated to the processor 130. Hereinafter, the thread allocation list 18 is simply referred to as an “allocation list”.
- the scheduling array 20 is a schedule table that holds the assignment status of threads to the processors 130, and is an array in which processor numbers that identify individual processors 130 are associated with threads that are assigned to the processors 130.
- FIG. 9 is a diagram for explaining the scheduling array 20.
- the scheduling array 20 stores a processor number 80, a thread 82 assigned to the processor, and a mark 84 in association with each other.
- the processor number 80 is an identification number uniquely corresponding to the processor.
- the mark 84 is used as a flag for ensuring the assignment of threads to processors in the marking process of the assignment list generator 12.
- the total number of processors is 4, and the first to fourth processors are identified by numbers 1 to 4.
- Processor numbers 1 to 3 are assigned three threads thla, thlb, and thlc in the first thread group, respectively, and processor number 4 is assigned thread th2a in the second thread group.
- the allocation list generation unit 12 initializes the counter 16 to zero and empties the allocation list 18.
- the allocation list generation unit 12 sequentially extracts the primary thread in the order of the leading force of the execution waiting queue 30.
- the thread group to which the extracted primary thread belongs is referred to as an “assignment candidate thread group”.
- the allocation list generation unit 12 adds the number of threads belonging to the allocation candidate thread group to the counter 16. If the value of counter 16 exceeds the total number of processors in the multiprocessor system, allocation list generator 12 The allocation candidate thread group is removed from the allocation candidate group, and the value of counter 16 is returned to the value before addition.
- the allocation list generation unit 12 refers to the scheduling array 20 to check whether or not the allocation candidate thread groups sequentially extracted from the execution queue 30 are already in execution. If each thread belonging to the allocation candidate thread group is in the scheduling array 20, each thread belonging to the allocation candidate thread group is being executed. In that case, in the scheduling array 20, the processor number to which the executing thread is assigned is marked. This is called “marking process”. As a result of the marking process, a thread already assigned to the marked processor number is allocated to the processor so that the assignment destination is not changed by another processor.
- the allocation list generation unit 12 determines that if each thread belonging to the allocation candidate thread group is not in the scheduling array 20, that is, if the allocation candidate thread group is not in the running state, the allocation candidate thread group Add the primary thread to assignment list 18 . This is called “allocation list generation processing”. Through the assignment list generation processing, the assignment list 18 lists the thread groups that are newly assigned to the processor 130 in the current scheduling.
- the allocation list generation unit 12 is the force at which the value of the counter 16 reaches the total number of processors.
- the waiting power of the execution waiting queue 30 is also used for marking processing and allocation list generation processing until the primary thread is extracted. Repeat these steps.
- the thread allocation unit 14 extracts the primary thread from the allocation list 18, and all threads belonging to the thread group are marked in the scheduling array 20! / ⁇ Allocate to the processor number. At this time, the thread assigned to the unmarked processor number and in the executing state is preempted and transitions to the execution waiting state. The thread allocation unit 14 notifies the thread state management unit 32 of the thread that has been provisioned, and the thread state management unit 32 updates the thread state table 34 and manages the state change of the thread.
- Red is assigned to processor 130 for execution.
- a thread that has already been in execution is continuously executed on the same processor 130, and a thread that is in the execution waiting state is newly assigned to the processor 130 and changes to the execution state.
- the thread state management unit 32 updates the thread state table 34 and manages the state change of each thread.
- FIG. 10 is a flowchart for explaining a thread scheduling procedure by the scheduling apparatus 200 having the above configuration.
- the thread state management unit 32 instructs the allocation list generation unit 12 to perform thread scheduling when the transition state of the thread changes from the running state force to the synchronization waiting state or the suspended state, or when the thread is terminated.
- the allocation list generator 12 initializes the counter 16 and the allocation list 18 (S10).
- the allocation list generation unit 12 extracts the allocation candidate thread group as well as the leading force of the waiting queue 30 (S 12).
- the allocation list generation unit 12 counts the number of hitting threads by counting the number of threads belonging to the allocation candidate thread group to the counter 16 (S14).
- the allocation list generator 12 determines whether or not the value of the counter 16 is equal to or less than the total number of processors (S16). If the value of counter 16 exceeds the total number of processors, all threads belonging to that allocation candidate thread group cannot be assigned to any processor at the same time! The number of threads is subtracted to return the counter value to the original value (S18), and the process proceeds to step S26.
- the allocation list generation unit 12 checks whether each thread belonging to the allocation candidate thread group is stored in the scheduling array 20 ( S20). If a thread belonging to the allocation candidate thread group is assigned to one of the processor numbers in the scheduling array 20, the thread is assigned to that processor in the previous scheduling and is executed. That's right.
- the allocation list generation unit 12 stores the thread in the scheduling array 20. Then, the processor number to which the thread is allocated is marked (S22). The thread assigned to the marked processor number is allocated to the processor so that it cannot be relocated by changing the assignment destination to another processor.
- the allocation list generation unit 12 assigns the allocation candidate thread group to the allocation list 18 (S23).
- allocation list generation unit 12 finishes generating allocation list 18 and cannot proceed to step S30 because no more threads can be allocated. .
- the allocation candidate generation thread group is one in which the tail power of the waiting queue 30 has been extracted (Y in S26)
- the allocation list generator 12 also has no next thread to allocate. The generation of allocation list 18 is completed, and the process proceeds to step S30.
- the allocation list generation unit 12 does not reach the number of processors in the counter 16 (N in S24), and the allocation candidate thread group is not one that has been extracted from the end queue of the waiting queue 30 (S26). N), the next thread group in the waiting queue 30 is taken out (S28), and the processing after step S14 is repeated.
- step S30 the thread assignment unit 14 assigns each thread belonging to the thread group stored in the assignment list 18 to a processor number that is marked! /? In the scheduling array 20. At this time, a thread that has already been allocated to an unmarked processor number is preempted from its assignment to that processor. When all the thread groups stored in the allocation list 18 have been allocated to the processor numbers, the series of thread scheduling processes ends.
- 11 to 13 are diagrams for explaining a thread scheduling procedure under the conditions shown in the thread state table 34 of FIG.
- FIG. 11 (a) shows the initial state of the waiting queue 30, and the primary thread pthl (hereinafter referred to as the first primary thread) of the first thread group is assigned to the second thread in the priority 1 entry.
- the primary thread pth2 of the thread group (hereinafter referred to as the second primary thread) and the primary thread pth3 of the third thread group (hereinafter referred to as the third primary thread) are assigned to the priority 2 entry and the primary thread pth4 of the fourth thread group. (Hereinafter referred to as the 4th primary thread) are queued to priority 4 entries.
- the execution queue 30 is a queue in which the priority is determined in the order of the first primary thread pthl, the second primary thread pth2, the third primary thread pth3, and the fourth primary thread pth4.
- FIG. 11 (b) is a diagram for explaining the process of the marking process and the allocation list generation process by the allocation list generation unit 12.
- the processing process table 15 indicates whether the allocation list generation unit 12 has performed the marking process or the allocation list generation process for the primary thread that has sequentially taken out the leading force of the waiting queue 30, and the counter at that time. 1 shows the value of 6.
- the allocation list generator 12 also takes out the first primary thread pthl as the leading force of the execution queue 30 in FIG. 11A, and adds the number of threads 3 in the first thread group to the counter 16. Since the scheduling array 20 is empty and no thread is subject to the marking process, the first primary thread pthl is stored in the allocation list 18 as it is.
- the allocation list generator 12 takes out the second primary thread pth2, which is the next entry in the waiting queue 30 in FIG. 11 (a), and sets the number of threads 1 in the second thread group to the counter 16. to add.
- the second primary thread pth2 is not subject to the marking process and is added to the allocation list 18.
- the counter value is 4, and since the total number of preset processors has been reached, the allocation list generator 12 finishes generating the allocation list 18.
- the thread allocation unit 14 is configured to mark all threads belonging to the first and second thread groups listed in the allocation list 18 of FIG. Allocate to V, N, and processor numbers.
- FIG. 11 (c) shows a scheduling array 20 in which threads are allocated according to the allocation list 18. None of the processor numbers are marked, the first to third processors are assigned three threads thla, thlb, thlc in the first thread group, and the fourth thread processor is assigned 1 in the second thread group. One thread th2a is allocated. This completes the thread scheduling at the current time to.
- FIG. 12A shows the execution waiting queue 30 at time tl. Since the first primary thread pthl is neither waiting nor being executed, the thread state management unit 32 removes the first primary thread pthl from the waiting queue 30. As a result, at the time tl, the head of the waiting queue 30 is the second primary thread pth2.
- the allocation list generation unit 12 Upon receiving the notification from the thread state management unit 32, the allocation list generation unit 12 initializes the counter 16 and the allocation list 18 and starts scheduling.
- FIG. 12 (b) shows the marking process and the allocation list generation process by the allocation list generation unit 12 at time tl.
- the allocation list generation unit 12 takes out the second primary thread pth 2 as the leading force of the waiting queue 30, adds 1 to the counter 16, and sets the counter value to 1.
- the allocation list generation unit 12 checks whether the thread th2a of the second thread group is in the scheduling array 20. At this time, the scheduling array 20 is in the state shown in FIG. 11 (c) at the previous time tO, and the thread th2a of the second thread group is assigned to the processor number 4, so the assignment list generator 12 Mark processor number 4 in scheduling array 20 as shown in Fig. 12 (c).
- the allocation list generation unit 12 takes out the third primary thread pth3, which is the next entry in the waiting queue 30, and adds 2 to the counter 16 as the number of threads in the third thread group. Is 3.
- the allocation list generator 12 schedules the threads th3a and th3b of the third thread group. Check if it is in one ring array 20. Since the threads th3a and th3b of the third thread group are not in the scheduling array 20 at time tO shown in FIG. 11 (c), the allocation list generation unit 12 adds the third primary thread pth3 to the allocation list 18. .
- the allocation list generation unit 12 takes out the fourth primary thread pth4, which is the next entry in the waiting queue 30, and adds 1 to the counter 16 for the number of threads in the fourth thread group.
- the allocation list generation unit 12 adds the fourth primary thread pth4 to the allocation list 18.
- the allocation list generator 12 finishes generating the allocation list 18 because the value of the counter 16 has reached the total number of processors 4.
- the thread allocation unit 14 assigns all threads belonging to the third and fourth thread groups listed in the allocation list 18 of Fig. 12 (b) to the processor number, marked V in the scheduling array 20. Allocate.
- FIG. 12 (c) is a diagram showing a scheduling array 20 in which threads are allocated according to the allocation list 18. Since the processor number 4 is marked, the thread th2a of the second thread group allocated to the processor number remains assigned. Processor numbers 1 to 3 that are not marked are assigned two threads th3a and th3b of the third thread group and one thread th4a of the fourth thread group, respectively. This completes thread scheduling at the current time tl.
- FIG. 13 is a diagram showing a temporal change in the thread assignment state by the thread scheduling described in FIG. 11 and FIG.
- the first to third processors PE1 to PE3 are assigned three threads thla to thlc of the first thread group, respectively, and the fourth processor (PE4) is assigned to thread th2a of the second thread group. Is assigned and executed.
- FIG. 14 to FIG. 16 are diagrams for explaining another example of thread scheduling. In this example, we explain that “priority inversion” occurs.
- FIG. 14 shows a thread state table 34 in this example.
- the third thread group differs from the example in Fig. 7 only in that the number of threads is 4, and the other conditions are the same as in the example in Fig. 7. Therefore, the scheduling result at the first time tO is the same as in FIG.
- the scheduling procedure at time tl when the threads in the first thread group are out of the waiting queue 30 due to, for example, waiting for synchronization will be described.
- FIG. 15 (a) is a diagram showing the state of the execution waiting queue 30 at time tl. As in FIG. 12 (a), as a result of the first primary thread pthl being removed from the waiting queue 30, the waiting queue 30 starts with the second primary thread pth2.
- FIG. 15B is a diagram for explaining the process of the marking process and the allocation list generation process by the allocation list generation unit 12 at time tl.
- the allocation list generator 12 uses the second primary thread pth as the starting force of the waiting queue 30.
- the allocation list generating unit 12 assigns the processor number 4 to which the thread th2a is allocated in the scheduling array 20 as shown in Fig. 15 (c). Put a mark.
- the allocation list generator 12 takes out the third primary thread pth3, which is the next entry in the execution queue 30.
- the allocation list generator 12 determines that the third thread group cannot be allocated because the counter value is 5 when the number of threads 4 of the third thread group is added to the counter 16, and the counter value becomes 5. For the 3 thread group, it is excluded from the allocation candidates, and neither the marking process nor the allocation list generation process is performed.
- the allocation list generator 12 takes out the fourth primary thread pth4, which is the next entry in the waiting queue 30.
- the counter 16 calculates the number of threads in the 4th thread group by 1, and sets the counter value to 2.
- the allocation list generator 12 is a thread of the fourth thread group. Since the node th4a is not in the scheduling array 20, the fourth primary thread pth4 is added to the allocation list 18. Since the thread th4a of the fourth thread group is the last entry in the waiting queue 30, the allocation list generator 12 finishes generating the allocation list 18.
- the thread allocation unit 14 allocates all threads belonging to the fourth thread group listed in the allocation list 18 of Fig. 15 (b) to unmarked V processor numbers in the scheduling array 20.
- FIG. 15 (c) shows a scheduling array 20 in which threads are assigned according to the assignment list 18.
- the thread th2a in the second thread group assigned to the marked processor number 4 is kept allocated and marked as it is! / ⁇ , one thread th4a in the fourth thread group is assigned to processor number 1. . This completes the scheduling of the thread at the current time tl.
- FIG. 16 is a diagram showing a change over time in the thread assignment state in this example.
- the thread assignment at time tO is the same as in FIG.
- the thread th2a of the second thread group that should be given the highest priority is kept in the same state as in FIG. 13, but the third thread group that should be given the next priority is the number of threads. Therefore, it cannot be assigned to a free processor, and the priority is lower than that of the third thread group, and the thread th4a of the fourth thread group is assigned to the first processor and executed.
- FIGS. 17 to 22 are diagrams for explaining yet another thread scheduling example. This example illustrates a situation where a thread that has already been allocated is preempted by another higher priority thread.
- FIG. 17 is a diagram for explaining the thread state table 34.
- the first thread group has a thread group up to the fifth thread group, the number of threads is 2, 3, 1, 1, 3, and the priority is 1, 2, 3, 4, 5, respectively.
- FIGS. 18A to 18C are diagrams for explaining scheduling at the first time tO. As shown in FIG. 18 (a), the first to fifth primary threads pthl to pth5 are queued in this order in the waiting queue 30.
- FIG. 18 (b) shows the process of marking processing and allocation list generation processing by the allocation list generation unit 12.
- the allocation list generation unit 12 also takes out the first primary thread pthl as the head force of the waiting queue 30, counts the number of threads 2 in the counter 16, sets the counter value to 2, and sets the first primary thread pthl. Add to assignment list 18.
- the allocation list generator 12 has the ability to extract the second primary thread pth2, which is the next entry in the waiting queue 30.
- the number of threads in the second thread group is 3, and when added to the counter 16, the total number of processors is 4.
- the second thread group cannot be assigned.
- the allocation list generation unit 12 takes out the third primary thread pth3, which is the next entry in the waiting queue 30, and adds the number of threads 1 in the third thread group to the counter 16 to obtain the counter value. 3 and add the third primary thread pth3 to allocation list 18. This causes a reversal of the priority in which the third thread group, which has a lower priority than the second thread group, is preferentially assigned to the processor. [0127] Furthermore, the allocation list generator 12 takes out the fourth primary thread pth4 which is the next entry in the waiting queue 30, adds 1 to the counter 16, and adds the number of threads 1 in the fourth thread group to the counter 16. 4 and the fourth primary thread pth4 is added to allocation list 18. The allocation list generator 12 finishes generating the allocation list 18 because the value of the counter 16 has reached the total number of processors 4.
- the thread allocation unit 14 allocates each thread belonging to the first, third, and fourth thread groups listed in the allocation list 18 of FIG. 18B to the scheduling array 20. As shown in Fig. 18 (c), two threads la and lb of the first thread group are allocated to processor numbers 1 and 2, respectively, and thread 3a of the third thread group is allocated to processor number 3 and the processors Number 4 is assigned to thread th4a of the 4th thread group.
- each thread of the first thread group waits for synchronization at time tl.
- the head of the waiting queue 30 becomes the second primary thread p th2.
- the allocation list generation unit 12 also extracts the second primary thread pth2 from the head force of the waiting queue 30, and adds the number of threads 3 of the second thread group to the counter 16.
- the counter value is 3. Since the thread of the second thread group is not in the scheduling array 20 at the previous time tO, the allocation list generator 12 adds the second primary thread pth2 to the allocation list 18.
- the allocation list generator 12 takes out the third primary thread pth3, which is the next entry in the waiting queue 30, and adds the number of threads 1 in the third thread group to the counter 16 to obtain the counter value. Is 4. Since the thread th3a of the third thread group is in the scheduling array 20 at the previous time tO, the allocation list generation unit 12 is assigned to the scheduling array 20 in the scheduling array 20 as shown in FIG. Mark processor number 3 to which thread th3a in the thread group is assigned.
- the thread allocation unit 14 Since the value of the counter 16 has reached the total number of processors 4, as shown in Fig. 19 (c), the thread allocation unit 14 has three threads th2a and th2b belonging to the second thread group listed in the allocation list 18. Th2c scheduling array unmarked processor number 20 Allocate to 1, 2, and 4. At this time, the thread th4a of the fourth thread group assigned to the processor number 4 is preempted by the thread th2c of the second thread group by the assignment to the processor.
- the allocation list generator 12 takes out the second primary thread pth2 from the head of the waiting queue 30, and adds the number of threads 3 of the second thread group to the counter 16 The counter value is 3. Since each thread of the second thread group is already in the scheduling array 20, the allocation list generator 12 assigns the processor number to which the threads th2a, th2b, th2c of the second thread group are allocated as shown in FIG. Mark 1, 2, and 4.
- the allocation list generator 12 takes out the fourth primary thread pth4, which is the next entry in the waiting queue 30, and adds the number of threads 1 in the fourth thread group to the counter 16 to obtain the counter value. Since the thread of the fourth thread group is not in the scheduling array 20, the fourth primary thread pth4 is added to the allocation list 18.
- the thread assignment unit 14 assigns the thread th4a of the fourth thread group listed in the assignment list 18 to the scheduling array 20 as shown in FIG. 20 (c). Allocate to unmarked processor number 3.
- the allocation list generator 12 extracts the fourth primary thread pth4 from the head of the waiting queue 30, and adds the number of threads 1 of the fourth thread group to the counter 16 The counter value is 1. Since the threads of the fourth thread group are already in the scheduling array 20, the allocation list generator 12 marks the processor number 3 to which the thread th4a of the fourth thread group is allocated as shown in FIG. 21 (c). Put on.
- the allocation list generator 12 performs the fifth entry, which is the next entry in the waiting queue 30. Take out the immediate thread pth5 and add the number of threads 3 in the fifth thread group to the counter 16 to set the counter value to 4. Since the thread of the fifth thread group is not in the scheduling array 20, the fifth primary thread pth5 is added to the allocation list 18.
- the thread assignment unit 14 assigns threads th5a, th5b, and th5c of the fifth thread group listed in the assignment list 18. Assigned to unmarked processor numbers 1, 2, and 4 in scheduling array 20, respectively.
- FIG. 22 is a diagram showing a temporal change in the thread assignment state in this example.
- two threads thla and t hlb of the first thread group are allocated to the first processor and the second processor, a thread th3a of the third thread group is allocated to the third processor, and the fourth thread is allocated to the fourth processor.
- the group thread th4a is assigned and executed.
- the first thread group waits for synchronization and rescheduling occurs.
- the thread th4a of the fourth thread group with the lower priority assigned to the fourth processor is assigned. Is preempted.
- the thread t h4a of the fourth thread group is assigned to the third processor instead.
- the threads th5a, th5b, and th5c of the fifth thread group are assigned to the first, second, and fourth processors, respectively, instead.
- threads are grouped, and a plurality of threads belonging to the same thread group are allocated to!
- the synchronization / exclusive control mechanism of the multiprocessor system can be used to efficiently refer to each other's address space among the threads in the thread group and to perform the exclusive processing of the memory efficiently.
- threads in a thread group are assigned to processors at the same time, enabling efficient communication between threads and sharing of memory.
- the thread with the highest priority is given the highest priority as much as possible under the condition that all threads belonging to the same thread group are simultaneously assigned to the processor. Resource utilization efficiency can be maximized.
- a thread with a lower priority than previously assigned is preempted. This preemption can help keep the priority.
- the thread group is given a lower priority and the priority order may be reversed. This reversal of priority can improve processor utilization.
- the execution queue 30 queues not only the thread group in the execution waiting state but also the thread group in the execution state in the order of priority and in the FIFO order within the same priority. Yes. As a result, the scheduling can be performed while maintaining the FIFO order of the thread group. If the thread group in the running state is removed from the execution queue 30, it is necessary to store the FIFO order separately to maintain the FIFO order, which complicates the processing and increases the efficiency. Will be reduced. However, in this embodiment, since the thread groups in the running state are also held in the execution queue 30 in the FIFO order, allocation processing can be performed in a batch while maintaining the FIFO order. For this reason, it is easy to perform processing with high efficiency of allocation processing.
- the allocation list generator 12 performs marking processing in the scheduling array 20, so that the already allocated threads are rearranged by changing the allocation destination processor. It can be guaranteed that nothing will happen.
- Running status When a thread that is in a state is continuously scheduled and executed, the thread is continuously executed on the same processor, so that the process of assigning a thread to a processor can be omitted. Processing efficiency is improved.
- the multiprocessor system according to the second embodiment has the same configuration as that of the multiprocessor system of FIG. 1, and one thread is assigned to each processor 130 at a certain time by thread scheduling, and a plurality of threads are paralleled in the entire multiprocessor system. The thread is executed.
- At least one processor 130 out of a plurality of processors 130 is excluded from thread scheduling, and threads are allocated to the remaining processor 130 by thread scheduling.
- thread scheduling Different from Embodiment 1.
- a thread group including one or more threads is defined, and the scheduling is performed on a thread group basis.
- a thread group is not particularly defined. Scheduling is performed in units of threads.
- a normal round robin method or priority method that controls the assignment of threads to processors in the order of priority described in the first embodiment and within the same priority order is adopted. May be.
- An execution entity that exclusively occupies the resources in the processing element 100 operates on the processor 130 of the processing element 100 that is not a thread allocation target (hereinafter referred to as a non-allocation target PE). Is not subject to scheduling, so once assigned to a processor, the assignment to that processor is not intercepted.
- a non-scheduling execution entity an execution entity that is not a scheduling target that operates on this non-allocation target PE is referred to as a “non-scheduling execution entity”.
- the non-scheduled execution entity can occupy and use all resources such as the local memory 140 in the non-allocation target PE and the registers in the memory control unit 150. This is because the thread power allocated to the processing element 100 by thread scheduling is the local memory 140 in the processing element 100 or the memory control unit 1 It is the same as being able to occupy and use all resources such as 50 internal registers. In addition, for resources occupied by non-scheduled execution entities, almost all of them are allowed except for critical resources so that some accesses are not permitted so that they can be accessed from the outside, that is, other processing elements 100. Resources are mapped into the address space.
- FIG. 23 is a diagram for explaining the address space 170 as seen from a thread assigned to a certain processor 130.
- the resources that the non-scheduling execution entity operating in the non-allocation target PE occupies in time are memory mapped in the address space 170 of each thread operating in the other processing element 100.
- the address space 170 includes a main memory area 172 to which main memory including shared data is mapped, and a non-scheduling target execution entity map area 176 to which occupied resources of the non-scheduling target execution entity are mapped.
- two non-scheduling target execution entity maps # 1 and # 2 are arranged in the non-scheduling target execution entity map area 176.
- two processing elements 100 are selected as non-allocation target PEs, and non-scheduling target execution entities operate on each non-allocation target PE.
- Each non-scheduled execution entity map # 1, # 2 is a memory map of the resources that each non-scheduled execution entity occupies in the non-allocation target PE.
- local memory and memory It includes a register group for controlling controller 150 from the outside.
- the register group includes a program control register for executing and stopping programs, and a D for controlling DMA.
- the first non-scheduled execution entity map # 1 is allocated an area for the non-scheduled execution entity map with the non-scheduled execution entity base address as the start address.
- Second non-scheduled execution entity pine The start address of # 2 is the address obtained by adding the offset value corresponding to the size of the non-scheduled execution entity map to the non-scheduled execution entity base address.
- there are only two non-scheduled execution entity maps # 1 and # 2 but in general, only the number of processing elements 100 that are not subject to thread scheduling and have non-scheduled execution entities running.
- a non-scheduling target execution entity map is provided.
- the ID power returned as the return value of the generation function also determines the number of the non-scheduled execution entity map, and the non-scheduled execution entity in the address space 170 Whether to use a non-scheduled execution entity map is determined statically.
- the memory control unit 150 of each processing element 100 holds the power of which non-scheduled execution entity map is used by each non-scheduled execution entity map as setting information of the non-scheduling execution entity map.
- the memory control unit 150 of each processing element 100 can grasp the force that the resource of each non-scheduled execution entity is memory-mapped to which non-scheduled execution entity map from the setting information of the non-scheduling execution entity map. Based on the non-scheduled execution entity map in the address space 170, the access request for the resource of the non-scheduling execution entity can be processed by the DMA.
- the first and second processors are also removed from the thread scheduling target, the first non-scheduled execution entity R1 operates on the first processor, and the second non-scheduled target on the second processor. Assume that the execution entity R2 operates. Also, assume that threads are scheduled and allocated to the third and fourth processors.
- the resource cache of the first non-scheduled execution entity R1 is mapped to the first area ER1 of the thread address space and the second area ER2 Assume that the resource cache of the second non-scheduled execution entity R2 has been mapped. Assume that the first thread A1 is assigned to the third processor and the second thread A2 is assigned to the fourth processor by thread scheduling.
- the resource of the first processor is referred to as the resource of the first non-scheduling execution entity R 1.
- the access from the first thread A1 to the first area ER1, which is the non-scheduled execution entity map of the first non-scheduled execution entity R1 is related to which processor the first non-scheduling execution entity R1 is operating on.
- the access to the resource of the first non-scheduled execution entity R1 is guaranteed. The same applies when the first thread A1 accesses the second area ER2, which is the non-scheduled execution entity map of the second non-scheduled execution entity R2.
- the second thread A2 operating on the fourth processor accesses the first area ER1 and the second area ER2, which are the non-scheduled execution entity maps of the first and second non-scheduled execution entities Rl and R2. The case is exactly the same.
- a thread allocated to any processor 130 accesses the address of the non-scheduled execution entity map set in the address space 170, thereby occupying the non-scheduled execution entity.
- the resource to be accessed can be directly accessed by DMA.
- the synchronization mechanism described in the first embodiment is also effective in the present embodiment.
- the thread performs an operation to write a value to the communication register in the memory control unit 150, which is one of the resources of the non-scheduled execution entity that is memory-mapped in the address space, and the non-scheduling execution entity communicates with it. By waiting for the completion of writing to the register for execution, synchronization can be established between the non-scheduled execution entity and the thread.
- Another use of the non-scheduled execution entity is to process the non-scheduled execution entity by mapping the occupied resources of the non-scheduled execution entity into the memory space of a device such as a graphics display device. A synchronization mechanism that uses the occupied resources of the non-scheduled execution entity may be realized between the server and the graphics display device.
- the thread group is not defined. Threads may be grouped as in the first embodiment, and scheduling may be performed in units of thread groups.
- the multiprocessor system according to the third embodiment is the same as the multiprocessor system according to the first embodiment.
- the method of memory-mapping the occupied resources of the non-scheduled execution entity described in the second embodiment is described in the second embodiment.
- At least one processor 130 out of the plurality of processors 130 is excluded from thread scheduling, and threads are thread-scheduled to the remaining processors 130.
- a thread group including one or more threads is defined, and scheduling is performed in units of thread groups. Descriptions of configurations and operations that are common to Embodiments 1 and 2 are omitted, and only different configurations and operations are described.
- FIG. 24 is a diagram for explaining the address space 170 as seen from a thread assigned to a certain processor 130.
- a main memory area 172 to which main memory including shared data is mapped a thread map area 174 to which the occupied resources of each thread in the same group are mapped, and an occupied resource of the non-scheduled execution entity And a non-scheduled execution entity map area 176 to which is mapped.
- the thread map area 174 is as described in the first embodiment, and the non-scheduling target execution entity map area 176 is as described in the second embodiment.
- the resources included in each thread map indicated by reference numeral 175 and the resources included in each non-scheduled execution entity map indicated by reference numeral 177 are included in the thread map. There is a difference that some resources are not allowed to be accessed. Since the types of resources to be mapped are the same, the size of both maps is the same, and the offset value for the start address is the same. .
- the thread map area 174 is set for the address space of threads belonging to the same group, and cannot be referenced from threads belonging to different groups, but the non-scheduled execution entity map area. 176 is fixedly arranged regardless of the group to which the thread belongs, and can be referred to by the same address. Further, since the non-scheduling target execution entity map area 176 is not saved in the main memory 120, it can be referenced at any time in the thread address space.
- FIG. 25 is a diagram showing a temporal change in the thread assignment state by the thread scheduling according to the present embodiment.
- the first and second processors are selected as non-assignment target PEs, and threads are scheduled and assigned to the other third to sixth processors.
- the first non-scheduled execution entity is executed in the first processor, and the second non-scheduled execution entity is executed in the second processor. Since these non-scheduling target execution entities are not subject to scheduling, they continue to occupy each processor in time until the non-scheduling target execution entities are deleted.
- threads are scheduled and allocated in units of thread groups in the same manner as the thread scheduling example of the first embodiment described in FIG.
- the processor may be added to the target allocated by the thread. For example, if the second non-scheduled execution entity is deleted and the second processor is released, the second processor is added to the thread allocation target at the next scheduling timing, and the second to A thread may be scheduled and assigned to the sixth processor.
- a symmetric multiprocessor system in which all processing elements have the same configuration will be described as an example of a multiprocessor system, and one of the V ⁇ processing elements is used to manage threads. It was configured to have a scheduling function.
- the multiprocessor system may be an asymmetric multiprocessor system including a management processing element, and the management processing element may have a thread management 'scheduling function.
- the scheduling function may be realized as a part of the operating system (OS) function or as a process running on the OS.
- OS operating system
- the present invention can be applied to multiprocessor scheduling techniques.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011039666A (ja) * | 2009-08-07 | 2011-02-24 | Hitachi Ltd | バリア同期方法及び計算機 |
US10553315B2 (en) * | 2015-04-06 | 2020-02-04 | Preventice Solutions, Inc. | Adverse event prioritization and handling |
Families Citing this family (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7913206B1 (en) * | 2004-09-16 | 2011-03-22 | Cadence Design Systems, Inc. | Method and mechanism for performing partitioning of DRC operations |
DE102005001025A1 (de) * | 2005-01-07 | 2006-07-27 | Infineon Technologies Ag | Multithread-Prozessor mit Kontext-Umschaltung ohne Einschränkungen und/oder Zyklenverlust und Verfahren zum Betreiben eines solchen |
US7631130B2 (en) * | 2005-02-04 | 2009-12-08 | Mips Technologies, Inc | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
US7506140B2 (en) * | 2005-02-04 | 2009-03-17 | Mips Technologies, Inc. | Return data selector employing barrel-incrementer-based round-robin apparatus |
US7664936B2 (en) * | 2005-02-04 | 2010-02-16 | Mips Technologies, Inc. | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages |
US7613904B2 (en) * | 2005-02-04 | 2009-11-03 | Mips Technologies, Inc. | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler |
US7681014B2 (en) * | 2005-02-04 | 2010-03-16 | Mips Technologies, Inc. | Multithreading instruction scheduler employing thread group priorities |
US7853777B2 (en) * | 2005-02-04 | 2010-12-14 | Mips Technologies, Inc. | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions |
US7490230B2 (en) * | 2005-02-04 | 2009-02-10 | Mips Technologies, Inc. | Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor |
US7657891B2 (en) | 2005-02-04 | 2010-02-02 | Mips Technologies, Inc. | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency |
US7752627B2 (en) * | 2005-02-04 | 2010-07-06 | Mips Technologies, Inc. | Leaky-bucket thread scheduler in a multithreading microprocessor |
US7657883B2 (en) * | 2005-02-04 | 2010-02-02 | Mips Technologies, Inc. | Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor |
US7904852B1 (en) | 2005-09-12 | 2011-03-08 | Cadence Design Systems, Inc. | Method and system for implementing parallel processing of electronic design automation tools |
JP4388518B2 (ja) * | 2005-11-01 | 2009-12-24 | 株式会社ソニー・コンピュータエンタテインメント | スレッドデバッグ装置、スレッドデバッグ方法及びプログラム |
EP1963963A2 (en) * | 2005-12-06 | 2008-09-03 | Boston Circuits, Inc. | Methods and apparatus for multi-core processing with dedicated thread management |
US8448096B1 (en) | 2006-06-30 | 2013-05-21 | Cadence Design Systems, Inc. | Method and system for parallel processing of IC design layouts |
US7657856B1 (en) | 2006-09-12 | 2010-02-02 | Cadence Design Systems, Inc. | Method and system for parallel processing of IC design layouts |
US7990989B2 (en) * | 2006-09-16 | 2011-08-02 | Mips Technologies, Inc. | Transaction selector employing transaction queue group priorities in multi-port switch |
US7760748B2 (en) * | 2006-09-16 | 2010-07-20 | Mips Technologies, Inc. | Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch |
US7773621B2 (en) * | 2006-09-16 | 2010-08-10 | Mips Technologies, Inc. | Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch |
US7961745B2 (en) * | 2006-09-16 | 2011-06-14 | Mips Technologies, Inc. | Bifurcated transaction selector supporting dynamic priorities in multi-port switch |
JP5050601B2 (ja) * | 2007-03-23 | 2012-10-17 | 日本電気株式会社 | ジョブへの資源割当方式、ジョブへの資源割当方法およびプログラム |
US20080271027A1 (en) * | 2007-04-27 | 2008-10-30 | Norton Scott J | Fair share scheduling with hardware multithreading |
US9384159B2 (en) * | 2007-05-24 | 2016-07-05 | International Business Machines Corporation | Creating a checkpoint for a software partition in an asynchronous input/output environment |
JP2009020692A (ja) * | 2007-07-11 | 2009-01-29 | Toshiba Corp | タスク管理装置、タスク管理方法及びタスク管理プログラム |
TWI386851B (zh) * | 2007-09-14 | 2013-02-21 | Hon Hai Prec Ind Co Ltd | 排程任務更新系統及方法 |
JP4907488B2 (ja) * | 2007-10-24 | 2012-03-28 | 株式会社リコー | 画像処理装置、画像処理方法及び該方法を実行させるためのプログラムを格納したコンピュータ読み取り可能な記録媒体 |
TWI462011B (zh) * | 2007-12-28 | 2014-11-21 | Accton Technology Corp | 程序之執行緒群組管理方法 |
CN101494636B (zh) * | 2008-01-23 | 2013-01-16 | 中兴通讯股份有限公司 | 一种基于快速io互连技术的数据排序方法及装置 |
US8561072B2 (en) * | 2008-05-16 | 2013-10-15 | Microsoft Corporation | Scheduling collections in a scheduler |
US8566830B2 (en) * | 2008-05-16 | 2013-10-22 | Microsoft Corporation | Local collections of tasks in a scheduler |
US8769048B2 (en) * | 2008-06-18 | 2014-07-01 | Commvault Systems, Inc. | Data protection scheduling, such as providing a flexible backup window in a data protection system |
US8296773B2 (en) | 2008-06-30 | 2012-10-23 | International Business Machines Corporation | Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance |
WO2010001736A1 (ja) | 2008-07-04 | 2010-01-07 | 日本電気株式会社 | マルチプロセッサシステム、マルチスレッド処理方法、及びプログラム |
JP5173713B2 (ja) | 2008-09-30 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | マルチスレッドプロセッサ及びそのハードウェアスレッドのスケジュール方法 |
JP5173711B2 (ja) | 2008-09-30 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | マルチスレッドプロセッサ及びそのハードウェアスレッドのスケジュール方法 |
JP5173712B2 (ja) | 2008-09-30 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | マルチスレッドプロセッサ |
GB0820920D0 (en) * | 2008-11-14 | 2008-12-24 | Wolfson Microelectronics Plc | Codec apparatus |
WO2010089900A1 (en) * | 2009-02-05 | 2010-08-12 | Nec Corporation | Method, system and program for deadline constrained task admission control and scheduling using genetic approach |
JP5241550B2 (ja) * | 2009-02-12 | 2013-07-17 | 株式会社日立製作所 | ファイル入出力方法 |
WO2010092483A1 (en) * | 2009-02-13 | 2010-08-19 | Alexey Raevsky | Devices and methods for optimizing data-parallel processing in multi-core computing systems |
US20110010716A1 (en) * | 2009-06-12 | 2011-01-13 | Arvind Raghuraman | Domain Bounding for Symmetric Multiprocessing Systems |
US8352946B2 (en) * | 2009-08-11 | 2013-01-08 | International Business Machines Corporation | Managing migration ready queue associated with each processor based on the migration ready status of the tasks |
US8832712B2 (en) * | 2009-09-09 | 2014-09-09 | Ati Technologies Ulc | System and method for synchronizing threads using shared memory having different buffer portions for local and remote cores in a multi-processor system |
CN101673223B (zh) * | 2009-10-22 | 2012-03-21 | 同济大学 | 基于片上多处理器的线程调度实现方法 |
JP5526748B2 (ja) * | 2009-12-09 | 2014-06-18 | 日本電気株式会社 | パケット処理装置、パケット振り分け装置、制御プログラム及びパケット分散方法 |
CN101788908B (zh) * | 2010-01-26 | 2014-11-05 | 浪潮(山东)电子信息有限公司 | 一种支持断点续航的批量数据处理方法 |
JP5429363B2 (ja) | 2010-03-25 | 2014-02-26 | 富士通株式会社 | マルチコアプロセッサシステム、制御プログラム、および制御方法 |
US9886315B2 (en) * | 2010-08-27 | 2018-02-06 | Ebay Inc. | Identity and semaphore-based quality of service |
US8789065B2 (en) | 2012-06-08 | 2014-07-22 | Throughputer, Inc. | System and method for input data load adaptive parallel processing |
US20130117168A1 (en) * | 2011-11-04 | 2013-05-09 | Mark Henrik Sandstrom | Maximizing Throughput of Multi-user Parallel Data Processing Systems |
US9158592B2 (en) | 2011-05-02 | 2015-10-13 | Green Hills Software, Inc. | System and method for time variant scheduling of affinity groups comprising processor core and address spaces on a synchronized multicore processor |
RU2011117765A (ru) * | 2011-05-05 | 2012-11-10 | ЭлЭсАй Корпорейшн (US) | Устройство (варианты) и способ реализации двухпроходного планировщика задач линейной сложности |
US9262181B2 (en) * | 2011-05-10 | 2016-02-16 | International Business Machines Corporation | Process grouping for improved cache and memory affinity |
EP2707796A4 (en) * | 2011-05-13 | 2016-06-08 | Samsung Electronics Co Ltd | METHOD AND APPARATUS FOR ENHANCING APPLICATION PROCESSING SPEED IN DIGITAL DEVICE |
KR101897598B1 (ko) * | 2011-05-13 | 2018-09-13 | 삼성전자 주식회사 | 디지털 디바이스의 어플리케이션 처리 속도 향상 방법 및 장치 |
CN102193779A (zh) * | 2011-05-16 | 2011-09-21 | 武汉科技大学 | 一种面向MPSoC的多线程调度方法 |
US9448847B2 (en) | 2011-07-15 | 2016-09-20 | Throughputer, Inc. | Concurrent program execution optimization |
US8745626B1 (en) * | 2012-12-17 | 2014-06-03 | Throughputer, Inc. | Scheduling application instances to configurable processing cores based on application requirements and resource specification |
US9158587B2 (en) * | 2012-01-19 | 2015-10-13 | International Business Machines Corporation | Flexible task and thread binding with preferred processors based on thread layout |
US9069564B1 (en) * | 2012-02-14 | 2015-06-30 | Netlogic Microsystems, Inc. | Weighted instruction count scheduling |
US9286115B2 (en) * | 2012-06-21 | 2016-03-15 | Microsoft Technology Licensing, Llc | Performant runtime pause with no CPU utilization |
CN102929707B (zh) * | 2012-11-06 | 2015-10-07 | 无锡江南计算技术研究所 | 并行任务动态分配方法 |
JP5676664B2 (ja) * | 2013-02-27 | 2015-02-25 | Necプラットフォームズ株式会社 | リソース管理装置、リソースの管理方法、及びプログラム |
CN104422694A (zh) * | 2013-09-11 | 2015-03-18 | 法国圣戈班玻璃公司 | 测量数据的处理装置及处理方法、光学测量系统 |
GB2521151B (en) * | 2013-12-10 | 2021-06-02 | Advanced Risc Mach Ltd | Configurable thread ordering for a data processing apparatus |
GB2521155B (en) | 2013-12-10 | 2021-06-02 | Advanced Risc Mach Ltd | Configuring thread scheduling on a multi-threaded data processing apparatus |
US9798596B2 (en) | 2014-02-27 | 2017-10-24 | Commvault Systems, Inc. | Automatic alert escalation for an information management system |
JP6364827B2 (ja) * | 2014-03-10 | 2018-08-01 | 日本電気株式会社 | 情報処理装置、及び、そのリソースアクセス方法、並びに、リソースアクセスプログラム |
JP6442947B2 (ja) * | 2014-09-19 | 2018-12-26 | 日本電気株式会社 | 情報処理装置、情報処理方法及びそのプログラム |
CN105656973B (zh) * | 2014-11-25 | 2018-11-13 | 中国科学院声学研究所 | 一种分布式节点组内任务调度方法及系统 |
US9727944B2 (en) | 2015-06-22 | 2017-08-08 | Apple Inc. | GPU instruction storage |
US20180032376A1 (en) * | 2016-07-27 | 2018-02-01 | Samsung Electronics Co .. Ltd. | Apparatus and method for group-based scheduling in multi-core processor system |
CN106445675B (zh) * | 2016-10-20 | 2019-12-31 | 焦点科技股份有限公司 | 一种b2b平台分布式应用调度与资源分配方法 |
US10789240B2 (en) * | 2017-11-06 | 2020-09-29 | Google Llc | Duplicative data detection |
JP7042105B2 (ja) | 2018-02-16 | 2022-03-25 | 日立Astemo株式会社 | プログラム実行制御方法および車両制御装置 |
US10761942B2 (en) | 2018-03-12 | 2020-09-01 | Commvault Systems, Inc. | Recovery point objective (RPO) driven backup scheduling in a data storage management system using an enhanced data agent |
US11048656B2 (en) * | 2018-03-31 | 2021-06-29 | Micron Technology, Inc. | Multi-threaded, self-scheduling reconfigurable computing fabric |
US10754706B1 (en) | 2018-04-16 | 2020-08-25 | Microstrategy Incorporated | Task scheduling for multiprocessor systems |
CN108595366A (zh) * | 2018-04-16 | 2018-09-28 | 哈尔滨工业大学(威海) | 一种实时的容错的多处理器系统结构模型 |
US10860443B2 (en) | 2018-12-10 | 2020-12-08 | Commvault Systems, Inc. | Evaluation and reporting of recovery readiness in a data storage management system |
JP7105927B2 (ja) * | 2019-01-30 | 2022-07-25 | 富士フイルム株式会社 | 医用画像解析装置、方法およびプログラム |
CN112667369A (zh) * | 2020-06-08 | 2021-04-16 | 宸芯科技有限公司 | 一种线程调度方法、装置、存储介质及电子设备 |
CN114237274B (zh) * | 2021-09-28 | 2024-04-19 | 航天时代飞鸿技术有限公司 | 融合imu的旋翼无人机环境障碍物快速感知方法及系统 |
US20230135951A1 (en) * | 2021-10-29 | 2023-05-04 | Blackberry Limited | Scheduling of threads for clusters of processors |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09179834A (ja) * | 1995-12-25 | 1997-07-11 | Hitachi Ltd | 並列システムにおけるプロセスのスケジューリング方法 |
JPH09274608A (ja) * | 1996-04-04 | 1997-10-21 | Hitachi Ltd | マルチプロセッサシステムにおけるプロセッサ間の負荷配分制御方法 |
JPH1063525A (ja) * | 1996-08-23 | 1998-03-06 | Canon Inc | 情報処理装置、情報処理システム及びその制御方法 |
JP3557947B2 (ja) * | 1999-05-24 | 2004-08-25 | 日本電気株式会社 | 複数のプロセッサで同時にスレッドの実行を開始させる方法及びその装置並びにコンピュータ可読記録媒体 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06187312A (ja) * | 1992-12-18 | 1994-07-08 | Omron Corp | マルチcpuシステムにおける処理方法および装置 |
JP3259620B2 (ja) * | 1995-12-21 | 2002-02-25 | 株式会社日立製作所 | 資源割り当て方法 |
GB2334116A (en) * | 1998-02-04 | 1999-08-11 | Ibm | Scheduling and dispatching queued client requests within a server computer |
US6601146B2 (en) * | 1998-06-16 | 2003-07-29 | International Business Machines Corporation | Technique for efficiently transferring moderate amounts of data across address space boundary |
US6314501B1 (en) * | 1998-07-23 | 2001-11-06 | Unisys Corporation | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
US6910210B1 (en) * | 1998-11-24 | 2005-06-21 | Microsoft Corp. | System and method for terminating applications |
US6526491B2 (en) * | 2001-03-22 | 2003-02-25 | Sony Corporation Entertainment Inc. | Memory protection system and method for computer architecture for broadband networks |
JP2003263331A (ja) * | 2002-03-07 | 2003-09-19 | Toshiba Corp | マルチプロセッサシステム |
US7360219B2 (en) * | 2002-12-13 | 2008-04-15 | Hewlett-Packard Development Company, L.P. | Systems and methods for facilitating fair and efficient scheduling of processes among multiple resources in a computer system |
US20040237087A1 (en) * | 2003-05-08 | 2004-11-25 | Nong Ye | Job scheduling techniques to reduce the variance of waiting time |
JP3892829B2 (ja) * | 2003-06-27 | 2007-03-14 | 株式会社東芝 | 情報処理システムおよびメモリ管理方法 |
-
2004
- 2004-12-01 JP JP2004348479A patent/JP4606142B2/ja active Active
-
2005
- 2005-11-25 WO PCT/JP2005/021663 patent/WO2006059543A1/ja active Application Filing
- 2005-11-25 CN CN2005800412782A patent/CN101069161B/zh active Active
- 2005-11-25 EP EP05809655.3A patent/EP1837762B1/en active Active
- 2005-11-30 US US11/291,073 patent/US7913257B2/en active Active
- 2005-12-01 TW TW094142287A patent/TWI410866B/zh active
-
2011
- 2011-01-24 US US13/012,054 patent/US8166482B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09179834A (ja) * | 1995-12-25 | 1997-07-11 | Hitachi Ltd | 並列システムにおけるプロセスのスケジューリング方法 |
JPH09274608A (ja) * | 1996-04-04 | 1997-10-21 | Hitachi Ltd | マルチプロセッサシステムにおけるプロセッサ間の負荷配分制御方法 |
JPH1063525A (ja) * | 1996-08-23 | 1998-03-06 | Canon Inc | 情報処理装置、情報処理システム及びその制御方法 |
JP3557947B2 (ja) * | 1999-05-24 | 2004-08-25 | 日本電気株式会社 | 複数のプロセッサで同時にスレッドの実行を開始させる方法及びその装置並びにコンピュータ可読記録媒体 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1837762A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011039666A (ja) * | 2009-08-07 | 2011-02-24 | Hitachi Ltd | バリア同期方法及び計算機 |
US10553315B2 (en) * | 2015-04-06 | 2020-02-04 | Preventice Solutions, Inc. | Adverse event prioritization and handling |
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US7913257B2 (en) | 2011-03-22 |
TW200632743A (en) | 2006-09-16 |
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EP1837762A4 (en) | 2014-09-17 |
EP1837762A1 (en) | 2007-09-26 |
TWI410866B (zh) | 2013-10-01 |
CN101069161A (zh) | 2007-11-07 |
US20110119674A1 (en) | 2011-05-19 |
US20060123420A1 (en) | 2006-06-08 |
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