WO2006034697A1 - Procede de fabrication d'un collet destine a un composant a semiconducteurs et collet ainsi fabrique - Google Patents

Procede de fabrication d'un collet destine a un composant a semiconducteurs et collet ainsi fabrique Download PDF

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Publication number
WO2006034697A1
WO2006034697A1 PCT/DE2005/001723 DE2005001723W WO2006034697A1 WO 2006034697 A1 WO2006034697 A1 WO 2006034697A1 DE 2005001723 W DE2005001723 W DE 2005001723W WO 2006034697 A1 WO2006034697 A1 WO 2006034697A1
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WO
WIPO (PCT)
Prior art keywords
flange
alloy
metallic material
layer
copper
Prior art date
Application number
PCT/DE2005/001723
Other languages
German (de)
English (en)
Inventor
Jochen Dangelmaier
Volker GÜNGERICH
Stefan Paulus
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2006034697A1 publication Critical patent/WO2006034697A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for the production of a flange for a semiconductor component according to the preamble of patent claim 1 and to a flange produced by the method according to claim 20.
  • TC thermal conductivity
  • CTE thermal expansion coefficient
  • Such a component is known from US Pat. No. 6,261,868 B1. Copper (Cu), alloys of copper and tungsten (W) or alloys of copper and molybdenum (Mo) are used here as the flange material. Furthermore, laminates of the aforementioned materials are used. As a result, first materials with suitable thermal expansion coefficients with second materials having suitable heat conductivity can be used be suitably combined to optimize the overall thermomechanical flanging properties.
  • Such laminate flanges have been produced by roller cladding for a long time, as is known, for example, from DE 103 10 646 A1.
  • a base material of the flange as a so-called flange core, in this case, for example, a thin plate is used, consisting for example of a copper-tungsten alloy (CuW), a copper-molybdenum alloy (CuMo) or ceramic (eg beryllium (BeO)). These materials are inexpensive and relatively easy to manufacture.
  • a thermally highly conductive metallic layer On both sides of the flange core, a thermally highly conductive metallic layer, the so-called cover layer, can be produced by PVD (physical vapor deposition) or CVD (chemical vapor deposition). drive or was ⁇ applied by means of galvanic Abborgüng.
  • This highly conductive layer may consist, for example, of copper (Cu), silver (Ag), gold (Au) or aluminum (Al).
  • a PVD method for depositing the cover layer on the flange core is used (claim 2).
  • This is e.g. realized by vapor deposition of the second material, which may be highly thermally conductive (claim 3).
  • thermal and electron beam vapor deposition methods are suitable here.
  • the latter method is preferably suitable for high-melting materials which are to be applied simultaneously to the substrate at a high deposition rate.
  • the PVD method can be realized by cathode sputtering (so-called sputtering) of the material to be applied (claim 4). Especially with low requirements on the deposition rate, both the structure and the stoichiometry of the covering layer to be applied can be well controlled in this process.
  • the CVD technology often used elsewhere in semiconductor processing technology can also be used to produce the cover layer (claim 5).
  • a production of the cover layer by means of electrodeposition (claim 6) has the advantage that, in particular, in comparison to other PVD processes, on the one hand no vacuum conditions are required and, on the other hand, the coating of the flange core at a relatively high coating rate of both Pages can be made.
  • the flange core material is an electrically conductive material.
  • the preferred flange core is ceramics, e.g. Berylli ⁇ oxide (claim 7).
  • the thermal expansion coefficient (CTE) of the flange core is adapted as far as possible to that of the semiconductor chip. Due to the generally dominant layer thickness of the flange core in the later semiconductor device, this adaptation is of particular importance.
  • metals or metal alloys of copper for example, CuW or CuMo alloys.
  • the thermal expansion coefficient (CTE) is adjustable between 11.5 and 7.1 x 10 ⁇ 6 -.
  • all further materials are suitable as the flange core, which have a thermal expansion coefficient (CTE) which is sufficiently similar to the semiconductor chip (claim 9).
  • CTE thermal expansion coefficient
  • the selection of the cover layer material is essentially based on the criteria of maximizing the thermal conductivity (thermal conductivity). This property is combined with sufficient mechanical and chemical resistance as well as integration into existing manufacturing processes.
  • Materials which have the required properties are in particular copper (Cu), silver (Ag), aluminum (Al) and gold (Au) or alloys with the respective main constituent of these materials (claims 10 to 13).
  • cover layers which have a high thermal conductivity (thermal conductivitiy) for discharging the heat energy generated in the semiconductor chip (claim 14).
  • the application of the semiconductor chip on the flange is preferably carried out by soldering; Adhesive methods are also possible here.
  • the mediating layer is hereby tuned to commercially available solders or adhesives and ensures the cohesion of the composite of semiconductor chip and flange.
  • the network layer may e.g. nickel (Ni), gold (Au) or a nickel-gold (NiAu) alloy. Alloys with the main constituent of one of the abovementioned materials can also be used here (claims 16 to 18).
  • multiple layers built up of two or three partial layers, are used as the switching layer.
  • nickel or a nickel-cobalt (NiCo) alloy is used as the first part-layer.
  • NiCo nickel-cobalt
  • second sub-layer one uses eg silver (Ag), gold (Au), Palladium (Pd), non-ferrous phosphorus (NiP) or palladium-nickel (PdNi).
  • the composite of these partial layers fulfills the task of a diffusion barrier and on the other serves as a mechanical buffer layer.
  • undesirable intermetallic phases eg Cu in Au-Si compound
  • the selected sub-layer sequence is resistant to corrosion, in particular resistant to organic soiling.
  • the third sublayer e.g. Gold (Au) are applied to provide additional protection against corrosion while providing the best possible chip and wire bondability (claim 19).
  • Au Gold
  • the network layer is applied on both sides to both the lower and the upper cover layer. This gives a complete symmetry of the flange, which causes distortions, e.g. the unwanted bimetallic effect, largely minimized.
  • the thickness of the cover layer is freely adjustable over an almost arbitrary layer thickness range.
  • Li ⁇ mit michmaschineen exist to thin layers only by physi ⁇ cal limits, which are given here in particular by the Grundla ⁇ conditions of the layer growth (epitaxy). Limitations to thick layers exist in practice only by the process time, which can be provided economically for the growth of the layer in the existing manufacturing process.
  • Heatsink is the layer thickness of Cover layer preferably selected in the range 10 ⁇ m to 500 ⁇ m (claim 21).
  • Fig. 2 based on a component cross-section (extract), a first embodiment of a flange according to the invention.
  • FIG. 1 compares a method for producing a ternary flange according to the prior art (a) with an embodiment of the method (b) according to the invention.
  • the flange consists of a flange core made of copper-molybdenum (CuMo) alloy, to which a cover layer of copper (Cu) is applied on both sides by rolling.
  • CuMo copper-molybdenum
  • step S1 After providing a molybdenum (Mo) powder (step S1), it is filled into a mold (step S2). The filled mold is sintered (step S3) and subsequently infiltrated with Cu (step S4). This is followed by rolling of the resulting flange core (step S5). On the ge ⁇ rolled flange copper (Cu) is deposited by plating both sides. The plating takes place by hot rolling (Step S6). The ternary flange blank is then tempered for the purpose of reducing the mechanical stresses introduced in the sixth step (step S7). This is followed by another rolling operation (step S8), followed by flattening (step S9) in order to smooth the flange blank and to largely minimize its surface roughness.
  • Mo molybdenum
  • step S10 the blank is tempered a further time.
  • the blank is now prepared by cutting to the punching of the individual flanges (step Sil). Subsequently, the individual flanges are punched to the desired level (step S12) and pressed (step S13) to correct the bending introduced during punching.
  • step S14 a third annealing step to again reduce the stresses introduced into the flange.
  • step Sl After providing a tungsten (W) powder (step Sl '), it is filled into a mold (step S2').
  • the filled mold is sintered (step S3 ') and then infiltrated with Cu (step S4').
  • step S5 ' While the prior art would follow standard metallurgical processes (eg, rolling), the present flange core is now wobbled (step S5 '), which is understood to mean deburring in a rotating drum.
  • step S6 ' lapping
  • step S7' grinding of the flange core in order to achieve the required surface properties, esp. a sufficiently low surface roughness, which is required for further flange production.
  • step S8 ' After a further walkthrough (step S8 '), the flange core is now pressed on both sides by a deposition process (eg CVD, PVD electroplating). Method) copper (Cu) applied (step S9 '). Since the deposition takes place-in contrast to conventional shaping processes-largely stress-free, further steps for reducing mechanical stresses are not required.
  • a deposition process eg CVD, PVD electroplating.
  • Cu copper
  • the comparison further shows that the coating of flange cores by deposition processes is possible in fewer process steps with at the same time less distortion and greater degree of freedom with regard to the choice of the respective layer thickness.
  • Fig. 2 shows an embodiment of a device according to the invention.
  • the flange core A consists for example of copper-tungsten (CuW) or copper-molybdenum (CuMo) alloy.
  • the cover layers Bl and B2 consist for example of copper (Cu), silver (Ag), aluminum (Al) or gold (Au).
  • the interface between both A and Bl as well as between A and B2 is due to the manufacture largely thermomechanically stress-free.
  • an upper (C1) and a lower (C2) network layer were furthermore applied in each case. An improved connection with the material to a semiconductor chip fixing S is made possible by the upper network layer C1.
  • the second network layer C2 brings about a complete symmetry of the flange, which largely precludes the possibility of a thermomechanical bending perpendicular to the flange plane.
  • Typical materials for the mediating layer are, for example, nickel (Ni) or gold (Au).
  • Ni nickel
  • Au gold
  • For applying a semiconductor chip (Ch) to the flange all commercially available solders or adhesives are suitable as material for the fixation S.
  • the choice of materials for combining laminate flanges becomes obvious when comparing the thermal conductivity (TC) and thermal coefficient coefficients (CTE) coefficients (Table 1).

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un collet composé d'au moins trois couches, destiné à recevoir une puce à semiconducteurs. Ledit collet est fabriqué par application d'une couche de couverture métallique supérieure et d'une couche de couverture métallique inférieure sur un noyau de collet composé d'un premier matériau, au moyen d'un procédé de dépôt, afin de réduire les contraintes thermomécaniques à l'intérieur du collet.
PCT/DE2005/001723 2004-09-30 2005-09-28 Procede de fabrication d'un collet destine a un composant a semiconducteurs et collet ainsi fabrique WO2006034697A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200410047659 DE102004047659A1 (de) 2004-09-30 2004-09-30 Verfahren zur Herstellung eines Flansches für ein Halbleiterbauelement sowie nach diesem Verfahren hergestellter Flansch
DE102004047659.4 2004-09-30

Publications (1)

Publication Number Publication Date
WO2006034697A1 true WO2006034697A1 (fr) 2006-04-06

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ID=35510998

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2005/001723 WO2006034697A1 (fr) 2004-09-30 2005-09-28 Procede de fabrication d'un collet destine a un composant a semiconducteurs et collet ainsi fabrique

Country Status (2)

Country Link
DE (1) DE102004047659A1 (fr)
WO (1) WO2006034697A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2188194A (en) * 1986-03-21 1987-09-23 Plessey Co Plc Carrier for high frequency integrated circuits
EP0386459A1 (fr) * 1989-03-04 1990-09-12 Oerlikon-Contraves AG Méthode pour fabriquer des circuits imprimés à couches minces
JPH07122678A (ja) * 1993-10-21 1995-05-12 Ngk Spark Plug Co Ltd 半導体セラミック容器本体
US5814880A (en) * 1989-12-22 1998-09-29 Northrop Grumman Corporation Thick film copper metallization for microwave power transistor packages
US6107638A (en) * 1997-03-14 2000-08-22 Kabushiki Kaisha Toshiba Silicon nitride circuit substrate and semiconductor device containing same
US6261868B1 (en) * 1999-04-02 2001-07-17 Motorola, Inc. Semiconductor component and method for manufacturing the semiconductor component
DE10310646A1 (de) * 2002-03-22 2003-10-16 Plansee Gmbh Package mit Substrat hoher Wärmeleitfähigkeit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2188194A (en) * 1986-03-21 1987-09-23 Plessey Co Plc Carrier for high frequency integrated circuits
EP0386459A1 (fr) * 1989-03-04 1990-09-12 Oerlikon-Contraves AG Méthode pour fabriquer des circuits imprimés à couches minces
US5814880A (en) * 1989-12-22 1998-09-29 Northrop Grumman Corporation Thick film copper metallization for microwave power transistor packages
JPH07122678A (ja) * 1993-10-21 1995-05-12 Ngk Spark Plug Co Ltd 半導体セラミック容器本体
US6107638A (en) * 1997-03-14 2000-08-22 Kabushiki Kaisha Toshiba Silicon nitride circuit substrate and semiconductor device containing same
US6261868B1 (en) * 1999-04-02 2001-07-17 Motorola, Inc. Semiconductor component and method for manufacturing the semiconductor component
DE10310646A1 (de) * 2002-03-22 2003-10-16 Plansee Gmbh Package mit Substrat hoher Wärmeleitfähigkeit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 08 29 September 1995 (1995-09-29) *

Also Published As

Publication number Publication date
DE102004047659A1 (de) 2006-04-13

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