WO2006034697A1

WO2006034697A1 - Method for producing a flange for a semiconductor component, and flange produced according to said method

Info

Publication number: WO2006034697A1
Application number: PCT/DE2005/001723
Authority: WO
Inventors: Jochen Dangelmaier; Volker GÜNGERICH; Stefan Paulus
Original assignee: Infineon Technologies Ag
Priority date: 2004-09-30
Filing date: 2005-09-28
Publication date: 2006-04-06
Also published as: DE102004047659A1

Abstract

The invention relates to a flange consisting of at least three layers and used to receive a semiconductor chip. Said flange is produced by applying both an upper and a lower metallic covering layer to a flange core consisting of a first material, by means of a deposition method, in order to reduce the thermomechanical stresses inside the flange.

Description

Method for producing a flange for a semiconductor component as well as a flange produced by this method

The present invention relates to a method for the production of a flange for a semiconductor component according to the preamble of patent claim 1 and to a flange produced by the method according to claim 20.

In order to provide the housing of an integrated semiconductor component, it is necessary to provide materials with a high thermal conductivity (TC), whereby at the same time the thermal expansion coefficient (CTE) of these materials is as large as possible should be adapted to those of the semicon terchips of the semiconductor device. As a result, damage to the semiconductor chip due to mechanical stresses can be avoided in the production process and the probability of failure can be reduced during later operation. Particularly in the case of power semiconductor components, the thermal adaptation of the housing to the semiconductor material is of crucial importance. In order to optimize the dissipation of heat from the semiconductor chip to the environment, flanges are used as substrates. Flange here is to be understood as meaning a substrate which is at least partially constructed from metallic materials. A typical semiconductor device in which a flange is used as the substrate is known e.g. an RF transistor.

Such a component is known from US Pat. No. 6,261,868 B1. Copper (Cu), alloys of copper and tungsten (W) or alloys of copper and molybdenum (Mo) are used here as the flange material. Furthermore, laminates of the aforementioned materials are used. As a result, first materials with suitable thermal expansion coefficients with second materials having suitable heat conductivity can be used be suitably combined to optimize the overall thermomechanical flanging properties. Such laminate flanges have been produced by roller cladding for a long time, as is known, for example, from DE 103 10 646 A1. Due to a rolling texture, a mechanical prestress is introduced into the flange by this type of production, which in the further production process and / or operating state can damage or even destroy the semiconductor component by thermomechanically induced cracking. Furthermore, a minimum thickness of the layers to be laminated is predetermined by the use of rolling processes, which must not be exceeded. A Miniaturisie¬ tion, in particular a minimization of the flange thickness, is therefore very difficult.

It is an object of the present invention to provide an easily durch¬ feasible method for producing a thermomechanically stable and in the thermal properties terchip adapted to the Halblei¬ terchip flange with a small thickness and a flange produced by this method available.

According to the invention, this object is achieved by a method which comprises the features of claim 1 and by a flange having the features of patent claim 20. Advantageous embodiments of the invention are indicated by the features of the subclaims.

As a base material of the flange, as a so-called flange core, in this case, for example, a thin plate is used, consisting for example of a copper-tungsten alloy (CuW), a copper-molybdenum alloy (CuMo) or ceramic (eg beryllium (BeO)). These materials are inexpensive and relatively easy to manufacture. On both sides of the flange core, a thermally highly conductive metallic layer, the so-called cover layer, can be produced by PVD (physical vapor deposition) or CVD (chemical vapor deposition). drive or wer¬ applied by means of galvanic Abscheidüng. This highly conductive layer may consist, for example, of copper (Cu), silver (Ag), gold (Au) or aluminum (Al).

As a result, one obtains a three-layered, i. ternary, flange.

In a preferred embodiment of the invention, a PVD method for depositing the cover layer on the flange core is used (claim 2). This is e.g. realized by vapor deposition of the second material, which may be highly thermally conductive (claim 3). Both thermal and electron beam vapor deposition methods are suitable here. The latter method is preferably suitable for high-melting materials which are to be applied simultaneously to the substrate at a high deposition rate.

In a further embodiment, the PVD method can be realized by cathode sputtering (so-called sputtering) of the material to be applied (claim 4). Especially with low requirements on the deposition rate, both the structure and the stoichiometry of the covering layer to be applied can be well controlled in this process.

As an alternative to PVD methods, the CVD technology often used elsewhere in semiconductor processing technology can also be used to produce the cover layer (claim 5).

A production of the cover layer by means of electrodeposition (claim 6) has the advantage that, in particular, in comparison to other PVD processes, on the one hand no vacuum conditions are required and, on the other hand, the coating of the flange core at a relatively high coating rate of both Pages can be made. Prerequisite for the use of the galvanic deposition method is that the flange core material is an electrically conductive material.

To produce thermally highly loadable flanges, the preferred flange core is ceramics, e.g. Berylli¬ oxide (claim 7).

In order to achieve the desired effect, it is unwe¬ stlich whether the flanges are produced individually, or whether a semi-finished product is first created, which is later isolated in indi¬ viduelle flanges.

In order to minimize the thermo-mechanical stresses between the flange and the semiconductor chip, the thermal expansion coefficient (CTE) of the flange core is adapted as far as possible to that of the semiconductor chip. Due to the generally dominant layer thickness of the flange core in the later semiconductor device, this adaptation is of particular importance. For this purpose, metals or metal alloys of copper, for example, CuW or CuMo alloys. When using copper-molybdenum cores, it has proven to be particularly advantageous to choose the molybdenum content between 50 and 85 percent by weight (wt%). Here, the thermal expansion coefficient (CTE) is adjustable between 11.5 and 7.1 x 10 ^{~ 6} -. When using copper tungsten cores, it has proved to be particularly advantageous to choose the tungsten content between 75 and 95 percent by weight (wt%). Thereby, a thermal expansion coefficient (CTE) between 9.0 and 6.4 x 10 ^{~ 6} - can be achieved (claim 8). K

In addition to the explicitly mentioned examples, all further materials are suitable as the flange core, which have a thermal expansion coefficient (CTE) which is sufficiently similar to the semiconductor chip (claim 9). The selection of the cover layer material is essentially based on the criteria of maximizing the thermal conductivity (thermal conductivity). This property is combined with sufficient mechanical and chemical resistance as well as integration into existing manufacturing processes. Materials which have the required properties are in particular copper (Cu), silver (Ag), aluminum (Al) and gold (Au) or alloys with the respective main constituent of these materials (claims 10 to 13).

In addition to the explicitly mentioned examples, all further materials are suitable as cover layers, which have a high thermal conductivity (thermal conductivitiy) for discharging the heat energy generated in the semiconductor chip (claim 14).

In the further manufacturing process of the flange, it is advantageous to apply a further layer to the cover layer at least on one side, the so-called switching layer, which facilitates chip assembly (claim 15).

The application of the semiconductor chip on the flange (so-called diebonding) is preferably carried out by soldering; Adhesive methods are also possible here. The mediating layer is hereby tuned to commercially available solders or adhesives and ensures the cohesion of the composite of semiconductor chip and flange. The network layer may e.g. nickel (Ni), gold (Au) or a nickel-gold (NiAu) alloy. Alloys with the main constituent of one of the abovementioned materials can also be used here (claims 16 to 18).

Alternatively, multiple layers (multilayers), built up of two or three partial layers, are used as the switching layer. For example, nickel or a nickel-cobalt (NiCo) alloy is used as the first part-layer. As second sub-layer one uses eg silver (Ag), gold (Au), Palladium (Pd), non-ferrous phosphorus (NiP) or palladium-nickel (PdNi). On the one hand, the composite of these partial layers fulfills the task of a diffusion barrier and on the other serves as a mechanical buffer layer. Furthermore, the formation of undesirable intermetallic phases (eg Cu in Au-Si compound) is prevented and an adhesion improvement between the semiconductor chip and the flange is achieved. Finally, the selected sub-layer sequence is resistant to corrosion, in particular resistant to organic soiling.

Optionally, the third sublayer, e.g. Gold (Au), are applied to provide additional protection against corrosion while providing the best possible chip and wire bondability (claim 19).

For further thermomechanical optimization of the flange properties, in a preferred embodiment of the invention, the network layer is applied on both sides to both the lower and the upper cover layer. This gives a complete symmetry of the flange, which causes distortions, e.g. the unwanted bimetallic effect, largely minimized.

It is particularly advantageous in the method according to the invention that the thickness of the cover layer is freely adjustable over an almost arbitrary layer thickness range. Li¬ mitierungen exist to thin layers only by physi¬ cal limits, which are given here in particular by the Grundla¬ conditions of the layer growth (epitaxy). Limitations to thick layers exist in practice only by the process time, which can be provided economically for the growth of the layer in the existing manufacturing process. To ensure functionality as a heat conductor and heat sink. (Heatsink) is the layer thickness of Cover layer preferably selected in the range 10 μm to 500 μm (claim 21).

The invention will now be described with reference to the accompanying drawings. Show it:

Fig. 1, the essential steps of the invention

Method in direct comparison to the steps in a method according to the prior art and

Fig. 2 based on a component cross-section (extract), a first embodiment of a flange according to the invention.

In the figures, the same reference numerals designate the same or functionally identical elements.

FIG. 1 compares a method for producing a ternary flange according to the prior art (a) with an embodiment of the method (b) according to the invention.

Hereinafter, the prior art method is explained in detail with reference to the production of a commercially available ternary Cu / CuMo / Cu flange (a). The flange consists of a flange core made of copper-molybdenum (CuMo) alloy, to which a cover layer of copper (Cu) is applied on both sides by rolling.

The process steps in detail:

After providing a molybdenum (Mo) powder (step S1), it is filled into a mold (step S2). The filled mold is sintered (step S3) and subsequently infiltrated with Cu (step S4). This is followed by rolling of the resulting flange core (step S5). On the ge ^¬ rolled flange copper (Cu) is deposited by plating both sides. The plating takes place by hot rolling (Step S6). The ternary flange blank is then tempered for the purpose of reducing the mechanical stresses introduced in the sixth step (step S7). This is followed by another rolling operation (step S8), followed by flattening (step S9) in order to smooth the flange blank and to largely minimize its surface roughness. To further reduce the mechanical stresses, the blank is tempered a further time (step S10). The blank is now prepared by cutting to the punching of the individual flanges (step Sil). Subsequently, the individual flanges are punched to the desired level (step S12) and pressed (step S13) to correct the bending introduced during punching. The final process step is followed by a third annealing step (step S14) to again reduce the stresses introduced into the flange.

The process according to the invention will now be explained with reference to the preparation of a ternary Cu / CuW / Cu flange (b). Copper is applied to a flange core of copper-tungsten (CuW) alloy on both sides by a deposition process.

The process steps in detail:

After providing a tungsten (W) powder (step Sl '), it is filled into a mold (step S2'). The filled mold is sintered (step S3 ') and then infiltrated with Cu (step S4'). While the prior art would follow standard metallurgical processes (eg, rolling), the present flange core is now wobbled (step S5 '), which is understood to mean deburring in a rotating drum. This is followed by lapping (step S6 ') and grinding (step S7') of the flange core in order to achieve the required surface properties, esp. a sufficiently low surface roughness, which is required for further flange production. After a further walkthrough (step S8 '), the flange core is now pressed on both sides by a deposition process (eg CVD, PVD electroplating). Method) copper (Cu) applied (step S9 '). Since the deposition takes place-in contrast to conventional shaping processes-largely stress-free, further steps for reducing mechanical stresses are not required.

While a total of 14 steps for producing the flange are required according to the prior art, the method according to the invention requires only 9 steps.

The comparison further shows that the coating of flange cores by deposition processes is possible in fewer process steps with at the same time less distortion and greater degree of freedom with regard to the choice of the respective layer thickness.

Fig. 2 shows an embodiment of a device according to the invention. On the flange core A is ever an upper (Bl) and a lower (Bl) cover layer. The flange core A consists for example of copper-tungsten (CuW) or copper-molybdenum (CuMo) alloy. The cover layers Bl and B2 consist for example of copper (Cu), silver (Ag), aluminum (Al) or gold (Au). The interface between both A and Bl as well as between A and B2 is due to the manufacture largely thermomechanically stress-free. In the present exemplary embodiment, an upper (C1) and a lower (C2) network layer were furthermore applied in each case. An improved connection with the material to a semiconductor chip fixing S is made possible by the upper network layer C1. The second network layer C2 brings about a complete symmetry of the flange, which largely precludes the possibility of a thermomechanical bending perpendicular to the flange plane. Typical materials for the mediating layer are, for example, nickel (Ni) or gold (Au). For applying a semiconductor chip (Ch) to the flange, all commercially available solders or adhesives are suitable as material for the fixation S. The choice of materials for combining laminate flanges becomes obvious when comparing the thermal conductivity (TC) and thermal coefficient coefficients (CTE) coefficients (Table 1).

Tab. 1

While pure copper (Cu) has a particularly high thermal conductivity and is therefore recommended as a cover layer material, it is due to the relatively high thermal expansion, which is about four times as high at 100 ° C as that of silicon (Si), As flange core material largely unsuitable.

LIST OF REFERENCE NUMBERS

A flange core

Bi upper cover layer

B ₂ Lower cover layer

Ci Upper network layer

C ₂ Lower network layer

S material for fixing the semiconductor chip

Ch semiconductor chip

Claims

claims

A method of fabricating a ternary flange for receiving a semiconductor chip for a semiconductor device, wherein both top (Bl) and bottom (B2) cover layers of a second metallic material are applied to a flange core (A) of a first material , characterized in that the second metallic material is applied to the first material by deposition.

2. The method according to claim 1, characterized in that the deposition takes place after a PVD process.

3. The method of claim 2, wherein: the PVD process is a vapor deposition process.

4. The method of claim 2, wherein: the PVD process is a sputtering process.

5. The method according to claim 1, characterized in that the deposition takes place after a CVD process.

6. The method according to claim 1, characterized in that the deposition takes place galvanically.

7. Method according to one of the preceding claims, characterized in that a ceramic, in particular beryllium oxide, is selected as the first material.

8. The method according to any one of claims 1 to 6, characterized in that the first material is a copper alloy, in particular

Copper tungsten or copper molybdenum, is selected.

9. The method according to claim 1, wherein the thermal expansion coefficient (CTE) of the first material is at least substantially equal to the thermal expansion coefficient (CTE) of the semiconductor chip.

10. The method according to any one of the preceding claims, d a d u r c h e c e n e c h e s in that as the second, metallic material copper or an alloy with the main component of copper is selected.

11. Method according to one of the preceding claims, characterized in that silver or an alloy having the main constituent silver is selected as the second metallic material.

12. Method according to one of the preceding claims, characterized in that aluminum or an alloy with the main constituent aluminum is selected as the second, metallic material.

13. Method according to one of the preceding claims, characterized in that gold or a alloy having the main constituent gold is selected as the second metallic material.

14. Method according to one of the preceding claims, characterized in that the second, metallic material is thermally highly conductive.

15. The method according to any one of the preceding claims, characterized a further layer (Cl) is applied to the cover layer on at least one side to improve chip mounting.

16. The method according to claim 15, wherein a further layer (Cl) is nickel or an alloy with the main constituent nickel is selected.

17. The method according to claim 15, wherein a further layer (Cl) is selected from gold or an alloy with the main constituent gold.

18. The method according to claim 15, characterized in that a nickel-gold alloy is selected as the further layer (C1).

19. The method according to claim 15, wherein as a further layer (Cl) a multilayer layer is selected, wherein as at least one of the multilayer auf¬ substructive layer nickel or an alloy with the main component nickel is selected.

20. Method according to one of the preceding claims, characterized in that the flange core (1) is ground or lapped before the application of the second metallic material.

21. A flange for semiconductor device, produced by a method according to any one of the preceding claims.

22. Flange according to claim 21, characterized the layer thickness of the second, metallic material is about 10 μm to 500 μm.