WO2006013675A1 - パイプラインadc開発方法、パイプラインadc開発装置、パイプラインadc開発プログラム、及び記録媒体 - Google Patents
パイプラインadc開発方法、パイプラインadc開発装置、パイプラインadc開発プログラム、及び記録媒体 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/004—Reconfigurable analogue/digital or digital/analogue converters
- H03M1/007—Reconfigurable analogue/digital or digital/analogue converters among different resolutions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
Definitions
- the present invention relates to a pipeline ADC (Analog Digital Converter) development method, and in particular, a developer only needs to input ADC specifications to select an optimal ADC architecture and sub-block circuit configuration. It relates to a method of developing a pipeline ADC that can be performed automatically.
- ADC Analog Digital Converter
- FIGS. 9B and 9C are flowcharts illustrating the layout creation processing of the pipeline ADC using the pipeline ADC development apparatus of FIG. 9A.
- the developer first sets the bit configuration of the analog-digital conversion circuit based on the specification 301 including the required number of bits.
- the required capacity value 302 of the operational amplifier at each stage for which the number of bits and the architecture power are also determined is input from the input device 503 to the layout creating device 500.
- the CPU 501 of the layout creation device 500 determines the feedback capacitance value of each stage operational amplifier based on the determined architecture and the input required capacity value 302 of each stage operational amplifier! (Step S112).
- CPU 501 of layout creating apparatus 500 determines specification 304 including the circuit area and circuit shape of each stage after determining the value of feedback capacitance (step S113). As a result, the data 303 of the circuit area and circuit shape of each stage is obtained.
- the developer inputs a specification 304 including the entire circuit area and circuit shape of the analog-digital conversion circuit to the layout creating apparatus 500.
- the CPU 501 of the layout creation device 500 is based on the circuit area and circuit shape data 303 of each stage and the specification 304.
- the circuit arrangement in each stage is selected by selecting one of the layouts 315 of the plurality of types of modules prepared as the stage library 313 (step S114).
- CPU 501 of layout creation apparatus 500 determines the arrangement of modules at each stage selected based on the bit configuration (step S115).
- the CPU 501 of the layout creation device 500 extracts the load capacity of the operational amplifier at each stage of the analog-digital conversion circuit based on the selected layout 315 (step S116). As a result, the load capacity information 305 is obtained.
- the developer uses the input device 503 to input the required specifications 306 for the operational amplifier such as the slew rate and the maximum operating frequency.
- the CPU 501 of the layout creation device 500 selects the circuit configuration of the operational amplifier based on the load capacity information 305 and the input required specification 306 and determines the noise current of the operational amplifier. (Step S117).
- the developer inputs the relationship 307 between the bias current of the operational amplifier, the predetermined magnification (shrink rate), and the bias current of the bias generation circuit to the layout generation device 500 using the input device 503.
- the predetermined magnification is a magnification when a plurality of types of layouts are created by uniformly reducing or enlarging channel widths (gate widths) of a plurality of transistors constituting an operational amplifier.
- the CPU 501 of the layout creation device 500 uses a plurality of layouts prepared as the operational amplifier library 309 so as to satisfy the bias current of the operational amplifier determined in step S117 based on the input relation 307.
- a layout 311 having a predetermined magnification is selected from 311 and a noise current (bias voltage) of the bias generation circuit is determined (step S118).
- the developer uses the input device 503 to obtain device information 308 such as a power supply voltage, a load capacity, an input signal and other usage environment, and characteristics of transistors constituting the operational amplifier. Enter 500.
- device information 308 such as a power supply voltage, a load capacity, an input signal and other usage environment, and characteristics of transistors constituting the operational amplifier. Enter 500.
- the CPU 501 of the layout creation device 500 is selected in step S 118 using the input usage environment, the device information 308, the netlist 310 prepared as the operational amplifier library 309, and the analog function description language. 311 simulation (Step SI 19).
- the CPU 501 performs a simulation using the circuit simulator 312. If the simulation result does not satisfy the required specification (NO in step S120), the process returns to step S117, and CPU 501 again determines the bias current of the operational amplifier. Thereafter, the processes in steps S117 to S120 are repeated until the simulation result satisfies the required specifications.
- the CPU 501 of the layout creation device 500 uses the netlist prepared as the operating environment, device information 308, and operational amplifier library 309.
- the entire analog-digital conversion circuit is simulated using 310, the netlist 314 prepared as the stage library 313, and the analog function description language (step S121).
- the CPU 501 performs simulation using the circuit simulators 312 and 316.
- an analog function description language is used. Therefore, parameters of the analog function description language model are extracted from the netlist 314.
- step S 122 If the simulation does not satisfy the required specifications (NO in step S 122), the process returns to step S 117 and CPU 501 again determines the operational amplifier bias current. Thereafter, the processing of steps 3117 to 3120 is repeated until the simulation result satisfies the required specifications.
- the module layout 315 of each stage is generated as a stage library 313 (step S123). Thereafter, the generated layout 315 is used to output the entire layout of the analog-digital conversion circuit to the screen of the display 502 and the like, and save it in the external storage device 507 (step S124).
- the layout creating apparatus 500 shown in FIG. 9A can automatically create the layout of the analog-to-digital conversion circuit.
- Patent Document 1 Japanese Patent Laid-Open No. 2002-223165 (pages 10-11, 5, 7, 8) Disclosure of the Invention Problems to be solved by the invention
- the present invention has been made in view of the conventional problems as described above, and a developer only has to input ADC specifications, and select an optimal ADC architecture and circuit configuration of sub-blocks.
- the purpose is to provide a medium.
- the pipeline ADC development method is a specification fetching process for fetching the specifications of the pipeline ADC to be developed, and evaluating the fetched specifications.
- the architecture selection step for selecting the circuit diagram data of the architecture according to the evaluation result of the evaluation step from the circuit diagram data of the plurality of architectures stored in the database, and the sub-block stored in the database
- a circuit configuration selection step of selecting circuit diagram data of a circuit constituting a sub-block according to an evaluation result of the evaluation step from a plurality of circuit diagram data of the circuit to be configured. is there.
- the pipeline ADC development method according to claim 2 of the present invention is the pipeline ADC development method according to claim 1, wherein the evaluation step is performed for each condition of the captured specification.
- a step of setting a required level, the imported specification, and the key Based on the architecture selected in the architecture selection step, calculating a required performance for each circuit constituting the sub-block, and setting a required level of the condition for each of the calculated required performance conditions
- the required level set for each required performance condition of each circuit in the circuit configuration selecting step The circuit diagram data of the circuit composing the sub-block corresponding to is selected.
- the pipeline ADC development method according to claim 3 of the present invention is the pipeline ADC development method according to claim 2, wherein the sub-block includes a gain amplifier, a comparator, and a DAC. It is characterized by comprising.
- a pipeline ADC development method is the pipeline ADC development method according to any one of claims 1 to 3, wherein the architecture selection step includes: An estimation process for estimating the performance achieved by the selected circuit diagram data based on the circuit diagram data of the selected architecture and the circuit diagram data of the circuit constituting the sub-block selected in the circuit configuration selection process. And a determination step for determining whether the estimated performance satisfies all the conditions of the specification, and when the conditions of the specification not satisfied by the determination step are detected, the evaluation The process is re-evaluated by the process, and the architecture selection process and the circuit configuration selection process are executed again.
- the pipeline ADC development apparatus includes a specification fetching section for fetching the specifications of the pipeline ADC to be developed, an evaluation section for evaluating the fetched specifications, and a database.
- An architecture selection unit that selects circuit diagram data corresponding to the evaluation result of the evaluation unit from a plurality of circuit diagram data stored in the architecture, and a plurality of circuits that constitute sub-blocks stored in the database
- a circuit configuration selection unit that selects circuit diagram data corresponding to the evaluation result in the evaluation unit from the diagram data.
- the pipeline ADC development device is the pipeline ADC development device according to claim 5, wherein the evaluation unit includes the condition of the captured specification. Based on the first requirement level setting unit that sets the required level of the condition for each case, the imported specification, and the architecture selected by the architecture selection unit, the required performance for each circuit that constitutes the sub-block And a second required level setting unit for setting a required level of the condition for each of the calculated required performance conditions.
- the architecture selecting unit is configured to include the first block level calculating unit.
- the required level setting unit selects the circuit diagram data of the architecture corresponding to the required level set for each condition of the specification, and the second required level setting unit determines the required performance for each circuit.
- the circuit diagram data of the circuit constituting the sub-block corresponding to the required level set for each condition is selected.
- the pipeline ADC development device is the pipeline ADC development device according to claim 6, wherein the sub-block includes a gain amplifier, a comparator, and a DAC. It is characterized by comprising.
- the pipeline ADC development device is the pipeline ADC development device according to any one of claims 5 to 7, wherein the architecture selected by the architecture selection unit is selected.
- the estimation unit for estimating the performance achieved by the selected circuit diagram data and the estimation A determination unit that determines whether the performance meets all the conditions of the specification, and when the condition of the specification that is not satisfied by the determination unit is detected, the evaluation unit re-evaluates the condition.
- the circuit diagram data of the architecture and the circuit diagram data of the circuits constituting the sub-block are selected again.
- the noopline ADC development program includes a specification fetching process for fetching the specifications of the nopline ADC to be developed into a computer, and an evaluation process for evaluating the fetched specifications. And an architecture selection step for selecting circuit diagram data corresponding to the evaluation result of the evaluation step from circuit diagram data of a plurality of architectures stored in the database, and a plurality of circuits constituting sub-blocks stored in the database. And a circuit configuration selection step of selecting circuit diagram data corresponding to the evaluation result of the evaluation step from the circuit diagram data.
- the pipeline ADC development program according to claim 10 of the present invention is the pipeline ADC development program according to claim 9, wherein the evaluation process is performed by the computer for each condition of the fetched specification.
- a step of setting a required level of the condition a step of calculating a required performance for each circuit constituting the sub-block based on the captured specification and the architecture selected in the architecture selection step, and the calculated And a step of setting a required level of each condition for each required performance condition.
- the architecture selection step the circuit diagram data of the architecture corresponding to the required level set for each condition of the specification is selected.
- the circuit configuration selection step the circuit that configures the sub-block corresponding to the required level set for each required performance condition of each circuit. To select the road map data, it is characterized in.
- the pipeline ADC development program according to claim 11 of the present invention is the pipeline ADC development program according to claim 9 or claim 10, wherein the architecture of the architecture selected in the architecture selection step is stored in a computer.
- the estimation step for estimating the performance achieved by the selected circuit diagram data and the above estimation A determination step for determining whether or not the performance satisfies all the conditions of the specification, and when a condition of the specification that is not satisfied by the determination step is detected, the evaluation step Re-evaluation is performed, and the architecture selection step and the circuit configuration selection step are executed again. It is.
- a computer-readable recording medium recording the pipeline ADC development program according to claim 12 of the present invention includes a specification fetching process for fetching the specifications of the pipeline ADC to be developed into the computer, An evaluation process for evaluating the imported specifications, an architecture selection process for selecting circuit diagram data corresponding to the evaluation result of the evaluation process from circuit diagram data of a plurality of architectures stored in the database, and a database stored in the database And a circuit configuration selection step of selecting circuit diagram data corresponding to the evaluation result of the evaluation step from a plurality of circuit diagram data of the circuits constituting the sub-block.
- a computer-readable recording medium according to claim 12 wherein in the recording medium according to claim 12, as the evaluation step, a step of setting a required level of the condition for each condition of the captured specification and the capturing Based on the specifications and the architecture selected in the architecture selection step, the required level of the condition is calculated for each step of calculating the required performance for each circuit constituting the sub-block and the calculated required performance condition.
- the circuit diagram data of the architecture corresponding to the required level set for each condition of the specification is selected in the architecture selection step, and then each circuit is selected in the circuit configuration selection step. Select the circuit diagram data of the circuits that make up the sub-prox according to the required level set for each required performance condition. That.
- a computer-readable recording medium in which the pipeline ADC development program according to claim 14 of the present invention is recorded is the recording medium according to claim 12 or 13, wherein the computer Based on the circuit diagram data of the architecture selected in the architecture selection step and the circuit diagram data of the circuit constituting the sub-block selected in the circuit configuration selection step, the performance achieved by the selected circuit diagram data is estimated.
- the condition is reevaluated by the evaluation step, and the architecture selection step and the circuit configuration selection step are executed again. Thereby, it is the Chi to feature that.
- the evaluation unit evaluates the specifications input by the developer using the evaluation unit, and then uses the circuit diagram data of a plurality of architectures stored in the architecture selection unit database. And selecting circuit diagram data corresponding to the evaluation result of the evaluation unit, and the circuit configuration selection unit from the plurality of circuit diagram data of the circuits constituting the sub-block stored in the database, the evaluation result of the evaluation unit
- the developer can automatically select the ADC architecture and sub-block circuit configuration simply by inputting the ADC specifications. It is possible to achieve the effect of realizing short-term development and high-quality design.
- the architecture selecting unit and the circuit configuration selecting unit include circuit diagram data of the architecture corresponding to the evaluation result of the specification and a sub block corresponding to the evaluation result of the specification.
- the performance achieved by this is estimated based on the circuit diagram data. Therefore, if the estimated performance meets all the conditions of the specifications, and if the conditions of the specifications are not met, re-evaluate the conditions of the unsatisfied specifications, and re-check the circuit of the architecture.
- By selecting diagram data and selecting circuit diagram data for the circuits that make up the block it is possible to automatically develop high-quality pipeline ADCs that meet the specifications specified by the developer. An effect that can be performed is obtained.
- FIG. 1 is a block diagram showing an example of the configuration of a pipeline ADC development device according to Embodiment 1 of the present invention.
- FIG. 2 shows an example of the configuration of a pipeline ADC developed by the pipeline ADC development apparatus according to Embodiment 1 of the present invention.
- FIG. 3 is a flowchart for explaining a pipeline ADC development method according to the first embodiment of the present invention.
- FIG. 4 is a flowchart for explaining a specific architecture selection process.
- FIG. 5 is a flowchart for explaining a specific process of selecting a gain amplifier.
- FIG. 6 is a flowchart for explaining a specific comparator selection process.
- FIG. 7 is a flowchart for explaining specific DAC selection processing.
- FIG. 8 is a flowchart for explaining the reselection process in step S9 of FIG.
- FIG. 9 (a) is a diagram showing a configuration of a conventional pipeline ADC development apparatus.
- FIG. 9 (b) is a flowchart for explaining a pipeline ADC layout creation process using the pipeline ADC development apparatus of FIG. 9 (a).
- FIG. 9 (c) is a flowchart illustrating a pipeline ADC layout creation process using the pipeline ADC development apparatus of FIG. 9 (a).
- FIG. 1 is a block diagram showing an example of the configuration of a pipeline ADC development device according to Embodiment 1 of the present invention.
- the pipeline ADC development apparatus includes a specification capturing unit 1, an evaluation unit 2, an architecture selection unit 3, a database 4, a circuit configuration selection unit 5, and a database. 6, an estimation unit 7, and a determination unit 8.
- the databases 4 and 6 may be provided outside the pipeline ADC development device. In this case, each database provided outside the pipeline ADC development device is assigned to the architecture selection unit 3.
- the circuit configuration selection unit 5 may be connected by wired or wireless communication means.
- the specification capture unit 1 captures the specifications of the Knipline ADC that is being developed, such as the resolution, conversion frequency, area, power consumption, and input range that the developer has entered using a keyboard or the like.
- the evaluation unit 2 evaluates the specifications captured by the specification capturing unit 1, and as illustrated, the first requirement level setting unit 2a, the sub-block performance calculation unit 2b, and the second And a required level setting unit 2c.
- the first required level setting unit 2a sets the required level for each condition of the specification depending on the architecture.
- the sub-block performance calculation unit 2b calculates the required performance for each circuit constituting the sub-block based on the fetched specifications and the architecture selected by the architecture selection unit 3. Further, the second required level setting unit 2c sets the required level of the condition for each required performance condition calculated by the sub-block performance calculating unit 2b.
- the conditions of the above specifications mean conditions such as resolution, conversion frequency, area, power consumption, and input range required for the pipeline ADC to be developed. In addition to a request for input from the developer in advance, it may be calculated based on information input by the developer.
- the required level means information ranked for each condition of the specification or the required performance based on a preset threshold value of 1 or 2 or more.
- the required performance for each circuit that constitutes a sub-block means the required performance required for each circuit that constitutes the sub-block.
- the required performance for each condition such as area and power consumption is Each is calculated.
- the architecture selection unit 3 selects an architecture according to the evaluation result made by the first request level setting unit 2a of the evaluation unit 2 from the database 4, and circuit diagram data of the selected architecture is obtained. Import from database 4.
- the database 4 is an architecture database that collects a plurality of circuit diagram data related to the pipeline ADC architecture to be selected by the architecture selector 3.
- the first requirement level setting unit 2a has the ability to explain what sets the requirement level for each condition depending on the architecture of the imported specification. Part 2a sets the required level for all conditions of the imported specifications, and from the set specification conditions, the architecture selection part 3 selects the specification conditions that depend on the architecture, and selects the architecture. Again, okay.
- the circuit configuration selection unit 5 selects from the database 6 the circuit configuration of each circuit constituting the sub-block according to the evaluation result made by the second required level setting unit 2c of the evaluation unit 2.
- the selected circuit diagram data is fetched from the database 6.
- the database 6 is a database obtained by collecting a plurality of circuit diagram data of each circuit constituting a sub-block for the circuit configuration selection unit 5 to select a circuit configuration from the circuit configuration selection unit 5.
- the estimation unit 7 estimates the performance achieved by the selected circuit diagram data based on the circuit diagram data selected and fetched by the architecture selection unit 3 and the circuit configuration selection unit 5. is there.
- the determination unit 8 determines whether the performance estimated by the estimation unit 7 satisfies all the conditions of the specification. At this time, when a condition of the specification that is not satisfied by the determination unit 8 is detected, the evaluation unit 2 re-evaluates the condition, and again, the architecture selection unit 3 selects the architecture, And the sub block by the circuit configuration selector 5 Selection of the circuit configuration of the circuits constituting the network.
- FIG. 2 shows an example of the configuration of a pipeline ADC developed by the pipeline ADC development apparatus according to Embodiment 1 of the present invention.
- the pipeline ADC is composed of four stages 22, 23, 24, 25 and a logic circuit 21.
- the first three stages 22, 23, 24 are each composed of gain amplifiers 11, 12, 13, comparators 14, 15, 16, and DACs 18, 19, 20, and the last stage 25 is a comparator. It consists of only 17!
- the pipeline ADC configured as described above first receives an analog input from the first stage 22 and performs nl-bit AD conversion by the comparator 14.
- the result of AD conversion performed by the comparator 14 is D / A converted by the DAC 18, converted back to an analog signal, and the analog input force is subtracted. This difference is amplified by Ml times with the gain amplifier 11 and sent to the next stage 23.
- analog signals are processed in the same manner as in stage 22, and sent to the next stages 24 and 25, respectively.
- the final stage 25 only n4-bit AD conversion by the comparator 17 is performed. Then, the nl-bit, n2-bit, n3-bit, and n4-bit digital values obtained by AD conversion at each stage are combined by the logic circuit 21 and output as the final digital output.
- the database 4 in FIG. 1 is adapted to the configuration of the pipeline ADC to be developed. And the following data in database 6 in advance
- the pipeline selection circuit 3 to be selected by the architecture selection unit 3, such as a calibration circuit, a shared amplifier, a multi-bit configuration, etc. prepare an architectural database that collects multiple schematic data related to the architecture.
- circuit diagram data of a plurality of gain amplifiers such as a source grounded amplifier, a cascode amplifier, a telescopic amplifier, a folded amplifier, a gain boost amplifier, a triple cascode amplifier, and a two-stage amplifier are collected.
- a database of comparators that collects the circuit diagram data of multiple comparators, such as 2-stage comparators, and a database of DACs that collects circuit diagram data of multiple DACs, such as capacitive array DACs and resistor string DACs And prepare.
- FIG. 3 is a flowchart for explaining the pipeline ADC development method according to the first embodiment of the present invention.
- the specification capture unit 1 captures the specifications of the pipeline ADC that is being developed, such as the resolution, conversion frequency, area, power consumption, and input range input by the developer. (Step S1), the captured specifications are output to the first required level setting unit 2a and the sub-block performance calculation unit 2b.
- the first request level setting unit 2a sets a request level for each condition depending on the architecture of the fetched specification (step S2), and outputs the request level to the architecture selection unit 3. .
- the architecture selection unit 3 Based on the requirement level set for each condition of the specification output from the first requirement level setting unit 2a, the architecture selection unit 3 satisfies all the requirement levels for each condition of the specification. Select the desired architecture from Database 4 and import the relevant schematic data (Step S3).
- the sub-block performance calculation unit 2b based on the specification fetched by the specification fetch unit 1 and the architecture selected by the architecture selector 3, the gain amplifier, comparator, Each of the DACs calculates the required performance (step S4), and outputs the calculated required performance for each circuit to the second required level setting unit 2.
- the required level is calculated for each required performance condition of the gain amplifier, the comparator, and the DAC calculated by the sub-block performance calculating unit 2b. Is set (step S5), and the set required level is output to the circuit configuration selection unit 5.
- the second required level setting unit 2c outputs, based on the required level set for each required performance condition of each circuit, for each required performance condition of each circuit.
- the circuit configurations of the gain amplifier, the comparator, and the DAC that satisfy all the set required levels are selected from the database 6 and the corresponding circuit diagram data is captured (step S6).
- the estimation unit 7 includes circuit diagram data of the architecture selected by the architecture selection unit 3, and circuit diagram data indicating the circuit configuration of the gain amplifier, the comparator, and the DAC selected by the circuit configuration selection unit 5. Based on the above, the performance achieved by the selected circuit diagram data is estimated (step S7).
- the determination unit 8 determines whether the developed pipeline ADC's sexual capability specification capture unit 1 satisfies the specifications captured by the specification. Judgment is made for each condition (step S8). If all the conditions of the specification are satisfied as a result of the determination, the circuit diagram data of the pipeline ADC is output and the process is terminated. On the other hand, if even one of the specification conditions is not met, go to step S9.
- Step S9 is performed, and the process of selecting the architecture or the circuit configuration of the circuit that constitutes the sub-block again is performed so that the developed pipeline ADC satisfies all the conditions of the specification.
- the developer can automatically select the pipeline ADC architecture and the circuit configuration of the circuits that make up the sub-blocks simply by inputting the pipeline ADC specifications. It is possible to achieve short-term development and high-quality design.
- FIG. 4 is a flowchart for explaining a specific architecture selection process.
- the first required level setting unit 2a of the evaluation unit 2 sets the required level in two stages, high and low, for each condition of the specification.
- the first requirement level setting unit 2a of the evaluation unit 2 determines whether the requirement level of the specification fetched by the specification fetching unit 1 is different for each architecture-dependent specification condition such as resolution, power consumption, and area. Judge whether “high” or “low” is based on the predetermined threshold value held by the second requirement level setting unit 2c, and set “high” or “low” as the required level for each specification condition. (Step S21).
- the first required level setting unit 2a of the evaluation unit 2 evaluates the required level of resolution, power consumption, and area.
- the architecture selection unit 3 detects the required level of resolution set by the first required level setting unit 2a (step S22), and if the required level of resolution is "high", The calibration circuit diagram data is taken from the architecture database 4 (step S23). If “low”, calibration is not adopted and the process proceeds to the next step.
- the architecture selection unit 3 detects the required level of power consumption set by the first required level setting unit 2a (step S24), and if the required level of power consumption is "high". For example, the circuit diagram data of the shared amplifier is taken from the architecture database 4 (step S25), and if it is “low”, the shared amplifier is not adopted and the process proceeds to the next step.
- the architecture selection unit 3 detects the required level of the area set by the first required level setting unit 2a (step S26), and if the required level of area is “high”, The multi-bit schematic data is taken from the architecture database 4 (step S28), and if low, the single-bit schematic data is taken from the architecture database 4 (step S27).
- FIG. 5 is a flowchart for explaining specific gain amplifier selection processing.
- the second required level setting unit 2c of the evaluation unit 2 sets the required level in two steps, high and low, for each required performance condition of the gain amplifier. explain about.
- the sub-block performance calculation unit 2b of the evaluation unit 2 calculates the required performance of the gain amplifier alone (step S31).
- the second required level setting unit 2c of the evaluation unit 2 includes the DC gain, output amplitude, UGF (utility gain frequency), area, power consumption, etc. calculated by the sub-block performance calculation unit 2b. For each of the performance requirements of the gain amplifier alone, determine whether the required level is “high” or “low” based on the predetermined threshold held by the second required level setting unit 2c. Set “High” or “Low” for each condition (step S32).
- the second required level setting unit 2c of the evaluation unit 2 evaluates the required level of DC gain, output amplitude, UGF (utility gain frequency), area, and power consumption of the gain amplifier alone. Shall be worthy.
- the circuit configuration selection unit 5 detects the DC gain request level set by the second request level setting unit 2c (step S33), and the DC gain request level is "high”. If there is, the process proceeds to step S41. If “low”, the process proceeds to step S34.
- step S34 the circuit configuration selection unit 5 detects the required output amplitude level set by the second required level setting unit 2c.
- the circuit diagram data of the old dead amplifier is fetched from the database 6 having the gain amplifier database (step S35), and the process is terminated. If it is “Low”, the folded amplifier is not adopted and the process proceeds to the next step S36.
- step S36 the circuit configuration selection unit 5 detects the UFG request level set by the second request level setting unit 2c, and if the UGF request level is "high", the circuit configuration selector 5 The circuit diagram data is fetched from the database 6 having the gain amplifier database (step S37), and the process is terminated. If it is “Low”, the telescopic amplifier is not used and the process proceeds to the next step S38.
- step S38 the circuit configuration selection unit 5 detects the required level of the area set by the second required level setting unit 2c. If the required level of area is “high”, the source grounding key The circuit diagram data of the amplifier is incorporated into the database with the gain amplifier database (step S39), and the process is terminated. If “low”, the circuit diagram data of the cascode amplifier is fetched from the database 6 having the database of the gain amplifier (step S40), and the process is terminated.
- step S41 the circuit configuration selection unit 5 detects the required output amplitude level set by the second required level setting unit 2c, and if the required output amplitude level is “high”, 2
- the stage amplifier circuit diagram data is also taken in the database 6 having the gain amplifier database (step S42), and the process is terminated. If it is “Low”, the two-stage amplifier is not adopted and the process proceeds to the next step S43.
- step S43 the circuit configuration selection unit 5 detects the required level of the area set by the second required level setting unit 2c. If the required level of the area is "high”, the triple cascade amplifier Is retrieved from the database 6 having the gain amplifier database (step S45), and the process is terminated. If it is “Low”, the triple cascode amplifier is not adopted and the process proceeds to the next step S44.
- step S44 the circuit configuration selection unit 5 detects the required power consumption level set by the second required level setting unit 2c. If the required power consumption level is "high”, the circuit configuration selection unit 5 Import the circuit diagram data of the pull-cascode amplifier from the database 6 having the database of the gain amplifier (step S45). If “low”, import the circuit diagram data of the gain boost amplifier from the database 6 having the database of the gain amplifier ( Step S46), the process ends.
- the developer simply enters the specifications of the pipeline ADC, and the gain that satisfies the specifications of the DC gain, output amplitude, UGF, area, and power consumption of the gain amplifier alone included in the pipeline ADC.
- the amplifier circuit configuration can be selected automatically, and short-term development and high-quality design can be realized.
- FIG. 6 is a flowchart for explaining a specific comparator selection process.
- the second required level setting unit 2c of the evaluation unit 2 sets the required level in two stages, high and low, for each required performance condition of the comparator. explain about.
- the sub-block performance calculation unit 2b of the evaluation unit 2 calculates the required performance of the single comparator (step S51).
- the second required level setting unit 2c of the evaluation unit 2 performs a request for each required performance condition of the comparator alone such as gain, speed, and power consumption calculated by the sub-block performance calculating unit 2b. Whether the level is “high” or “low” is determined based on a predetermined threshold held by the second required level setting unit 2c, and “high” or “low” is set as the required level for each condition. Set (Step S52). Here, it is assumed that the required level of the gain, speed, and power consumption of the second required level setting unit 2c force comparator of the evaluation unit 2 is evaluated.
- the circuit configuration selection unit 5 detects the required level of gain set by the second required level setting unit 2c (step S53), and if the required level of gain is “high”, The circuit diagram data of the two-stage comparator is fetched from the database 6 having the comparator database (step S54), and the process is terminated. If it is “Low”, the two-stage comparator is not adopted and the process proceeds to the next step S55.
- step S55 the circuit configuration selection unit 5 detects the required speed level set by the second required level setting unit 2c, and if the required speed level is "high", the clamp comparator Schematic data database with comparator database
- step S56 Capture from 6 (step S56), and the process ends. If it is “Low”, the clamp comparator is not used and the process proceeds to the next step S57.
- step S57 the circuit configuration selection unit 5 detects the required power consumption level set by the second required level setting unit 2c. If the required power consumption level is “high”, the ladder is selected. H comparator circuit diagram data database with comparator database
- the circuit diagram data of the inverter comparator is fetched from the database 6 having the database of the comparator (step S59), and the process ends. [0095] By doing this, the developer can select the circuit configuration of the comparator that satisfies the gain, speed, and power consumption specifications of the single comparator included in the pipeline ADC by simply inputting the specifications of the pipeline ADC. Can be done automatically, short-term development and high-quality design can be realized.
- FIG. 7 is a flowchart for explaining specific DAC selection processing.
- the second requirement level setting unit 2c of the evaluation unit 2 sets the request level in two steps, high and low, for each DAC required performance condition. explain
- the sub-block performance calculation unit 2b of the evaluation unit 2 calculates the required performance of the DAC alone.
- the second requirement level setting unit 2c of the evaluation unit 2 has a high requirement level for each requirement performance condition of the DAC alone, such as power consumption, calculated by the sub-block performance calculation unit 2b. "Low” or “Low” based on a predetermined threshold held by the second required level setting unit 2c, and sets "High” or “Low” as the required level for each condition. (Step S72).
- the second required level setting unit 2c of the evaluation unit 2 evaluates only the level required for the power consumption of the DAC alone.
- the circuit configuration selector 5 detects the required level of power consumption set by the second required level setting unit 2c (step S73), and the required level of power consumption is “high”. If there is, the circuit diagram data of the resistor string type DAC is taken from the database 6 having the database of the DAC (step S74). If “low”, the circuit diagram data of the capacitor array type DAC is obtained from the DAC. Work from database 6 that has a database (step S75), and finish the process.
- step S9 of the flowchart in FIG. 3 will be described in detail with reference to FIG.
- FIG. 8 is a flowchart for explaining the reselection processing in step S9 of FIG.
- the determination unit 8 determines that the performance estimation result by the estimation unit 7 does not satisfy all the conditions of the specification, first, it detects the condition of the specification that is not satisfied (step) S81).
- the determination unit 8 determines whether or not it is possible to satisfy any of the detected unsatisfied specification conditions by changing the architecture. Specifically, the determination unit 8 detects whether any of the unsatisfied specification conditions matches the architecture-dependent specification condition, and if a matching specification condition exists, It is determined whether the required level of the conditions of the specification can be further increased (step S82). Whether or not the request level can be further increased is determined by setting the request level in two stages, high and low, so that it is determined whether the request level is low or not. Will be done. Then, as a result of the determination, if any of the unsatisfied usage conditions can be satisfied by changing the architecture, the process goes to step S83, and if not, the process goes to step S85.
- step S83 the determination unit 8 instructs the evaluation unit 2 to further increase the required level of the unsatisfied specifications. Then, the first required level setting unit 2a of the evaluation unit 2 increases the required level of the condition of the specification instructed by the determining unit 8 by one step.
- the architecture selection unit 3 selects an architecture that satisfies the requirements of the specification whose request level has been raised, and then fetches the circuit diagram data of the selected architecture from the architecture database 4 (step S84). Go to step S89.
- step S85 the determination unit 8 satisfies any one of the detected unsatisfied conditions by changing the circuit configuration of any circuit constituting the sub-block. Judgment whether or not it is possible to Specifically, if the judgment unit 8 can detect the condition of the required performance of the circuit unit constituting the sub-block, which affects the condition of the specification that is not satisfied, and if it can be detected, the detection is performed. Judge whether the required level of the required performance condition can be further increased. Furthermore, the request level can be further increased Depending on whether or not it is possible, the request level is set in two steps, high and low, so that it is determined whether or not the request level is low.
- step S86 if any of the unsatisfied conditions for use can be satisfied by changing the circuit configuration of any of the circuits constituting the sub-block, go to step S86. If it cannot be satisfied! /, If it is impossible to develop a pipeline ADC that satisfies the specifications, the process ends.
- step S86 determination unit 8 identifies which circuit of the plurality of sub-blocks is to be raised in required level.
- the determination unit 8 further increases the required level of the required performance condition related to the unsatisfied specification condition with respect to the circuit specified in step S86. Instruct.
- the second required level setting unit 2c of the evaluation unit 2 raises the required level of the required performance condition instructed by the determining unit 8 by one level (step S87).
- the circuit configuration selection unit 5 selects again the circuit configuration that satisfies the requirements of the specification whose request level has been raised (step S88), and goes to step S89.
- step S89 the estimation unit 7 selects again by the architecture selection unit 3 or the circuit configuration selection unit 5, and the performance achieved by these circuit diagram data based on the captured circuit diagram data. Estimate.
- the determination unit 8 again determines whether the performance estimated by the estimation unit 7 satisfies all the conditions of the specification (step S90). As a result of the determination, all the conditions of the specification are satisfied. If so, the circuit diagram data of the pipeline ADC is output and the process is terminated. On the other hand, if even one of the specification conditions is not satisfied, the process returns to step S81, and the processing from step S81 to step S89 is repeated again.
- the pipeline ADC development device and the pipeline ADC development method according to the first embodiment of the present invention after the specification input by the developer is evaluated, based on the evaluation result.
- the circuit diagram of the multiple architectures stored in the database is used to select the circuit diagram data with the optimum data power, and based on the evaluation results, the multiple circuit diagrams of the circuits that make up the sub-blocks stored in the database.
- the architecture selected by the architecture selection unit 3 or the circuit configuration selection unit 5 described in Embodiment 1 of the present invention and the circuit configuration of the circuit constituting the sub-block are typical examples.
- Databases 4 and 6 may include architectures and circuit configurations other than those listed above as options.
- the requirement level is set in two stages of "high” and "low".
- the requirement level is not limited to two, and the request level may be three or more.
- the selection of the circuit configuration of the sub-block the selection of the circuit configuration of the gain amplifier, the comparator, and the DAC is explained. You can select other sub-blocks such as reference circuit selection and bias circuit.
- the estimation unit 7 and the pipeline ADC development apparatus Although the judgment unit 8 is provided and the estimation unit 7 performs the performance estimation process and the judgment unit 8 detects the unsatisfied specifications, the processes of the estimation unit 7 and the judgment unit 8 described above are described. It is also possible to use a circuit simulator or a circuit synthesis tool outside of the pipeline ADC development device.
- the present invention can also be realized by making the procedure described with reference to the flowcharts of Figs. 3 to 8 into a program and executing the program by a central processing unit (CPU) of a computer or the like. Is possible. Further, such a program itself can be recorded on various storage media such as a flexible disk, an optical disk, and a semiconductor storage device, or can be transmitted via a communication line such as the Internet.
- a central processing unit CPU
- a program itself can be recorded on various storage media such as a flexible disk, an optical disk, and a semiconductor storage device, or can be transmitted via a communication line such as the Internet.
- pipeline ADC can be developed in a short period of time, and high quality design can be achieved. Therefore, the use of the pipeline ADC, for example, video signal processing of television and video, communication signals such as wireless LAN, It is useful for processing with high quality, low cost, and low power consumption.
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JPH06231197A (ja) * | 1993-02-05 | 1994-08-19 | Fuji Elelctrochem Co Ltd | 電源設計装置 |
JP2002223165A (ja) * | 2001-01-29 | 2002-08-09 | Sanyo Electric Co Ltd | アナログ−デジタル変換回路、レイアウト作成方法、レイアウト作成装置およびレイアウト作成プログラム |
JP2002231811A (ja) * | 2001-01-29 | 2002-08-16 | Sanyo Electric Co Ltd | 演算増幅器の設計資産の再利用方法、レイアウト作成装置およびレイアウト作成プログラム |
JP2004178507A (ja) * | 2002-11-29 | 2004-06-24 | Matsushita Electric Ind Co Ltd | 暗号回路設計装置および暗号回路設計方法 |
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JPH06231197A (ja) * | 1993-02-05 | 1994-08-19 | Fuji Elelctrochem Co Ltd | 電源設計装置 |
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