Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0635—Clock or time synchronisation in a network
  • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
  • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements

Definitions

• This invention relates to routers and more specifically to broadcast routers that route asynchronous signals.
• a router comprises a device that routes one or more signals appearing at the router input(s) to one or more outputs.
• Routers used in the broadcast industry typically employ at least a first router portion with a plurality of router modules (also referred to as matrix cards) coupled to at least one expansion module.
• the expansion module couples the first router chassis to one or more second router portion to allow further routing of signals.
• Asynchronous signal routing by such linearly expandable routers requires an accurate clock signal throughout the entire route to preserve the integrity of routed data. For an asynchronous signal, a difference in clock frequency from one location to another can cause corruption of the signal and loss of the data represented by that signal.
• Typical examples of data corruption include repeated or dropped signal samples.
• a clock signal constitutes a signal that oscillates between a high and a low state at defined intervals.
• Typical clock signals oscillate with a 50% duty cycle.
• clocks having other duty cycles are also commonly employed. Circuits using clock signals for synchronization become active upon one of the rising or falling edge of the clock signal.
• a so-called, "clock multiplexer” refers to a circuit, as typically exists within a linearly expandable router, for selecting at least one clock signal from a plurality of available clock signals.
• the selected clock signal(s) serve to trigger other elements.
• the output signal selected by the clock multiplexer should not include any undefined pluses. Undefined pulses occur, for example, when a selected clock signal undergoes a disruption. Such a disruption can include a missing clock signal as well as a clock signal that fails to switch states as expected. Some times, an input clock signal will remain "stuck" indefinitely at one logic state or the other.
• Prior art attempts to avoid undefined pulses at the output of a clock multiplexer include so-called "safe" clock multiplexers.
• a typical safe clock multiplexer switches from a presently selected input to a next selected input in an orderly manner. Thus, a safe multiplexer does not switch until the selected input clock signal transitions to a known state and the subsequently selected clock signal transitions to the same state as the previously selected clock signal.
• a method for selecting a clock signal from among at least first and second clock signals commences by detecting a failure of a first clock signal to change state and by detecting a failure of a second clock signal to change state.
• a selection occurs from among the first and second clock signals and an oscillator signal, based in part on whether at least one of the first and second clock signals has toggled
• FIGURE 1 illustrates a block schematic diagram of a router according to an illustrative embodiment of the present principles: [0011]
• FIGURE 2 illustrates a first alternate arrangement of input and output modules for the router of FIG. 1
• FIGURE 3 illustrates a second alternate arrangement of input and output modules for the router of FIG. 1 ;
• FIGURE 4 illustrates a third alternate arrangement of input and output modules for the router of FIG. 1
• FIGURE 5 illustrates a first network of clock selector circuits for use in the router of FIG. 1;
• FIGURE 6 depicts a second network of clock selector circuits for use in the router of FIG. 1
• FIGURE 7 depicts a block schematic diagram of an illustrative embodiment of a clock selector circuit within the networks of FIGS. 5 and 6;
• FIGURE 8 depicts a safe clock multiplexer system of for use in the selector circuit of FIG. 4.
• FIGURE 1 depicts a block schematic of a broadcast router 100 in accordance with a preferred embodiment of the present principles.
• the router 100 comprises at least one, and preferably a plurality input modules 402 1 , 402 2 ...402* where x is an integer greater than zero, and at least one, and preferably, a plurality of output modules 404] ...404 j ,, where y is an integer.
• Each input module, such as input module 402j comprises at least one, and preferably a plurality of input cards 406 1 , 406 2 ...40O 2 , where z is an integer -A-
• Each input card has at least one, and preferably, a plurality of inputs for receiving signals for multiplexing into an output signal. Different input cards typically have different signal receiving capabilities to afford the ability to receive signals from a variety of sources.
• An expansion card 408 within each input module, such as module 4021, multiplexes the output signals from the input cards 406i-406 z into an output signal.
• Each second module such as second module 4041, has a matrix 410 card which de-multiplexes the input signals from one or more of the input modules for delivery to at least one, and preferably a plurality of output cards 412
• Each output card delivers one or more output signals to one or more external devices (not shown).
• a control card 414 controls the matrix card 410 in response to an external control signal C to cause the matrix card to route its output signal among various of the output cards A ⁇ 2 ⁇ -A ⁇ 2 P . In this way, the matrix card 410 can effectuate routing based on the external control signal C.
• the router 100 of FIG. 1 has each of its input modules 402,, 4O2 2... 4O2 ⁇ coupled to each of the output modules 404 1 , 402 2 ...404 v .
• FIGURE 2 illustrates a first alternate arrangement of input and output cards for the router 100 of FIG. 1 wherein the input and output modules are arranged to provide the same number of inputs and outputs.
• FIGURE 3 illustrates a second alternate arrangement of input and output modules for the router 100 of FIG. 1 in which there are more inputs than outputs.
• FIGURE 4 illustrates a third alternate arrangement of input and output modules for the router 100 of FIG. 1 in which there are more outputs than inputs.
• the input modules 402i-402 ⁇ and the output modules A0A ⁇ -A0A y of FIG. 1 typically each include at least one of clock modules 500
• -500 ⁇ where n > x + y
• each clock module having a structure as described in greater detail with respect to FIG. 5.
• separate clock modules can exist in within one or more the elements within each input and output module of FIG. 1.
• one or more clock module 500i-500 n could exist as separate modular elements in the router 100, much like one of the input or output modules.
• the clock modules 500r500 n can interconnect with each other in a daisy chain fashion to yield a network 600 of clock modules.
• the clock module 500j supplies its clock signal to the clock module 50O 2 as well as each of clock modules 50O 3 , 500, + y and 500, + i, where i ⁇ n, whereas the clock module 50O 2 supplies its clock signal to each of modules 500,, 5OO, + 2 and 500, + ⁇ .
• Each of the clock modules 500 ⁇ , 50O 2 ...50O n also receives the clock signal from a preceding one of clock modules 50O 2 ...500,...500 «. / , respectively.
• FIGURE 6 depicts an alternate arrangement of clock modules wherein the modules are arranged in first and second networks 600
• provide clock signals to one or more of the clock modules 500i-500 ⁇ of network 60O 2 .
• FIGURE 7 depicts a block schematic diagram of an exemplary clock module 500,.
• the clock module 500, of FIG. 4 includes first and second clock inputs that receive first and second clock signals Clock_l and Clock_2, respectively.
• Each of the external clock signals Clock_l and Clock_2 can comprise clock signals from a separate upstream clock selector circuit in the network of FIG 2 or a clock signal from a reference clock circuit formed by an oscillator 508.
• the clock selector circuit 500 includes a pair of toggle detectors 502 and 504 which each receive a separate one of the Clock_l and Clock_2 signals. Each toggle detector provides an output signal indicative of whether its respective input clock signal has toggled, i.e., a changed from one state to another.
• a logic block 506 receives the output signals of the toggle detectors 502 and 504, along with the output of an oscillator circuit 508 that generates a clock signal useful for meeting the timing requirements of various circuit elements.
• the logic block 506 also receives two external status signals; (1) A_not B and (2) Master_not Slave.
• the state of the status signal A_not B indicates whether or not the clock circuit 500, will provide the primary clock signal.
• the state of the Master_not Slave signal determines the clock circuit 500, operates as its own master, or as a slave to another clock signal.
• the logic block 506 generates an output control for controlling a safe clock multiplexer system 510 to select among the clock signals Clock_l, Clock_2 and the output signal of the oscillator 508, to provide a single clock signal to downstream elements (not shown).
• the output control signal of the logic block 506 has a prescribed relationship to the logic circuit input signals as shown in Table 1, with the "x" entries constituting "don't care” values. (In other words, the value of the particular input signal has no effect on the output of the logic block 506.) TABLE I
• the clock circuit 500 only selects between Clock_2 and Oscillator 508. Under such conditions, the toggling of the Clock_l signal, and hence the output signal of the toggle detector 504 has no effect.
• the output states of the toggle detector 504, and the output state of the toggle detector 502 determine which of the Clock_l, Clock_2, and oscillator 508 signals appear at the output of the safe clock multiplexer system 510.
• the clock signal selected by the safe clock multiplexer system 510 provides a timing signal for local use as well as for input to elements within the router 100 of FIG. 1.
• the safe clock multiplexer system 510 of FIG. 4 has the structure shown in FIG. 5 to afford the clock module 500, of FIG. 3 the ability to tolerate an input clock pulse that has become stuck.
• first and second toggle detectors 701 1 and 70I 2 receive the Clock_l and Clock_2 signals, respectively, as do each of a pair of multiplexers 702j and 702 2 , respectively.
• Each of the multiplexers 702] and 702 2 receives a signal and a logic "0" level at its second input.
• the toggle detectors 701 1 and 70I 2 control the multiplexers 702] and 702j in accordance with the state of Clock_l and Clock_2 signals, respectively, as measured against the output signal of the oscillator 508. In other words, each of the toggle detectors 701 1 and 70I 2 determines whether a respective one of the Clock_l and Clock_2 signals has changed state (i.e., toggled) relative to the output signal of the oscillator 508.
• toggle detectors 701 1 and 70I 2 determines that a corresponding one of the ClockJ and Clock_2 signals has toggled relative to the oscillator 508 output signal, then that toggle detector gates a corresponding one of the multiplexers 702i and 702 2 .
• and 702 2 passes and associated one of the Clock_l and Clock_2 signals.
• the corresponding one of the multiplexers 7021 and 702 2 will output a logic zero level signal.
• a multiplexer 704 receives at its first and second inputs the output signals of the multiplexers 702 1 and 702 2 , respectively. In accordance with a signal from the logic block 506 of FIG. 4, the multiplexer passes the output signal of one of the multiplexers 702 1 and 702 2 to a first input of a multiplexer 706 1 and to the input of a toggle detector 708 1 .
• has its second input supplied with a signal at a logic zero level.
• the toggle detector 708 1 controls the multiplexer 706 1 in accordance with the relationship between the output signal of the multiplexer 704 and the output signal of the oscillator 508. In other words, the toggle detector 708i determines whether the output signal of the multiplexer 704 has changed state relative to the output signal of the oscillator 508. If the output signal of the multiplexer 704 toggles relative to the oscillator 508 output signal, then the toggle detector 708i causes the multiplexers 706i to pass the output signal of the multiplexer 704. Otherwise, should the output signal of the multiplexer 704 not toggle relative to the output signal of the oscillator 508, the multiplexer 706 1 will output a logic zero level signal.
• a multiplexer 706 2 receives at its first and second inputs the output signal of the oscillator 508 and a logic zero level signal, respectively.
• a toggle detector 708 2 controls the multiplexer 706 2 in accordance with the oscillator 508 output signal. In other words, the toggle detector 708 2 determines whether the output signal of the oscillator 508 periodically changes state. If the oscillator 508 output signal does toggle, then the toggle detector 708 2 gates the multiplexer 706 2 to pass the output signal of the oscillator 508. Otherwise, should the output signal of the oscillator 508 not toggle, then the multiplexer 706 2 will output a logic zero level signal.
• a multiplexer 710 receives at its first and second inputs the output signals of the multiplexers 706] and 706 2 , respectively. Like the multiplexer 704, the multiplexer 710 operates under the control of the logic block 506 of FIG. 4. Thus, depending on output signal of the logic block 506, the multiplexer 710 will either output a selected one of the Clock_l and Clock_2 signals (assuming at least one has toggled relative to the oscillator 508 output signal) or the output signal of the oscillator 508 (assuming it has toggled.)
• the multiplexers 7021 and 702 2 and the multiplexers 704 and 710 serve as clock multiplexers as described earlier.
• the safe clock multiplexer system 510 of FlG. 5 precludes the possibility of a missing clock pulse.
• a clock selector circuit 500 including a safe multiplexer system 510, for distributing clock pulses so as to provide for redundancy while assuring clock synchronism.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Time-Division Multiplex Systems (AREA)
• Electronic Switches (AREA)

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• 2005
  • 2005-06-01 DE DE602005025761T patent/DE602005025761D1/de not_active Expired - Lifetime
  • 2005-06-01 EP EP05762318A patent/EP1756988B1/en not_active Ceased
  • 2005-06-01 CA CA2569018A patent/CA2569018C/en not_active Expired - Fee Related
  • 2005-06-01 CN CN2005800196590A patent/CN101095300B/zh not_active Expired - Fee Related
  • 2005-06-01 WO PCT/US2005/019115 patent/WO2006009605A1/en not_active Ceased
  • 2005-06-01 KR KR1020067026532A patent/KR101095832B1/ko not_active Expired - Fee Related
  • 2005-06-01 JP JP2007516524A patent/JP4650956B2/ja not_active Expired - Fee Related

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