Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges

Definitions

• the invention relates to a device for data exchange on at least two bus systems according to the preamble of patent claim 1 and an associated method.
• microcontrollers which, in addition to the primary control functions, also include the gateway functionality of the controller, i. perform the interface-related functions needed to exchange data. Therefore, the computing power of the microcontroller is normally burdened by occurring interrupts, since the microcontroller process the interrupt actions and all subsequent functionalities usually sequentially.
• the processor unit includes in its functional structure a scalable arithmetic unit, a
• Vehicle communication interface unit with at least two communication interfaces and a communication co-processor as a separate structural component.
• the communication co-processor is between the scalable arithmetic unit and the
• Vehicle communication interface unit connected and used to perform data communication operations between the scalable processing unit and the vehicle communication interface unit and directly between communication interfaces of the vehicle communication interface unit with each other.
• DE 102 18 448 A1 describes an electronic control unit, in particular for a motor vehicle, which comprises a housing, a power supply and connection contacts.
• a gateway for data exchange between different data networks is integrated.
• the gateway is used with a common use of the power supply and the connection contacts in the housing of the control unit, wherein the gateway and the control unit each comprise separate microprocessors and memory modules.
• DE 101 39 610 A1 describes a universal computer architecture for a means of transport with a microprocessor for processing control programs.
• the computer architecture comprises memory means for the data calculated thereby and an interface which allows a connection of the computer to a data bus in the transport, wherein the computer has control programs for controlling devices intended in the transport and the control commands are transmitted via device interfaces to the device to be controlled, wherein the computer has a reconfigurable hardware that allows a nightly reconfiguration of peripheral components or an interface in the installed state of the computer.
• transmission means are provided which transmit an algorithm for reconfiguring the hardware onto the storage means in the means of transport, so that a process for reconfiguring the hardware or the interface relating to the peripheral component can be carried out.
• the object of the invention is to provide a device for exchanging data on different bus systems, which relieves an associated microcontroller and to specify an associated method for the data exchange.
• the invention solves this problem by providing a device for data exchange on at least two bus systems with the features of patent claim 1 and by a method for data exchange on at least two bus systems with the features of patent claim 8.
• At least two control units are designed as reconfigurable hardware units which execute interface-related functions for data exchange on at least two data bus systems in parallel, the interface-related functions
• Network management functions and / or diagnostic functions and / or function management functions include
• a plurality of control units are configured as reconfigurable hardware units and execute interface-related functions for data exchange on at least two data bus systems in parallel, the number of the control units corresponding to the number of data bus systems exchanging data with each other and the interface-related functions
• Network management functions and / or diagnostic functions and / or function management functions include.
• the embodiments of the data exchange device according to the invention advantageously allow a parallel processing of the interface-related functions, which are also referred to below as gateway functions or gateway functionality, i.
• the invention takes over the complete gateway functionality and works in parallel. This relieves the burden on the microcontroller and the parallel processing of the gateway functionality ensures much better performance.
• the device can also be completely reconfigured during runtime, ie during operation For example, to be adapted to new hardware and / or software components.
• any number of bus systems can advantageously be connected to the device according to the invention by the parallel execution of the gateway functionality.
• the associated microcontroller When used in a control unit, the associated microcontroller is completely freed from the interface interrupt load by the device according to the invention.
• the device according to the invention is designed as an FPGA (Field Programmable Gate Array), wherein the control units can be arranged on a common FPGA or separately on at least two FPGAs.
• FPGAs Field Programmable Gate Array
• Such FPGAs have memory cells, such as flip-flops, which can change their function even after manufacture. These memory cells are freely configurable with each other, wherein electrically conductive connections are reconnected, so that various logical circuits can be constructed thereby.
• the device according to the invention comprises at least one routing memory which is assigned to at least one bus system and in which information about the interface-related functions of the associated bus system is stored, which is provided by the at least one control unit for processing the interface-related Functions to be requested.
• the storage of the gateway functionality in a memory ensures that the configuration of the device can also be changed at runtime.
• At least one configuration memory is provided, which comprises configuration data for bus control circuits, which are each assigned to one of the bus systems.
• the device comprises, for example, at least one bus management unit, each comprising a configuration unit and an Rx / Tx handler.
• bus systems CAN and / or LIN and / or FLEXRAY and / or MOST and / or FIREWIRE and / or RS232 and / or USB and / or S-ATA can be connected to the device for data exchange.
• the first control unit loads from an associated first or second routing memory the interface functionality belonging to the first message or the second message and processes the information.
• the first control unit transfers the first message to the second bus system, according to the stored information from the first routing memory), and the second control unit transmits the second message to the first bus system, according to the information stored in the second routing memory.
• Fig. 1 is a block diagram of an apparatus for
• Fig. 3 is a block diagram of a control unit of
• FIG. 4 is a block diagram of a routing memory of FIG.
• FIG. 1 shows a device 1 for reconfigurable data exchange on various bus systems 2.1, 2.2, 2.3, which can be implemented in an ASIC, system on chip (SOC) or in any reconfigurable hardware, preferably in a field programmable gate array (FPGA). Because this module provides internally integrated memory resources which can be used directly because of the design of the device.
• SOC system on chip
• FPGA field programmable gate array
• the device 1 forms a reconfigurable gateway between different bus systems 2.1, 2.2 and 2.3, ie the device operates interface-related functions in parallel, such as message routing functions and / or signal routing functions and / or signal extraction functions and / or protocol conversion functions and / or Network management functions and / or diagnostic functions and / or function management functions.
• a corresponding control unit 8.1, 8.2 and 8.3 available ie the number of control units 8.1, 8.2, 8.3 corresponds to the number of data bus systems 2.1, 2.2, 2.3, with each other Exchange data.
• These bus systems 2.1, 2.2, 2.3 can be located in a motor vehicle or in any electronically networked systems.
• the device 1 can be used in any electronic system where the communication between different or several similar bus systems 2.1, 2.2, 2.3 must be ensured. This means that it can be connected by a bus system 2.1, 2.2, 2.3 more buses or only one. Each bus system has a special physical layer. Physical layers can be: CAN, LIN, FLEXRAY, MOST, FIREWIRE, RS232, USB, 5-ATA. The device 1 can thus realize a connection between any bus system 2.1, 2.2, 2.3.
• the device 1 can change its functionality at runtime. This is possible since the complete functionality is stored in routing memories 9.1, 9.2, 9.3 and in configuration memories 7.1, 7.2, 7.3, ie the gateway functionality is completely configurable by the memory contents of these memory cells and can be changed during runtime.
• Each of the routing memories 9.1, 9.2, 9.3 includes, for example, the complete information of the gateway functionality of a bus system 2.1, 2.2, 2.3.
• Each bus system 2.1, 2.2, 2.3 which is connected to the device, a routing memory 9.1, 9.2, 9.3 assigned. This division ensures parallel processing and simplifies the creation of configuration files for the gateway functionality.
• the received identification of the bus system 2.1, 2.2, 2.3 is directly to the address lines 9Al, 9Bl, 9Cl of the respective routing memory
• the control unit 8.1, 8.2, 8.3 decodes the information and performs the corresponding function or action.
• a message from one of the bus systems 2.1, 2.2, 2.3 is sent to the device 1 via a bus transceiver 3.1, 3.2, 3.3 assigned to the respective bus system, then it is read in and buffered by a bus controller 5.1, 5.2, 5.3 assigned to the respective bus system.
• the respective bus management unit 6.1, 6.2, 6.3 comprises, as can be seen from FIG. 2, a configuration unit 6A and an Rx / Tx handler 6B.
• the Rx / Tx handler retrieves the message and transmits it to a respective bus system 2.1, 2.2, 2.3 associated control unit 8.1, 8.2, 8.3, which processes and executes the corresponding functionality based on the information stored in the associated routing memory 9.1, 9.2, 9.3 ,
• the corresponding bus transceiver 3.1, 3.2, 3.2 is connected in series or in parallel with the associated bus controller 5.1, 5.2, 5.3 and converts the message located on the bus 2, 1, 2, 2, 3 into a digital signal and transmits this message serial or parallel to the respective bus controller 5.1, 5.2, 5.3.
• the respective bus controller 5.1, 5.2, 5.3 negotiates the bus protocol for receiving and sending messages. It receives the messages or data from the respective bus system 2.1, 2.2, 2.3, stores these messages in an internal memory and signals the associated
• Bus Management Unit 6.1, 6.2, 6.3 that a new message has been received and ready for pickup. If the corresponding bus management unit 6.1, 6.2, 6.3 transmits a message to be sent by one of the control units 8.1, 8.2, 8.3 to the corresponding bus controller 5.1, 5.2, 5.3, the bus controller temporarily stores this message in an internal memory until the respective bus system 2.1 , 2.2, 2.3 is free to transmit this message.
• the bus controller 5.1, 5.2, 5.3 includes various configuration registers in order to reinitialize the respective bus system 2.1, 2.2, 2.3 after a reset process.
• the required configuration data is received by the respective bus controller 5.1, 5.2, 5.3 after the reset process via the configuration unit 6A from the associated bus management unit 6.1, 6.2, 6.3, which reads out the data from the associated configuration memory 7.1, 7.2, 7.3.
• the respective bus management unit 6.1, 6.2, 6.3 comprises, as can be seen from FIG. 2, the configuration unit 6A and the Rx / Tx handler 6B for the respective bus controller 5.1, 5.2, 5.3.
• the configuration unit 6A of the respective bus management unit 6.1, 6.2, 6.3 writes after a reset operation the configuration data for the respective bus system 2.1, 2.2, 2.3, which are stored in the associated configuration memory 7.1, 7.2, 7.3, in the associated bus controller 5.1, 5.2, 5.3 and start the corresponding bus system 2.1, 2.2, 2.3.
• the Rx / Tx handler 6B of the respective bus management unit 6.1, 6.2, 6.3 ensures that messages received by the bus controllers 5.1, 5.2, 5.3 are forwarded to the corresponding one of the control units 8.1, 8.2, 8.3 and from one of the control units 8.1, 8.2, 8.3 data to be transmitted to the respective bus controller 5.1, 5.2, 5.3 are transmitted.
• the Rx / Tx handler 6B supplements the received message additionally with a recognizable for the corresponding control unit 8.1, 8.2,8.3 identification.
• ID an identification
• the Rx / Tx handler 6B recognizes the respective bus management unit 6.1, 6.2, 6.3 on the basis of an identification transmitted by the corresponding control unit 8.1, 8.2, 8.3 in which time slot the message to be sent must be inserted and outputs this information to the relevant bus controller 5.1, 5.2, 5.3 continue.
• the Rx / Tx handler 6B can also be provided with an internal memory for storing the messages to be sent and / or a time slot in the TDM method.
• each of the bus management units 6.1, 6.2, 6.3 includes its own Rx / Tx Handler 6B, which is integrated, for example, in the module 6 and manages the received and to be sent messages and in each case to the bus controller 5.1, 5.2, 5.3 or to the control units 8.1, 8.2, 8.3 forwards.
• the parallel processing of the individual bus systems 2.1, 2.2, 2.3 results in a considerable increase in performance.
• the respective control unit 8.1, 8.2, 8.3 then processes the received messages. Due to the parallel processing, any number of bus systems can be connected to the device 1.
• the control units 8.1, 8.2, 8.3 are responsible for the complete execution functionality and comprise, as can be seen from the blocks shown in FIG. 3, a message routing function 8A, a signal routing function 8B, a signal extraction function 8C, a protocol conversion function 8D, respectively
• Network management function 8E a diagnostic function 8F and a function management function 8G.
• the message routing function 8A forwards a message received from one of the bus systems 2.1, 2.2, 2.3 to another of the bus systems 2.1, 2.2, 2.3 or to an interface 10 of the device without changing the information content.
• the signal routing function 8B extracts individual information (bits) from a received message and inserts them into a newly generated message. This new message is then transmitted to the desired one of the bus systems 2.1, 2.2, 2.3 or to the interface 10.
• the signal extraction function 8C extracts individual information (bits) from a received message and transmits these to the interface 10 for further processing.
• the protocol conversion function 8D ensures communication between bus systems 2.1, 2.2, 2.3 with different protocols. It ensures the compatibility of the different bus systems 2.1, .2.2, 2.3. In addition to the adaptation of the protocols of the different bus systems, the protocol conversion function 8d can take on additional tasks which can not be assumed by the Rx / Tx handler 6B, for example the temporary storage of messages for bus systems 2.1, 2.2, 2.3 with different transmission rates.
• the network management function 8E undertakes special tasks, especially in a motor vehicle, as described, for example, in the OSEKIVDX Network Management Specification known to the person skilled in the art.
• the diagnosis function 8F manages bus-specific diagnostic messages and carries out various actions depending on the stored functionality.
• the function management function 8G coordinates, for example, the interaction of the individual functionalities of the corresponding control unit 8.1, 8.2 8.3.
• the function management function 8G activates e.g. in the message routing, Signalrouting- and / or diagnostic function 8A, 8B, 8F between bus systems with different transmission methods automatically the
• Protocol conversion function 8D Furthermore, the function management function 8G coordinates the communication between the The function management function coordinates the reconfiguration of the memories 7 and / or 9 possible at runtime, whereby during operation the functionality of the device 1 regarding message routing 8A, signal routing 8B, signal extraction 8C and diagnosis 8F as well as the configuration of the bus systems 2.1, 2.2, 2.3 can be changed.
• the respective control unit 8.1, 8.2, 8.3 picks up the message received from the corresponding Rx / Tx handler 6B and identifies it based on the contained identification. With the identification, the respective control unit 8.1, 8.2, 8.3 can read in parallel the functionality associated with the message from the associated routing memory 9.1, 9.2, 9.3. On the basis of the functionality read out from the corresponding routing memory 9.1, 9.2, 9.3, the control unit 8.1, 8.2, 8.3 performs the corresponding functions such as message routing 8A, signal routing 8B, signal extraction 8C, network management 8E and / or diagnosis 8F with a possible protocol conversion 8D.
• the interface 10 of the device 1 establishes a connection to the external periphery 11 or to further functional units 12 which are located in the same reconfigurable hardware, ASIC or SOC. Via the external periphery 11 or via further functional units 12, the gateway functionality can be changed during initialization or at runtime. Furthermore, the interface is used for data exchange of the different bus systems 2.1, 2.2, 2.3, with further functional units 12. In this data exchange complete messages or only individual signal information can be exchanged.
• the interface 10 is usually adapted individually to the connected internal or external functional units. The exchange of information of the interface with other modules, for example, in the form of shared memory -zB a dual port RAM (when connecting an external microcontroller) or via a bus bridge.
• gateway functionalities of the device 1 will be described below on the basis of an example for message routing.
• On the bus systems 2.1 and 2.2 are simultaneously received messages with the bus transceivers 3.1, 3.2. These messages are forwarded by the two bus transceivers 3.1, 3.2 to the respective bus controllers 5.1, 5.2 of the device 1.
• the control unit 8.1, 8.2 transfers the respective message to the Rx / Tx handler 6B belonging to the respective target bus system 2.1, 2.2, 2.3.
• the associated bus controller 5.1, 5.2, 5.3 stores the corresponding message in an internal memory until the respective bus system 2.1, 2.2, 2.3 is free to send this message via the respective bus transceiver 3.1, 3.2, 3.3.
• the device according to the invention for data exchange on at least two data bus systems comprises at least one control unit configured as a reconfigurable hardware unit for parallel processing of interface-related functions, such as message routing functions and / or signal routing functions and / or signal extraction functions and / or protocol conversion functions and / or network management functions and / or diagnostic functions and / or function management functions , whereby the performance of an associated microcontroller, especially in control units in a motor vehicle is increased.
• the number of control units corresponds to the number of data bus systems which exchange data with each other via the device according to the invention.

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• 2004
  • 2004-07-13 DE DE200410033761 patent/DE102004033761A1/de not_active Withdrawn
• 2005
  • 2005-06-24 JP JP2007520694A patent/JP2008506204A/ja active Pending
  • 2005-06-24 WO PCT/EP2005/006833 patent/WO2006005427A1/de not_active Application Discontinuation
  • 2005-06-24 EP EP05755624A patent/EP1766522A1/de not_active Withdrawn

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