WO2006004096A2 - 固体撮像装置 - Google Patents
固体撮像装置 Download PDFInfo
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- WO2006004096A2 WO2006004096A2 PCT/JP2005/012352 JP2005012352W WO2006004096A2 WO 2006004096 A2 WO2006004096 A2 WO 2006004096A2 JP 2005012352 W JP2005012352 W JP 2005012352W WO 2006004096 A2 WO2006004096 A2 WO 2006004096A2
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- imaging device
- state imaging
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- 238000003384 imaging method Methods 0.000 title claims abstract description 113
- 238000006243 chemical reaction Methods 0.000 claims abstract description 112
- 238000001514 detection method Methods 0.000 claims description 73
- 238000009792 diffusion process Methods 0.000 claims description 38
- 238000009825 accumulation Methods 0.000 claims description 10
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 50
- 230000003321 amplification Effects 0.000 description 25
- 238000003199 nucleic acid amplification method Methods 0.000 description 25
- 230000008030 elimination Effects 0.000 description 23
- 238000003379 elimination reaction Methods 0.000 description 23
- 230000009467 reduction Effects 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000008859 change Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 239000013256 coordination polymer Substances 0.000 description 5
- 238000005070 sampling Methods 0.000 description 5
- 230000002596 correlated effect Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920001690 polydopamine Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/76—Circuitry for compensating brightness variation in the scene by influencing the image signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/627—Detection or reduction of inverted contrast or eclipsing effects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
Definitions
- the present invention relates to a solid-state imaging device mounted on a PDA such as a video camera, a digital camera, or a mobile phone, and does not detect a saturation signal level when shooting a high-luminance subject.
- the present invention relates to a technique for avoiding a phenomenon that a black image is detected where a signal level or a negative level is detected and a white image should be obtained.
- a circuit configuration for detecting the accumulated charge of the photoelectric conversion element PD in the pixel portion and its timing are roughly classified as a type AMI-type solid-state imaging device and a floating diffusion amplifier.
- FIG. 1 is a diagram showing a configuration of an AMI type solid-state imaging device.
- the solid-state imaging device 900 includes a plurality (two in the figure) of pixel portions lOanl, 10an2 arranged two-dimensionally, and a plurality (in the figure, one) common column provided for each column.
- Each pixel unit lOanl, 10an2 includes a photoelectric conversion element PD that converts incident light into electric charges, a reset transistor Q12a that initializes the power sword of the photoelectric conversion element PD to the power supply voltage VDD by a RES ET pulse, and photoelectric conversion From the voltage conversion amplification transistor Q 13a that detects the charge of the element PD, and the row selection transistor Q14 that transfers the voltage output from the voltage conversion amplification transistor Q 13a by the VSEL pulse to the common column signal line Ln for each row.
- a photoelectric conversion element PD that converts incident light into electric charges
- a reset transistor Q12a that initializes the power sword of the photoelectric conversion element PD to the power supply voltage VDD by a RES ET pulse
- photoelectric conversion From the voltage conversion amplification transistor Q 13a that detects the charge of the element PD
- the row selection transistor Q14 that transfers the voltage output from the voltage conversion amplification transistor Q 13a by the VSEL pulse to the common column signal line Ln for
- the sample and hold transistor Q31 samples and holds the voltage output to the common column signal line Ln by the SH pulse.
- the noise signal elimination circuit 40 is also operated by the clamp transistor Q42, the clamp capacitor C41, and the sample hold capacitor C42.
- the photoelectric conversion element detected by each pixel unit lOanl, 10an2 By taking the difference between the PD initialization voltage and the voltage detected by the charge according to the amount of light
- the signal component from which the noise component is eliminated is detected.
- FIG. 2 is a diagram showing the drive timing of the solid-state imaging device 900 of FIG.
- the row selection transistor Q14 of the pixel portion lOanl is turned on by the VSEL pulse, and then the sample hold transistor Q31 is turned on by the SH pulse at time t2, and during the period from time t3 to time t4, The clamp transistor Q42 of the noise signal elimination circuit 40 is turned ON by the CP pulse.
- the RESET pulse of the pixel unit lOanl is turned on.
- the accumulated charge of the photoelectric conversion element PD of the pixel unit lOanl is converted into the voltage conversion amplification transistor Q of the pixel unit lOanl.
- the signal is held in the sample hold capacitance C42 of the noise signal elimination circuit 40 via 13a.
- the holding signal at this time is assumed to be voltage A.
- the reset transistor Q12a is turned on by the RESET pulse, the photoelectric conversion element PD is initialized to the power supply voltage VDD level, and then the sample hold transistor Q31 is turned off by the SH pulse t7 Within the period up to, the initialization level of the photoelectric conversion element PD is held again in the sample hold capacitor C42 of the noise signal removal circuit 40 via the voltage conversion amplification transistor Q13a.
- the holding signal at this time is assumed to be voltage B.
- the noise signal removal circuit 40 the accumulated signal component installed in the two-dimensional imaging region from which the noise signal component is removed is detected by subtracting the voltage A held earlier and the voltage B held later.
- the row selection transistor Q14 is turned off by the VSEL pulse, so that the charge detection operation for one row of the photoelectric conversion elements PD installed in the two-dimensional imaging region is completed.
- FIG. 3 is a diagram showing a configuration of an FDA type solid-state imaging device.
- the solid-state imaging device 950 is configured using pixel units lObnl and 10bn2 instead of the pixel units lOanl and 10an2.
- Each pixel unit lObnl, 10bn2 includes a transfer transistor Q11 that reads out charges from the photoelectric conversion element PD, and a floating diffusion FD that temporarily stores charges, in addition to the components of the pixel units lOanl, 10an2.
- the reset transistor Q12a initializes the floating diffusion FD to the power supply voltage VDD, and the voltage conversion amplification transistor Q13a detects the voltage of the accumulated charge in the floating diffusion FD.
- FIG. 4 is a diagram showing the drive timing of the solid-state imaging device 950.
- the initialization level of the floating diffusion FD is held in the sample hold capacitor C42 of the noise signal elimination circuit 40 via the voltage conversion amplification transistor Q13a.
- the holding signal at this time is assumed to be voltage C.
- the transfer transistor Q11 is turned ON by the TRANS pulse, the accumulated charge of the photoelectric conversion element PD is transferred to the floating diffusion FD, and then the sample hold transistor Q31 is turned OFF by the SH pulse t7
- the charge accumulated in the floating diffusion FD of the pixel portion lObnl is held in the sample hold capacitor C42 of the noise signal removal circuit 40 via the voltage conversion amplification transistor Q13a within the period up to.
- the holding signal at this time is assumed to be voltage D.
- the noise signal elimination circuit 40 detects the accumulated signal component installed in the two-dimensional imaging area from which the noise signal component has been removed by subtracting the voltage C held earlier and the voltage D held later. .
- the row selection transistor Q14 is turned off by the VSEL pulse, whereby the charge detection operation for one row of the photoelectric conversion elements PD installed in the two-dimensional imaging region is completed.
- the MOS type solid-state imaging device as described above cannot detect a high-luminance portion as a saturation signal level when shooting with a high-luminance illuminant such as sunlight as a background. There is a phenomenon of detecting as no signal level.
- FIGS. Fig. 5 and Fig. 6 show the pixel unit lOanl called (AMI type).
- Fig. 5 shows the case where normal charge detection is performed with the incident light as the standard light amount.
- Fig. 6 shows the incident light as the standard light amount. This is the case where abnormal charge detection is performed with a light intensity that is 200,000 times higher than the above.
- FIG. 5 (a) shows a potential diagram of the pixel portion lOanl in the period from time t3 to time t5 in FIG.
- FIG. 5B shows a potential diagram of the pixel portion lOanl in the period from time t5 to time t6 in FIG.
- the photoelectric conversion element PD is initialized to the power supply voltage VDD level.
- FIG. 5 (c) shows a potential diagram of the pixel portion lOanl in the period from time t6 to time t7 in FIG.
- the photoelectric conversion element PD is kept initialized to the power supply voltage VDD level, and this level is held in the noise signal removal circuit 40 via the voltage conversion amplification amplifier of the pixel section lOanl.
- the holding signal at this time is assumed to be voltage B.
- the noise signal elimination circuit 40 the difference between the previously held voltage A and the later held voltage B can be obtained to detect the accumulated signal component installed in the two-dimensional imaging area from which the noise signal component has been removed. It will be.
- FIG. 6 (a) shows a potential diagram of the pixel portion lOanl in the period from time t3 to time t5 in FIG.
- the accumulated charge of the photoelectric conversion element PD is held in the noise signal removal circuit 40 via the voltage conversion amplifier of the pixel portion lOanl.
- the holding signal at this time is assumed to be voltage A.
- FIG. 6B shows a potential diagram of the pixel portion lOanl in the period from time t5 to time t6 in FIG.
- the photoelectric conversion element PD is initialized to the power supply voltage VDD level.
- FIG. 6 (c) shows a potential diagram of the pixel portion lOanl in the period from time t6 to time t7 in FIG.
- the photoelectric conversion element PD is initialized to the power supply voltage VDD level. I can keep it!
- the incident light is a bright light that is 200,000 times or more the standard light amount
- immediately after the photoelectric conversion element PD is initialized to the power supply voltage VDD level, that is, immediately after the time t6 when the RESET pulse of the pixel 1 Oanl is turned off.
- the noise signal elimination circuit 40 via the voltage conversion amplification amplifier of the pixel unit 10an 1.
- the holding signal at this time is assumed to be voltage B
- the difference between the voltage A held earlier and the voltage B held later in the noise signal elimination circuit 40 is 0 or minus, and the noise signal component is removed 2 It becomes impossible to detect the accumulated signal component installed in the dimensional imaging area.
- FIG. 7A shows a potential diagram of the pixel portion lObnl in the period from time t3 to time t4 in FIG.
- the reset transistor Q12a is turned on by the RESET pulse of the pixel part lObnl to initialize the charge detection part (floating diffusion) of the pixel part lObnl to the power supply voltage VDD level.
- FIG. 7B shows a potential diagram of the pixel portion lObnl in the period from time t4 to time t5 in FIG.
- the charge detection unit (floating diffusion) of the pixel unit lObnl is kept initialized to the power supply voltage VDD level, and is held in the noise signal elimination circuit 40 via the voltage conversion amplifier transistor Q13a of the pixel unit lObnl. ing.
- the holding signal at this time is assumed to be voltage C.
- FIG. 7C shows a potential diagram of the pixel portion lOanl in the period from time t5 to time t7 in FIG.
- the noise signal removal circuit 40 the accumulated signal component installed in the two-dimensional imaging region from which the noise signal component is removed is obtained by differentiating the voltage C held earlier and the voltage D held later. It can be detected.
- FIG. 8 (a) shows a potential diagram of the pixel portion lObnl in the period from time t3 to time t4 in FIG.
- the reset transistor Q12a is turned on by the RESET pulse to initialize the charge detection part (floating diffusion) of the pixel part lObnl to the power supply voltage VDD level.
- FIG. 8B shows a potential diagram of the pixel portion lObnl in the period from time t4 to time t5 in FIG.
- the charge detection part (floating diffusion) of the pixel part lObnl can be kept initialized to the power supply voltage VDD level.
- the incident light is a high-intensity light quantity 200,000 times or more of the standard light quantity
- the potential of the photoelectric conversion element PD region is greatly lowered, and the charge detection section (flowtain) (Giffusion) Region force also creates a path for current flow.
- FIG. 8C shows a potential diagram of the pixel portion lObnl in the period from time t5 to time t7 in FIG.
- the transfer transistor Q11 is turned ON by the TRANS pulse of the pixel unit lObnl
- the charge detection of the pixel unit lObnl is already performed because the accumulated charge equal to or higher than that at the time of the photoelectric conversion element PD force saturation accumulation flows.
- the voltage level of the part drops, and this voltage level is held in the noise signal elimination circuit 40 via the voltage conversion amplifier transistor Q13a of the pixel part lObnl.
- this held signal is assumed to be voltage D, the difference between the previously held voltage C and the later held voltage D will be 0 or minus, and it will not be installed in the two-dimensional imaging area where the noise signal component has been removed. The accumulated signal component cannot be detected (see Patent Document 1).
- the pixel output signal is detected by a signal processing circuit and corrected.
- a method of adding such information has been proposed (see Patent Document 2).
- Patent Document 1 Japanese Unexamined Patent Publication No. 2003-46865 (Pages 1-8, Fig. 1)
- the present invention has been made in view of the above-described problems, and follows variations in the threshold value of the transistor that always occur in the manufacturing process, and can be corrected in real time even during multi-pixel high-speed continuous shooting. Since a solid-state image sensor can be incorporated with a relatively simple circuit, a high-intensity part is normally detected as a saturated signal level by using a signal processing element or a correction circuit that does not need to be transferred to the circuit. Therefore, an object of the present invention is to provide an S-type solid-state imaging device that generates a natural captured image.
- a pixel unit arranged one-dimensionally or two-dimensionally, and a pixel output output from the pixel unit to a common column signal line
- a voltage level detecting means for detecting a voltage
- a column for outputting a predetermined voltage to the horizontal output means based on the logic output voltage of the voltage level detecting means and the pixel output voltage.
- Signal processing means, and the column signal processing means outputs either a voltage corresponding to the pixel output voltage or a fixed voltage according to the logic output voltage.
- the output signal level of the pixel unit can be immediately determined inside the solid-state imaging device, and the signal at the time of high-luminance incidence can be corrected, and a high-speed correction process by a separate signal processing circuit can be performed. It becomes unnecessary.
- the column signal processing means includes noise signal removal means for receiving the pixel output voltage and outputting a voltage to the horizontal output means, and the noise signal The removing unit may output a difference between the pixel output voltage when the pixel unit is initialized and the pixel output voltage when the pixel unit is accumulated.
- the noise of each pixel unit included in the pixel output signal output to the pixel unit force common column signal line is deleted by performing correlated double sampling by the noise signal removing unit. be able to.
- the column signal processing unit further includes a voltage control unit, and when the column signal processing unit outputs the fixed voltage, the pixel unit is initialized. Instead of the pixel output voltage at the time, a predetermined initialization voltage is input to the voltage control means power to the noise signal removal means.
- the voltage control unit includes an initialization voltage generation unit that generates the same voltage as the pixel output voltage at the time of initialization of the pixel unit, and the initial stage. It is characterized by comprising replacement means for reproducing the initialization state of the pixel portion by inputting the initialization voltage generated by the activation voltage generation means to the common column signal line.
- the initialization voltage generating means is configured by the same transistor in the same element, the same potential as the initialization voltage in the pixel portion causes transistor threshold variation due to the manufacturing process. Since it can be generated accurately without being affected, the correction accuracy can be increased.
- the voltage control means uses the charge detection period to the pixel signal force noise signal removing means performed within a horizontal blanking period as an operation period, and performs the operation It is characterized by being set to the non-operational state except for the period.
- the current consumed by the correction circuit can be significantly reduced.
- the voltage level detection unit includes a saturation voltage generation unit that generates the same voltage as the pixel output voltage at the time of saturation accumulation of the pixel unit; And determining means for comparing the saturation voltage generated by the saturation voltage generating means with the pixel output voltage.
- the saturation voltage generating means is configured by the same transistor in the same element, the same voltage as the saturation voltage in the pixel portion is caused by the manufacturing process. Since it can be generated accurately without being influenced by variations in the transistor threshold, it is possible to immediately and accurately determine whether or not the pixel portion has high luminance incidence.
- the saturation voltage generating unit is formed outside the region of the pixel unit, and the determining unit is provided for each common column signal line. It is a feature that characterizes this.
- a high-intensity portion that occurs when a high-luminance illuminant such as sunlight is photographed in the background is detected as a no-signal level rather than being detected as a saturation signal level.
- the phenomenon is not affected by transistor threshold variations that always occur during the manufacturing process, and can be corrected in real time even during high-speed continuous shooting with multiple pixels, and can be incorporated into a solid-state image sensor with a relatively simple circuit.
- the high-intensity part is normally output as a saturated signal level, and a solid-state image that generates natural images without failure is generated.
- FIG. 2 is a diagram showing drive timing of the solid-state imaging device 900 of FIG.
- FIG. 5 is a potential diagram of the solid-state imaging device 900 during normal operation.
- FIG. 8 is a potential diagram of the solid-state imaging device 950 at the time of high-luminance incidence.
- FIG. 12 is a diagram showing the drive timing of the MOS type solid-state imaging device 1.
- FIG. 15 is a diagram showing a circuit configuration of a MOS type solid-state imaging device 3 in which the voltage control circuit 60 is embodied.
- FIG. 17 is a diagram showing a circuit configuration of the MOS type solid-state imaging device 4 in which the power consumption of the voltage control circuit 60 is reduced.
- FIG. 19 is a diagram showing a circuit configuration of an FDA-type MOS solid-state imaging device 5.
- FIG. 10 is a circuit schematic diagram of the solid-state imaging device according to Embodiment 1 of the present invention.
- the MOS type solid-state imaging device 1 has a plurality (two in the figure) of pixel units lOanl arranged in a two-dimensional manner, similar to the solid-state imaging device 900. , 10a n2, a plurality (one in the figure) of common column signal lines Ln provided for each column, a load transistor Q21a connected to each common column signal line Ln, and a common column signal line Ln.
- a voltage level detection circuit 50, a voltage control circuit 60, and a horizontal output circuit 90 are further provided. Composed.
- the voltage level detection circuit 50 detects the voltage output from the voltage conversion amplification transistor Q 13a to the common column signal line Ln.
- the voltage control circuit 60 directly controls the voltage of the common column signal line Ln based on a signal from the voltage level detection circuit 50. More specifically, the voltage control circuit 60 has the power to set the voltage of the common column signal line Ln to the voltage output from the voltage conversion amplification transistor Q13a according to the logic level output as the comparison result of the voltage level detection circuit 50. Control whether to replace with a predetermined voltage.
- the column signal processing circuit 80 is configured by the sample-and-hold transistor Q31, the noise signal removal circuit 40, and the voltage control circuit 60.
- the voltage force determined in advance is the same as the voltage at the time of initialization of the photoelectric conversion element, at the time of initialization of the photoelectric conversion element that does not appear on the common column signal line at the time of high luminance incidence Thus, the voltage change of the photoelectric conversion element can be normally detected.
- a predetermined voltage corresponds to the output voltage of the noise signal removal circuit at the time of saturation accumulation of the photoelectric conversion element, that is, the input to the horizontal output circuit 90.
- the saturation level correction is forcibly applied to the output part of the noise signal removal circuit even if the voltage at the time of initialization of the photoelectric conversion element does not appear on the common column signal line at the time of high luminance incidence.
- FIG. 12 is a diagram showing the drive timing of the MOS type solid-state imaging devices 1 and 7.
- This timing represents an example of the timing at which the voltage level detection circuit 50 and the voltage control circuit 60 become active for the charge detection of the AMI type photoelectric conversion element PD by the pixel unit lOanl.
- the voltage control circuit 60 that determines direct control of the voltage output from the voltage conversion amplification transistor Q13a for each column based on the signal from the voltage level detection circuit 50 is a photoelectric conversion element PD that is performed within the horizontal blanking period. Only the charge detection period up to the force noise signal elimination circuit 40 is set as a necessary operation period, and it is set to a non-operation state except the necessary operation period.
- the output signal of the photoelectric conversion element can be immediately determined while reducing power consumption, and the voltage of the common column signal line corresponds to the voltage output from the amplifier circuit and the initialization voltage of the photoelectric conversion element.
- the voltage can be corrected to any one of the voltages.
- FIG. 13 is a diagram showing a circuit configuration of the MOS type solid-state imaging device 2 in which the voltage level detection circuit 50 is specifically implemented. In the figure, the horizontal output circuit 90 and the like are not shown.
- the voltage level detection circuit 50 includes an individual unit 501 provided for each column and a common unit 502 provided in common for the MOS type solid-state imaging device.
- the common unit 502 includes a saturation voltage generation initialization transistor Q51a, a reset transistor Q12b configured in the same size and in the same manner as the reset transistor Q12a of the pixel unit lOanl, and a voltage control circuit input unit initialization. It has a transistor Q52 and functions as a saturation voltage generation circuit that generates the same potential as the saturation voltage in the photoelectric conversion element PD.
- the individual unit 501 includes a voltage level detection transistor Q13b having the same manufacturing method and the same size as the voltage conversion amplification transistor Q13a of the pixel unit lOanl, and is connected to the common column signal line from the voltage conversion amplification transistor Q13a. Based on the output voltage and a voltage corresponding to the same potential as the saturation voltage generated by the common unit 502, it functions as a determination circuit that determines high-luminance incidence in the photoelectric conversion element PD. [0095] The drain of the voltage level detection transistor Q13b is generated by the common column signal line Ln, its source is generated by the input of the voltage control circuit 60, and its gate is generated by the saturation voltage generating initialization transistor Q51a and the reset transistor Q12b. The correct voltage level is input.
- FIG. 14 is a diagram showing drive timing of the MOS type solid-state imaging device 2 of FIG.
- the saturation voltage generation initialization transistor Q51a is turned ON by the RSVSS pulse, and the voltage is controlled by the RSVDD noise. Turn on the initialization transistor Q52 for circuit input.
- the saturation voltage of the photoelectric conversion element PD is input to the gate of the voltage level detection transistor Q13b, and the power supply voltage VDD is input to the source.
- the voltage level input to the gate of the voltage level detection transistor Q13b is the same as the level determined when the gate of the reset transistor Q12a that initializes the photoelectric conversion element PD is OFF. This is because the voltage level stored in the photoelectric conversion element PD when an incident light is input is determined by the threshold value when the gate of the reset transistor Q 12a is turned off, and does not become a lower voltage level. When the drain is the power supply voltage VDD and the source is the floating node, this corresponds to the source potential determined when the gate of the reset transistor Q12a is turned off. As a result, the photoelectric conversion element Since level detection can be performed without unnecessarily sweeping away the saturated charge accumulated in the child PD, the dynamic range can be utilized to the maximum.
- FIG. 15 is a diagram showing a circuit configuration of the MOS type solid-state imaging device 3 in which the voltage control circuit 60 is specifically implemented. In the figure, the horizontal output circuit 90 and the like are not shown.
- the voltage control circuit 60 includes an individual unit 601a provided for each column and a common unit 602 provided in common to the MOS type solid-state imaging device.
- the common unit 602 includes a reset transistor Q12c formed in the same size and the same manufacturing method as the reset transistor Q12a of the pixel unit lOanl for generating an initialization voltage, and a GND for resetting to a GND level for generating a saturation voltage. It consists of a level setting transistor Q5 lb, a detection transistor Q13c whose gate is the generated initialization voltage or saturation voltage, and a load transistor Q21b that forms a source follower circuit.
- the initialization voltage of the photoelectric conversion element PD is Functions as an initialization voltage generation circuit that generates the same voltage level as the output common column signal line Ln.
- the individual unit 601a includes a common column signal line connection transistor Q61 whose gate changes to a low level due to high luminance incidence, an inverter circuit INV that receives the source of the voltage level detection transistor Q13b, and an output of the inverter circuit INV.
- the correction signal line connection transistor Q62 connecting the common column signal line Ln and the detection signal output Ls correction signal line Ls, and the transistor connecting the gate of the correction signal line connection transistor Q62 and the output of the inverter circuit INV Q63, and the same voltage generated by the common unit 602 is input to the common column signal line Ln.
- it functions as a replacement circuit that replaces the initialization voltage of the photoelectric conversion element PD.
- the output voltage of the voltage control circuit (the gate of the correction signal line connection transistor Q62) becomes a logical high level, and connects the correction signal line Ls and the common column signal line Ln. .
- the common column signal line connection transistor Q61 simultaneously changes to the gate force SLow level due to high-intensity incidence, so that the output of the common column signal line Ln with the two-dimensional imaging region force is cut off.
- the voltage of the correction signal line Ls that is, the same voltage as the common column signal line Ln from which the saturation voltage of the photoelectric conversion element PD is output is replaced with the original output of the common column signal line Ln to remove the noise signal. Input to circuit 40.
- the saturation voltage and initialization voltage of the photoelectric conversion element PD are connected to the correction signal line Ls.
- the force that generates the same voltage as the common column signal line Ln from which the voltage is output is because the voltage level accumulated in the photoelectric conversion element PD immediately after saturation is the same as when the gate of the reset transistor is turned off.
- the voltage level stored in the photoelectric conversion element PD immediately after initialization is determined by the threshold value, and is a force determined by the threshold value when the gate of the reset transistor is turned on.
- a photoelectric conversion element PD group is separately provided in addition to the two-dimensional imaging region.
- the same voltage level as that of the photoelectric conversion element PD in the two-dimensional imaging region can be input because the same voltage as that of the common column signal line Ln from which the conversion voltage is output is generated. Therefore, it is possible to input an accurate voltage level regardless of the threshold value variation of the transistor that always occurs in the manufacturing process.
- the voltage control circuit 60 is activated only during the charge detection period up to the noise signal elimination circuit 40 during the horizontal blanking period, and is deactivated during other horizontal scanning periods. By setting, power consumption can be reduced. A specific example is shown in FIG.
- FIG. 17 is a diagram showing a circuit configuration of the MOS type solid-state imaging device 4 in which the power consumption of the voltage control circuit 60 is reduced. Also in this figure, the illustration of the horizontal output circuit 90 and the like is omitted.
- the individual unit 601b of the voltage control circuit 60 includes a current reduction transistor Q64 disposed between the input of the inverter circuit INV and the ground, and a correction signal line connection transistor Q62. And a current reduction transistor Q 65 disposed between the gate and the ground.
- FIG. 18 is a diagram showing the drive timing of the MOS type solid-state imaging device 4 of FIG.
- the current reduction transistor Q64 is turned ON by the voltage control circuit current reduction pulse A at the time tOO, and the input terminal of the voltage control circuit 60 is logically set. Set to low potential. As a result, the current path of the subsequent inverter circuit INV is interrupted. Next, from time tO to time t8, the photoelectric conversion element in Embodiment 1 is used. After the charge detection operation of the child PD is completed, the current reduction transistor Q65 is turned on by the voltage control circuit current reduction pulse B, and the voltage control circuit output voltage (gate of the correction signal line connection transistor Q62) is logically leveled.
- Charge detection in the floating diffusion amplifier type with the function of transferring the accumulated charge from the photoelectric conversion element PD to the charge detection unit (floating diffusion) as the potential at the photoelectric conversion element PD that converts the incident light into charges.
- the potential of the part (floating diffusion) can also be applied.
- FIG. 19 shows a circuit diagram
- FIG. 19 is a diagram showing a circuit configuration of the FDA-type MOS solid-state imaging device 5. In the figure, the horizontal output circuit 90 and the like are not shown.
- the accumulated charge of the photoelectric conversion element PD is transferred to the floating diffusion FD once by the transfer transistor Q11, and the potential of the floating diffusion is output as a voltage by the voltage conversion amplification transistor Q13a.
- Fig. 20 shows the timing when there is high-intensity incidence.
- the RSVSS pulse and RSVDD pulse are turned ON.
- the saturation voltage of the photoelectric conversion element PD is input to the gate of the voltage level detection transistor Q13b, and the power supply voltage VDD is input to the source.
- the row selection transistor Q14 is turned on by the VSEL pulse of the pixel unit lOanl at time tl, a signal appears on the common column signal line Ln via the voltage conversion amplification transistor Q13a of the pixel unit 10a nl.
- the input of the voltage control circuit 60 is the power supply voltage VDD voltage (logically high), which is equivalent to the voltage level output to the common column signal line Ln, and is logically low.
- VDD voltage logically high
- the voltage control circuit output voltage becomes logically high, and the voltage of the correction signal line Ls is connected to the common column signal line Ln.
- the common column signal line connection transistor Q61 has its gate changed to a low level due to high luminance incidence, so that the output of the common column signal line Ln from the two-dimensional imaging region force is cut off.
- the reset transistors Q12a and Q12c are turned on by the RESET pulse at time t3
- the voltage of the correction signal line Ls that is, the same voltage as the common column signal line Ln from which the initialization voltage of the photoelectric conversion element PD is output is originally
- the common column signal line Ln is replaced with the output from the common column signal line Ln and input to the noise signal elimination circuit 40.
- the RSVSS pulse At time t3, after being clamped as an initialization signal by the CP pulse inside the noise signal elimination circuit 40, at time t5, at the timing when the accumulated signal level of the photoelectric conversion element PD is detected, the RSVSS pulse generates saturation voltage.
- the correction signal line Ls has the same voltage as the voltage level of the common column signal line Ln from which the saturation voltage of the photoelectric conversion element PD is output. As a result, it is replaced with the original common column signal line Ln output and input to the noise signal elimination circuit 40.
- time t6 correlated double sampling is performed in the noise signal removal circuit 40, and charge detection of the normal photoelectric conversion element PD from which noise is removed can be performed.
- Charge detection in the floating diffusion amplifier type with the function of transferring the accumulated charge from the photoelectric conversion element PD to the charge detection unit (floating diffusion) as the potential at the photoelectric conversion element PD that converts the incident light into charges.
- the initialization voltage of the part (floating diffusion) can also be applied.
- FIG. 21 shows a circuit diagram
- FIG. 21 is a diagram showing a circuit configuration of the FDA-type MOS solid-state imaging device 6. In the figure, the horizontal output circuit 90 and the like are not shown. [0132] The difference from the MOS type solid-state imaging device 4 is that the AMI type force of the pixel portion is also the FDI type. That is, in the pixel unit lObnl, the accumulated charge of the photoelectric conversion element PD is transferred to the floating diffusion FD by the transfer transistor Q11, and the potential of the floating diffusion FD is converted to a voltage by the voltage conversion amplification transistor Q13a and output. Is.
- Figure 22 shows the timing in the case of high-intensity incidence.
- the current reduction transistor Q64 is turned ON by the current reduction pulse A for the voltage control circuit, and the input terminal of the voltage control circuit 60 is set to the logically low potential. As a result, the current path of the subsequent inverter circuit INV is interrupted.
- the RSVSS pulse and RSVDD pulse are turned ON. As a result, the saturation voltage of the photoelectric conversion element PD is input to the gate of the voltage level detection transistor Q13b, and the power supply voltage VDD is input to the source.
- the row selection transistor Q14 of the pixel unit lObnl When the row selection transistor Q14 of the pixel unit lObnl is turned on by the VSEL pulse at time tl, a signal appears on the common column signal line Ln via the voltage conversion amplification transistor Q13a of the pixel unit lObnl, but high-intensity incident light is input. In this case, the voltage level output to the common column signal line Ln is drastically reduced, and the charge passes through the gate of the voltage level detection transistor Q13b, which is the source potential of the voltage level detection transistor Q13b.
- the input of the voltage control circuit 60 is the power supply voltage VDD voltage (logically high), which is equivalent to the voltage level output to the common column signal line Ln, and logically goes to the low potential. And change.
- the output signal level of the pixel unit is instantly set inside the solid-state image sensor by the MOS-type image sensor 403 realized by the solid-state image sensor. It is possible to realize a high-quality camera that can determine the position of the object and correct the signal at the time of high-intensity incidence.
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- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
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Priority Applications (3)
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CN200580022718XA CN1981517B (zh) | 2004-07-06 | 2005-07-04 | 固体摄像装置 |
US11/571,461 US7667171B2 (en) | 2004-07-06 | 2005-07-04 | Solid-state imaging device |
JP2006528891A JP4279880B2 (ja) | 2004-07-06 | 2005-07-04 | 固体撮像装置 |
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JP2004199803 | 2004-07-06 | ||
JP2004-199803 | 2004-07-06 |
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WO2006004096A2 true WO2006004096A2 (ja) | 2006-01-12 |
WO2006004096A1 WO2006004096A1 (ja) | 2006-01-12 |
WO2006004096A3 WO2006004096A3 (ja) | 2006-03-09 |
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Cited By (4)
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JP2010005212A (ja) * | 2008-06-27 | 2010-01-14 | Canon Inc | 放射線撮像装置、その制御方法及び放射線撮像システム |
JP2012073035A (ja) * | 2010-09-27 | 2012-04-12 | Olympus Corp | スペクトル情報測定方法、カラーセンサおよびバーチャルスライド装置 |
JP2016001713A (ja) * | 2014-05-23 | 2016-01-07 | パナソニックIpマネジメント株式会社 | 撮像装置 |
JP2020113859A (ja) * | 2019-01-10 | 2020-07-27 | キヤノン株式会社 | 光電変換装置及び光電変換システム |
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JP2000287131A (ja) * | 1998-12-25 | 2000-10-13 | Toshiba Corp | 固体撮像装置 |
JP2001024949A (ja) * | 1999-07-08 | 2001-01-26 | Canon Inc | 固体撮像装置及びそれを用いた撮像システム |
JP2004312700A (ja) * | 2003-03-25 | 2004-11-04 | Matsushita Electric Ind Co Ltd | 撮像装置及び撮像方法 |
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JP2000287131A (ja) * | 1998-12-25 | 2000-10-13 | Toshiba Corp | 固体撮像装置 |
JP2001024949A (ja) * | 1999-07-08 | 2001-01-26 | Canon Inc | 固体撮像装置及びそれを用いた撮像システム |
JP2004312700A (ja) * | 2003-03-25 | 2004-11-04 | Matsushita Electric Ind Co Ltd | 撮像装置及び撮像方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010005212A (ja) * | 2008-06-27 | 2010-01-14 | Canon Inc | 放射線撮像装置、その制御方法及び放射線撮像システム |
JP2012073035A (ja) * | 2010-09-27 | 2012-04-12 | Olympus Corp | スペクトル情報測定方法、カラーセンサおよびバーチャルスライド装置 |
US8884210B2 (en) | 2010-09-27 | 2014-11-11 | Olympus Corporation | Spectrum information measurement method, color sensor and virtual slide device |
JP2016001713A (ja) * | 2014-05-23 | 2016-01-07 | パナソニックIpマネジメント株式会社 | 撮像装置 |
JP2020113859A (ja) * | 2019-01-10 | 2020-07-27 | キヤノン株式会社 | 光電変換装置及び光電変換システム |
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Publication number | Publication date |
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JP4279880B2 (ja) | 2009-06-17 |
CN1981517B (zh) | 2010-05-26 |
CN1981517A (zh) | 2007-06-13 |
US20080061216A1 (en) | 2008-03-13 |
WO2006004096A3 (ja) | 2006-03-09 |
JPWO2006004096A1 (ja) | 2008-04-24 |
US7667171B2 (en) | 2010-02-23 |
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