WO2006003940A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2006003940A1
WO2006003940A1 PCT/JP2005/011955 JP2005011955W WO2006003940A1 WO 2006003940 A1 WO2006003940 A1 WO 2006003940A1 JP 2005011955 W JP2005011955 W JP 2005011955W WO 2006003940 A1 WO2006003940 A1 WO 2006003940A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
insulating film
barrier
barrier film
Prior art date
Application number
PCT/JP2005/011955
Other languages
French (fr)
Japanese (ja)
Inventor
Kouichi Nagai
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to CN2005800266413A priority Critical patent/CN1993828B/en
Priority to JP2006528750A priority patent/JP5202846B2/en
Publication of WO2006003940A1 publication Critical patent/WO2006003940A1/en
Priority to US11/647,198 priority patent/US8552484B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.
  • Ferroelectric Random Access Memory using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, excellent writing Z-reading durability, etc. It is a non-volatile memory with features, and further development is expected in the future.
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside.
  • a standard FeRAM ferroelectric capacitor in which a lower electrode made of a Pt film, a ferroelectric film made of a PZT film, and an upper electrode made of a Pt film are sequentially stacked,
  • the substrate is heated to a temperature of about 200 ° C in an atmosphere with a partial pressure of 40 Pa (0.3 Torr)
  • the ferroelectricity of the PbZr Ti O film PZT film
  • Patent Document 1 JP 2003-197878
  • Patent Document 2 JP 2001-68639 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2003-174145
  • Patent Document 4 Japanese Patent Laid-Open No. 2002-176149
  • Patent Document 5 Japanese Unexamined Patent Publication No. 2003-100994
  • Patent Document 6 JP 2001-36026 A
  • Patent Document 7 Japanese Unexamined Patent Publication No. 2001-15703
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. For this reason, it has been difficult for conventional FeRAMs to obtain good test results for the PTHS (Pressure Temperature Humidity Stress) test, which is one of the accelerated life tests.
  • PTHS Pressure Temperature Humidity Stress
  • the PTHS test is performed under conditions of, for example, a temperature of 135 ° C and a humidity of 85% based on the JEDEC (Joint Electron Device Engineering Council) standard.
  • JEDEC Joint Electron Device Engineering Council
  • An object of the present invention is to provide a semiconductor device that is excellent in resistance to hydrogen gas and moisture resistance, sufficiently suppresses deterioration of characteristics of a ferroelectric capacitor, and can improve PTHS characteristics, and its manufacture It is to provide a method.
  • a ferroelectric capacitor comprising: a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film; Is formed on the flat first barrier film for preventing the diffusion of moisture, the second barrier film having a planarized surface, and the second insulating film formed on the first barrier film.
  • a semiconductor device having a flat second barrier film that prevents diffusion of hydrogen or moisture.
  • a lower electrode, a ferroelectric film formed on the lower electrode, and a ferroelectric film formed on the semiconductor film are formed on the semiconductor substrate.
  • a ferroelectric capacitor having an upper electrode; a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film.
  • a semiconductor device is provided.
  • a lower electrode formed on a semiconductor substrate, a ferroelectric film formed on the lower electrode, and formed on the ferroelectric film.
  • a ferroelectric capacitor having an upper electrode, a first insulating film formed on the semiconductor substrate and the ferroelectric capacitor, the surface of which is flattened, and a shape formed on the first insulating film.
  • a flat first barrier film formed to prevent diffusion of hydrogen or moisture, a second insulating film formed on the first barrier film and having a flat surface, and the second insulating film A chip region formed on the semiconductor substrate and having a flat second barrier film for preventing diffusion of hydrogen or moisture; and a scribe portion provided on the semiconductor substrate adjacent to the chip region; At least one of the first Noria film and the second Noria film is the -Up territory A semiconductor device formed over the region and the scribe portion is provided.
  • a lower electrode, a ferroelectric film formed on the lower electrode, and an upper part formed on the ferroelectric film are formed on a semiconductor substrate.
  • a semiconductor device having a body capacitor a first insulating film formed on a semiconductor substrate and a ferroelectric capacitor and having a planarized surface and a first insulating film are formed on the first insulating film.
  • a flat second barrier film that prevents diffusion of hydrogen or moisture is formed, so that hydrogen and moisture are securely barriered, and the hydrogen and moisture reach the ferroelectric film of the ferroelectric capacitor. Can be reliably prevented.
  • deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • FIG. 1 is a plan view showing a chip configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing an area configuration of a chip surface layer of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a sectional view (No. 1) showing the structure of the semiconductor device according to the first embodiment of the invention.
  • FIG. 4 is a sectional view (No. 2) showing the structure of the semiconductor device according to the first embodiment of the invention.
  • FIG. 5 is a plan view (No. 1) showing a range where a noria film is formed in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a plan view (part 2) showing a range where a noria film is formed in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a transmission electron micrograph showing the result of cross-sectional observation of the SOG film in which the ferroelectric capacitor is embedded.
  • FIG. 8 is a transmission electron micrograph showing the result of cross-sectional observation of the aluminum oxide film formed on the step by the ferroelectric capacitor.
  • FIG. 9 is a process cross-sectional view (part 1) for explaining inconvenience when a barrier film is formed on a coating type insulating film.
  • FIG. 10 is a cross-sectional view (part 2) for explaining the inconvenience when a barrier film is formed on a coating type insulating film.
  • FIG. 11 is a process cross-sectional view (part 1) for explaining another inconvenience when a noria film is formed on a coating type insulating film.
  • FIG. 12 is a process cross-sectional view (part 2) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
  • FIG. 11 is a process cross-sectional view (part 3) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
  • FIG. 12 is a process cross-sectional view (part 4) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
  • FIG. 15 is a graph showing the evaluation results of the barrier film by the temperature programmed desorption analysis method.
  • FIG. 16 is a diagram for explaining inconveniences when the noria film is formed relatively thick. is there.
  • FIG. 17 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 18 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 19 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 20 is a view for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 21 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 22 is a cross-sectional view illustrating a defect generated in a conductor plug embedded in an interlayer insulating film including a noria film.
  • FIG. 23 is a transmission electron micrograph observing defects generated in a conductor plug embedded in an interlayer insulating film including a NORA film.
  • FIG. 24 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 25 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 26 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 27 is a process cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 28 is a process cross-sectional view (part 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 29 is a process sectional view (No. 6) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 30 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. It is a surface view (part 7).
  • FIG. 31 is a process cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 32 is a process sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 33 is a process cross-sectional view (No. 10) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 34 is a process sectional view (No. 11) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 35 is a process cross-sectional view (part 12) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 36 is a process cross-sectional view (No. 13) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention
  • FIG. 37 is a process sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 38 is a process sectional view (No. 15) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 39 is a process cross-sectional view (No. 16) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 40 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 41 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 42 is a plan view showing a range where a barrier film is formed in the semiconductor device according to the second embodiment of the present invention.
  • FIG. 43 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 44 is a process sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the invention. It is a side view (part 2).
  • FIG. 45 is a process cross-sectional view (part 3) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 46 is a process cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 47 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 48 is a sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 49 is a plan view showing a range where a barrier film is formed in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 50 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 51 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
  • FIG. 52 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
  • FIG. 53 is a cross-sectional view (part 1) showing the structure of a FeRAM structure semiconductor device having a stack type cell to which the present invention is applied.
  • FIG. 54 is a sectional view (No. 2) showing the structure of the FeRAM structure semiconductor device having the stack type cell to which the present invention is applied.
  • FIG. 55 is a cross-sectional view showing the structure of the bonding pad when Cu wiring is used.
  • FIGS. 1-10 A semiconductor device and a manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
  • FIG. 1 is a plan view showing the chip configuration of the semiconductor device according to the present embodiment.
  • FIG. 2 is a plan view showing the area configuration of the chip surface layer of the semiconductor device according to the present embodiment.
  • Figure 1 (b) is a plan view showing the FeRAM chip region in one shot
  • FIG. 1 (a) is an enlarged plan view showing the FeRAM chip region in FIG. 1 (b).
  • Fig. 2 (a) is a plan view showing the area structure of the chip surface layer along the ⁇ - ⁇ 'line in Fig. 1 (a)
  • Fig. 2 (b) is along the 1- ⁇ ' line in Fig. 1 (a). It is a top view which shows the area structure of the chip
  • a plurality of FeRAM chip regions 302 are formed for each shot 300 on the semiconductor substrate 10. Between adjacent FeRAM chip regions 302, a scribe portion 304, which is a cutting region for dividing each FeRAM chip region 302 into FeRAM chips, is provided.
  • a FeRAM cell part 306 in which FeRAM cells are formed a peripheral circuit part 308 in which peripheral circuits of FeRAM are formed, a logic circuit part 310 in which logic circuits are formed, and a logic circuit Peripheral circuit portions 312 in which the peripheral circuits are formed are provided.
  • a pad portion 314 in which a bonding pad for connecting the chip circuit and an external circuit is formed is provided at the peripheral portion of the FeRAM chip region 302. Note that the pad portion 314 may be formed over all sides of the peripheral portion of the square FeRAM chip region 302 according to the type of FeRAM package or the like, or may be formed only on a pair of opposing sides. .
  • the area structure of the chip surface layer along the X—X 'line in Fig. 1 (a) is as follows. Scribe part 'pad part boundary part 316, pad part 314, pad part-circuit part boundary part 318, FeRAM cell part 306, circuit part-circuit part boundary part 320, logic circuit part 310, pad part-circuit part The boundary portion 318, the pad portion 314, the scribe portion and the pad portion boundary portion 316, and the scribe portion 304 are formed.
  • the area structure of the chip surface layer along the Y— line in Fig. 1 (a) is the scribe portion 304 and the scribe portion 'pad in order, with the heel side force also directed to the side.
  • FIGS. 3 and 4 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment
  • FIGS. 5 and 6 are plan views showing ranges in which a barrier film is formed in the semiconductor device according to the present embodiment.
  • FIG. 4 the cross-sectional structure across the FeRAM chip region 302 and the scribe portion 304 is shown as it is, but in FIG. 3, for convenience, the FeRAM chip portion 306, the peripheral circuit portion 308, and the pad portion that constitute the FeRAM chip region 302 are shown.
  • 314 is a simplified cross-sectional structure.
  • an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon.
  • a semiconductor substrate 10 made of, for example, silicon.
  • wells 14a and 14b are formed in the semiconductor substrate 10 in which the element isolation region 12 is formed.
  • a gate electrode (gate wiring) 18 is formed via a gate insulating film 16 on the semiconductor substrate 10 on which the wells 14a and 14b are formed.
  • the gate electrode 18 has, for example, a polycide structure in which a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • an insulating film 19 made of a silicon oxide film is formed on the gate electrode 18.
  • Sidewall insulating films 20 are formed on the side walls of the gate electrode 18 and the insulating film 19.
  • a source / drain diffusion layer 22 is formed on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed.
  • the transistor 24 having the gate electrode 18 and the source / drain diffusion layer 22 is formed.
  • the gate length of the transistor 24 is set to, for example, 0.35 / ⁇ ⁇ , or 0.11 to 0.18 / z m, for example.
  • a SiON film 25 having a thickness of, for example, 200 nm and a silicon oxide film 26 having a thickness of, for example, 600 nm are sequentially stacked.
  • an interlayer insulating film 27 is formed by sequentially laminating the Si ON film 25 and the silicon oxide film 26. The surface of the interlayer insulating film 27 is planarized.
  • a silicon oxide film 34 having a film thickness of lOOnm is formed on the interlayer insulating film 27, for example. Since the silicon oxide film 34 is formed on the planarized interlayer insulating film 27, the silicon oxide film 34 is flat.
  • a lower electrode 36 of the ferroelectric capacitor 42 is formed on the silicon oxide film 34.
  • the lower electrode 36 includes, for example, an aluminum oxide film 36a having a thickness of 20 to 50 nm and a thickness of 100 to It is composed of a laminated film in which a 200 nm Pt film 36b is sequentially laminated.
  • the film thickness of the Pt film 36b is set to 165 nm.
  • a ferroelectric film 38 of the ferroelectric capacitor 42 is formed on the lower electrode 36.
  • ferroelectric film 38 for example, a PbZrTiO film (PZT film) having a film thickness of 100 to 250 nm is used.
  • ferroelectric film 38 a 150 nm-thickness PZT film is used for the ferroelectric film 38.
  • the upper electrode 40 of the ferroelectric capacitor 42 is formed.
  • the upper electrode 40 includes, for example, an IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm.
  • IrO film 40a IrO film 40a
  • the film thickness is set to 50 nm, and the film thickness of the IrO film 40b is set to 200 nm.
  • the oxygen composition ratio Y of the O film 40b is set higher than the oxygen composition ratio X of the IrO film 40a.
  • the ferroelectric capacitor 42 including the lower electrode 36, the ferroelectric film 38, and the upper electrode 40 is configured.
  • a barrier film 44 is formed on the ferroelectric film 38 and the upper electrode 40 so as to cover the upper and side surfaces of the ferroelectric film 38 and the upper electrode 40.
  • the noria film 44 for example, an aluminum oxide (Al 2 O 3) film of 20 to 100 nm is used.
  • the barrier film 44 is a film having a function of preventing the diffusion of hydrogen and moisture.
  • the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen or moisture.
  • the electrical characteristics of the ferroelectric capacitor 42 Will deteriorate.
  • a noria film 46 is formed on the ferroelectric capacitor 42 and the silicon oxide film 34 covered with the noria film 44.
  • the noria film 46 for example, an aluminum oxide film having a film thickness of 20 to: LOOnm is used.
  • the barrier film 46 is a film having a function of preventing the diffusion of hydrogen and moisture, like the noria film 44.
  • the surface of the silicon oxide film 48 is flattened.
  • the silicon oxide film 48 is formed by, for example, a vapor phase growth method such as a CVD method or a MOCVD method.
  • the silicon oxide film 34, the barrier film 46, and the silicon oxide film 48 constitute an interlayer insulating film 49.
  • contact holes 50a and 50b reaching the source Z drain diffusion layer 22 are formed, respectively.
  • a contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 48, the barrier film 46, and the barrier film 44.
  • a contact hole 52b reaching the lower electrode 36 is formed in the silicon oxide film 48, the barrier film 46, and the barrier film 44.
  • a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm-thick Ti film and a 50 nm-thick TiN film, for example.
  • the Ti film is formed to reduce contact resistance
  • the TiN film is formed to prevent diffusion of tungsten, which is a conductor plug material.
  • the NORA metal film formed on each of the contact holes described later is also formed for the same purpose.
  • Conductor plugs 54a and 54b made of tungsten are embedded in the contact holes 50a and 50b in which the noria metal film is formed.
  • a wiring 56 a electrically connected to the conductor plug 54 a and the upper electrode 40 is formed on the silicon oxide film 48 and in the contact hole 52 a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 48 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 48.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially formed. It is comprised by the laminated film formed by laminating
  • the source Z drain diffusion layer 22 of the transistor 24 and the upper electrode 40 of the ferroelectric capacitor 42 are electrically connected via the conductor plug 54a and the wiring 56a, so that one transistor 24 and 1 FeRAM 1T1C memory cell with two ferroelectric capacitors 42 Is configured.
  • multiple memory cell powers are arranged in the memory cell area of the SFeRAM chip.
  • a noria film 58 is formed so as to cover the upper and side surfaces of the self-line 56a, 56b, 56c. ing.
  • a 20 nm aluminum oxide film is used as the noria film 58! /.
  • the barrier film 58 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44 and 46.
  • the barrier film 58 is also used to suppress damage caused by plasma.
  • the surface of the silicon oxide film 60 is flattened.
  • the flattened silicon oxide film 60 remains on the self-aligned wires 56a, 56b, and 56c with a film thickness of i lOOOnm.
  • a silicon oxide film 61 having a film thickness of lOOnm is formed on the silicon oxide film 60. Since the silicon oxide film 61 is formed on the flattened silicon oxide film 60, the silicon oxide film 61 is flat.
  • a noria film 62 is formed on the silicon oxide film 61.
  • an oxide aluminum film having a thickness of 20 to 70 nm is used as the noria film 62.
  • a 50 nm-thick aluminum oxide film is used as the noria film 62. Since the NORA film 62 is formed on the flat silicon oxide film 61, the barrier film 62 is flat.
  • the noria film 62 is a film having a function of preventing the diffusion of hydrogen and moisture. Further, the barrier film 62 is flat because it is formed on the flat silicon oxide film 61, and is formed with extremely good coverage as compared with the barrier films 44, 46, and 58. Therefore, such a flat NOR film 62 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 62 is formed not only in the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also in the FeRAM chip region 302 and the scribe part 304. In other words, it is formed over the adjacent FeRAM chip region 302. This point will be described later.
  • a silicon oxide film 64 having a film thickness of 50 to: LOOnm is formed on the noria film 62.
  • the thickness of the silicon oxide film 64 is set to lOOnm.
  • the silicon oxide film 64 functions as a stubbing film for etching when forming wirings 72a and 72b described later.
  • the silicon oxide film 64 protects the barrier film 62, and prevents the thickness of the barrier film 62 from being reduced or the removal of the NOR film 62 by etching when the wirings 72a and 72b are formed. be able to. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 62 from being deteriorated.
  • the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64 constitute the interlayer insulating film 66.
  • a contact hole 68 reaching the wiring 56c is formed.
  • a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm thick Ti film and a 50 nm thick TiN film, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • a conductive plug 70 made of tungsten is buried in the contact hole 68 in which the nore metal film is formed.
  • a wiring 72 a is formed on the interlayer insulating film 66.
  • a wiring 72b electrically connected to the conductor plug 70 is formed.
  • Wiring 72a, 72b (second metal wiring layer 72) is formed by sequentially laminating, for example, a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, a 5 nm thick Ti film, and a 150 nm thick TiN film. It is comprised by the laminated film which becomes. Note that the TiN film under the AlCu alloy film need not be formed.
  • a silicon oxide film 76 having a film thickness of lOOnm is formed on the silicon oxide film 74. Since the silicon oxide film 76 is formed on the flattened silicon oxide film 74, the silicon oxide film 76 is flat.
  • a noria film 78 is formed on the silicon oxide film 76.
  • the noria film 78 for example, an oxide-aluminum film having a film thickness of 20 to: LOOnm is used.
  • the barrier film 78 an aluminum oxide film having a thickness of 50 nm is used. Since the NORA film 78 is formed on the flat silicon oxide film 76, the barrier film 78 is flat.
  • the noria film 78 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44, 46, 58, and 62.
  • the NORA film 78 is flat because it is formed on the flat silicon oxide film 61, and is very good as compared with the barrier films 44, 46, and 58, like the NORIA film 62. It is formed with coverage. Therefore, diffusion of hydrogen and moisture can be prevented more reliably by using such a flat NOR film 62.
  • the NOR film 78 is not only the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitors 42 are arranged, but also the FeRAM chip area 302 and the scribe part, as in the barrier film 62. 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
  • a silicon oxide film 80 having a film thickness of 50 to: LOOnm is formed on the noria film 78, for example.
  • the thickness of the silicon oxide film 80 is set to lOOnm.
  • the silicon oxide film 80 functions as an etching stopper film when forming wirings 88a and 88b described later.
  • the silicon oxide film 80 protects the barrier film 78 and prevents the thickness of the barrier film 78 from being reduced or the removal of the noor film 62 due to etching when the wirings 88a and 88b are formed. Can do. As a result, it is possible to prevent the hydrogen and moisture diffusing functions of the NORA film 78 from being deteriorated.
  • the interlayer insulating film 82 is constituted by the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80.
  • contact holes 84a and 84b reaching the wirings 72a and 72b are formed, respectively.
  • a barrier metal film (not shown) is formed by sequentially laminating, for example, a Ti film with a thickness of 20 nm and a TiN film with a thickness of 50 nm, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • Conductor plugs 86a and 86b made of tungsten are embedded in the contact holes 84a and 84b in which the noria metal film is formed.
  • the wiring 88a electrically connected to the conductor plug 86a and the wiring electrically connected to the conductor plug 86b (bonding pad) 88b is formed on the interlayer insulating film 82 in which the conductor plugs 86a and 86b are embedded.
  • Wiring 88a, 88b (third metal wiring layer 88) For example, a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, and a 150 nm thick TiN film are sequentially stacked. Note that the TiN film under the AlCu alloy film need not be formed.
  • the thickness of the silicon oxide film 90 is set to lOOnm.
  • a silicon nitride film 92 having a thickness of 350 nm is formed on the silicon oxide film 90.
  • a laminated film 93 is formed by sequentially laminating the silicon oxide film 90 and the silicon nitride film 92 on the interlayer insulating film 82 and the wirings 88a and 88b.
  • a polyimide resin film 94 having a film thickness of 2 to 6 ⁇ m is formed on the silicon nitride film 92.
  • An opening 96 reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94, the silicon nitride film 92, and the silicon oxide film 90. That is, in the silicon nitride film 92 and the silicon oxide film 90, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92 and the silicon oxide film 90.
  • An external circuit (not shown) is electrically connected to the wiring (bonding pad) 88b through the opening 96.
  • FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to this embodiment corresponding to the area configuration shown in FIG. 5 and 6 are plan views showing ranges in which the barrier films 62 and 78 are formed in the semiconductor device according to the present embodiment, respectively.
  • an FeRAM cell unit 306 and a logic circuit unit 31 are formed on the semiconductor substrate 10.
  • transistor 24 is formed.
  • An interlayer insulating film 27 is formed on the entire surface of the semiconductor substrate 10 on which the transistor 24 is formed.
  • a ferroelectric capacitor 42 is formed on the interlayer insulating film 27 in the FeRAM cell portion 306.
  • An interlayer insulating film 49 is formed on the entire surface of the interlayer insulating film 27 on which the ferroelectric capacitor 42 is formed.
  • the first metal wiring layer 56 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314.
  • the first metal wiring layer 56 in the FeRAM cell portion 306 is appropriately electrically connected to the upper electrode 40, the lower electrode 36, or the transistor 24 of the ferroelectric capacitor 42 through a conductor plug.
  • the first metal wiring layer 56 in the logic circuit section 310 is appropriately electrically connected to the transistor 24 through a conductor plug.
  • An interlayer insulating film 66 is formed on the entire surface of the interlayer insulating film 49 on which the first metal wiring layer 56 is formed.
  • the noria film 62 constituting the interlayer insulating film 66 is formed over the FeRAM chip region 302 and the scribe portion 304 and adjacent to the FeRAM chip region 302. It is formed over to. That is, the noria film 62 includes a sliver portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a nod portion 314, and a scribe portion that is a boundary portion between them. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
  • the second metal wiring layer 72 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314.
  • the second metal wiring layer 72 is appropriately electrically connected to the first metal wiring layer 56 through a conductor plug.
  • An interlayer insulating film 82 is formed on the entire surface of the interlayer insulating film 66 on which the second metal wiring layer 72 is formed.
  • the noria film 78 constituting the interlayer insulating film 82 is formed over the FeRAM chip region 302 and the scribe portion 304 and adjacent to the FeRAM chip region 302. It is formed over to. That is, the noria film 78 includes a sliver 304, an FeRAM cell 306, an FeRAM peripheral circuit 308, and a logic circuit 310.
  • a third metal wiring layer 88 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314.
  • the third metal wiring layer 88 in the pad portion 314 is a bonding pad 88b.
  • the third metal wiring layer 88 is appropriately electrically connected to the second metal wiring layer 72 through a conductor plug.
  • a laminated film 93 is formed on the interlayer insulating film 82 on which the third metal wiring layer 88 is formed.
  • a polyimide resin film 94 is formed on the laminated film 93.
  • An opening 96 reaching the bonding pad 88 b is formed in the laminated film 93 and the polyimide resin film 94 in the nod portion 314.
  • a moisture-resistant ring 322 for suppressing the influence of humidity on the FeRAM chip is formed.
  • Insulation film 27, 49, 66, 82, 93 Insulation-resistant, moisture ring 322 ⁇ , and the like.
  • the moisture-resistant ring 322 is configured so as not to be short-circuited with the wiring in the FeRA M chip region 302! RU
  • the semiconductor device according to the present embodiment is configured.
  • a barrier film made of acid-aluminum or the like to be prevented is formed.
  • the coverage of the noria film is not so good, so hydrogen or moisture in the noria film. Can not sufficiently prevent the spread of.
  • a coating type insulating film such as an organic insulating film or a SOG (Spin On Glass) film is formed on a surface including irregularities due to a wiring layer, a ferroelectric capacitor, etc. It is difficult to make the surface of the mold insulating film sufficiently flat. For this reason, a step or an inclination occurs on the surface of the coating type insulating film.
  • FIG. 7 is a transmission electron micrograph showing the result of cross-sectional observation of the SOG film in which the ferroelectric capacitor is embedded.
  • a lower electrode 402 on the interlayer insulating film 400, a lower electrode 402, a ferroelectric film 404, an upper electrode 406, and a ferroelectric capacitor 408 that is powerful are formed.
  • the ferroelectric capacitor 408 is embedded with the SOG film 410.
  • a wiring 412 electrically connected to the upper electrode 406 is formed on the SOG film 410.
  • the surface of the SOG film 410 is not flat and has a gentle step.
  • the noria film made of an aluminum oxide film or the like is formed on the base having a step or inclination on the surface as described above, the thickness of the noria film becomes nonuniform.
  • FIG. 8 is a transmission electron micrograph showing the result of cross-sectional observation of an aluminum oxide film formed on a step by a ferroelectric capacitor.
  • the 50 nm aluminum oxide film 414 is formed almost uniformly on the substantially horizontal surface of the upper electrode 406.
  • the thickness of the acid aluminum film 414 decreases as it goes downward along the inclined surface in a section sandwiched by arrows in the figure.
  • FIG. 9 and FIG. 10 are process cross-sectional views for explaining inconveniences when a barrier film is formed on a coating type insulating film.
  • a ferroelectric capacitor 408 including a lower electrode 402, a ferroelectric film 404, and an upper electrode 406 is formed on the interlayer insulating film 400 (see FIG. 9 (a)).
  • an interlayer insulating film 416 made of a coating type insulating film such as an organic insulating film or an SOG film is formed on the interlayer insulating film 400 on which the ferroelectric capacitor 408 is formed (see FIG. 9B). .
  • the surface of the interlayer insulating film 416 is not sufficiently flat, and a step or tilt is generated on the surface of the interlayer insulating film 416.
  • a barrier film 418 made of an acid aluminum film, an acid oxide titanium film, or the like is formed on the interlayer insulating film 416 (see FIG. 9C).
  • the barrier film 418 is formed by a method other than the MOCVD method, the thickness of the barrier film 418 is reduced on the inclined surface of the interlayer insulating film 416 as compared to the horizontal plane of the interlayer insulating film 416.
  • a photoresist film 420 is formed by exposing a region where a contact hole is to be formed reaching the upper electrode 406 and the lower electrode 402 and covering the other region by photolithography (see FIG. 9D).
  • the noria film 418 and the interlayer insulating film 416 are etched using the photoresist film 420 as a mask.
  • a contact hole 422a reaching the upper electrode 406 and a contact hole 422b reaching the lower electrode 402 are formed in the noria film 418 and the interlayer insulating film 416, respectively (see FIG. 10A).
  • a metal film 424 for forming wiring is formed on the entire surface (see FIG. 10B).
  • a photolithography process is performed to form a photoresist film 426 that covers the regions where wirings to be connected to the upper electrode 406 and the lower electrode 402 are to be formed and exposes other regions (see FIG. 10 (c)). .
  • the metal film 424 is etched using the photoresist film 426 as a mask.
  • a wiring 428a made of the metal film 424 and connected to the upper electrode 406 and a wiring 428b made of the metal film 424 and connected to the lower electrode 402 are formed (see FIG. 10D).
  • the barrier film 418 is also used as an etching stopper film. For this reason, the noria film 418 is also etched and the film thickness is reduced.
  • the thickness of the barrier film 418 is thin due to the level difference or inclination of the base, the thickness of the thin film is significantly reduced by etching, and the noria film 418 is removed. There is. As a result, the noria film 418 cannot sufficiently exhibit the function of preventing the diffusion of hydrogen and moisture.
  • the film thickness of the noria film is set to lOOnm
  • the film thickness of the barrier film is reduced to 50 nm by etching on the horizontal plane by 50 nm, whereas the film thickness of the barrier film is reduced to 50 nm by etching.
  • a defect is generated when the barrier film is removed.
  • the thickness of the barrier film is set to 200 nm
  • the thickness of the barrier film is reduced to 150 nm by etching on the horizontal plane by 50 nm
  • the thickness of the barrier film is reduced to 150 nm by etching. Decreases to 0 to 50 nm, and a defect in which the noria film is removed occurs in part.
  • FIG. 11 to FIG. 14 are process cross-sectional views illustrating another inconvenience when a barrier film is formed on a coating type insulating film.
  • 11 and 12 show the case where a 50 nm-thick noria film is formed
  • FIGS. 13 and 14 show the case where a lOOnm-thick noria film is formed.
  • the wiring 434 is formed on the interlayer insulating film 432 in which the conductor plug 430 is embedded (see FIG. 11 (a)).
  • an interlayer insulating film 436 made of a coating type insulating film such as an organic insulating film or SOG film is formed on the interlayer insulating film 432 on which the wiring 434 is formed (see FIG. 11B).
  • the surface of the interlayer insulating film 436 is not sufficiently flat, and a step or an inclination occurs on the surface of the interlayer insulating film 436.
  • a barrier film 438 having a thickness of 50 nm is formed on the interlayer insulating film 436 (see FIG. 11C).
  • FIG. 12 is an enlarged cross-sectional view of the barrier film 438 shown in FIG. 11 (c).
  • the thickness of the noria film 438 is 50 nm.
  • the thickness of the noria film 438 is actually 20 nm or less.
  • the wiring 434 is formed on the interlayer insulating film 432 in which the conductor plug 430 is embedded (see FIG. 13 (a)).
  • an interlayer insulating film 436 made of a coating type insulating film such as an organic insulating film or an SOG film is formed on the interlayer insulating film 432 on which the wiring 434 is formed (see FIG. 13B).
  • the surface of the interlayer insulating film 436 is not sufficiently flat, and a step or an inclination occurs on the surface of the interlayer insulating film 436.
  • a barrier film 438 having a thickness of lOOnm is formed on the interlayer insulating film 436 (see FIG. 13C).
  • an interlayer insulating film 440 is formed on the barrier film 438 (see FIG. 13D).
  • FIG. 14 is an enlarged cross-sectional view of the barrier film 438 shown in FIG. 13 (c).
  • the film thickness of the noria film 438 is lOOnm.
  • the film thickness of the barrier film 438 is actually 20 to 50 nm. However, at the steepest portion of the inclined surface S, the thickness of the barrier film 438 is 20 nm or less.
  • the coverage is better than that of the film having a film thickness of 50 nm.
  • the film thickness of the noria film 438 is as thin as 20 nm or less. For this reason, the Noria film 438 cannot sufficiently exhibit the function of preventing the diffusion of hydrogen and moisture.
  • the film thickness on the horizontal plane is 100 nm, whereas a defect in which the noria film is not formed on the inclined surface occurs in part.
  • the film thickness on the horizontal plane is 200 nm, whereas the film thickness on the inclined surface is 50 to: LOOnm.
  • FIG. 15 is a graph showing the evaluation results of the barrier film by thermal desorption spectroscopy (TDS).
  • TDS thermal desorption spectroscopy
  • the horizontal axis indicates the substrate temperature
  • the vertical axis indicates the amount of hydrogen ions deposited with the sample strength.
  • the difference between the vertical axis in Fig. 15 (a) and the vertical axis in Fig. 15 (b) is due to the size of the area of the sample analyzed by TDS.
  • FIG. 15 (a) shows a case where a barrier film is formed on a base having a gentle step on the surface.
  • an SOG film was formed on a silicon substrate by a coating method, and then an oxide aluminum film was formed as a barrier film on the entire surface by a sputtering method.
  • the arrow marks indicate the case where no aluminum oxide film is formed.
  • the ⁇ mark indicates the case where the thickness of the aluminum oxide film is 20 nm.
  • the mouth mark indicates the case where the film thickness of the aluminum oxide film is 50 nm.
  • the arrow indicates the case where the thickness of the aluminum oxide film is lOOnm.
  • FIG. 15B shows a case where a barrier film is formed on a base having a flat surface, like the barrier films 62 and 78 in the semiconductor device according to the present embodiment.
  • a silicon oxide film was formed on a silicon substrate by plasma TEOSCVD, and then an oxide aluminum film was formed as a barrier film on the entire surface by sputtering.
  • the arrow marks indicate the case where no acid aluminum film is formed.
  • the ⁇ mark indicates the case where the thickness of the acid aluminum film is 10 nm.
  • the mouth mark shows the case where the thickness of the aluminum oxide film is 20 nm.
  • the arrow indicates the case where the thickness of the aluminum oxide film is 50 nm.
  • a circle indicates a case of only a silicon substrate.
  • a barrier film is formed on the base having a flat surface. It can be seen that the hydrogen ion deposition amount in the case of the film thickness is remarkably smaller than the hydrogen ion precipitation amount in the case where the film thickness is 10 nm, 20 nm, and 50 nm when the barrier film is not formed. From this, when the barrier film is formed on the base having a flat surface as in the semiconductor device according to the present embodiment, sufficient noreality with respect to hydrogen can be obtained, and the barrier film prevents hydrogen from diffusing. If it can be surely prevented.
  • the barrier property against moisture is basically linked to the barrier property against hydrogen, and when the noria property against hydrogen cannot be obtained, the noria property against moisture cannot also be obtained.
  • the TDS evaluation result for the noria property against moisture is similar to the evaluation result for the barrier property against hydrogen described above.
  • hydrogen is a substance smaller than water, so that it has a sufficiently flat surface to obtain a sufficient NORA for both hydrogen and water. It can be said that it is necessary to form a noria film.
  • the barrier film is formed with a relatively thick film thickness in order to obtain hydrogen and sufficient no-reactivity against hydrogen. It is possible.
  • the Noria film is formed relatively thick, for example, with a film thickness of lOOnm or more, there is a disadvantage that etching for forming the contact hole becomes difficult.
  • inconveniences when the noria film is formed to be relatively thick will be described with reference to FIG.
  • the conductor plug 444 that connects the upper electrode 406 of the ferroelectric capacitor 408 and the A1 wiring 442
  • the upper electrode 406 and the A1 wiring 442 A barrier film is formed in the interlayer insulating film between.
  • the thickness of the barrier film is relatively large, the width of the bottom of the contact hole 446 becomes narrower during etching to form the contact hole 446 in which the conductor plug 444 is embedded, and the contact resistance increases. Or contact failure occurs.
  • FIG. 16B is a sectional view showing the contact hole 446 in which the conductor plug 444 is embedded.
  • the width of the contact hole 446 on the A1 wiring 442 side is W
  • the width of the contact hole 446 bottom where the upper electrode 406 is exposed is 446.
  • the difference W-W between the two is defined as etch shift.
  • the etch shift is The contact resistance increased to 150 nm.
  • the etch shift was over 300 nm, resulting in poor contact.
  • the SOG film generally has a very high residual moisture in the film, although the film stress is small. For this reason, when an SOG film is used as an interlayer insulating film, if heat of 250 ° C or higher is applied in the subsequent process, the moisture in the SOG film reaches the ferroelectric capacitor, and the characteristics of the ferroelectric capacitor are It is thought that it will deteriorate.
  • the flat noria film formed on the flattened insulating film in the semiconductor device according to the present embodiment is Coverability is very good. Therefore, hydrogen and moisture can be reliably blocked by such a flat noria film, and hydrogen and moisture can be prevented from reaching the ferroelectric film of the ferroelectric capacitor.
  • FIG. 17 is a cross-sectional view showing a defect portion generated in a flat barrier film formed in a semiconductor device having a ferroelectric capacitor.
  • the semiconductor device shown in FIG. 17 unlike the semiconductor device according to the present embodiment, only one barrier film 78 is formed as a flat barrier film, and the noria film 62 is formed.
  • the defect portion 110 has a poor coverage due to a step caused by micro scratches generated on the surface of the underlying insulating film. Is considered to occur.
  • two flat barrier films that is, the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42, A flat barrier film 62 formed between the first metal wiring layer 72 and a flat noria film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed.
  • FIGS. 18 and 19 there may be a case where a defective portion 110 with poor coverage is generated in the two-layer flat barrier films 62 and 78. is assumed.
  • FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment
  • FIG. 19B is an enlarged plan view showing a region including the pad portion 314 shown in FIG. 19A.
  • the notch 110 formed in the two flat barrier films 62 and 78 is schematically shown.
  • the detailed mechanism is unknown. Since the two-layer barrier films 62 and 78 are formed, the residual film existing in the interlayer insulating film is present between the two-layer barrier films 62 and 78. It is considered that hydrogen is sealed, and residual hydrogen on the ferroelectric capacitor 42 is prevented from reaching the ferroelectric capacitor 42. Such other factors are also considered to prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 and improve the PTHS characteristics.
  • the two-layer barrier films 62 and 78 are formed as in the semiconductor device according to the present embodiment shown in FIG. 21, the residual hydrogen in the interlayer insulating film It will be sealed during 78. This prevents residual hydrogen on the ferroelectric capacitor 42 from reaching the ferroelectric capacitor 42. As a result, it is considered that the deterioration of the electrical characteristics of the ferroelectric capacitor 42 can be prevented and the PTHS characteristics can be improved.
  • the barrier films 62 and 78 are formed over the FeRAM chip region 302 and the scribe part 304, and are formed over the adjacent FeRAM chip region 302.
  • the main characteristic is that
  • the barrier film 62, 78 force FeRAM chip region 302 And the scribe part 304, and also extends to the adjacent FeRAM chip area 302, so that the hydrogen or moisture force above the FeRAM cell part 306 or lateral force enters the SFeRAM cell part 306. This can be surely prevented. Therefore, for example, it is possible to reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42 caused by leaving it for a long time in a high humidity environment.
  • the barrier films 62 and 78 which are not required to be formed relatively thick in order to ensure the coverage of the barrier films 62 and 78 are relatively thin. Can be formed. Therefore, when contact holes are formed in the interlayer insulating films 66 and 82 including the barrier films 62 and 78, the etch shift can be suppressed to 70 nm or less in each part in the FeRAM chip region 306. Thereby, an increase in contact resistance can be suppressed. In addition, it is possible to reliably form fine contact holes and contribute to miniaturization of semiconductor devices.
  • the flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed, so that hydrogen and moisture can be surely removed, and hydrogen and moisture can be removed. Can be reliably prevented from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • the flat barrier films 62 and 78 include the scribe part 304, the FeRAM cell part 306, the peripheral circuit part 308 of the FeRAM, the logic circuit part 310, and the peripheral circuit part of the mouth circuit. 312, pad part 314, scribe part which is a boundary part between them, pad part boundary part 316, pad part / circuit part boundary part 318, and circuit part / circuit part boundary part 320. Therefore, it is possible to more reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture.
  • the thickness of the barrier films 62 and 78 is preferably set to, for example, 50 nm or more and less than 100 nm, more preferably 50 nm or more and 80 nm or less, from the viewpoint described below.
  • the thickness of the barrier films 62 and 78 may be set to, for example, 40 nm or more and less than lOOnm, and more preferably 40 nm or more and 80 nm or less, from the viewpoint of preventing defects in the conductor plug. Hope U ,. This point will be described with reference to FIGS. 22 and 23.
  • FIG. 22 is a cross-sectional view illustrating a defect occurring in a conductor plug embedded in an interlayer insulating film including a barrier film.
  • FIG. 22 (a) shows the case where the barrier film is relatively thin
  • FIG. 22 (b) shows the case where the barrier film is relatively thick.
  • FIG. 23 is a transmission electron micrograph observing defects generated in the conductor plug embedded in the interlayer insulating film including the noria film.
  • a wiring layer 326 is formed on the interlayer insulating film 324.
  • An interlayer insulating film 330 including a flat noria film 328 is formed on the interlayer insulating film 324 on which the wiring layer 326 is formed.
  • a contact hole 332 reaching the wiring layer 326 is formed in the interlayer insulating film 330.
  • a conductor plug 334 made of tungsten is embedded in the contact hole 332.
  • a wiring layer 336 is formed on the interlayer insulating film 330 in which the conductor plug 334 is embedded.
  • the conductor plug 334 is sufficiently embedded in the contact hole 332 as shown in FIG. There is no defect in 334.
  • FIG. 23 (a) and FIG. 23 (b) are transmission electron micrographs observing defects generated in a conductor plug embedded in an interlayer insulating film including a noria film. It has been confirmed that such defects 338 occur at a high frequency when the film thickness force of the noria film becomes more than SlOOnm.
  • the thickness of the barrier films 62 and 78 is desirably set to, for example, 40 nm or more and less than lOOnm, and more preferably 40 nm or more and 80 nm or less, from the viewpoint of preventing defects in the conductor plug. .
  • the film thickness of the barrier films 62 and 78 is preferably set to 50 nm or more, for example.
  • the film thicknesses of the barrier films 62 and 78 are, for example, 50 nm or more and less than lOOnm. Preferably, it is set to 50 nm or more and 80 nm or less.
  • the transistors, wirings, etc. in the power logic circuit part 310, the peripheral circuit parts 308, 312, etc. which are basically explained using the process cross-sectional view corresponding to the cross-sectional structure of the semiconductor device shown in FIG. It can be formed using a normal semiconductor device manufacturing process.
  • the element isolation region 12 that defines the element region is formed on the semiconductor substrate 10 made of, for example, silicon by, for example, the LOCOS (LOCal Oxidation of Silicon) method.
  • LOCOS LOCal Oxidation of Silicon
  • dopants are introduced by ion implantation to form the wells 14a and 14b.
  • a transistor 24 having a gate electrode (gate wiring) 18 and a source Z drain diffusion layer 22 is formed in the element region by using a normal transistor formation method (see FIG. 24A). .
  • a 200 nm-thickness SiON film 25 is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition).
  • a silicon oxide film 26 of, eg, a 600 nm-thickness is formed on the entire surface by a plasma TEOSCVD method (see FIG. 24B).
  • the interlayer insulating film 27 is constituted by the SiON film 25 and the silicon oxide film 26.
  • the surface of the interlayer insulating film 27 is planarized by, eg, CMP (see FIG. 24 (c)).
  • the heat treatment is performed.
  • a silicon oxide film 34 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 25 (a)).
  • the heat treatment is performed.
  • heat treatment is performed in an oxygen atmosphere by, for example, RTA (Rapid Thermal Annealing).
  • the heat treatment temperature is, for example, 650 ° C.
  • the heat treatment time is, for example, 1-2 minutes.
  • a laminated film 36 composed of the aluminum oxide film 36a and the Pt film 36b is formed.
  • the multilayer film 36 becomes a lower electrode of the ferroelectric capacitor 42.
  • a ferroelectric film 38 is formed on the entire surface by, eg, sputtering.
  • a PZT film having a thickness of 100 to 250 nm is formed.
  • the ferroelectric film 38 is formed by the sputtering method has been described as an example, but the method of forming the ferroelectric film is not limited to the sputtering method.
  • the ferroelectric film may be formed by a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD method, or the like.
  • heat treatment is performed in an oxygen atmosphere by, for example, the RTA method.
  • the heat treatment temperature is, for example, 550 to 600 ° C
  • the heat treatment time is, for example, 60 to 120 seconds.
  • IrO having a film thickness of 25 to 75 nm is formed by sputtering or MOCVD.
  • a film 40a is formed.
  • heat treatment is performed in an atmosphere of argon and oxygen, for example, 600 to 800 ° C, 10 to: LOO seconds.
  • the IrO film 40b is formed so as to be higher than the composition ratio X.
  • the laminated film 40 including the IrO film 40a and the IrO film 40b is formed (see FIG. 25B).
  • the laminated film 40 becomes an upper electrode of the ferroelectric capacitor 42.
  • a photoresist film 98 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 98 is patterned into the planar shape of the upper electrode 40 of the ferroelectric capacitor 42 by photolithography.
  • the stacked film 40 is etched using the photoresist film 98 as a mask. etching
  • Ar gas and C1 gas are used as the gas.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 700 ° C for 30 to 120 minutes. This heat treatment is intended to prevent the surface of the upper electrode 40 from becoming abnormal.
  • a photoresist film 100 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 100 is patterned into the planar shape of the ferroelectric film 38 of the ferroelectric capacitor 42 by photolithography.
  • ferroelectric film 38 is etched using the photoresist film 100 as a mask (FIG. 26).
  • heat treatment is performed in an oxygen atmosphere, for example, at 300 to 400 ° C for 30 to 120 minutes.
  • the noria film 44 is formed by, for example, the snotter method or the CVD method (see FIG. 26B).
  • the noria film 44 for example, an aluminum oxide film having a thickness of 20 to 50 nm is formed.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • a photoresist film 102 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 102 is patterned into the planar shape of the lower electrode 36 of the ferroelectric capacitor 42 by photolithography.
  • the noria film 44 and the laminated film 36 are etched (see FIG. 26C).
  • the lower electrode 36 made of a laminated film is formed.
  • the noria film 44 remains so as to cover the upper electrode 40 and the ferroelectric film 38. Thereafter, the photoresist film 102 is peeled off.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • the barrier film 46 is formed on the entire surface by, eg, sputtering or CVD.
  • the noria film 46 for example, an oxide aluminum film having a film thickness of 20 to: LOOnm is formed (FIG. 27).
  • the noria film 46 is formed so as to further cover the ferroelectric capacitor 42 covered with the barrier film 44.
  • a silicon oxide film 48 made of a silicon oxide film having a thickness of, eg, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 27B).
  • the surface of the silicon oxide film 48 is flattened by, eg, CMP (see FIG. 27C).
  • This heat treatment is for removing moisture in the silicon oxide film 48 and changing the film quality of the silicon oxide film 48 so that the moisture does not easily enter the silicon oxide film 48.
  • the surface of the silicon oxide film 48 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 48.
  • contact holes 50a, 50b reaching the source / drain diffusion layer 22 are formed in the silicon oxide film 48, the barrier film 46, the silicon oxide film 34, and the interlayer insulating film 27 by photolithography and etching. (See FIG. 28 (a)).
  • a Ti film of, eg, a 20 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • the Ti film and the TiN film constitute a barrier metal film (not shown).
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film and the barrier metal film are polished by, for example, CMP until the surface of the silicon oxide film 48 is exposed.
  • the conductor plugs 54a and 54b made of tungsten are embedded in the contact holes 50a and 50b, respectively (see FIG. 28B).
  • a SiON film 104 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD.
  • the contact hole 52a reaching the upper electrode 40 of the ferroelectric capacitor 42 and the ferroelectric film are formed in the SiON film 104, the silicon oxide film 48, the barrier film 46, and the barrier film 44.
  • a contact hole 52a reaching the lower electrode 36 of the body capacitor 42 is formed (see FIG. 28 (c)).
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the heat treatment is performed in an oxygen atmosphere
  • the heat treatment may be performed in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen can be supplied to the ferroelectric film 38 of the capacitor, and the electrical characteristics of the ferroelectric capacitor 42 can be recovered.
  • the SiON film 104 is removed by etching.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • a barrier film 58 is formed on the entire surface by, eg, sputtering or CVD.
  • the noria film 58 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed (see FIG. 29B).
  • the noria film 58 an aluminum oxide film having a thickness of 20 nm is formed.
  • the barrier film 58 is formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, and 56c.
  • a silicon oxide film 60 of, eg, a 2600 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 30A).
  • the surface of the silicon oxide film 60 is flattened by, eg, CMP (see FIG. 30B).
  • a silicon oxide film 61 having a thickness of, for example, lOOnm is formed on the planarized silicon oxide film 60 by, eg, plasma TEOSCVD. Since the silicon oxide film 61 is formed on the planarized silicon oxide film 60, the silicon oxide film 61 becomes flat.
  • This heat treatment is for removing moisture in the silicon oxide film 61 and changing the film quality of the silicon oxide film 61 so that moisture does not easily enter the silicon oxide film 61.
  • the surface of the silicon oxide film 61 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 61.
  • a barrier film 62 is formed on the flat silicon oxide film 61 by, for example, sputtering or CVD.
  • the noria film 62 for example, an acid aluminum film having a thickness of 20 to 70 nm is formed.
  • an oxide aluminum film having a thickness of 50 nm is formed as the noor film 62. Since the barrier film 62 is formed on the flat silicon oxide film 61, the NOR film 62 becomes flat.
  • a noria film 62 is formed on a silicon oxide film 60 whose surface is flattened by the CMP method via a silicon oxide film 61. For this reason, it is possible to suppress the occurrence of a defective portion in the barrier film 62 due to a step or the like generated on the surface of the silicon oxide film 60 by the micro scratch.
  • the noor film 62 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304 and also to the adjacent FeRAM chip region 302. That is, the NORA film 62 is a scribe part 304, a FeRAM cell part 306, a peripheral circuit part 308 of the FeRAM, a logic circuit part 310, a peripheral circuit part 312 of the logic circuit, a node part 314, and a boundary part thereof.
  • the scribe portion is formed across the pad portion boundary portion 316, the pad portion and the circuit portion boundary portion 318, and the circuit portion and circuit portion boundary portion 320.
  • a silicon oxide film 64 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 32A).
  • An interlayer insulating film 66 is constituted by the conic acid film 64.
  • This heat treatment is for removing moisture in the silicon oxide film 64 and changing the film quality of the silicon oxide film 64 so that moisture does not easily enter the silicon oxide film 64.
  • the surface of the silicon oxide film 64 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 64.
  • contact holes reaching the wiring 56c are formed in the silicon oxide film 64, the noria film 62, the silicon oxide film 61, the silicon oxide film 60, and the barrier film 58 by photolithography and dry etching. 68 (see FIG. 32 (b)).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film is etched back until the surface of the silicon oxide film 64 is exposed, for example, by an EB (etch back) method.
  • the conductor plug 70 made of tandastain is embedded in the contact hole 68 (see FIG. 33 (a)).
  • an AlCu alloy film having a thickness of, for example, 500 nm, a Ti film having a thickness of, for example, 5 nm, and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the second metal wiring layer 72 that is, the wiring 72a and the wiring 72b electrically connected to the conductor plug 70 are formed (see FIG. 33B).
  • the silicon oxide film 64 functions as an etching stopper film.
  • the silicon oxide film 64 protects the barrier film 62, and prevents the thickness of the barrier film 62 from being reduced or the removal of the NOR film 62 by etching when the wirings 72a and 72b are formed. Can do. Thereby, it is possible to prevent the hydrogen and moisture diffusing function of the nore film 62 from being deteriorated.
  • a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 34 (a)).
  • the surface of the silicon oxide film 74 is flattened by, eg, CMP (see FIG. 34B).
  • This heat treatment is for removing moisture in the silicon oxide film 74 and changing the film quality of the silicon oxide film 74 so that the moisture does not easily enter the silicon oxide film 74.
  • the surface of the silicon oxide film 74 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 74.
  • a silicon oxide film 76 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD. Since the silicon oxide film 76 is formed on the planarized silicon oxide film 74, the silicon oxide film 76 becomes flat.
  • This heat treatment is for removing moisture in the silicon oxide film 76 and changing the film quality of the silicon oxide film 76 so that moisture does not easily enter the silicon oxide film 76.
  • the surface of the silicon oxide film 76 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 76.
  • a barrier film 78 is formed on the flat silicon oxide film 76 by, eg, sputtering or CVD.
  • the NOR film 78 for example, an acid aluminum film having a film thickness of 20 to 70 nm is formed.
  • an oxide aluminum film having a thickness of 50 nm is formed as the noria film 78. Since the barrier film 78 is formed on the flat silicon oxide film 76, the NOR film 78 becomes flat. Further, a noor film 78 is formed on the silicon oxide film 74 whose surface is flattened by the CMP method via the silicon oxide film 76. For this reason, it is possible to suppress the occurrence of a defective portion in the barrier film 78 due to a step or the like generated on the surface of the silicon oxide film 74 by the micro scratch.
  • the noria film 78 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304 and also to the adjacent FeRAM chip region 302. That is, the NORA film 78 is formed of the scribe portion 304, the FeRAM cell portion 306, and the FeRAM.
  • a silicon oxide film 80 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 36A).
  • the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80 constitute the interlayer insulating film 82.
  • This heat treatment is for removing moisture in the silicon oxide film 80 and changing the film quality of the silicon oxide film 76 so that the moisture does not easily enter the silicon oxide film 80.
  • the surface of the silicon oxide film 80 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 80.
  • contact holes 84a, 84b reaching the wirings 72a, 72b are formed on the silicon oxide film 80, the barrier film 78, the silicon oxide film 76, and the silicon oxide film 74 by photolithography and dry etching. (See Figure 36 (b)).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tandastain film is etched back by, for example, the EB method until the surface of the silicon oxide film 80 is exposed.
  • the inner surfaces of the contact holes 84a and 84b and the conductor plugs 86a and 86b made of tungsten are embedded (see FIG. 37 (a)).
  • an AlCu alloy film having a thickness of, for example, 500 nm and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the wiring electrically connected to the third metal wiring layer 88 that is, the conductor plug 86a.
  • a line 88a and a wiring 88b electrically connected to the conductor plug 86b are formed (see FIG. 37 (b)).
  • the silicon oxide film 80 functions as an etching stover film.
  • the silicon oxide film 80 protects the barrier film 78, and prevents the film thickness of the barrier film 78 from being reduced or removed from the etching when the wirings 88a and 88b are formed. Can do. As a result, it is possible to prevent the hydrogen and moisture diffusing functions of the NORA film 78 from deteriorating.
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • This heat treatment is for removing water in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that the water does not easily enter the silicon oxide film 90.
  • the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
  • the silicon nitride film 92 blocks moisture and the metal wiring layer 88,
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • an opening 108 is formed in the photoresist film 106 that exposes a region where an opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90.
  • Etch 90 an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90 (see FIG. 38B). Thereafter, the photoresist film 106 is peeled off.
  • a wiring (bonding pad) is formed on the polyimide resin film 94 by photolithography.
  • the FeRAM chip of the semiconductor device according to the present embodiment was stored under conditions of 2 atm, temperature 121 ° C, and humidity 100%, and 168 hours, 336 hours, 504 hours, 504 hours, and 672 At each time point, the presence or absence of defective cells was confirmed for each of the five chip samples formed using the same wafer.
  • the film thickness of the barrier film 58 was 20 nm
  • the film thickness of the flat barrier film 62 was 50 nm
  • the film thickness of the flat barrier film 78 was 70 nm.
  • the PTHS test similar to the above was performed when the flat noria film 58 was not formed, that is, when only one flat noria film was formed.
  • the thickness of the barrier film 58 was set to 70 nm
  • the thickness of the flat barrier film 78 was set to 70 nm.
  • the thickness of the noria film 58 was 2 Onm
  • the thickness of the flat barrier film 78 was 50 nm.
  • the structure of the semiconductor device according to Comparative Examples 1 and 2 was the same as that of the semiconductor device according to the present embodiment except that the flat barrier film 58 was not formed.
  • defective cells occur at all of 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours for all five chip samples. Hana was strong.
  • one of the five chip samples had one defective cell after 168 hours, and three defective cells after 336 hours.
  • 504 hours passed there were 10 defective cells, and when 672 hours passed, there were 18 bad cells.
  • a defective cell was not generated until 168 hours and 336 hours passed.
  • One defective cell was generated when 504 hours passed, and failed after 672 hours passed.
  • no defective cells were generated until 168 hours and 336 hours had passed.
  • At the end of 504 hours 22 defective cells were generated, and at the end of 672 hours, the number of defective senors reached 62.
  • the five chip samples only 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours have passed! /. Met.
  • the PTHS characteristic of the semiconductor device having the ferroelectric capacitor can be greatly improved, and the mass production certification level of the PTHS test for FeRAM is sufficiently exceeded. It was confirmed that it was possible.
  • the barrier film for preventing the diffusion of hydrogen and moisture is formed above the ferroelectric capacitor 42 in addition to the noria films 44, 46, and 58.
  • FIGS. 40 and 41 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment
  • FIG. 42 is a plan view showing the area where the barrier film is formed in the semiconductor device according to the present embodiment
  • FIGS. It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment.
  • the same components as those in the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that it further includes a barrier film 114 formed above the third metal wiring layer 88 (wirings 88a and 88b).
  • a silicon oxide film 112 having a thickness of 1500 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b.
  • the surface of the silicon oxide film 112 is flattened by, for example, CMP after the formation thereof, and the silicon oxide film 112 on the wiring 88b remains with a film thickness of, for example, 350 nm.
  • a noor film 114 is formed on the planarized silicon oxide film 112.
  • the barrier film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is used. Since the barrier film 114 is formed on the flattened silicon oxide film 112, the barrier film 114 is flat.
  • the noria film 114 is a film that has a function of preventing the diffusion of hydrogen and moisture.
  • the NORA film 114 is flat because it is formed on the flattened silicon oxide film 112, and compared with the NORA films 44, 46, and 58, like the barrier films 62 and 78. Thus, it is formed with extremely good coverage. Accordingly, such a flat barrier film 114 can more reliably prevent hydrogen and moisture from diffusing.
  • the NOR film 114 is not only the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the Fe RAM chip region 302, like the barrier films 62 and 78.
  • the scribe portion 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
  • the silicon oxide film 90 functions as a stubbing film for etching when a wiring (not shown) is formed.
  • the silicon oxide film 90 protects the barrier film 114, and prevents the film thickness of the barrier film 114 from being reduced or removed by etching during the formation of the wiring layer. it can. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 62 from being deteriorated.
  • a silicon nitride film 92 having a thickness of 350 nm is formed on the silicon oxide film 90.
  • a polyimide resin film 94 having a film thickness of 3 to 6 ⁇ m is formed on the silicon nitride film 92.
  • An opening 96 reaching the wiring (bonding pad) 88b is formed in the conoxide film 112. That is, in the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112, an opening 96a reaching the wiring (bonding pad) 88b is formed.
  • an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112. .
  • the noria film 114 is formed across the FeRAM chip area 302 and the scribe section 304 as shown in FIGS. 41 and 42, and adjacent FeRAM chip areas. It is formed over 302. That is, the noria film 114 includes a scribe portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a pad portion 314, and a sliver portion that is a boundary portion thereof. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
  • the semiconductor device according to the present embodiment is formed above the ferroelectric capacitor 42 over the barrier films 44, 46, 58 as a barrier film for preventing diffusion of hydrogen and moisture.
  • a flat barrier film 62 formed between the first metal wiring layer 56 (wirings 56a, 56b, 56c) and the second metal wiring layer 72 (wirings 72a, 72b), and a second metal wiring layer 72 (
  • a flat barrier film 114 formed between the first metal wiring layer 56 (wirings 56a, 56b, 56c) and the second metal wiring layer 72 (wirings 72a, 72b), and a second metal wiring layer 72 (
  • the flat noria film 114 is formed above the third metal wiring layer 88.
  • hydrogen and moisture can be more reliably blocked, and hydrogen and moisture can be more reliably prevented from reaching the ferroelectric film 38 of the ferroelectric capacitor 42.
  • deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved.
  • the flat barrier films 62, 78, and 114 are Eve portion 304, FeRAM cell portion 306, FeRAM peripheral circuit portion 308, logic circuit portion 310, logic circuit peripheral circuit portion 312, nod portion 314, and a scribe portion-pad portion boundary portion 316 that is a boundary portion thereof, pad Since it is formed over the boundary part 318 between the circuit part and the circuit part and the boundary part 320 between the circuit part and the circuit part, the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be prevented more reliably. Can do.
  • the third metal wiring layer (wiring 88a, wiring 88b) is formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.
  • a silicon oxide film 112 of, eg, a 1500 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 43 (a)).
  • the surface of the silicon oxide film 112 is flattened by, eg, CMP (see FIG. 43B).
  • This heat treatment is for removing moisture in the silicon oxide film 112 and changing the film quality of the silicon oxide film 112 so that moisture enters the silicon oxide film 112.
  • the surface of the silicon oxide film 112 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 112.
  • a noria film 114 is formed on the flattened silicon oxide film 112 by, for example, sputtering or CVD.
  • the noria film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the noria film 114 becomes flat.
  • the noria film 114 is formed so as to extend over the FeRAM chip region 302 and the scribe portion 304, and also into the adjacent FeRAM chip region 302. That is, the noria film 114 includes a scribe part 304, a FeRAM cell part 306, a peripheral circuit part 308 of FeRAM, a logic circuit part 310, a peripheral circuit part 312 of a logic circuit, a pad part 314, and a scribe part that is a boundary part between them. Pad part boundary 316, pad part 'circuit It is formed over the inter-part boundary 318 and the circuit part / inter-circuit part boundary 320.
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • This heat treatment is for removing water in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that the water does not easily enter the silicon oxide film 90.
  • the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD.
  • the silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • the opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112 through the photoresist film 106.
  • An opening 108 that exposes a region to be formed is formed.
  • the photoresist film 106 is peeled off.
  • Opening 96b reaching 88b is formed (see FIG. 46 (b)).
  • the semiconductor device according to the present embodiment is manufactured.
  • the barrier film that prevents diffusion of hydrogen and moisture is used as the barrier film 44, 46, 58, and is formed above the ferroelectric capacitor 42.
  • a flat barrier film 62 formed between the metal wiring layer 56 and the second metal wiring layer 72 and the second metal wiring Since it has a flat barrier film 78 formed between the line layer 72 and the third metal wiring layer 88 and a flat noria film 114 formed above the third metal wiring layer 88, hydrogen and moisture can be removed. Further, the barrier can be surely prevented, and hydrogen and moisture can be prevented more reliably from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be further reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved. .
  • FIGS. 47 and 48 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment
  • FIG. 49 is a plan view showing the area where the barrier film is formed in the semiconductor device according to the present embodiment
  • FIGS. It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the first embodiment in that it further includes a flat barrier film 116 between the ferroelectric capacitor 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). This is different from the semiconductor device.
  • the noria film 116 is formed on the silicon oxide film 48 in which the conductor plugs 50a and 50b are embedded.
  • the noria film 116 for example, an aluminum oxide film having a thickness of 20 to 70 nm is used.
  • the silicon oxide film 48 is flattened, and the noria film 116 is formed on the flattened silicon oxide film 48, the barrier film 116 becomes flat.
  • the noria film 116 is a film having a function of preventing the diffusion of hydrogen and moisture. Further, the noria film 116 is flat because it is formed on the flattened silicon oxide film 48, and is similar to the barrier films 62, 78 in comparison with the barrier films 44, 46, 58. It is formed with very good coverage. Therefore, such a flat barrier film 116 can more reliably prevent the diffusion of hydrogen and moisture. wear.
  • the NOR film 116 is not only the FeRAM cell section 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the FeRA M chip region 302, as in the barrier films 62 and 78.
  • the scribe portion 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
  • a silicon oxide film 118 having a thickness of lOOnm is formed on the oxide film 116.
  • the silicon oxide film 118 functions as an etching stopper film when forming wirings 56a, 56b, and 56c described later.
  • the barrier film 116 is protected by the silicon oxide film 118, and the film thickness of the barrier film 116 is reduced or the NOR film 116 is removed by etching when forming the wirings 56a, 56b, 56c. Can be prevented. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 116 from deteriorating.
  • the silicon oxide film 34, the barrier film 46, the silicon oxide film 48, the NOR film 116, and the silicon oxide film 118 constitute an interlayer insulating film 49.
  • a contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 118, the NORA film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44. Further, a contact hole 52b reaching the lower electrode 36 is formed in the silicon oxide film 118, the NORA film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44.
  • a contact hole 120a reaching the conductor plug 54a is formed in the silicon oxide film 118 and the barrier film 116.
  • a contact hole 120b reaching the conductor plug 54b is formed in the silicon oxide film 118 and the barrier film 116.
  • a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the silicon oxide film 118, in the contact hole 52a, and in the contact hole 120a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 118 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 118 and in the contact hole 120b.
  • the nore film 116 is formed over the FeRAM chip region 302 and the scribe part 304 as shown in FIGS.
  • the eRAM chip region 302 is formed. That is, the noria film 116 includes a scribe portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a pad portion 314, and a sliver portion that is a boundary portion thereof. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
  • the semiconductor device covers the ferroelectric capacitors 42 and the ferroelectric capacitors as barrier films 44, 46, 58 as barrier films for preventing the diffusion of hydrogen and moisture.
  • the main feature is that it has a flat noria film 78 formed between the layers 88b).
  • the flat barrier films 62, 78, 116 include the sliver part 304, the FeRAM cell part 306, the FeRAM peripheral circuit part 308, the logic circuit part 310, and the periphery of the logic circuit.
  • the circuit part 312, the nod part 314, and the boundary part between the scribe part and the pad part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320 are formed. Therefore, the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be prevented more reliably.
  • conductor plugs 54a and 54b are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 24 to 27, FIG. 28 (a), and FIG. see a)).
  • plasma cleaning is performed using, for example, argon gas.
  • argon gas As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 54a and 54b are removed.
  • the noria film 116 is formed on the silicon oxide film 48 in which the conductor plugs 54a and 54b are embedded by, for example, a sputtering method or a CVD method.
  • the noria film 114 for example, an aluminum oxide film having a film thickness of 20 to 70 nm is formed. Since the silicon oxide film 48 is flattened and the barrier film 116 is formed on the flattened silicon oxide film 48, the barrier film 116 becomes flat.
  • the noria film 116 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304, and also into the adjacent FeRAM chip region 302.
  • the NORA film 116 is composed of the scribe part 304, the FeRAM cell part 306, the peripheral circuit part 308 of the FeRAM, the logic circuit part 310, the peripheral circuit part 312 of the logic circuit, the pad part 314, and the scribe part that is the boundary between them. It is formed over the 'pad portion boundary portion 316, the pad portion' circuit portion boundary portion 318, and the circuit portion / circuit portion boundary portion 320.
  • a silicon oxide film 118 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 50B).
  • a SiON film 122 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD (see FIG. 52A).
  • the strong dielectric capacitor 42 is formed on the SiON film 122, the silicon oxide film 118, the noria film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44 by photolithography and dry etching.
  • a contact hole 52a reaching the upper electrode 40 and a contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 are formed (see FIG. 52 (b)).
  • heat treatment is performed in an oxygen atmosphere at, for example, 500 ° C for 60 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the SiON film 122 is removed by etching.
  • a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm, for example, are sequentially laminated on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • the silicon oxide film 118 functions as an etching stopper film.
  • the silicon oxide film 118 protects the barrier film 118, and prevents the thickness of the barrier film 118 from being reduced or the removal of the noria film 118 by etching when forming the wirings 56a, 56b, 56c. can do. Thereby, it is possible to prevent the hydrogen and moisture diffusion functions of the barrier film 118 from being deteriorated.
  • the ferroelectric capacitors 42 and the ferroelectric capacitors 42 are provided as a barrier film for preventing diffusion of hydrogen and moisture.
  • Reaching the ferroelectric film 38 of 42 can be prevented more reliably.
  • deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water can be prevented more reliably.
  • the PTHS characteristics of semiconductor devices with ferroelectric capacitors can be greatly improved.
  • the noria film 116 is formed after the conductor plugs 54a and 54b are formed has been described. However, the noria film 116 is formed before the conductor plugs 54a and 54b are formed. May be.
  • a silicon oxide film whose surface is planarized by a CMP method in the same manner as in the method for manufacturing the semiconductor device according to the first embodiment shown in FIGS. 24 to 27 (c). Form up to 48.
  • a noria film 116 is formed on the silicon oxide film 48 whose surface is flattened by the CMP method.
  • the silicon oxide film on the noria film 116, the noria film 116, the silicon oxide film 48, the noria film 46, the silicon oxide film 34, and the interlayer insulating film 27 are supplied with the source / Contact holes 50a and 50b reaching the drain diffusion layer 22 are formed.
  • conductor plugs 54a and 54b embedded in the contact holes 50a and 50b are formed.
  • the noria film 116 may be formed before the conductor plugs 50a and 50b are formed.
  • ferroelectric film 38 is not limited to the PZT film, but any other ferroelectric film. Can be used as appropriate.
  • the lower electrode 36 is configured by the laminated film of the acid aluminum film 36a and the Pt film 36b.
  • the material of the conductor film or the like that configures the lower electrode 36 is a material to be covered. It is not limited to.
  • the lower electrode 38 may be formed of a (muruthenium oxide) film (SRO film) or a Pd film.
  • the upper electrode 40 is formed of a laminated film of the IrO film 40a and the IrO film 40b.
  • the material of the conductor film that constitutes the upper electrode 40 is not limited to the material to be covered.
  • the upper electrode 40 is composed of an Ir film, Ru film, RuO film, SRO film, and Pd film.
  • the barrier film 62 is formed between the first metal wiring layer 56 and the second metal wiring layer 72, and the second metal wiring is formed. It described the case of forming the barrier film 78 between the layer 7 2 and the third metal wiring layer 88, above the third metal interconnect layer 88 in addition to Bruno Riamaku 62, 78 in the second implementation embodiment. In the third embodiment, a case where the barrier film 116 is formed between the ferroelectric capacitor 42 and the first metal wiring layer 56 in addition to the noria films 62 and 78 will be described. The combination of the barrier films 62, 78, 114 and 116 to be formed is not limited to the case described in the above embodiment.
  • the flat noria film is formed by at least two layers of the barrier films 62, 78, 114, and 116! It is sufficient to form three layers of the noria films 62, 78, 114, and 116. It is also possible to form all of the four layers of 62, 78, 114, and 116. Further, more flat noria films may be formed according to the number of metal wiring layers formed on the semiconductor substrate 10 and the like. In this case, the thickness of the flat barrier film is desirably set to, for example, 50 nm or more and less than lOOnm, more preferably 50 nm or more and 80 nm or less, as described in the first embodiment.
  • a flat noria film is first formed between the bonding pad and the uppermost metal wiring layer under the bonding pad. It is desirable that another flat barrier film be formed between other metal wiring layers! /.
  • the noria film is not limited to the acid aluminum film.
  • a film having a function of preventing diffusion of hydrogen or moisture can be appropriately used as the noria film.
  • the noria film for example, a film made of a metal oxide can be used as appropriate.
  • the barrier film made of a metal oxide for example, a film made of tantalate oxide, titanate oxide, or the like can be used.
  • the barrier film is not limited to a film made of a metal oxide.
  • a silicon nitride film (SiN film) or silicon nitride oxide film (SiON film) is used as a barrier film.
  • a coating type oxide film, or an organic film having a hygroscopic property such as a resin film made of polyimide, polyarylene, polyarylene ether, benzocyclobutene, or the like can be used as the NORA film.
  • barrier films made of the same material are used for all the barrier films to be formed.
  • barrier films made of different materials can be used as appropriate.
  • the oxide film aluminum is used as the NORA film 62 that is formed closest to the ferroelectric capacitor 42 side.
  • a silicon nitride film may be used as the barrier film 78 or the barrier film 114 formed above the barrier film 62.
  • a titanium oxide film may be formed on the aluminum oxide film.
  • the flat metal films 62 and 78 formed below the third metal wiring layer 88 are made of a metal oxide such as an oxide aluminum film.
  • a metal oxide such as an oxide aluminum film.
  • an inorganic film such as a film or a silicon nitride film is used.
  • An organic film having properties may be formed.
  • the case where the CMP method is used as a method for flattening the surface of the insulating film constituting the interlayer insulating film has been described as an example.
  • the method for flattening the surface of the insulating film is described below. It is not limited to the CMP method.
  • the surface of the insulating film may be planarized by etching.
  • As an etching gas for example, Ar gas can be used.
  • the circuit is formed on the semiconductor substrate 10 by the three metal wiring layers of the first metal wiring layer 56, the second metal wiring layer 72, and the third metal wiring layer 88.
  • the number of metal wiring layers constituting the circuit on the semiconductor substrate 10 is not limited to three. The number of metal wiring layers can be appropriately set according to the design of the circuit configured on the semiconductor substrate 10.
  • the configuration of the force memory cell described as an example in which a 1T1C type memory cell having one transistor 24 and one ferroelectric capacitor 42 is formed is limited to the 1T1C type. Is not to be done.
  • various configurations such as a 2T2C type having two transistors and two ferroelectric capacitors can be used.
  • the force described for the FeRAM structure semiconductor device having the planar type cell is not limited to this.
  • the present invention can be applied even to a FeRAM structure semiconductor device having a stack type cell and a gate length set to, for example, 0.18 ⁇ m.
  • FIG. 53 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having stacked cells to which the present invention is applied.
  • the structure other than the FeRAM cell portion 306 is shown by omitting the structure other than the NORA film.
  • an element isolation region 212 that defines an element region is formed on a semiconductor substrate 210 made of, for example, silicon.
  • a semiconductor substrate 210 made of, for example, silicon.
  • Wenore 214a and 214b forces are formed.
  • a gate electrode (gate wiring) 218 is formed on the semiconductor substrate 210 on which the wells 214a and 214b are formed via a gate insulating film 216.
  • the gate electrode 218 has, for example, a polycide structure in which a metal silicide film such as a cobalt silicide film, a nickel silicide film, or a tungsten silicide film is stacked on a polysilicon film in accordance with the gate length of the transistor.
  • a silicon oxide film 219 is formed on the gate electrode 218.
  • a sidewall insulating film 220 is formed on the side walls of the gate electrode 218 and the silicon oxide film 219.
  • a source / drain diffusion layer 222 is formed on both sides of the gate electrode 218 on which the sidewall insulating film 220 is formed.
  • a transistor 224 having a gate electrode 218 and a source Z drain diffusion layer 222 is formed.
  • the gate length of transistor 224 is set to 0.18 m, for example.
  • an interlayer insulating film 227 formed by sequentially laminating a SiON film 225 and a silicon oxide film 226 is formed on the semiconductor substrate 210 on which the transistor 224 is formed.
  • Interlayer insulating film 227 The surface of the surface is flattened.
  • a barrier film 228 made of, for example, an oxide aluminum film is formed on the interlayer insulating film 227.
  • a barrier metal film (not shown) formed by sequentially stacking a Ti film and a TiN film is formed in the contact holes 230a and 230b! Speak.
  • Conductor plugs 232a and 232b made of tungsten are embedded in the contact holes 230a and 230b in which the rare metal film is formed.
  • An Ir film 234 electrically connected to the conductor plug 232a is formed on the noria film 228.
  • the lower electrode 236 of the ferroelectric capacitor 242 is formed.
  • a ferroelectric film 238 of the ferroelectric capacitor 242 is formed on the lower electrode 236, a ferroelectric film 238 of the ferroelectric capacitor 242 is formed.
  • the upper electrode 240 of the ferroelectric capacitor 242 is formed.
  • the upper electrode 240, the ferroelectric film 238, the lower electrode 236, and the Ir film 234 that are stacked are patterned together by etching and have substantially the same planar shape.
  • the ferroelectric capacitor 242 composed of the lower electrode 236, the ferroelectric film 238, and the upper electrode 240 is formed.
  • the lower electrode 236 of the ferroelectric capacitor 242 is electrically connected to the conductor plug 232a via the Ir film 234.
  • a SiON film 244 having a film thickness approximately the same as that of the Ir film 234 or thinner than the Ir film 234 is formed.
  • a silicon oxide film may be formed.
  • a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed on the ferroelectric capacitor 242 and the SiON film 244.
  • a silicon oxide film 248 is formed on the noria film 246 and is strongly attracted by the silicon oxide film 248. Electric capacitor 242 is embedded! The surface of the silicon oxide film 248 is flattened.
  • the NORA film 250 includes a scribe part 304, a FeRA M cell part 306, a peripheral circuit part (not shown) of the FeRAM, a logic circuit part 310, a peripheral circuit part (not shown) of the logic circuit, and a pad part 314.
  • the boundary portion 316 between the scribe portion and the pad portion, the boundary portion 318 between the pad portion and the circuit portion, and the boundary portion 320 between the circuit portion and the circuit portion are formed.
  • a silicon oxide film 252 is formed on the noria film 250.
  • the SiON film 244, the noria film 246, the silicon oxide film 248, the noria film 250, and the silicon oxide film 252 constitute the interlayer insulating film 253.
  • a contact hole 254a reaching the upper electrode 240 of the ferroelectric capacitor 242 is formed in the silicon oxide film 252, the NORA film 250, the silicon oxide film 248, and the barrier film 246.
  • a contact hole 254b reaching the conductor plug 232b is formed in the silicon oxide film 252, the noria film 250, the silicon oxide film 248, the noria film 246, and the SiON film 244.
  • a barrier metal film (not shown) is formed in the contact holes 254a and 254b by sequentially stacking a Ti film and a TiN film. In addition, without forming the Ti film as the rare metal film
  • a barrier metal film made of a TiN film may be formed.
  • Conductor plugs 256a and 256b made of tungsten are embedded in the contact holes 254a and 254b in which the nore metal film is formed!
  • a silicon oxide film 260 is formed on the silicon oxide film 252 on which the wirings 258a and 258b are formed, and the wirings 258a and 258b are embedded by the silicon oxide film 260. Silicon acid The surface of the oxide film 260 is flattened.
  • a flat noria film 262 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • the noria film 262 for example, an aluminum oxide film is used.
  • the noria film 262 is formed over the FeRAM chip region 302 and the sliver portion 304, and is formed over the adjacent FeRAM chip region 302. That is, the NORA film 262 includes the scribe part 304, the FeRA M cell part 306, the peripheral circuit part (not shown) of the FeRAM, the logic circuit part 310, the peripheral circuit part (not shown) of the logic circuit, and the pad part 314.
  • the boundary portion 316 between the scribe portion and the pad portion, the boundary portion 318 between the pad portion and the circuit portion, and the boundary portion 320 between the circuit portion and the circuit portion are formed.
  • a silicon oxide film 264 is formed on the noria film 262.
  • the interlayer insulating film 265 is constituted by the silicon oxide film 260, the noria film 262, and the silicon oxide film 264.
  • a rare metal film (not shown) formed by sequentially laminating a Ti film and a TiN film is formed.
  • a conductor plug 270 made of tungsten is embedded in the contact hole 268 in which the noria metal film is formed!
  • a silicon oxide film 274 is formed on the silicon oxide film 264 on which the wiring 272 is formed, and the wiring 272 is embedded by the silicon oxide film 274.
  • the surface of the silicon oxide film 274 is flat.
  • a flat noria film 276 having a function of preventing the diffusion of hydrogen and moisture is formed on the flattened silicon oxide film 274.
  • a flat noria film 276 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • an aluminum oxide film is used as the noria film 276, for example.
  • the noria film 276 is formed over the FeRAM chip region 302 and the sliver portion 304, and is formed in the adjacent FeRAM chip region 302. It is formed all the way.
  • the noria film 276 includes a scribe part 304, a FeRA M cell part 306, a peripheral circuit part (not shown) of FeRAM, a logic circuit part 310, a peripheral circuit part (not shown) of a logic circuit, a pad part 314, These boundary portions are formed across a scribe portion'pad portion boundary portion 316, a pad portion / circuit portion boundary portion 318, and a circuit portion / circuit portion boundary portion 320.
  • the flat barrier films 250, 262, 276 that prevent the diffusion of hydrogen and moisture are used.
  • the flat noria film for preventing the diffusion of hydrogen and moisture is not necessarily formed in all three layers of the noria films 250, 262, and 276 as long as at least two layers are formed. Also good. Further, more flat noria films may be formed as necessary.
  • the wiring mainly composed of A1 has been described as an example.
  • the wiring is not limited to the wiring mainly composed of A1, and Cu is mainly composed by the damascene method or the like. You can also form wiring to be used.
  • FIG. 54 is a cross-sectional view showing the structure of the semiconductor device shown in FIG. 53 when Cu wiring is used
  • FIG. 55 is a cross-sectional view showing the structure of the bonding pad when Cu wiring is used.
  • FIG. 54 shows the structure of a FeRAM semiconductor device having a stack type cell as in FIG.
  • the same components as those of the semiconductor device illustrated in FIG. 53 are denoted by the same reference numerals, and description thereof will be omitted or simplified.
  • a silicon oxide film 260a is formed on the interlayer insulating film 253 in which the conductor plugs 256a and 256b made of tungsten are embedded.
  • Wiring grooves 280a and 280b are formed in the silicon oxide film 260a.
  • Cu wiring 282a electrically connected to conductor plug 256a is embedded in wiring groove 280a. It is rare.
  • Cu wiring 282b electrically connected to the conductor plug 256b is embedded in the wiring groove 280b.
  • the silicon oxide film 260a in which the Cu wirings 282a and 282b are embedded the silicon oxide film
  • a silicon oxide film 264 is formed on the noria film 262.
  • the interlayer insulating film 265 is constituted by the silicon oxide film 260, the noria film 262, and the silicon oxide film 264.
  • a contact hole 268 reaching the Cu wiring 282b is formed in the silicon oxide film 264, the NORA film 262, and the silicon oxide film 260b.
  • a film is formed by sequentially stacking, for example, a Ta film with a thickness of 15 nm and a Cu film with a thickness of 130 nm, for example.
  • a barrier metal film made of Ta film made of Ta film
  • a conductor plug 270 made of Cu is embedded in the contact hole 268 in which (not shown) is formed.
  • the bonding pad is made of a metal film mainly composed of A1, such as an AlCu alloy film.
  • a wiring trench 285 is formed in the interlayer insulating film 284 made of a silicon oxide film.
  • Cu wiring 286 is embedded in the wiring groove 285.
  • An interlayer insulating film 288 made of a silicon oxide film is formed on the interlayer insulating film 284 in which the Cu wiring 286 is embedded.
  • the silicon oxide film constituting the interlayer insulating film 288 is formed by, for example, a plasma TEOSCVD method.
  • It is composed of an AlCu alloy film.
  • a barrier film that prevents diffusion of hydrogen and moisture may be formed between the Cu wiring 286 and the bonding pad 292.
  • a silicon oxide film 294 is formed on the interlayer insulating film 288 and the bonding pad 292.
  • the silicon oxide film 294 is formed by plasma TEOSCVD, for example.
  • a silicon nitride film 296 is formed on the silicon oxide film 294.
  • an opening 299 reaching the bonding pad 292 is formed in the polyimide resin film 298, the silicon nitride film 296, and the silicon oxide film 294. That is, an opening 299 a reaching the bonding pad 292 is formed in the silicon nitride film 296 and the silicon oxide film 294. In the polyimide resin film 298, an opening 299b is formed in a region including the opening 299a formed in the silicon nitride film 296 and the silicon oxide film 294.
  • An external circuit (not shown) is electrically connected to the bonding pad 292 through the opening 299.
  • the wiring mainly composed of A1 instead of the wiring mainly composed of A1, the wiring mainly composed of Cu may be used.
  • a first flat noria film should be formed between the Cu wiring and the second flat noria film should be formed between the bonding node and the uppermost Cu wiring under the bonding pad.
  • moisture resistance can be further improved by further forming a flat noria film between other Cu wirings.
  • the semiconductor device and the manufacturing method thereof according to the present invention are useful for improving the reliability of a semiconductor device having a ferroelectric capacitor.

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Abstract

Disclosed is a semiconductor device comprising a ferroelectric capacitor (42) formed on a semiconductor substrate (10) and having a lower electrode (36), a ferroelectric film (38) formed on the lower electrode (36) and an upper electrode (40) formed on the ferroelectric film (38); a silicon oxide film (60) formed over the semiconductor substrate (10) and the ferroelectric capacitor (42) and having a planarized surface; a flat barrier film (62) formed on the silicon oxide film (60) via a silicon oxide film (61) for preventing diffusion of hydrogen or moisture; a silicon oxide film (74) formed on the barrier film (62) and having a planarized surface; and a flat barrier film (78) formed on the silicon oxide film (74) via a silicon oxide film (76) for preventing diffusion of hydrogen or moisture.

Description

明 細 書  Specification
半導体装置及びその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、半導体装置及びその製造方法に係り、特に強誘電体キャパシタを有す る半導体装置及びその製造方法に関する。  TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.
背景技術  Background art
[0002] 近時、キャパシタの誘電体膜として強誘電体膜を用いることが注目されて 、る。この ような強誘電体キャパシタを用いた強誘電体メモリ (FeRAM : Ferroelectric Random Access Memory)は、高速動作が可能である、低消費電力である、書き込み Z読み出 し耐久性に優れている等の特徴を有する不揮発性メモリであり、今後の更なる発展が 見込まれている。  Recently, attention has been paid to the use of a ferroelectric film as a dielectric film of a capacitor. Ferroelectric Random Access Memory (FeRAM) using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, excellent writing Z-reading durability, etc. It is a non-volatile memory with features, and further development is expected in the future.
[0003] し力しながら、強誘電体キャパシタは、外部からの水素ガスや水分により容易にそ の特性が劣化するという性質を有している。具体的には、 Pt膜よりなる下部電極と、 P ZT膜よりなる強誘電体膜と、 Pt膜よりなる上部電極とが順次積層されてなる標準的 な FeRAMの強誘電体キャパシタの場合、水素分圧 40Pa (0. 3Torr)程度の雰囲 気にて 200°C程度の温度に基板を加熱すると、 PbZr Ti O膜 (PZT膜)の強誘電  [0003] However, the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. Specifically, in the case of a standard FeRAM ferroelectric capacitor in which a lower electrode made of a Pt film, a ferroelectric film made of a PZT film, and an upper electrode made of a Pt film are sequentially stacked, When the substrate is heated to a temperature of about 200 ° C in an atmosphere with a partial pressure of 40 Pa (0.3 Torr), the ferroelectricity of the PbZr Ti O film (PZT film)
1 -Χ X 3  1 -Χ X 3
性はほぼ失われてしまうことが知られている。また、強誘電体キャパシタが水分を吸着 した状態、或いは水分が強誘電体キャパシタの近傍に存在する状態にて熱処理を行 うと、強誘電体キャパシタの強誘電体膜の強誘電性は、著しく劣化してしまうことが知 られている。  It is known that sex is almost lost. In addition, if the heat treatment is performed with the ferroelectric capacitor adsorbing moisture or in the vicinity of the ferroelectric capacitor, the ferroelectricity of the ferroelectric film of the ferroelectric capacitor is significantly deteriorated. It is known to end up.
[0004] このような強誘電体キャパシタの性質のため、 FeRAMの製造工程においては、強 誘電体膜を形成した後のプロセスとして、可能な限り、水分の発生が少なぐ且つ低 温のプロセスが選択されている。また、層間絶縁膜を成膜するプロセスには、例えば 、水素の発生量の比較的少ない原料ガスを用いた CVD (Chemical Vapor Depositio n)法等による成膜プロセスが選択されている。  [0004] Due to the properties of such a ferroelectric capacitor, in the manufacturing process of FeRAM, as a process after forming a ferroelectric film, a process that generates as little moisture as possible and has a low temperature is possible. Is selected. As a process for forming an interlayer insulating film, for example, a film forming process by a CVD (Chemical Vapor Deposit) method using a source gas with a relatively small amount of hydrogen generation is selected.
[0005] さらには、水素や水分による強誘電体膜の劣化を防止する技術として、強誘電体キ ャパシタを覆うように酸ィ匕アルミニウム膜を形成する技術や、強誘電体キャパシタ上に 形成された層間絶縁膜上に酸ィ匕アルミニウム膜を形成する技術が提案されている。 酸ィ匕アルミニウム膜は、水素や水分の拡散を防止する機能を有している。このため、 提案されて 、る技術によれば、水素や水分が強誘電体膜に達するのを防止すること ができ、水素や水分による強誘電体膜の劣化を防止することが可能となる。このような 技術は、例えば特許文献 1〜7に記載されている。 [0005] Furthermore, as a technique for preventing the deterioration of the ferroelectric film due to hydrogen or moisture, a technique for forming an aluminum oxide film so as to cover the ferroelectric capacitor, or a technique for forming a ferroelectric capacitor on the ferroelectric capacitor. A technique for forming an aluminum oxide film on the formed interlayer insulating film has been proposed. The aluminum oxide film has a function of preventing diffusion of hydrogen and moisture. Therefore, according to the proposed technique, it is possible to prevent hydrogen and moisture from reaching the ferroelectric film, and it is possible to prevent deterioration of the ferroelectric film due to hydrogen and moisture. Such techniques are described in Patent Documents 1 to 7, for example.
特許文献 1 :特開 2003— 197878号公報  Patent Document 1: JP 2003-197878
特許文献 2 :特開 2001— 68639号公報  Patent Document 2: JP 2001-68639 A
特許文献 3 :特開 2003— 174145号公報  Patent Document 3: Japanese Patent Laid-Open No. 2003-174145
特許文献 4：特開 2002— 176149号公報  Patent Document 4: Japanese Patent Laid-Open No. 2002-176149
特許文献 5 :特開 2003— 100994号公報  Patent Document 5: Japanese Unexamined Patent Publication No. 2003-100994
特許文献 6 :特開 2001— 36026号公報  Patent Document 6: JP 2001-36026 A
特許文献 7 :特開 2001— 15703号公報  Patent Document 7: Japanese Unexamined Patent Publication No. 2001-15703
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] 上述のように、強誘電体キャパシタは外部からの水素ガスや水分により容易にその 特性が劣化するという性質を有している。このため、従来の FeRAMは、加速寿命試 験の一つである PTHS (Pressure Temperature Humidity Stress)試験について良好 な試験結果を得ることが困難であった。  [0006] As described above, the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. For this reason, it has been difficult for conventional FeRAMs to obtain good test results for the PTHS (Pressure Temperature Humidity Stress) test, which is one of the accelerated life tests.
[0007] 通常、 PTHS試験は、 JEDEC (Joint Electron Device Engineering Council)規格等 に基づき、例えば温度 135°C、湿度 85%の条件下で行われている。このような PTH S試験では、 FeRAMの水素に対する耐性や耐湿性が充分に確保されて ヽな 、と、 強誘電体キャパシタが劣化し、不良が発生してしまう。  [0007] Normally, the PTHS test is performed under conditions of, for example, a temperature of 135 ° C and a humidity of 85% based on the JEDEC (Joint Electron Device Engineering Council) standard. In such a PTHS test, if the FeRAM has sufficient hydrogen resistance and moisture resistance, the ferroelectric capacitor deteriorates and a defect occurs.
[0008] これまでに、水素や水分による強誘電体膜の劣化を防止する技術が提案されては V、るものの、強誘電体キャパシタを有する FeRAM等の半導体装置の PTHS特性を 向上し、 PTHS試験について量産認定レベルを充分に上回るような良好な試験結果 を得ることを可能とするには、これまでの技術は充分なものではなかった。  [0008] Although a technology for preventing the deterioration of the ferroelectric film due to hydrogen or moisture has been proposed so far, the PTHS characteristics of a semiconductor device such as FeRAM having a ferroelectric capacitor have been improved. Previous technologies have not been sufficient to allow the test to achieve good test results well above the mass production certification level.
[0009] 本発明の目的は、水素ガスに対する耐性及び耐湿性に優れ、強誘電体キャパシタ の特性の劣化を充分に抑制し、 PTHS特性を向上しうる半導体装置及びその製造 方法を提供することにある。 An object of the present invention is to provide a semiconductor device that is excellent in resistance to hydrogen gas and moisture resistance, sufficiently suppresses deterioration of characteristics of a ferroelectric capacitor, and can improve PTHS characteristics, and its manufacture It is to provide a method.
課題を解決するための手段  Means for solving the problem
[0010] 本発明の一観点によれば、半導体基板上に形成され、下部電極と、前記下部電極 上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極とを有する 強誘電体キャパシタと、前記半導体基板上及び前記強誘電体キャパシタ上に形成さ れ、表面が平坦化された第 1の絶縁膜と、前記第 1の絶縁膜上に形成され、水素又 は水分の拡散を防止する平坦な第 1のバリア膜と、前記第 1のバリア膜上に形成され 、表面が平坦化された第 2の絶縁膜と、前記第 2の絶縁膜上に形成され、水素又は 水分の拡散を防止する平坦な第 2のバリア膜とを有する半導体装置が提供される。  According to an aspect of the present invention, a lower electrode formed on a semiconductor substrate, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, A ferroelectric capacitor comprising: a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film; Is formed on the flat first barrier film for preventing the diffusion of moisture, the second barrier film having a planarized surface, and the second insulating film formed on the first barrier film. There is provided a semiconductor device having a flat second barrier film that prevents diffusion of hydrogen or moisture.
[0011] また、本発明の他の観点によれば、半導体基板上に形成され、下部電極と、前記 下部電極上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極 とを有する強誘電体キャパシタと、前記半導体基板上及び前記強誘電体キャパシタ 上に形成され、表面が平坦化された第 1の絶縁膜と、前記第 1の絶縁膜上に形成さ れ、水素又は水分の拡散を防止する平坦な第 1のバリア膜と、前記第 1のバリア膜上 に形成され、表面が平坦化された第 2の絶縁膜と、前記第 2の絶縁膜上に形成され、 水素又は水分の拡散を防止する平坦な第 2のバリア膜とを有するメモリセル部と、ボ ンディッグパッドが形成されたパッド部とを有し、前記第 1のバリア膜及び前記第 2の ノリア膜の少なくとも 、ずれかは、前記メモリセル部及び前記パッド部にわたって形 成されている半導体装置が提供される。  [0011] According to another aspect of the present invention, a lower electrode, a ferroelectric film formed on the lower electrode, and a ferroelectric film formed on the semiconductor film are formed on the semiconductor substrate. A ferroelectric capacitor having an upper electrode; a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film. A flat first barrier film for preventing diffusion of hydrogen or moisture, a second insulating film formed on the first barrier film and having a flat surface, and on the second insulating film A memory cell portion that is formed and has a flat second barrier film that prevents diffusion of hydrogen or moisture, and a pad portion on which a bond pad is formed, the first barrier film and the first barrier film 2 at least, the displacement of the noria film is determined by the memory cell portion and the pad portion. A semiconductor device is provided.
[0012] また、本発明の更に他の観点によれば、半導体基板上に形成され、下部電極と、 前記下部電極上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部 電極とを有する強誘電体キャパシタと、前記半導体基板上及び前記強誘電体キャパ シタ上に形成され、表面が平坦化された第 1の絶縁膜と、前記第 1の絶縁膜上に形 成され、水素又は水分の拡散を防止する平坦な第 1のバリア膜と、前記第 1のバリア 膜上に形成され、表面が平坦化された第 2の絶縁膜と、前記第 2の絶縁膜上に形成 され、水素又は水分の拡散を防止する平坦な第 2のバリア膜とを有するチップ領域と 、前記半導体基板に、前記チップ領域に隣接して設けられたスクライブ部とを有し、 前記第 1のノリア膜及び前記第 2のノリア膜の少なくともいずれかは、前記チップ領 域及び前記スクライブ部にわたって形成されている半導体装置が提供される。 [0012] According to still another aspect of the present invention, a lower electrode formed on a semiconductor substrate, a ferroelectric film formed on the lower electrode, and formed on the ferroelectric film. A ferroelectric capacitor having an upper electrode, a first insulating film formed on the semiconductor substrate and the ferroelectric capacitor, the surface of which is flattened, and a shape formed on the first insulating film. A flat first barrier film formed to prevent diffusion of hydrogen or moisture, a second insulating film formed on the first barrier film and having a flat surface, and the second insulating film A chip region formed on the semiconductor substrate and having a flat second barrier film for preventing diffusion of hydrogen or moisture; and a scribe portion provided on the semiconductor substrate adjacent to the chip region; At least one of the first Noria film and the second Noria film is the -Up territory A semiconductor device formed over the region and the scribe portion is provided.
[0013] また、本発明の更に他の観点によれば、半導体基板上に、下部電極と、前記下部 電極上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極とを 有する強誘電体キャパシタを形成する工程と、前記半導体基板上及び前記強誘電 体キャパシタ上に、第 1の絶縁膜を形成する工程と、前記第 1の絶縁膜の表面を平坦 化する工程と、前記第 1の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 1 のノリア膜を形成する工程と、前記第 1のバリア膜上に、第 2の絶縁膜を形成するェ 程と、前記第 2の絶縁膜の表面を平坦化する工程と、前記第 2の絶縁膜上に、水素 又は水分の拡散を防止する平坦な第 2のバリア膜を形成する工程とを有する半導体 装置の製造方法が提供される。  [0013] According to still another aspect of the present invention, a lower electrode, a ferroelectric film formed on the lower electrode, and an upper part formed on the ferroelectric film are formed on a semiconductor substrate. Forming a ferroelectric capacitor having electrodes; forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor; and planarizing a surface of the first insulating film. Forming a flat first noria film for preventing diffusion of hydrogen or moisture on the first insulating film; and forming a second insulating film on the first barrier film. And planarizing the surface of the second insulating film, and forming a flat second barrier film for preventing diffusion of hydrogen or moisture on the second insulating film. A method for manufacturing a semiconductor device is provided.
[0014] なお、本願明細書において、「基板上」、「強誘電体キャパシタ上」、「絶縁膜上」、「 配線層上」等の記載における「上」は、基板等の「直上」のみならず、「上方」をも含む ものとする。  In the specification of the present application, “above” in the description of “on the substrate”, “on the ferroelectric capacitor”, “on the insulating film”, “on the wiring layer”, etc. is only “immediately above” the substrate. It should also include “above”.
発明の効果  The invention's effect
[0015] 本発明によれば、半導体基板上に形成され、下部電極と、前記下部電極上に形成 された強誘電体膜と、強誘電体膜上に形成された上部電極とを有する強誘電体キヤ パシタを有する半導体装置にぉ 、て、半導体基板上及び強誘電体キャパシタ上に 形成され、表面が平坦化された第 1の絶縁膜と、第 1の絶縁膜上に形成され、水素又 は水分の拡散を防止する平坦な第 1のバリア膜と、第 1のバリア膜上に形成され、表 面が平坦化された第 2の絶縁膜と、第 2の絶縁膜上に形成され、水素又は水分の拡 散を防止する平坦な第 2のバリア膜とが形成されて 、るので、水素及び水分を確実 にバリアし、水素及び水分が強誘電体キャパシタの強誘電体膜に達するのを確実に 防止することができる。これにより、水素及び水分による強誘電体キャパシタの電気 的特性の劣化を確実に防止することができ、強誘電体キャパシタを有する半導体装 置の PTHS特性を大幅に向上することができる。  According to the present invention, a ferroelectric formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. In a semiconductor device having a body capacitor, a first insulating film formed on a semiconductor substrate and a ferroelectric capacitor and having a planarized surface and a first insulating film are formed on the first insulating film. Is formed on the flat first barrier film for preventing moisture diffusion, the second barrier film formed on the first barrier film, the flat surface, and the second insulating film. A flat second barrier film that prevents diffusion of hydrogen or moisture is formed, so that hydrogen and moisture are securely barriered, and the hydrogen and moisture reach the ferroelectric film of the ferroelectric capacitor. Can be reliably prevented. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
図面の簡単な説明  Brief Description of Drawings
[0016] [図 1]図 1は、本発明の第 1実施形態による半導体装置のチップ構成を示す平面図で ある。 [図 2]図 2は、図 2は、本発明の第 1実施形態による半導体装置のチップ表層のエリア 構成を示す平面図である。 FIG. 1 is a plan view showing a chip configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing an area configuration of a chip surface layer of the semiconductor device according to the first embodiment of the present invention.
[図 3]図 3は、本発明の第 1実施形態による半導体装置の構造を示す断面図 (その 1) である。  FIG. 3 is a sectional view (No. 1) showing the structure of the semiconductor device according to the first embodiment of the invention.
[図 4]図 4は、本発明の第 1実施形態による半導体装置の構造を示す断面図 (その 2) である。  FIG. 4 is a sectional view (No. 2) showing the structure of the semiconductor device according to the first embodiment of the invention.
[図 5]図 5は、本発明の第 1実施形態による半導体装置においてノリア膜が形成され ている範囲を示す平面図（その 1)である。  FIG. 5 is a plan view (No. 1) showing a range where a noria film is formed in the semiconductor device according to the first embodiment of the present invention.
[図 6]図 6は、本発明の第 1実施形態による半導体装置においてノリア膜が形成され て!、る範囲を示す平面図（その 2)である。  FIG. 6 is a plan view (part 2) showing a range where a noria film is formed in the semiconductor device according to the first embodiment of the present invention.
[図 7]図 7は、強誘電体キャパシタを埋め込む SOG膜の断面観察の結果を示す透過 型電子顕微鏡写真である。  FIG. 7 is a transmission electron micrograph showing the result of cross-sectional observation of the SOG film in which the ferroelectric capacitor is embedded.
圆 8]図 8は、強誘電体キャパシタによる段差上に形成された酸ィ匕アルミニウム膜の断 面観察の結果を示す透過型電子顕微鏡写真である。 [8] FIG. 8 is a transmission electron micrograph showing the result of cross-sectional observation of the aluminum oxide film formed on the step by the ferroelectric capacitor.
圆 9]図 9は、塗布型絶縁膜上にバリア膜を形成した場合の不都合を説明する工程 断面図（その 1)である。 [9] FIG. 9 is a process cross-sectional view (part 1) for explaining inconvenience when a barrier film is formed on a coating type insulating film.
圆 10]図 10は、塗布型絶縁膜上にバリア膜を形成した場合の不都合を説明するェ 程断面図（その 2)である。 [10] FIG. 10 is a cross-sectional view (part 2) for explaining the inconvenience when a barrier film is formed on a coating type insulating film.
[図 11]図 11は、塗布型絶縁膜上にノリア膜を形成した場合の他の不都合を説明す る工程断面図（その 1)である。  FIG. 11 is a process cross-sectional view (part 1) for explaining another inconvenience when a noria film is formed on a coating type insulating film.
圆 12]図 12は、塗布型絶縁膜上にバリア膜を形成した場合の他の不都合を説明す る工程断面図（その 2)である。 12] FIG. 12 is a process cross-sectional view (part 2) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
圆 13]図 11は、塗布型絶縁膜上にバリア膜を形成した場合の他の不都合を説明す る工程断面図（その 3)である。 [13] FIG. 11 is a process cross-sectional view (part 3) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
圆 14]図 12は、塗布型絶縁膜上にバリア膜を形成した場合の他の不都合を説明す る工程断面図（その 4)である。 [14] FIG. 12 is a process cross-sectional view (part 4) for explaining another inconvenience when a barrier film is formed on a coating type insulating film.
[図 15]図 15は、昇温離脱分析法によるバリア膜の評価結果を示すグラフである。  FIG. 15 is a graph showing the evaluation results of the barrier film by the temperature programmed desorption analysis method.
[図 16]図 16は、ノリア膜を比較的厚く形成した場合における不都合を説明する図で ある。 [FIG. 16] FIG. 16 is a diagram for explaining inconveniences when the noria film is formed relatively thick. is there.
[図 17]図 17は、本発明の第 1実施形態による半導体装置の効果を説明する図 (その FIG. 17 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
1)である。 1).
[図 18]図 18は、本発明の第 1実施形態による半導体装置の効果を説明する図 (その FIG. 18 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
2)である。 2).
[図 19]図 19は、本発明の第 1実施形態による半導体装置の効果を説明する図 (その FIG. 19 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
2)である。 2).
[図 20]図 20は、本発明の第 1実施形態による半導体装置の効果を説明する図 (その FIG. 20 is a view for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
3)である。 3).
[図 21]図 21は、本発明の第 1実施形態による半導体装置の効果を説明する図 (その FIG. 21 is a diagram for explaining the effect of the semiconductor device according to the first embodiment of the present invention.
4)である。 4).
[図 22]図 22は、ノリア膜を含む層間絶縁膜に埋め込まれた導体プラグに生じる欠損 を説明する断面図である。  FIG. 22 is a cross-sectional view illustrating a defect generated in a conductor plug embedded in an interlayer insulating film including a noria film.
[図 23]図 23は、ノ リア膜を含む層間絶縁膜に埋め込まれた導体プラグに生じた欠損 を観察した透過型電子顕微鏡写真である。  FIG. 23 is a transmission electron micrograph observing defects generated in a conductor plug embedded in an interlayer insulating film including a NORA film.
[図 24]図 24は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 1)である。  FIG. 24 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
[図 25]図 25は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 2)である。  FIG. 25 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 26]図 26は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 3)である。  FIG. 26 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 27]図 27は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 4)である。  FIG. 27 is a process cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
[図 28]図 28は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 5)である。  FIG. 28 is a process cross-sectional view (part 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 29]図 29は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 6)である。  FIG. 29 is a process sectional view (No. 6) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
[図 30]図 30は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 7)である。 FIG. 30 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. It is a surface view (part 7).
[図 31]図 31は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 8)である。  FIG. 31 is a process cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 32]図 32は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 9)である。  FIG. 32 is a process sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 33]図 33は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 10)である。  FIG. 33 is a process cross-sectional view (No. 10) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 34]図 34は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 11)である。  FIG. 34 is a process sectional view (No. 11) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 35]図 35は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 12)である。  FIG. 35 is a process cross-sectional view (part 12) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
[図 36]図 36は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 13)である。  FIG. 36 is a process cross-sectional view (No. 13) showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
[図 37]図 37は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 14)である。  FIG. 37 is a process sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 38]図 38は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 15)である。  FIG. 38 is a process sectional view (No. 15) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 39]図 39は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 16)である。  FIG. 39 is a process cross-sectional view (No. 16) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention;
[図 40]図 40は、本発明の第 2実施形態による半導体装置の構造を示す断面図（その FIG. 40 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention
1)である。 1).
[図 41]図 41は、本発明の第 2実施形態による半導体装置の構造を示す断面図 (その FIG. 41 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention.
2)である。 2).
[図 42]図 42は、本発明の第 2実施形態による半導体装置においてバリア膜が形成さ れて 、る範囲を示す平面図である。  FIG. 42 is a plan view showing a range where a barrier film is formed in the semiconductor device according to the second embodiment of the present invention.
[図 43]図 43は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 1)である。  FIG. 43 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
[図 44]図 44は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 2)である。 FIG. 44 is a process sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the invention. It is a side view (part 2).
[図 45]図 45は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 3)である。  FIG. 45 is a process cross-sectional view (part 3) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
[図 46]図 46は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 4)である。  FIG. 46 is a process cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
[図 47]図 47は、本発明の第 3実施形態による半導体装置の構造を示す断面図 (その FIG. 47 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
1)である。 1).
[図 48]図 48は、本発明の第 3実施形態による半導体装置の構造を示す断面図（その FIG. 48 is a sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention
2)である。 2).
[図 49]図 49は、本発明の第 3実施形態による半導体装置においてバリア膜が形成さ れて 、る範囲を示す平面図である。  FIG. 49 is a plan view showing a range where a barrier film is formed in the semiconductor device according to the third embodiment of the present invention.
[図 50]図 50は、本発明の第 3実施形態による半導体装置の製造方法を示す工程断 面図（その 1)である。  FIG. 50 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention;
[図 51]図 51は、本発明の第 3実施形態による半導体装置の製造方法を示す工程断 面図（その 2)である。  FIG. 51 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
[図 52]図 52は、本発明の第 3実施形態による半導体装置の製造方法を示す工程断 面図（その 3)である。  FIG. 52 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
[図 53]図 53は、本発明を適用したスタック型セルを有する FeRAM構造の半導体装 置の構造を示す断面図（その 1)である。  FIG. 53 is a cross-sectional view (part 1) showing the structure of a FeRAM structure semiconductor device having a stack type cell to which the present invention is applied.
[図 54]図 54は、本発明を適用したスタック型セルを有する FeRAM構造の半導体装 置の構造を示す断面図（その 2)である。  FIG. 54 is a sectional view (No. 2) showing the structure of the FeRAM structure semiconductor device having the stack type cell to which the present invention is applied.
[図 55]図 55は、 Cu配線を用いた場合におけるボンディングパッドの構造を示す断面 図である。  FIG. 55 is a cross-sectional view showing the structure of the bonding pad when Cu wiring is used.
符号の説明 Explanation of symbols
10· ··半導体基板 10 ··· Semiconductor substrate
12· ··素子分離領域  12 ... Element isolation region
14a、 14b…ゥエル 14a, 14b ... well
16· ··ゲート絶縁膜 …ゲート電極 16 ... Gate insulation film ... Gate electrode
…絶縁膜... Insulating film
···サイドウォール絶縁膜···ソース Zドレイン拡散層·· 'トランジスタ 〜SiON膜 ··· Sidewall insulating film ··· Source Z drain diffusion layer · 'Transistor to SiON film
…シリコン酸ィ匕膜 …層間絶縁膜 …シリコン酸ィ匕膜... Silicon oxide film ... Interlayer insulating film ... Silicon oxide film
···下部電極.... Lower electrode
a…酸ィ匕アルミニウム膜b- "PtH a… Oxidized aluminum film b- "PtH
…強誘電体膜... Ferroelectric film
···上部電極.... Upper electrode
a- --IrO膜 a- --IrO film
X X
b- · -IrO膜 b- · -IrO film
Υ Υ
···強誘電体キャパシタ···バリア膜 ··· Ferroelectric capacitor ··· Barrier film
…バリア膜 ... Barrier film
…シリコン酸ィ匕膜 …層間絶縁膜... Silicon oxide film ... Interlayer insulation film
a、 50b…コンタクトホールa、 52b…コンタク卜ホールa、 54b…導体プラグ …第 1金属配線層a、 56b、 56c"'st線···バリア膜 a, 50b ... contact hole a, 52b ... contact hole a, 54b ... conductor plug ... first metal wiring layer a, 56b, 56c "'st wire ... barrier film
…シリコン酸ィ匕膜 ···シリコン酸ィ匕膜 …バリア膜 ... Silicon oxide film .... Silicon oxide film ... Barrier film
…シリコン酸ィ匕膜 …層間絶縁膜... Silicon oxide film ... Interlayer insulation film
···コンタクトホール …導体プラグ …第 2金属配線層a, 72b…配線 …シリコン酸ィ匕膜 …シリコン酸ィ匕膜 …バリア膜 ... Contact hole ... Conductor plug ... Second metal wiring layer a, 72b ... Wiring ... Silicon oxide film ... Silicon oxide film ... Barrier film
…シリコン酸ィ匕膜 …層間絶縁膜a、 84b…コンタクトホ、a、 86b…導体プラグ …第 3金属配線層a, 88b…配線 …シリコン酸ィ匕膜 …シリコン窒化膜 …積層膜 ... Silicon oxide film ... Interlayer insulation films a and 84b ... Contact ho, a and 86b ... Conductor plugs ... Third metal wiring layers a and 88b ... Wiring ... Silicon oxide film ... Silicon nitride film ... Laminated film
…ポリイミド榭脂膜 、 96a, 96a…開口部 …フォトレジスト膜0…フォトレジスト膜2…フォトレジスト膜4-"SiONI... Polyimide resin film, 96a, 96a ... Opening ... Photoresist film 0 ... Photoresist film 2 ... Photoresist film 4- "SiONI
6…フォトレジスト膜8···開口部 110…欠陥部分 6 ... Photoresist film 8 ... opening 110… Defects
112…シリコン酸ィ匕膜  112 ... Silicon oxide film
114···バリア膜  114 ··· Barrier film
116···バリア膜  116 ··· Barrier film
118…シリコン酸ィ匕膜  118 ... Silicon oxide film
120a, 120b…コンタクトホーノレ 120a, 120b… Contact Honoré
122-"SiON膜 122- "SiON film
210…半導体基板  210 ... Semiconductor substrate
212···素子分離領域  212 ... Element isolation region
214a, 214b…ウエノレ  214a, 214b ... Uenore
216···ゲート絶縁膜  216 ... Gate insulation film
218···ゲー卜電極  218 ... Gate electrode
219···シリコン酸ィ匕膜  219 ... Silic acid film
220…サイドウォール絶縁膜 220… Side wall insulation film
222· ··ソース Zドレイン拡散層222 ... Source Z Drain diffusion layer
224· "トランジスタ 224 · "Transistor
225〜SiON膜  225-SiON film
226···シリコン酸ィ匕膜  226 ···· Silicon oxide film
227…層間絶縁膜  227… Interlayer insulating film
228…バリア膜  228… Barrier film
230a, 230b…コンタク卜ホール 230a, 230b ... Contact Hall
232a, 232b…導体プラグ232a, 232b ... Conductor plug
234-"Ir膜 234- "Ir film
236…下部電極  236 ... Bottom electrode
238···強誘電体膜  238 ... Ferroelectric film
240···上部電極  240 ··· Upper electrode
242…強誘電体キャパシタ 242… Ferroelectric capacitor
244-"SiON膜 246···バリア膜 244- "SiON film 246 ··· Barrier film
248…シリコン酸ィ匕膜  248 ... Silicon oxide film
250···バリア膜  250 ··· Barrier film
252···シリコン酸ィ匕膜  252 ... Silic acid film
253…層間絶縁膜  253 ... Interlayer insulating film
254a, 254b…コンタクトホール 254a, 254b… Contact hole
256a、 256b…導体プラグ 256a, 256b ... Conductor plug
258a, 258b…配線  258a, 258b ... wiring
260、 260a, 260b—シジ =fン酸ィ匕 H 260, 260a, 260b—Siji = f acid H
262…バリア膜 262 ... Barrier film
264…シリコン酸ィ匕膜  264… Silicon oxide film
265…層間絶縁膜  265… Interlayer insulation film
268···コンタクトホーノレ  268 ··· Contact Honoré
270…導体プラグ  270 ... Conductor plug
272…酉己線  272 ... Toshimi Line
274…シリコン酸ィ匕膜  274 ... Silicon oxide film
276···バリア膜  276 ··· Barrier film
278…シリコン酸ィ匕膜  278 ... Silicon oxide film
280a, 280b…配線溝  280a, 280b ... Wiring groove
282a、 282b- "Cu配線  282a, 282b- "Cu wiring
284…層間絶縁膜  284… Interlayer insulation film
285…配線溝  285 ... Wiring groove
286 Cu酉己線  286 Cu Line
288···シリコン酸ィ匕膜  288 ... Silic acid film
289···コンタク卜ホーノレ  289 .. Contact 卜 Honore
290…導体プラグ  290 ... Conductor plug
292…ボンディングパッド  292 ... Bonding pads
294…シリコン酸ィ匕膜 296· ··シリコン窒化膜 294 ... Silicon oxide film 296 ... Silicon nitride film
298· ··ポリイミド樹脂膜  298 ... Polyimide resin film
299、 299a, 299b…開口部  299, 299a, 299b… Opening
300·' '·ショット  300 '' 'shot
302·' •FeRAMチップ領域  302 · '• FeRAM chip area
304·' '·スクライブ部  304 '' Scribe Club
306·· •FeRAMセル部  306 · FeRAM cell section
308·· •FeRAMの周辺回路部 308 • Peripheral circuit section of FeRAM
310·· '·ロジック回路部 310 ··· Logic circuit
312·· '·ロジック回路の周辺回路部 312 '' Peripheral circuit part of logic circuit
314·· 'パッド部 314 'Pad
316·· -スクライブ部'パッド部間境界部 316 ·· -Scribe part 'pad part boundary part
318·· -パッド部 ·回路部間境界部318-Pad part-Boundary part between circuit parts
320·, -回路部 ·回路部間境界部320, -Circuit part
322·· '耐湿リング 322 ·· 'Moisture resistant ring
324·· -層間絶縁膜  324-Interlayer insulation film
326·· '配線層  326 'Wiring layer
328·· 'バリア膜  328 'Barrier film
330·· -層間絶縁膜  330 ...-Interlayer insulation film
332·· 'コンタクトホール  332 ... Contact hole
334·· -導体プラグ  334 ...-Conductor plug
336·· '配線層  336 ... 'Wiring layer
338·· '導体プラグの欠損  338 '
400·· -層間絶縁膜  400 ...
402·· -下部電極  402 ·· -Bottom electrode
404·· -強誘電体膜  404 ··· Ferroelectric film
406·· -上部電極  406-Upper electrode
408·· '強誘電体キャパシタ 410 SOG膜 408 ... 'Ferroelectric capacitor 410 SOG membrane
412…酉己線  412… Toshimi Line
414…酸ィ匕アルミニウム膜  414 ... Oxidized aluminum film
416…層間絶縁膜  416… Interlayer insulating film
418· ··バリア膜  418 ... Barrier membrane
420· ··フォトレジスト膜  420 ··· Photoresist film
422a, 422b…コンタク卜ホーノレ  422a, 422b… Contact Honoré
424…金属膜  424 ... Metal film
426· ··フォトレジスト膜  426 ... Photoresist film
428a, 428b…配線  428a, 428b ... wiring
430…導体プラグ  430 ... Conductor plug
432…層間絶縁膜  432 ... Interlayer insulating film
434…酉己線  434 ... Toshimi Line
436…層間絶縁膜  436… Interlayer insulating film
438· ··バリア膜  438 ... Barrier membrane
440· ··バリア膜  440 ... Barrier membrane
442"· A1酉己線  442 "· A1 Seimi Line
444· ··導体プラグ  444 ... Conductor plug
446· ··コンタクトホール  446 ... Contact hole
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0018] [第 1実施形態] [0018] [First embodiment]
本発明の第 1実施形態による半導体装置及びその製造方法を図 1乃至図 39を用 いて説明する。  A semiconductor device and a manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
[0019] (半導体装置） [0019] (Semiconductor device)
まず、本実施形態による半導体装置について図 1乃至図 23を用いて説明する。  First, the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0020] はじめに、本実施形態による半導体装置のチップ構成について図 1及び図 2を用い て説明する。図 1は本実施形態による半導体装置のチップ構成を示す平面図、図 2 は本実施形態による半導体装置のチップ表層のエリア構成を示す平面図である。図 1 (b)は 1ショットにおける FeRAMチップ領域を示した平面図であり、図 1 (a)は図 1 ( b)における FeRAMチップ領域を拡大して示した平面図である。図 2 (a)は図 1 (a)の Χ-Χ' 線に沿ったチップ表層のエリア構成を示す平面図であり、図 2 (b)は図 1 (a) Ύ—Ύ' 線に沿ったチップ表層のエリア構成を示す平面図である。 First, the chip configuration of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view showing the chip configuration of the semiconductor device according to the present embodiment. FIG. 2 is a plan view showing the area configuration of the chip surface layer of the semiconductor device according to the present embodiment. Figure 1 (b) is a plan view showing the FeRAM chip region in one shot, and FIG. 1 (a) is an enlarged plan view showing the FeRAM chip region in FIG. 1 (b). Fig. 2 (a) is a plan view showing the area structure of the chip surface layer along the Χ-Χ 'line in Fig. 1 (a), and Fig. 2 (b) is along the 1-Ύ' line in Fig. 1 (a). It is a top view which shows the area structure of the chip | tip surface layer.
[0021] 図 1に示すように、半導体基板 10には、ショット 300毎に、複数の FeRAMチップ領 域 302が形成されている。隣接する FeRAMチップ領域 302間には、各 FeRAMチッ プ領域 302を FeRAMチップに個片化するための切断領域であるスクライブ部 304 が設けられている。 As shown in FIG. 1, a plurality of FeRAM chip regions 302 are formed for each shot 300 on the semiconductor substrate 10. Between adjacent FeRAM chip regions 302, a scribe portion 304, which is a cutting region for dividing each FeRAM chip region 302 into FeRAM chips, is provided.
[0022] FeRAMチップ領域 302には、 FeRAMセルが形成された FeRAMセル部 306、 F eRAMの周辺回路が形成された周辺回路部 308、ロジック回路が形成されたロジッ ク回路部 310、及びロジック回路の周辺回路が形成された周辺回路部 312がそれぞ れ設けられている。また、 FeRAMチップ領域 302の周縁部には、チップ回路と外部 回路とを接続するためのボンディングパッドが形成されたパッド部 314が設けられて いる。なお、パッド部 314は、 FeRAMのパッケージの種類等に応じて、四角形状の FeRAMチップ領域 302周縁部のすべての辺にわたって形成されていてもよいし、 対向する一組の辺にのみ形成されて 、てもよ 、。  [0022] In the FeRAM chip region 302, a FeRAM cell part 306 in which FeRAM cells are formed, a peripheral circuit part 308 in which peripheral circuits of FeRAM are formed, a logic circuit part 310 in which logic circuits are formed, and a logic circuit Peripheral circuit portions 312 in which the peripheral circuits are formed are provided. In addition, a pad portion 314 in which a bonding pad for connecting the chip circuit and an external circuit is formed is provided at the peripheral portion of the FeRAM chip region 302. Note that the pad portion 314 may be formed over all sides of the peripheral portion of the square FeRAM chip region 302 according to the type of FeRAM package or the like, or may be formed only on a pair of opposing sides. .
[0023] 図 1 (a)における X— X' 線に沿ったチップ表層のエリア構成は、図 2 (a)に示すよう に、 X側から:^ 側に向力つて順に、スクライブ部 304、スクライブ部'パッド部間境界 部 316、パッド部 314、パッド部 ·回路部間境界部 318、 FeRAMセル部 306、回路 部 ·回路部間境界部 320、ロジック回路部 310、パッド部 ·回路部間境界部 318、パッ ド部 314、スクライブ部'パッド部間境界部 316、スクライブ部 304となっている。  [0023] As shown in Fig. 2 (a), the area structure of the chip surface layer along the X—X 'line in Fig. 1 (a) is as follows. Scribe part 'pad part boundary part 316, pad part 314, pad part-circuit part boundary part 318, FeRAM cell part 306, circuit part-circuit part boundary part 320, logic circuit part 310, pad part-circuit part The boundary portion 318, the pad portion 314, the scribe portion and the pad portion boundary portion 316, and the scribe portion 304 are formed.
[0024] 図 1 (a)における Y— 線に沿ったチップ表層のエリア構成は、図 2 (b)に示すよう に、 Υ側力も 側に向力つて順に、スクライブ部 304、スクライブ部'パッド部間境界 部 316、パッド部 314、パッド部 ·回路部間境界部 318、 FeRAMセル部 306、回路 部 ·回路部間境界部 320、 FeRAMの周辺回路部 308、回路部 ·回路部間境界部 3 20、ロジック回路の周辺回路部 312、パッド部'回路部間境界部 318、パッド部 314、 スクライブ部'パッド部間境界部 316、スクライブ部 304となっている。  [0024] As shown in Fig. 2 (b), the area structure of the chip surface layer along the Y— line in Fig. 1 (a) is the scribe portion 304 and the scribe portion 'pad in order, with the heel side force also directed to the side. 316, pad part 314, pad part-circuit part boundary part 318, FeRAM cell part 306, circuit part-circuit part boundary part 320, FeRAM peripheral circuit part 308, circuit part-circuit part boundary part 320, peripheral circuit portion 312 of the logic circuit, pad portion 'between circuit portion 318, pad portion 314, scribe portion' pad portion boundary portion 316, and scribe portion 304.
[0025] 次に、本実施形態による半導体装置の構造について図 3乃至図 6を用いて説明す る。図 3及び図 4は、本実施形態による半導体装置の構造を示す断面図、図 5及び図 6は本実施形態による半導体装置においてバリア膜が形成されている範囲を示す平 面図である。なお、図 4では、 FeRAMチップ領域 302及びスクライブ部 304にわたる 断面構造をそのまま示しているが、図 3では、便宜上、 FeRAMチップ領域 302を構 成する FeRAMチップ部 306、周辺回路部 308、パッド部 314をまとめて簡略ィ匕した 断面構造を示している。 Next, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. The 3 and 4 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment, and FIGS. 5 and 6 are plan views showing ranges in which a barrier film is formed in the semiconductor device according to the present embodiment. In FIG. 4, the cross-sectional structure across the FeRAM chip region 302 and the scribe portion 304 is shown as it is, but in FIG. 3, for convenience, the FeRAM chip portion 306, the peripheral circuit portion 308, and the pad portion that constitute the FeRAM chip region 302 are shown. 314 is a simplified cross-sectional structure.
[0026] 図 3に示すように、例えばシリコンよりなる半導体基板 10上には、素子領域を画定 する素子分離領域 12が形成されている。素子分離領域 12が形成された半導体基板 10内には、ゥエル 14a、 14bが形成されている。  As shown in FIG. 3, an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon. In the semiconductor substrate 10 in which the element isolation region 12 is formed, wells 14a and 14b are formed.
[0027] ゥエル 14a、 14bが形成された半導体基板 10上には、ゲート絶縁膜 16を介してゲ ート電極 (ゲート配線） 18が形成されている。ゲート電極 18は、例えば、ポリシリコン 膜上に、タングステンシリサイド膜等の金属シリサイド膜が積層されたポリサイド構造 を有している。ゲート電極 18上には、シリコン酸ィ匕膜よりなる絶縁膜 19が形成されて いる。ゲート電極 18及び絶縁膜 19の側壁部分には、サイドウォール絶縁膜 20が形 成されている。  A gate electrode (gate wiring) 18 is formed via a gate insulating film 16 on the semiconductor substrate 10 on which the wells 14a and 14b are formed. The gate electrode 18 has, for example, a polycide structure in which a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film. On the gate electrode 18, an insulating film 19 made of a silicon oxide film is formed. Sidewall insulating films 20 are formed on the side walls of the gate electrode 18 and the insulating film 19.
[0028] サイドウォール絶縁膜 20が形成されたゲート電極 18の両側には、ソース/ドレイン 拡散層 22が形成されている。こうして、ゲート電極 18とソース/ドレイン拡散層 22と を有するトランジスタ 24が構成されている。トランジスタ 24のゲート長は、例えば 0. 3 5 /ζ πι、或いは例えば 0. 11〜0. 18 /z mに設定されている。  A source / drain diffusion layer 22 is formed on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed. Thus, the transistor 24 having the gate electrode 18 and the source / drain diffusion layer 22 is formed. The gate length of the transistor 24 is set to, for example, 0.35 / ζ πι, or 0.11 to 0.18 / z m, for example.
[0029] トランジスタ 24が形成された半導体基板 10上には、例えば膜厚 200nmの SiON膜 25と、例えば膜厚 600nmのシリコン酸ィ匕膜 26とが順次積層されている。こうして、 Si ON膜 25とシリコン酸ィ匕膜 26とを順次積層してなる層間絶縁膜 27が形成されている 。層間絶縁膜 27の表面は平坦化されている。  [0029] On the semiconductor substrate 10 on which the transistor 24 is formed, a SiON film 25 having a thickness of, for example, 200 nm and a silicon oxide film 26 having a thickness of, for example, 600 nm are sequentially stacked. Thus, an interlayer insulating film 27 is formed by sequentially laminating the Si ON film 25 and the silicon oxide film 26. The surface of the interlayer insulating film 27 is planarized.
[0030] 層間絶縁膜 27上には、例えば膜厚 lOOnmのシリコン酸ィ匕膜 34が形成されている 。平坦化された層間絶縁膜 27上にシリコン酸ィ匕膜 34が形成されているため、シリコン 酸ィ匕膜 34は平坦となっている。  [0030] On the interlayer insulating film 27, for example, a silicon oxide film 34 having a film thickness of lOOnm is formed. Since the silicon oxide film 34 is formed on the planarized interlayer insulating film 27, the silicon oxide film 34 is flat.
[0031] シリコン酸ィ匕膜 34上には、強誘電体キャパシタ 42の下部電極 36が形成されている 。下部電極 36は、例えば、膜厚 20〜50nmの酸化アルミニウム膜 36aと膜厚 100〜 200nmの Pt膜 36bとを順次積層してなる積層膜により構成されている。ここでは、 Pt 膜 36bの膜厚は、 165nmに設定されている。 A lower electrode 36 of the ferroelectric capacitor 42 is formed on the silicon oxide film 34. The lower electrode 36 includes, for example, an aluminum oxide film 36a having a thickness of 20 to 50 nm and a thickness of 100 to It is composed of a laminated film in which a 200 nm Pt film 36b is sequentially laminated. Here, the film thickness of the Pt film 36b is set to 165 nm.
[0032] 下部電極 36上には、強誘電体キャパシタ 42の強誘電体膜 38が形成されている。 On the lower electrode 36, a ferroelectric film 38 of the ferroelectric capacitor 42 is formed.
強誘電体膜 38としては、例えば膜厚 100〜250nmの PbZr Ti O膜 (PZT膜）が  As the ferroelectric film 38, for example, a PbZrTiO film (PZT film) having a film thickness of 100 to 250 nm is used.
1 -X X 3  1 -X X 3
用いられている。ここでは、強誘電体膜 38には、膜厚 150nmの PZT膜が用いられて いる。  It is used. Here, a 150 nm-thickness PZT film is used for the ferroelectric film 38.
[0033] 強誘電体膜 38上には、強誘電体キャパシタ 42の上部電極 40が形成されている。  On the ferroelectric film 38, the upper electrode 40 of the ferroelectric capacitor 42 is formed.
上部電極 40は、例えば膜厚 25〜75nmの IrO膜 40aと、膜厚 150〜250nmの IrO  The upper electrode 40 includes, for example, an IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm.
X  X
膜 40bとを順次積層してなる積層膜により構成されている。ここでは、 IrO膜 40aの It is composed of a laminated film obtained by sequentially laminating the film 40b. Here, IrO film 40a
Y X Y X
膜厚は 50nmに設定され、 IrO膜 40bの膜厚は 200nmに設定されている。なお、 Ir  The film thickness is set to 50 nm, and the film thickness of the IrO film 40b is set to 200 nm. Ir
Y  Y
O膜 40bの酸素の組成比 Yは、 IrO膜 40aの酸素の組成比 Xより高く設定されてい The oxygen composition ratio Y of the O film 40b is set higher than the oxygen composition ratio X of the IrO film 40a.
Y X Y X
る。  The
[0034] こうして、下部電極 36と強誘電体膜 38と上部電極 40とからなる強誘電体キャパシタ 42が構成されている。  Thus, the ferroelectric capacitor 42 including the lower electrode 36, the ferroelectric film 38, and the upper electrode 40 is configured.
[0035] 強誘電体膜 38上及び上部電極 40上には、強誘電体膜 38及び上部電極 40の上 面及び側面を覆うようにバリア膜 44が形成されている。ノリア膜 44としては、例えば 2 0〜100nmの酸化アルミニウム（Al O )膜が用いられている。  A barrier film 44 is formed on the ferroelectric film 38 and the upper electrode 40 so as to cover the upper and side surfaces of the ferroelectric film 38 and the upper electrode 40. As the noria film 44, for example, an aluminum oxide (Al 2 O 3) film of 20 to 100 nm is used.
2 3  twenty three
[0036] バリア膜 44は、水素及び水分の拡散を防止する機能を有する膜である。強誘電体 キャパシタ 42の強誘電体膜 38に水素や水分が達すると、強誘電体膜 38を構成する 金属酸化物が水素や水分により還元されてしま ヽ、強誘電体キャパシタ 42の電気特 性が劣化してしまう。強誘電体膜 38及び上部電極 40の上面及び側面を覆うようにバ リア膜 44を形成することにより、強誘電体膜 38に水素及び水分が達するのが抑制さ れるため、強誘電体キャパシタ 42の電気的特性の劣化を抑制することが可能となる。  [0036] The barrier film 44 is a film having a function of preventing the diffusion of hydrogen and moisture. When hydrogen or moisture reaches the ferroelectric film 38 of the ferroelectric capacitor 42, the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen or moisture. The electrical characteristics of the ferroelectric capacitor 42 Will deteriorate. By forming the barrier film 44 so as to cover the upper surface and the side surfaces of the ferroelectric film 38 and the upper electrode 40, it is possible to suppress hydrogen and moisture from reaching the ferroelectric film 38. It is possible to suppress the deterioration of the electrical characteristics of the.
[0037] ノ リア膜 44により覆われた強誘電体キャパシタ 42上及びシリコン酸ィ匕膜 34上には 、 ノリア膜 46が形成されている。ノリア膜 46としては、例えば膜厚 20〜： LOOnmの酸 化アルミニウム膜が用いられて 、る。  A noria film 46 is formed on the ferroelectric capacitor 42 and the silicon oxide film 34 covered with the noria film 44. As the noria film 46, for example, an aluminum oxide film having a film thickness of 20 to: LOOnm is used.
[0038] バリア膜 46は、ノリア膜 44と同様に、水素及び水分の拡散を防止する機能を有す る膜である。 [0039] ノ リア膜 46上には、例えば膜厚 1500nmのシリコン酸ィ匕膜 48が形成されている。 シリコン酸ィ匕膜 48の表面は、平坦化されている。シリコン酸ィ匕膜 48は、例えば CVD 法、 MOCVD法等の気相成長法により形成されたものである。 The barrier film 46 is a film having a function of preventing the diffusion of hydrogen and moisture, like the noria film 44. A silicon oxide film 48 having a film thickness of 1500 nm, for example, is formed on the noria film 46. The surface of the silicon oxide film 48 is flattened. The silicon oxide film 48 is formed by, for example, a vapor phase growth method such as a CVD method or a MOCVD method.
[0040] シリコン酸ィ匕膜 34、バリア膜 46、及びシリコン酸ィ匕膜 48により層間絶縁膜 49が構 成されている。  [0040] The silicon oxide film 34, the barrier film 46, and the silicon oxide film 48 constitute an interlayer insulating film 49.
[0041] シリコン酸ィ匕膜 48、バリア膜 46、シリコン酸ィ匕膜 34、及び層間絶縁膜 27には、ソー ス Zドレイン拡散層 22に達するコンタクトホール 50a、 50bがそれぞれ形成されてい る。また、シリコン酸ィ匕膜 48、バリア膜 46、及びバリア膜 44には、上部電極 40に達す るコンタクトホール 52aが形成されている。また、シリコン酸ィ匕膜 48、バリア膜 46、及 びバリア膜 44には、下部電極 36に達するコンタクトホール 52bが形成されている。  In the silicon oxide film 48, the barrier film 46, the silicon oxide film 34, and the interlayer insulating film 27, contact holes 50a and 50b reaching the source Z drain diffusion layer 22 are formed, respectively. In addition, a contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 48, the barrier film 46, and the barrier film 44. Further, a contact hole 52b reaching the lower electrode 36 is formed in the silicon oxide film 48, the barrier film 46, and the barrier film 44.
[0042] コンタクトホール 50a、 50b内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nm の TiN膜とを順次積層してなるバリアメタル膜 (図示せず)が形成されている。ノ リアメ タル膜のうち Ti膜はコンタクト抵抗を低減するために形成され、 TiN膜は導体プラグ 材料のタングステンの拡散を防止するために形成されている。後述するコンタクトホ ールのそれぞれに形成されるノ リアメタル膜についても、同様の目的で形成されてい る。  In the contact holes 50a and 50b, a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm-thick Ti film and a 50 nm-thick TiN film, for example. Of the rare metal films, the Ti film is formed to reduce contact resistance, and the TiN film is formed to prevent diffusion of tungsten, which is a conductor plug material. The NORA metal film formed on each of the contact holes described later is also formed for the same purpose.
[0043] ノ リアメタル膜が形成されたコンタクトホール 50a、 50b内には、タングステンよりなる 導体プラグ 54a、 54bがそれぞれ埋め込まれて ヽる。  [0043] Conductor plugs 54a and 54b made of tungsten are embedded in the contact holes 50a and 50b in which the noria metal film is formed.
[0044] シリコン酸化膜 48上及びコンタクトホール 52a内には、導体プラグ 54aと上部電極 4 0とに電気的に接続された配線 56aが形成されている。また、シリコン酸ィ匕膜 48上及 びコンタクトホール 52b内には、下部電極 36に電気的に接続された配線 56bが形成 されている。また、シリコン酸ィ匕膜 48上には、導体プラグ 54bに電気的に接続された 配線 56cが形成されている。配線 56a、 56b、 56c (第 1金属配線層 56)は、例えば、 膜厚 150nmの TiN膜、膜厚 550nmの AlCu合金膜、膜厚 5nmの Ti膜、及び膜厚 1 50nmの TiN膜を順次積層してなる積層膜により構成されている。  A wiring 56 a electrically connected to the conductor plug 54 a and the upper electrode 40 is formed on the silicon oxide film 48 and in the contact hole 52 a. A wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 48 and in the contact hole 52b. On the silicon oxide film 48, a wiring 56c electrically connected to the conductor plug 54b is formed. For the wiring 56a, 56b, 56c (first metal wiring layer 56), for example, a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially formed. It is comprised by the laminated film formed by laminating | stacking.
[0045] こうして、トランジスタ 24のソース Zドレイン拡散層 22と強誘電体キャパシタ 42の上 部電極 40とが、導体プラグ 54a及び配線 56aを介して電気的に接続され、 1つのトラ ンジスタ 24及び 1つの強誘電体キャパシタ 42とを有する FeRAMの 1T1C型メモリセ ルが構成されている。実際には、複数のメモリセル力 SFeRAMチップのメモリセル領 域に配列されている。 [0045] Thus, the source Z drain diffusion layer 22 of the transistor 24 and the upper electrode 40 of the ferroelectric capacitor 42 are electrically connected via the conductor plug 54a and the wiring 56a, so that one transistor 24 and 1 FeRAM 1T1C memory cell with two ferroelectric capacitors 42 Is configured. Actually, multiple memory cell powers are arranged in the memory cell area of the SFeRAM chip.
[0046] 酉己線 56a、 56b、 56c力 S形成されたシリコン酸ィ匕膜 48上には、酉己線 56a、 56b、 56c の上面及び側面を覆うように、ノ リア膜 58が形成されている。ノ リア膜 58としては、例 えば 20nmの酸化アルミニウム膜が用いられて!/、る。  [0046] On the silicon oxide film 48 on which the self-line 56a, 56b, 56c force S is formed, a noria film 58 is formed so as to cover the upper and side surfaces of the self-line 56a, 56b, 56c. ing. For example, a 20 nm aluminum oxide film is used as the noria film 58! /.
[0047] ノ リア膜 58は、バリア膜 44、 46と同様に、水素及び水分の拡散を防止する機能を 有する膜である。また、バリア膜 58は、プラズマによるダメージを抑えるためにも用い られている。 [0047] The barrier film 58 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44 and 46. The barrier film 58 is also used to suppress damage caused by plasma.
[0048] ノ リア膜 58上には、例えば膜厚 2600nmのシリコン酸ィ匕膜 60が形成されている。  A silicon oxide film 60 having a thickness of 2600 nm, for example, is formed on the noria film 58.
シリコン酸ィ匕膜 60の表面は、平坦化されている。平坦化されたシリコン酸ィ匕膜 60は、 酉己線 56a、 56b、 56c上【こ、 f列え i lOOOnmの膜厚で残存して!/ヽる。  The surface of the silicon oxide film 60 is flattened. The flattened silicon oxide film 60 remains on the self-aligned wires 56a, 56b, and 56c with a film thickness of i lOOOnm.
[0049] シリコン酸ィ匕膜 60上には、例えば膜厚 lOOnmのシリコン酸ィ匕膜 61が形成されてい る。平坦化されたシリコン酸ィ匕膜 60上にシリコン酸ィ匕膜 61が形成されているため、シ リコン酸ィ匕膜 61は平坦となっている。  [0049] On the silicon oxide film 60, for example, a silicon oxide film 61 having a film thickness of lOOnm is formed. Since the silicon oxide film 61 is formed on the flattened silicon oxide film 60, the silicon oxide film 61 is flat.
[0050] シリコン酸ィ匕膜 61上には、ノ リア膜 62が形成されている。ノ リア膜 62としては、例 えば膜厚 20〜70nmの酸ィ匕アルミニウム膜が用いられている。ここでは、ノ リア膜 62 として、膜厚 50nmの酸ィ匕アルミニウム膜が用いられている。平坦なシリコン酸化膜 6 1上にノ リア膜 62が形成されているため、バリア膜 62は平坦となっている。  A noria film 62 is formed on the silicon oxide film 61. For example, an oxide aluminum film having a thickness of 20 to 70 nm is used as the noria film 62. Here, a 50 nm-thick aluminum oxide film is used as the noria film 62. Since the NORA film 62 is formed on the flat silicon oxide film 61, the barrier film 62 is flat.
[0051] ノ リア膜 62は、バリア膜 44、 46、 58と同様に、水素及び水分の拡散を防止する機 能を有する膜である。さらに、バリア膜 62は、平坦なシリコン酸化膜 61上に形成され ているため平坦となっており、バリア膜 44、 46、 58と比較して、極めて良好な被覆性 で形成されている。したがって、このような平坦なノ リア膜 62により、更に確実に水素 及び水分の拡散を防止することができる。なお、実際には、バリア膜 62は、強誘電体 キャパシタ 42を有する複数のメモリセルが配列された FeRAMセル部 306のみなら ず、 FeRAMチップ領域 302及びスクライブ部 304にわたつて形成されているとともに 、隣接する FeRAMチップ領域 302にまでわたって形成されている。この点について は後述する。  [0051] Like the barrier films 44, 46, and 58, the noria film 62 is a film having a function of preventing the diffusion of hydrogen and moisture. Further, the barrier film 62 is flat because it is formed on the flat silicon oxide film 61, and is formed with extremely good coverage as compared with the barrier films 44, 46, and 58. Therefore, such a flat NOR film 62 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 62 is formed not only in the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also in the FeRAM chip region 302 and the scribe part 304. In other words, it is formed over the adjacent FeRAM chip region 302. This point will be described later.
[0052] ノ リア膜 62上には、例えば膜厚 50〜： LOOnmのシリコン酸ィ匕膜 64が形成されてい る。ここでは、シリコン酸ィ匕膜 64の膜厚は、 lOOnmに設定されている。シリコン酸ィ匕 膜 64は、後述する配線 72a、 72bを形成する際のエッチングのストツバ膜として機能 する。このシリコン酸ィ匕膜 64によりバリア膜 62が保護され、配線 72a、 72bを形成する 際のエッチングによりバリア膜 62の膜厚が減少し或いはノ リア膜 62が除去されてしま うのを防止することができる。これにより、ノ リア膜 62の水素及び水分の拡散機能が 劣化するのを防止することができる。 [0052] On the noria film 62, for example, a silicon oxide film 64 having a film thickness of 50 to: LOOnm is formed. The Here, the thickness of the silicon oxide film 64 is set to lOOnm. The silicon oxide film 64 functions as a stubbing film for etching when forming wirings 72a and 72b described later. The silicon oxide film 64 protects the barrier film 62, and prevents the thickness of the barrier film 62 from being reduced or the removal of the NOR film 62 by etching when the wirings 72a and 72b are formed. be able to. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 62 from being deteriorated.
[0053] こうして、バリア膜 58、シリコン酸ィ匕膜 60、シリコン酸ィ匕膜 61、 バリア膜 62、及びシリ コン酸ィ匕膜 64により層間絶縁膜 66が構成されている。  Thus, the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64 constitute the interlayer insulating film 66.
[0054] 層間絶縁膜 66には、配線 56cに達するコンタクトホール 68が形成されている。  In the interlayer insulating film 66, a contact hole 68 reaching the wiring 56c is formed.
[0055] コンタクトホール 68内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nmの TiN 膜とを順次積層してなるバリアメタル膜 (図示せず)が形成されている。なお、 Ti膜を 形成せずに、 TiN膜よりなるバリアメタル膜を形成してもよ 、。  In the contact hole 68, a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm thick Ti film and a 50 nm thick TiN film, for example. A barrier metal film made of a TiN film may be formed without forming a Ti film.
[0056] ノ リアメタル膜が形成されたコンタクトホール 68内には、タングステンよりなる導体プ ラグ 70が埋め込まれて 、る。  A conductive plug 70 made of tungsten is buried in the contact hole 68 in which the nore metal film is formed.
[0057] 層間絶縁膜 66上には、配線 72aが形成されている。また、層間絶縁膜 66上には、 導体プラグ 70に電気的に接続された配線 72bが形成されている。配線 72a、 72b (第 2金属配線層 72)は、例えば、膜厚 50nmの TiN膜、膜厚 500nmの AlCu合金膜、 膜厚 5nmの Ti膜、及び膜厚 150nmの TiN膜を順次積層してなる積層膜により構成 されている。なお、 AlCu合金膜下の TiN膜は形成しなくてもよい。  A wiring 72 a is formed on the interlayer insulating film 66. On the interlayer insulating film 66, a wiring 72b electrically connected to the conductor plug 70 is formed. Wiring 72a, 72b (second metal wiring layer 72) is formed by sequentially laminating, for example, a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, a 5 nm thick Ti film, and a 150 nm thick TiN film. It is comprised by the laminated film which becomes. Note that the TiN film under the AlCu alloy film need not be formed.
[0058] 層間絶縁膜 66上及び配線 72a、 72b上には、例えば膜厚 2200nmのシリコン酸ィ匕 膜 74が形成されている。シリコン酸ィ匕膜 74の表面は、平坦化されている。  A silicon oxide film 74 having a thickness of 2200 nm, for example, is formed on the interlayer insulating film 66 and the wirings 72a and 72b. The surface of the silicon oxide film 74 is flattened.
[0059] シリコン酸ィ匕膜 74上には、例えば膜厚 lOOnmのシリコン酸ィ匕膜 76が形成されてい る。平坦化されたシリコン酸ィ匕膜 74上にシリコン酸ィ匕膜 76が形成されているため、シ リコン酸ィ匕膜 76は平坦となって 、る。  [0059] On the silicon oxide film 74, for example, a silicon oxide film 76 having a film thickness of lOOnm is formed. Since the silicon oxide film 76 is formed on the flattened silicon oxide film 74, the silicon oxide film 76 is flat.
[0060] シリコン酸ィ匕膜 76上には、ノ リア膜 78が形成されている。ノ リア膜 78としては、例 えば膜厚 20〜： LOOnmの酸ィ匕アルミニウム膜が用いられている。ここでは、バリア膜 7 8として、膜厚 50nmの酸ィ匕アルミニウム膜が用いられている。平坦なシリコン酸化膜 76上にノ リア膜 78が形成されているため、バリア膜 78は平坦となっている。 [0061] ノ リア膜 78は、バリア膜 44、 46、 58、 62と同様に、水素及び水分の拡散を防止す る機能を有する膜である。さらに、ノ リア膜 78は、平坦なシリコン酸化膜 61上に形成 されているため平坦となっており、ノ リア膜 62と同様に、バリア膜 44、 46、 58と比較し て、極めて良好な被覆性で形成されている。したがって、このような平坦なノ リア膜 6 2により、更に確実に水素及び水分の拡散を防止することができる。なお、実際には、 ノ リア膜 78は、バリア膜 62と同様に、強誘電体キャパシタ 42を有する複数のメモリセ ルが配列された FeRAMセル部 306のみならず、 FeRAMチップ領域 302及びスク ライブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領域 302 にまでわたって形成されて 、る。この点にっ ヽては後述する。 A noria film 78 is formed on the silicon oxide film 76. As the noria film 78, for example, an oxide-aluminum film having a film thickness of 20 to: LOOnm is used. Here, as the barrier film 78, an aluminum oxide film having a thickness of 50 nm is used. Since the NORA film 78 is formed on the flat silicon oxide film 76, the barrier film 78 is flat. The noria film 78 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44, 46, 58, and 62. Further, the NORA film 78 is flat because it is formed on the flat silicon oxide film 61, and is very good as compared with the barrier films 44, 46, and 58, like the NORIA film 62. It is formed with coverage. Therefore, diffusion of hydrogen and moisture can be prevented more reliably by using such a flat NOR film 62. In practice, the NOR film 78 is not only the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitors 42 are arranged, but also the FeRAM chip area 302 and the scribe part, as in the barrier film 62. 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
[0062] ノ リア膜 78上には、例えば膜厚 50〜： LOOnmのシリコン酸ィ匕膜 80が形成されてい る。ここでは、シリコン酸ィ匕膜 80の膜厚は lOOnmに設定されている。シリコン酸ィ匕膜 80は、後述する配線 88a、 88bを形成する際のエッチングのストッパ膜として機能す る。このシリコン酸ィ匕膜 80によりバリア膜 78が保護され、配線 88a、 88bを形成する際 のエッチングによりバリア膜 78の膜厚が減少し或いはノ リア膜 62が除去されてしまう のを防止することができる。これにより、ノ リア膜 78の水素及び水分の拡散機能が劣 化するのを防止することができる。  A silicon oxide film 80 having a film thickness of 50 to: LOOnm is formed on the noria film 78, for example. Here, the thickness of the silicon oxide film 80 is set to lOOnm. The silicon oxide film 80 functions as an etching stopper film when forming wirings 88a and 88b described later. The silicon oxide film 80 protects the barrier film 78 and prevents the thickness of the barrier film 78 from being reduced or the removal of the noor film 62 due to etching when the wirings 88a and 88b are formed. Can do. As a result, it is possible to prevent the hydrogen and moisture diffusing functions of the NORA film 78 from being deteriorated.
[0063] こうして、シリコン酸ィ匕膜 74、シリコン酸ィ匕膜 76、 バリア膜 78、及びシリコン酸化膜 8 0により層間絶縁膜 82が構成されている。  Thus, the interlayer insulating film 82 is constituted by the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80.
[0064] 層間絶縁膜 82には、配線 72a、 72bに達するコンタクトホール 84a、 84bがそれぞ れ形成されている。  [0064] In the interlayer insulating film 82, contact holes 84a and 84b reaching the wirings 72a and 72b are formed, respectively.
[0065] コンタクトホール 84a、 84b内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nm の TiN膜とを順次積層してなるバリアメタル膜 (図示せず)が形成されている。なお、 T i膜を形成せずに、 TiN膜よりなるバリアメタル膜を形成してもよ 、。  In the contact holes 84a and 84b, a barrier metal film (not shown) is formed by sequentially laminating, for example, a Ti film with a thickness of 20 nm and a TiN film with a thickness of 50 nm, for example. A barrier metal film made of a TiN film may be formed without forming a Ti film.
[0066] ノ リアメタル膜が形成されたコンタクトホール 84a、 84b内には、タングステンよりなる 導体プラグ 86a、 86bがそれぞれ埋め込まれて ヽる。  [0066] Conductor plugs 86a and 86b made of tungsten are embedded in the contact holes 84a and 84b in which the noria metal film is formed.
[0067] 導体プラグ 86a、 86bが埋め込まれた層間絶縁膜 82上には、導体プラグ 86aに電 気的に接続された配線 88a、及び導体プラグ 86bに電気的に接続された配線 (ボン デイングパッド） 88bが形成されている。配線 88a、 88b (第 3金属配線層 88)は、例え ば、膜厚 50nmの TiN膜、膜厚 500nmの AlCu合金膜、及び膜厚 150nmの TiN膜 を順次積層してなる積層膜により構成されている。なお、 AlCu合金膜下の TiN膜は 形成しなくてもよ ヽ。 [0067] On the interlayer insulating film 82 in which the conductor plugs 86a and 86b are embedded, the wiring 88a electrically connected to the conductor plug 86a and the wiring electrically connected to the conductor plug 86b (bonding pad) 88b is formed. Wiring 88a, 88b (third metal wiring layer 88) For example, a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, and a 150 nm thick TiN film are sequentially stacked. Note that the TiN film under the AlCu alloy film need not be formed.
[0068] 層間絶縁膜 82上及び配線 88a、 88b上には、例えば膜厚 100〜300nmのシリコ ン酸ィ匕膜 90が形成されている。ここでは、シリコン酸ィ匕膜 90の膜厚は、 lOOnmに設 定されている。  A silicon oxynitride film 90 having a thickness of 100 to 300 nm, for example, is formed on the interlayer insulating film 82 and the wirings 88a and 88b. Here, the thickness of the silicon oxide film 90 is set to lOOnm.
[0069] シリコン酸ィ匕膜 90上には、例えば膜厚 350nmのシリコン窒化膜 92が形成されてい る。  [0069] On the silicon oxide film 90, for example, a silicon nitride film 92 having a thickness of 350 nm is formed.
[0070] こうして、層間絶縁膜 82上及び配線 88a、 88b上に、シリコン酸ィ匕膜 90とシリコン窒 化膜 92とを順次積層してなる積層膜 93が形成されている。  Thus, a laminated film 93 is formed by sequentially laminating the silicon oxide film 90 and the silicon nitride film 92 on the interlayer insulating film 82 and the wirings 88a and 88b.
[0071] シリコン窒化膜 92上には、例えば膜厚 2〜6 μ mのポリイミド榭脂膜 94が形成され ている。 On the silicon nitride film 92, for example, a polyimide resin film 94 having a film thickness of 2 to 6 μm is formed.
[0072] ポリイミド榭脂膜 94、シリコン窒化膜 92、及びシリコン酸ィ匕膜 90には、配線 (ボンデ イングパッド) 88bに達する開口部 96が形成されている。すなわち、シリコン窒化膜 92 及びシリコン酸ィ匕膜 90には、配線 (ボンディングパッド) 88bに達する開口部 96aが形 成されている。ポリイミド榭脂膜 94には、シリコン窒化膜 92及びシリコン酸ィ匕膜 90に 形成された開口部 96aを含む領域に、開口部 96bが形成されている。  An opening 96 reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94, the silicon nitride film 92, and the silicon oxide film 90. That is, in the silicon nitride film 92 and the silicon oxide film 90, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92 and the silicon oxide film 90.
[0073] 配線 (ボンディングパッド) 88bには、開口部 96を介して、外部回路（図示せず）が 電気的に接続される。  [0073] An external circuit (not shown) is electrically connected to the wiring (bonding pad) 88b through the opening 96.
[0074] ここで、本実施形態による半導体装置におけるバリア膜 62、 78について図 4乃至 図 6を用いて詳述する。図 4は、図 2 (a)に示すエリア構成に対応する本実施形態に よる半導体装置の構造を示す断面図である。図 5及び図 6はそれぞれ本実施形態に よる半導体装置においてバリア膜 62、 78が形成されている範囲を示す平面図である  Now, the barrier films 62 and 78 in the semiconductor device according to the present embodiment will be described in detail with reference to FIGS. FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to this embodiment corresponding to the area configuration shown in FIG. 5 and 6 are plan views showing ranges in which the barrier films 62 and 78 are formed in the semiconductor device according to the present embodiment, respectively.
[0075] 図 4に示すように、半導体基板 10上には、 FeRAMセル部 306、ロジック回路部 31As shown in FIG. 4, an FeRAM cell unit 306 and a logic circuit unit 31 are formed on the semiconductor substrate 10.
0において、トランジスタ 24が形成されている。 At 0, transistor 24 is formed.
[0076] トランジスタ 24が形成された半導体基板 10上には、全面に、層間絶縁膜 27が形成 されている。 [0077] 層間絶縁膜 27上には、 FeRAMセル部 306において、強誘電体キャパシタ 42が 形成されている。 An interlayer insulating film 27 is formed on the entire surface of the semiconductor substrate 10 on which the transistor 24 is formed. A ferroelectric capacitor 42 is formed on the interlayer insulating film 27 in the FeRAM cell portion 306.
[0078] 強誘電体キャパシタ 42が形成された層間絶縁膜 27上には、全面に、層間絶縁膜 4 9が形成されている。  An interlayer insulating film 49 is formed on the entire surface of the interlayer insulating film 27 on which the ferroelectric capacitor 42 is formed.
[0079] 層間絶縁膜 49上には、 FeRAMセル部 306、ロジック回路部 310、及びパッド部 3 14において、第 1金属配線層 56が形成されている。 FeRAMセル部 306における第 1金属配線層 56は、導体プラグを介して、強誘電体キャパシタ 42の上部電極 40、下 部電極 36、又はトランジスタ 24に適宜電気的に接続されている。ロジック回路部 310 における第 1金属配線層 56は、導体プラグを介して、トランジスタ 24に適宜電気的に 接続されている。  On the interlayer insulating film 49, the first metal wiring layer 56 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314. The first metal wiring layer 56 in the FeRAM cell portion 306 is appropriately electrically connected to the upper electrode 40, the lower electrode 36, or the transistor 24 of the ferroelectric capacitor 42 through a conductor plug. The first metal wiring layer 56 in the logic circuit section 310 is appropriately electrically connected to the transistor 24 through a conductor plug.
[0080] 第 1金属配線層 56が形成された層間絶縁膜 49上には、全面に、層間絶縁膜 66が 形成されている。  An interlayer insulating film 66 is formed on the entire surface of the interlayer insulating film 49 on which the first metal wiring layer 56 is formed.
[0081] 層間絶縁膜 66を構成するノリア膜 62は、図 4及び図 5に示すように、 FeRAMチッ プ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接する FeR AMチップ領域 302にまでわたって形成されている。すなわち、ノリア膜 62は、スクラ イブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路部 310 、ロジック回路の周辺回路部 312、ノッド部 314、これらの境界部であるスクライブ部- パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界 部 320にわたつて形成されている。  As shown in FIGS. 4 and 5, the noria film 62 constituting the interlayer insulating film 66 is formed over the FeRAM chip region 302 and the scribe portion 304 and adjacent to the FeRAM chip region 302. It is formed over to. That is, the noria film 62 includes a sliver portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a nod portion 314, and a scribe portion that is a boundary portion between them. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
[0082] 層間絶縁膜 66上には、 FeRAMセル部 306、ロジック回路部 310、及びパッド部 3 14において、第 2金属配線層 72が形成されている。第 2金属配線層 72は、導体ブラ グを介して、適宜電気的に第 1金属配線層 56に電気的に接続されて!ヽる。  On the interlayer insulating film 66, the second metal wiring layer 72 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314. The second metal wiring layer 72 is appropriately electrically connected to the first metal wiring layer 56 through a conductor plug.
[0083] 第 2金属配線層 72が形成された層間絶縁膜 66上には、全面に、層間絶縁膜 82が 形成されている。  An interlayer insulating film 82 is formed on the entire surface of the interlayer insulating film 66 on which the second metal wiring layer 72 is formed.
[0084] 層間絶縁膜 82を構成するノリア膜 78は、図 4及び図 6に示すように、 FeRAMチッ プ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接する FeR AMチップ領域 302にまでわたって形成されている。すなわち、ノリア膜 78は、スクラ イブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路部 310 、ロジック回路の周辺回路部 312、ノッド部 314、これらの境界部であるスクライブ部- パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界 部 320にわたつて形成されている。 As shown in FIGS. 4 and 6, the noria film 78 constituting the interlayer insulating film 82 is formed over the FeRAM chip region 302 and the scribe portion 304 and adjacent to the FeRAM chip region 302. It is formed over to. That is, the noria film 78 includes a sliver 304, an FeRAM cell 306, an FeRAM peripheral circuit 308, and a logic circuit 310. The peripheral circuit part 312 of the logic circuit, the nod part 314, the boundary part between these, the scribe part-pad part boundary part 316, the pad part-circuit part boundary part 318, and the circuit part-circuit part boundary part 320 It has been formed.
[0085] 層間絶縁膜 82上には、 FeRAMセル部 306、ロジック回路部 310、及びパッド部 3 14において、第 3金属配線層 88が形成されている。パッド部 314における第 3金属 配線層 88は、ボンディングパッド 88bとなっている。第 3金属配線層 88は、導体ブラ グを介して、適宜電気的に第 2金属配線層 72に電気的に接続されて!ヽる。  On the interlayer insulating film 82, a third metal wiring layer 88 is formed in the FeRAM cell portion 306, the logic circuit portion 310, and the pad portion 314. The third metal wiring layer 88 in the pad portion 314 is a bonding pad 88b. The third metal wiring layer 88 is appropriately electrically connected to the second metal wiring layer 72 through a conductor plug.
[0086] 第 3金属配線層 88が形成された層間絶縁膜 82上には、積層膜 93が形成されてい る。  A laminated film 93 is formed on the interlayer insulating film 82 on which the third metal wiring layer 88 is formed.
[0087] 積層膜 93上には、ポリイミド榭脂膜 94が形成されている。  A polyimide resin film 94 is formed on the laminated film 93.
ノッド部 314における積層膜 93及びポリイミド榭脂膜 94には、ボンディングパッド 88 bに達する開口部 96が形成されている。  An opening 96 reaching the bonding pad 88 b is formed in the laminated film 93 and the polyimide resin film 94 in the nod portion 314.
[0088] スクライブ部'パッド部間境界部 316における層間絶縁膜 27、 49、 66、 82、 93中 には、 FeRAMチップへの湿度の影響を抑制するための耐湿リング 322が形成され て ヽる。耐、湿リング 322ίま、層 絶縁膜 27、 49、 66、 82、 93中【こ形成された金属酉己 線層、導体プラグと同様の金属層等により構成されている。耐湿リング 322は、 FeRA Mチップ領域 302における配線等と短絡しな 、ように構成されて！、る。  [0088] In the interlayer insulating films 27, 49, 66, 82, and 93 at the boundary portion 316 between the scribe portion and the pad portion, a moisture-resistant ring 322 for suppressing the influence of humidity on the FeRAM chip is formed. . Insulation film 27, 49, 66, 82, 93 Insulation-resistant, moisture ring 322ί, and the like. The moisture-resistant ring 322 is configured so as not to be short-circuited with the wiring in the FeRA M chip region 302! RU
[0089] こうして本実施形態による半導体装置が構成されて!ヽる。  Thus, the semiconductor device according to the present embodiment is configured.
[0090] 本実施形態による半導体装置は、水素及び水分の拡散を防止するバリア膜として、 ノリア膜 44、 46、 58にカ卩えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56 (配線 56a、 56b、 56c)と第 2金属配線層 72 (配線 72a、 72b)との間に形 成された平坦なバリア膜 62と、第 2金属配線層 72 (配線 72a、 72b)と第 3金属配線 層 88 (配線 88a、 88b)との間に形成された平坦なノリア膜 78とを有することに主たる 特徴がある。  In the semiconductor device according to the present embodiment, the first metal wiring formed above the ferroelectric capacitor 42 over the noria films 44, 46, 58 as a barrier film for preventing diffusion of hydrogen and moisture. Flat barrier film 62 formed between layer 56 (wiring 56a, 56b, 56c) and second metal wiring layer 72 (wiring 72a, 72b), and second metal wiring layer 72 (wiring 72a, 72b) And a flat noria film 78 formed between the third metal wiring layer 88 (wirings 88a and 88b).
[0091] 強誘電体キャパシタを有する半導体装置において、水素や水分による強誘電体キ ャパシタの電気的特性の劣化を防止する有効な手段として、強誘電体キャパシタの 上方に、水素や水分の拡散を防止する酸ィ匕アルミニウム等よりなるバリア膜を形成す ることが考免られる。 [0092] ここで、表面に段差や傾斜が生じている層間絶縁膜等の下地上にバリア膜を形成 した場合には、ノリア膜の被覆性があまり良好ではないため、ノリア膜において水素 や水分の拡散を十分に防止し得な 、。水素や水分が強誘電体キャパシタの強誘電 体膜に達すると、水素や水分により強誘電体膜の強誘電性が低下或いは消失し、強 誘電体キャパシタの電気的特性が劣化してしまうこととなる。 [0091] In a semiconductor device having a ferroelectric capacitor, as an effective means for preventing the deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen or moisture, diffusion of hydrogen or moisture above the ferroelectric capacitor is performed. It is considered that a barrier film made of acid-aluminum or the like to be prevented is formed. [0092] Here, when a barrier film is formed on the surface of an interlayer insulating film or the like having a step or inclination on the surface, the coverage of the noria film is not so good, so hydrogen or moisture in the noria film. Can not sufficiently prevent the spread of. When hydrogen or moisture reaches the ferroelectric film of the ferroelectric capacitor, the ferroelectricity of the ferroelectric film is reduced or lost by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor are degraded. Become.
[0093] 表面に段差や傾斜が生じている層間絶縁膜等の下地上にバリア膜を形成した場合 の不都合な点について図 7乃至図 16を用いて詳述する。  [0093] Inconvenient points when a barrier film is formed on the surface of an interlayer insulating film or the like having a step or inclination on the surface will be described in detail with reference to FIGS.
[0094] 例えば特許文献 1のように有機絶縁膜や SOG (Spin On Glass)膜等の塗布型絶縁 膜を、配線層や強誘電体キャパシタ等による凹凸を含む表面上に形成した場合、塗 布型絶縁膜の表面を十分に平坦にすることは困難である。このため、塗布型絶縁膜 の表面には、段差や傾斜が生じることとなる。  For example, when a coating type insulating film such as an organic insulating film or a SOG (Spin On Glass) film is formed on a surface including irregularities due to a wiring layer, a ferroelectric capacitor, etc. It is difficult to make the surface of the mold insulating film sufficiently flat. For this reason, a step or an inclination occurs on the surface of the coating type insulating film.
[0095] 図 7は、強誘電体キャパシタを埋め込む SOG膜の断面観察の結果を示す透過型 電子顕微鏡写真である。図 7に示す透過型電子顕微鏡写真では、層間絶縁膜 400 上に、下部電極 402と強誘電体膜 404と上部電極 406と力 なる強誘電体キャパシ タ 408が形成されている。強誘電体キャパシタ 408は、 SOG膜 410により埋め込まれ ている。 SOG膜 410上〖こは、上部電極 406に電気的に接続された配線 412が形成 されている。  FIG. 7 is a transmission electron micrograph showing the result of cross-sectional observation of the SOG film in which the ferroelectric capacitor is embedded. In the transmission electron micrograph shown in FIG. 7, on the interlayer insulating film 400, a lower electrode 402, a ferroelectric film 404, an upper electrode 406, and a ferroelectric capacitor 408 that is powerful are formed. The ferroelectric capacitor 408 is embedded with the SOG film 410. A wiring 412 electrically connected to the upper electrode 406 is formed on the SOG film 410.
[0096] 図 7に示す透過型電子顕微鏡写真力も明らかなように、 SOG膜 410の表面は平坦 になっておらず、緩やかな段差が生じている。  [0096] As is clear from the transmission electron microscopic photographic power shown in FIG. 7, the surface of the SOG film 410 is not flat and has a gentle step.
[0097] このように表面に段差や傾斜が生じている下地上に酸ィ匕アルミニウム膜等よりなる ノ リア膜を形成した場合、ノ リア膜の膜厚が不均一となる。  [0097] When the noria film made of an aluminum oxide film or the like is formed on the base having a step or inclination on the surface as described above, the thickness of the noria film becomes nonuniform.
[0098] 例えば、図 8は、強誘電体キャパシタによる段差上に形成された酸化アルミニウム 膜の断面観察の結果を示す透過型電子顕微鏡写真である。  For example, FIG. 8 is a transmission electron micrograph showing the result of cross-sectional observation of an aluminum oxide film formed on a step by a ferroelectric capacitor.
[0099] 図 8に示す透過型電子顕微鏡写真から明らかなように、上部電極 406のほぼ水平 な面上には、 50nmの酸化アルミニウム膜 414がほぼ均一に形成されている。他方、 上部電極 406の側端部の傾斜面上では、図中矢印で挟まれた区間において、傾斜 面に沿って下方に向かうにつれて酸ィ匕アルミニウム膜 414の膜厚が減少している。  As apparent from the transmission electron micrograph shown in FIG. 8, the 50 nm aluminum oxide film 414 is formed almost uniformly on the substantially horizontal surface of the upper electrode 406. On the other hand, on the inclined surface at the side end of the upper electrode 406, the thickness of the acid aluminum film 414 decreases as it goes downward along the inclined surface in a section sandwiched by arrows in the figure.
[0100] 上述のように、例えば特許文献 1のように有機絶縁膜や SOG膜等の塗布型絶縁膜 上にバリア膜を形成した場合には、ノリア膜の膜厚に厚薄が生じることとなる。このよ うな場合、以下に述べる不都合が生じることとなる。 [0100] As described above, for example, as described in Patent Document 1, a coating-type insulating film such as an organic insulating film or an SOG film When a barrier film is formed thereon, the thickness of the noria film is reduced. In such a case, the following inconvenience occurs.
[0101] 図 9及び図 10は、塗布型絶縁膜上にバリア膜を形成した場合の不都合を説明する 工程断面図である。  FIG. 9 and FIG. 10 are process cross-sectional views for explaining inconveniences when a barrier film is formed on a coating type insulating film.
[0102] まず、層間絶縁膜 400上に、下部電極 402と強誘電体膜 404と上部電極 406とか らなる強誘電体キャパシタ 408を形成する（図 9 (a)参照)。  First, a ferroelectric capacitor 408 including a lower electrode 402, a ferroelectric film 404, and an upper electrode 406 is formed on the interlayer insulating film 400 (see FIG. 9 (a)).
[0103] 次いで、強誘電体キャパシタ 408が形成された層間絶縁膜 400上に、有機絶縁膜 や SOG膜等の塗布型絶縁膜よりなる層間絶縁膜 416を形成する（図 9 (b)参照)。層 間絶縁膜 416の表面は十分に平坦にならず、層間絶縁膜 416の表面には段差や傾 斜が生じる。 Next, an interlayer insulating film 416 made of a coating type insulating film such as an organic insulating film or an SOG film is formed on the interlayer insulating film 400 on which the ferroelectric capacitor 408 is formed (see FIG. 9B). . The surface of the interlayer insulating film 416 is not sufficiently flat, and a step or tilt is generated on the surface of the interlayer insulating film 416.
[0104] 次いで、層間絶縁膜 416上に、酸ィ匕アルミニウム膜や酸ィ匕チタン膜等よりなるバリア 膜 418を形成する（図 9 (c)参照)。バリア膜 418は、 MOCVD法以外の方法により形 成すると、層間絶縁膜 416の水平面と比較して、層間絶縁膜 416の傾斜面において 膜厚が薄くなる。  Next, a barrier film 418 made of an acid aluminum film, an acid oxide titanium film, or the like is formed on the interlayer insulating film 416 (see FIG. 9C). When the barrier film 418 is formed by a method other than the MOCVD method, the thickness of the barrier film 418 is reduced on the inclined surface of the interlayer insulating film 416 as compared to the horizontal plane of the interlayer insulating film 416.
[0105] 次いで、フォトリソグラフィ一により、上部電極 406、下部電極 402に達するコンタクト ホールの形成予定領域を露出し、他の領域を覆うフォトレジスト膜 420を形成する（図 9 (d)参照)。  Next, a photoresist film 420 is formed by exposing a region where a contact hole is to be formed reaching the upper electrode 406 and the lower electrode 402 and covering the other region by photolithography (see FIG. 9D).
[0106] 次いで、フォトレジスト膜 420をマスクとして、ノリア膜 418及び層間絶縁膜 416をェ ツチングする。こうして、ノリア膜 418及び層間絶縁膜 416に、上部電極 406に達す るコンタクトホール 422a、及び下部電極 402に達するコンタクトホール 422bをそれぞ れ形成する（図 10 (a)参照)。  Next, the noria film 418 and the interlayer insulating film 416 are etched using the photoresist film 420 as a mask. Thus, a contact hole 422a reaching the upper electrode 406 and a contact hole 422b reaching the lower electrode 402 are formed in the noria film 418 and the interlayer insulating film 416, respectively (see FIG. 10A).
[0107] 次いで、全面に、配線を形成するための金属膜 424を形成する（図 10 (b)参照)。 [0107] Next, a metal film 424 for forming wiring is formed on the entire surface (see FIG. 10B).
[0108] 次いで、フォトリソグラフィ一により、上部電極 406、下部電極 402に接続される配線 の形成予定領域を覆い、他の領域を露出するフォトレジスト膜 426を形成する（図 10 (c)参照)。 Next, a photolithography process is performed to form a photoresist film 426 that covers the regions where wirings to be connected to the upper electrode 406 and the lower electrode 402 are to be formed and exposes other regions (see FIG. 10 (c)). .
[0109] 次!、で、フォトレジスト膜 426をマスクとして、金属膜 424をエッチングする。こうして 、金属膜 424よりなり、上部電極 406に接続された配線 428a、及び金属膜 424よりな り、下部電極 402に接続された配線 428bが形成される（図 10 (d)参照)。 [0110] 配線 428a、 428bを形成するために金属膜 424をエッチングする際には、バリア膜 418は、エッチングのストッパ膜としても利用される。このため、ノリア膜 418もエッチ ングされ、膜厚が減少する。このとき、下地の段差や傾斜によりバリア膜 418の膜厚 に厚薄が生じていると、膜厚の薄い部分では、エッチングにより著しく膜厚が減少し、 更にはノリア膜 418が除去されてしまう場合がある。この結果、ノリア膜 418が、水素 及び水分の拡散を防止する機能を十分に発揮することができないこととなる。 Next, the metal film 424 is etched using the photoresist film 426 as a mask. Thus, a wiring 428a made of the metal film 424 and connected to the upper electrode 406 and a wiring 428b made of the metal film 424 and connected to the lower electrode 402 are formed (see FIG. 10D). [0110] When the metal film 424 is etched to form the wirings 428a and 428b, the barrier film 418 is also used as an etching stopper film. For this reason, the noria film 418 is also etched and the film thickness is reduced. At this time, if the thickness of the barrier film 418 is thin due to the level difference or inclination of the base, the thickness of the thin film is significantly reduced by etching, and the noria film 418 is removed. There is. As a result, the noria film 418 cannot sufficiently exhibit the function of preventing the diffusion of hydrogen and moisture.
[0111] 例えば、ノリア膜の膜厚を lOOnmに設定した場合、水平面上ではエッチングにより 50nmの膜厚分だけ除去されバリア膜の膜厚が 50nmに減少するのに対し、傾斜面 上ではエッチングによりバリア膜が除去された欠損が生じる。また、バリア膜の膜厚を 200nmに設定した場合、水平面上ではエッチングにより 50nmの膜厚分だけ除去さ れバリア膜の膜厚が 150nmに減少するのに対し、傾斜面上ではエッチングにより膜 厚が 0〜50nmに減少し、ノリア膜が除去された欠損が一部に生じる。  [0111] For example, when the film thickness of the noria film is set to lOOnm, the film thickness of the barrier film is reduced to 50 nm by etching on the horizontal plane by 50 nm, whereas the film thickness of the barrier film is reduced to 50 nm by etching. A defect is generated when the barrier film is removed. In addition, when the thickness of the barrier film is set to 200 nm, the thickness of the barrier film is reduced to 150 nm by etching on the horizontal plane by 50 nm, whereas the thickness of the barrier film is reduced to 150 nm by etching. Decreases to 0 to 50 nm, and a defect in which the noria film is removed occurs in part.
[0112] また、上述した不都合に加えて、例えば特許文献 1のように有機絶縁膜や SOG膜 等の塗布型絶縁膜上にバリア膜を形成した場合には、以下に述べる不都合も生じる こととなる。  [0112] Further, in addition to the above-described inconveniences, when a barrier film is formed on a coating type insulating film such as an organic insulating film or an SOG film as in Patent Document 1, for example, the following inconveniences may occur. Become.
[0113] 図 11乃至図 14は、塗布型絶縁膜上にバリア膜を形成した場合の他の不都合を説 明する工程断面図である。図 11及び図 12は膜厚 50nmのノリア膜を形成した場合 を示し、図 13及び図 14は膜厚 lOOnmのノリア膜を形成した場合を示している。  FIG. 11 to FIG. 14 are process cross-sectional views illustrating another inconvenience when a barrier film is formed on a coating type insulating film. 11 and 12 show the case where a 50 nm-thick noria film is formed, and FIGS. 13 and 14 show the case where a lOOnm-thick noria film is formed.
[0114] まず、膜厚 50nmのノリア膜を形成した場合について図 11及び図 12を用いて説明 する。  First, the case where a noria film having a thickness of 50 nm is formed will be described with reference to FIGS.
[0115] まず、導体プラグ 430が埋め込まれた層間絶縁膜 432上に、配線 434を形成する（ 図 11 (a)参照)。  First, the wiring 434 is formed on the interlayer insulating film 432 in which the conductor plug 430 is embedded (see FIG. 11 (a)).
[0116] 次いで、配線 434が形成された層間絶縁膜 432上に、有機絶縁膜や SOG膜等の 塗布型絶縁膜よりなる層間絶縁膜 436を形成する（図 11 (b)参照)。層間絶縁膜 43 6の表面は十分に平坦にならず、層間絶縁膜 436の表面には段差や傾斜が生じる。  Next, an interlayer insulating film 436 made of a coating type insulating film such as an organic insulating film or SOG film is formed on the interlayer insulating film 432 on which the wiring 434 is formed (see FIG. 11B). The surface of the interlayer insulating film 436 is not sufficiently flat, and a step or an inclination occurs on the surface of the interlayer insulating film 436.
[0117] 次いで、層間絶縁膜 436上に、膜厚 50nmのバリア膜 438を形成する（図 11 (c)参 照)。  Next, a barrier film 438 having a thickness of 50 nm is formed on the interlayer insulating film 436 (see FIG. 11C).
[0118] 次いで、バリア膜 438上に、層間絶縁膜 440を形成する（図 11 (d)参照)。 [0119] 図 12は、図 11 (c)に示すバリア膜 438を拡大して示した断面図である。図示するよ うに、層間絶縁膜 436の水平面 H上では、ノリア膜 438の膜厚は 50nmとなっている 。他方、層間絶縁膜 436の傾斜面 Sにおいては、ノリア膜 438の膜厚は実際には 20 nm以下となってしまっている。このように、膜厚 50nmのバリア膜 438を形成した場合 には、被覆性が良好でなくバリア膜 438の膜厚が部分的に薄くなつてしまう。このため 、バリア膜 438は、水素及び水分の拡散を防止する機能を十分に発揮することがで きないこととなる。 Next, an interlayer insulating film 440 is formed on the barrier film 438 (see FIG. 11D). FIG. 12 is an enlarged cross-sectional view of the barrier film 438 shown in FIG. 11 (c). As illustrated, on the horizontal plane H of the interlayer insulating film 436, the thickness of the noria film 438 is 50 nm. On the other hand, on the inclined surface S of the interlayer insulating film 436, the thickness of the noria film 438 is actually 20 nm or less. Thus, when the barrier film 438 having a thickness of 50 nm is formed, the coverage is not good and the thickness of the barrier film 438 is partially reduced. For this reason, the barrier film 438 cannot sufficiently exhibit the function of preventing the diffusion of hydrogen and moisture.
[0120] 次に、膜厚 lOOnmのノリア膜を形成した場合について図 13及び図 14を用いて説 明する。  Next, the case where a noria film having a thickness of lOOnm is formed will be described with reference to FIGS. 13 and 14. FIG.
[0121] まず、導体プラグ 430が埋め込まれた層間絶縁膜 432上に、配線 434を形成する（ 図 13 (a)参照)。  First, the wiring 434 is formed on the interlayer insulating film 432 in which the conductor plug 430 is embedded (see FIG. 13 (a)).
[0122] 次いで、配線 434が形成された層間絶縁膜 432上に、有機絶縁膜や SOG膜等の 塗布型絶縁膜よりなる層間絶縁膜 436を形成する（図 13 (b)参照)。層間絶縁膜 43 6の表面は十分に平坦にならず、層間絶縁膜 436の表面には段差や傾斜が生じる。  Next, an interlayer insulating film 436 made of a coating type insulating film such as an organic insulating film or an SOG film is formed on the interlayer insulating film 432 on which the wiring 434 is formed (see FIG. 13B). The surface of the interlayer insulating film 436 is not sufficiently flat, and a step or an inclination occurs on the surface of the interlayer insulating film 436.
[0123] 次いで、層間絶縁膜 436上に、膜厚 lOOnmのバリア膜 438を形成する（図 13 (c) 参照)。  [0123] Next, a barrier film 438 having a thickness of lOOnm is formed on the interlayer insulating film 436 (see FIG. 13C).
[0124] 次いで、バリア膜 438上に、層間絶縁膜 440を形成する（図 13 (d)参照)。  Next, an interlayer insulating film 440 is formed on the barrier film 438 (see FIG. 13D).
[0125] 図 14は、図 13 (c)に示すバリア膜 438を拡大して示した断面図である。図示するよ うに、層間絶縁膜 436の水平面 H上では、ノリア膜 438の膜厚は lOOnmとなってい る。他方、層間絶縁膜 436の傾斜面 Sの大部分においては、バリア膜 438の膜厚は 実際には 20〜50nmとなっている。しかし、傾斜面 Sのうち最も急峻な部分において は、バリア膜 438の膜厚は、 20nm以下となっている。  FIG. 14 is an enlarged cross-sectional view of the barrier film 438 shown in FIG. 13 (c). As shown in the drawing, on the horizontal plane H of the interlayer insulating film 436, the film thickness of the noria film 438 is lOOnm. On the other hand, in most of the inclined surface S of the interlayer insulating film 436, the film thickness of the barrier film 438 is actually 20 to 50 nm. However, at the steepest portion of the inclined surface S, the thickness of the barrier film 438 is 20 nm or less.
[0126] このように、膜厚 lOOnmのノリア膜 438を形成した場合には、膜厚 50nmの場合と 比較して被覆性が良好なものとなる。しかし、ノリア膜 438の膜厚が 20nm以下と膜 厚が薄くなつてしまう部分が依然として存在している。このため、ノリア膜 438は、水 素及び水分の拡散を防止する機能を十分に発揮することができないこととなる。  Thus, when the noria film 438 having a film thickness of lOOnm is formed, the coverage is better than that of the film having a film thickness of 50 nm. However, there is still a portion where the film thickness of the noria film 438 is as thin as 20 nm or less. For this reason, the Noria film 438 cannot sufficiently exhibit the function of preventing the diffusion of hydrogen and moisture.
[0127] 上述のようにバリア膜の膜厚を lOOnmに設定した場合、水平面上での膜厚は 100 nmとなるのに対し、傾斜面上ではノリア膜が形成されない欠損が一部に生じる。ま た、ノリア膜の膜厚を 200nmに設定した場合、水平面上での膜厚は 200nmとなる のに対し、傾斜面上では膜厚が 50〜： LOOnmとなる。 [0127] As described above, when the thickness of the barrier film is set to lOOnm, the film thickness on the horizontal plane is 100 nm, whereas a defect in which the noria film is not formed on the inclined surface occurs in part. Ma When the film thickness of the noria film is set to 200 nm, the film thickness on the horizontal plane is 200 nm, whereas the film thickness on the inclined surface is 50 to: LOOnm.
[0128] 表面に緩や力な段差が存在する下地上にバリア膜を形成した場合と表面が平坦な 下地上にバリア膜を形成した場合との比較結果について図 15を用いて説明する。図 15は、昇温離脱分析法（Thermal Desorption Spectroscopy, TDS)によるバリア膜の 評価結果を示すグラフである。図 15において、横軸は基板温度を示しており、縦軸 は試料力もの水素イオンの析出量を示している。なお、図 15 (a)の縦軸の桁と図 15 ( b)の縦軸の桁との違いは、 TDSによる解析を行った試料の面積の広狭によるもので ある。 [0128] A comparison result between the case where the barrier film is formed on the base having a gentle step on the surface and the case where the barrier film is formed on the base having a flat surface will be described with reference to FIG. FIG. 15 is a graph showing the evaluation results of the barrier film by thermal desorption spectroscopy (TDS). In FIG. 15, the horizontal axis indicates the substrate temperature, and the vertical axis indicates the amount of hydrogen ions deposited with the sample strength. The difference between the vertical axis in Fig. 15 (a) and the vertical axis in Fig. 15 (b) is due to the size of the area of the sample analyzed by TDS.
[0129] 図 15 (a)は、表面に緩やかな段差が存在している下地上にバリア膜を形成した場 合を示している。試料としては、シリコン基板上に、塗布法により SOG膜により形成し 、その後、スパッタ法により全面にバリア膜として酸ィ匕アルミニウム膜を形成したものを 用いた。図 15 (a)において、參印は、酸ィ匕アルミニウム膜を形成しない場合を示して いる。△印は、酸ィ匕アルミニウム膜の膜厚が 20nmの場合を示している。口印は、酸 化アルミニウム膜の膜厚が 50nmの場合を示している。◊印は、酸ィ匕アルミニウム膜 の膜厚が lOOnmの場合を示している。  FIG. 15 (a) shows a case where a barrier film is formed on a base having a gentle step on the surface. As a sample, an SOG film was formed on a silicon substrate by a coating method, and then an oxide aluminum film was formed as a barrier film on the entire surface by a sputtering method. In FIG. 15 (a), the arrow marks indicate the case where no aluminum oxide film is formed. The Δ mark indicates the case where the thickness of the aluminum oxide film is 20 nm. The mouth mark indicates the case where the film thickness of the aluminum oxide film is 50 nm. The arrow indicates the case where the thickness of the aluminum oxide film is lOOnm.
[0130] 図 15 (b)は、本実施形態による半導体装置におけるバリア膜 62、 78のように、表面 が平坦な下地上にバリア膜を形成した場合を示している。試料としては、シリコン基板 上に、プラズマ TEOSCVD法によりシリコン酸ィ匕膜を形成し、その後、スパッタ法によ り全面にバリア膜として酸ィ匕アルミニウム膜を形成したものを用いた。図 15 (b)におい て、參印は、酸ィ匕アルミニウム膜を形成しない場合を示している。△印は、酸ィ匕アルミ -ゥム膜の膜厚が 10nmの場合を示している。口印は、酸ィ匕アルミニウム膜の膜厚が 20nmの場合を示している。◊印は、酸ィ匕アルミニウム膜の膜厚が 50nmの場合を示 している。〇印は、シリコン基板のみの場合を示している。  FIG. 15B shows a case where a barrier film is formed on a base having a flat surface, like the barrier films 62 and 78 in the semiconductor device according to the present embodiment. As a sample, a silicon oxide film was formed on a silicon substrate by plasma TEOSCVD, and then an oxide aluminum film was formed as a barrier film on the entire surface by sputtering. In FIG. 15 (b), the arrow marks indicate the case where no acid aluminum film is formed. The △ mark indicates the case where the thickness of the acid aluminum film is 10 nm. The mouth mark shows the case where the thickness of the aluminum oxide film is 20 nm. The arrow indicates the case where the thickness of the aluminum oxide film is 50 nm. A circle indicates a case of only a silicon substrate.
[0131] 図 15 (a)から明らかなように、表面に緩や力な段差が存在する下地上にバリア膜を 形成した場合には、水素に対する十分なノリア性を得ることができず、水素が拡散す るのをバリア膜により十分に防止することができないことが分かる。  [0131] As is apparent from FIG. 15 (a), when a barrier film is formed on a base having a gentle step on the surface, sufficient noreia with respect to hydrogen cannot be obtained. It can be seen that the diffusion cannot be sufficiently prevented by the barrier film.
[0132] これに対し、図 15 (b)から明らかなように、表面が平坦な下地上にバリア膜を形成し た場合における水素イオンの析出量は、膜厚 10nm、 20nm、 50nmのいずれの場 合も、バリア膜を形成しない場合における水素イオンの析出量に比べて著しく少なく なっていることが分かる。このことから、本実施形態による半導体装置のように表面が 平坦な下地上にバリア膜を形成した場合には、水素に対する十分なノリア性を得る ことができ、水素が拡散するのをバリア膜により確実に防止することができると 、える。 On the other hand, as is clear from FIG. 15 (b), a barrier film is formed on the base having a flat surface. It can be seen that the hydrogen ion deposition amount in the case of the film thickness is remarkably smaller than the hydrogen ion precipitation amount in the case where the film thickness is 10 nm, 20 nm, and 50 nm when the barrier film is not formed. From this, when the barrier film is formed on the base having a flat surface as in the semiconductor device according to the present embodiment, sufficient noreality with respect to hydrogen can be obtained, and the barrier film prevents hydrogen from diffusing. If it can be surely prevented.
[0133] なお、水分に対するバリア性は、基本的に水素に対するバリア性と連動しており、水 素に対するノリア性が得ることができない場合には、水分に対するノリア性もまた得 ることはできない。図示しないが、水分に対するノリア性に関して行った TDSによる 評価結果についても、上述した水素に対するバリア性に関する評価結果と同様の結 果が得られている。なお、物質の大きさという観点力もは、水よりも水素がより小さな物 質であるため、水素及び水の両者に対して十分なノ リア性を得るためには、十分に 平坦な下地上にノリア膜を形成する必要があるといえる。  [0133] Note that the barrier property against moisture is basically linked to the barrier property against hydrogen, and when the noria property against hydrogen cannot be obtained, the noria property against moisture cannot also be obtained. Although not shown in the figure, the TDS evaluation result for the noria property against moisture is similar to the evaluation result for the barrier property against hydrogen described above. In terms of the viewpoint of the size of the substance, hydrogen is a substance smaller than water, so that it has a sufficiently flat surface to obtain a sufficient NORA for both hydrogen and water. It can be said that it is necessary to form a noria film.
[0134] 表面に段差や傾斜が生じている下地上にバリア膜を形成した場合において、水素 及び水素に対する十分なノ リア性を得るためには、バリア膜を比較的厚い膜厚で形 成することが考えられる。し力しながら、ノリア膜を例えば膜厚 lOOnm以上のように比 較的厚く形成すると、コンタクトホールを形成するためのエッチングが困難になるとい う不都合が生じる。以下、ノリア膜を比較的厚く形成した場合における不都合につい て図 16を用いて説明する。  [0134] When a barrier film is formed on a base having a step or slope on the surface, the barrier film is formed with a relatively thick film thickness in order to obtain hydrogen and sufficient no-reactivity against hydrogen. It is possible. However, if the Noria film is formed relatively thick, for example, with a film thickness of lOOnm or more, there is a disadvantage that etching for forming the contact hole becomes difficult. Hereinafter, inconveniences when the noria film is formed to be relatively thick will be described with reference to FIG.
[0135] 図 16 (a)に示すように、強誘電体キャパシタ 408の上部電極 406と A1配線 442とを 接続する導体プラグ 444を形成する場合にぉ ヽて、上部電極 406と A1配線 442との 間の層間絶縁膜中に、バリア膜を形成する。このとき、バリア膜の膜厚が比較的厚い と、導体プラグ 444が埋め込まれるコンタクトホール 446を形成するためのエッチング の際に、コンタクトホール 446の底部の幅が狭くなつてしまい、コンタクト抵抗が上昇し 、或いはコンタクト不良が発生する。  As shown in FIG. 16 (a), when forming the conductor plug 444 that connects the upper electrode 406 of the ferroelectric capacitor 408 and the A1 wiring 442, the upper electrode 406 and the A1 wiring 442 A barrier film is formed in the interlayer insulating film between. At this time, if the thickness of the barrier film is relatively large, the width of the bottom of the contact hole 446 becomes narrower during etching to form the contact hole 446 in which the conductor plug 444 is embedded, and the contact resistance increases. Or contact failure occurs.
[0136] 図 16 (b)は導体プラグ 444が埋め込まれたコンタクトホール 446を示す断面図であ る。 A1配線 442側となるコンタクトホール 446上部の幅を Wとし上部電極 406が露出 するコンタクトホール 446底部の幅 Wとし、両者の差 W -Wをエッチシフトと定義す  FIG. 16B is a sectional view showing the contact hole 446 in which the conductor plug 444 is embedded. The width of the contact hole 446 on the A1 wiring 442 side is W, and the width of the contact hole 446 bottom where the upper electrode 406 is exposed is 446. The difference W-W between the two is defined as etch shift.
b t b  b t b
る。ノリア膜として膜厚 lOOnmの酸ィ匕アルミニウム膜を形成した場合、エッチシフトは 150nmとなり、コンタクト抵抗は上昇した。また、ノリア膜として膜厚 200nmの酸ィ匕ァ ルミ-ゥム膜を形成した場合、エッチシフトは 300nm以上となり、コンタクト不良が発 生した。 The When an oxide-aluminum film with a thickness of lOOnm is formed as a noria film, the etch shift is The contact resistance increased to 150 nm. In addition, when a 200 nm thick oxide film was formed as the noria film, the etch shift was over 300 nm, resulting in poor contact.
[0137] 以上、詳述したように、例えば特許文献 1のように有機絶縁膜や SOG膜等の塗布 型絶縁膜上にバリア膜を形成した場合、すなわち表面に段差や傾斜が生じている下 地上にバリア膜を形成した場合には、バリア膜の膜厚を比較的薄くしても比較的厚く しても、異なった不都合が生じてしまっていた。  [0137] As described above, when a barrier film is formed on a coating type insulating film such as an organic insulating film or SOG film as described in Patent Document 1, for example, there is a step or inclination on the surface. When a barrier film is formed on the ground, different inconveniences occur regardless of whether the barrier film is relatively thin or thick.
[0138] さらに、 SOG膜は、一般的に、膜応力は小さいものの、膜中の残留水分が非常に 多いことが知られている。このため、層間絶縁膜として SOG膜を用いた場合において 、後工程において 250°C以上の熱が加わると、 SOG膜中の水分が強誘電体キャパ シタまで到達し、強誘電体キャパシタの特性が劣化してしまうと考えられる。  [0138] Further, it is known that the SOG film generally has a very high residual moisture in the film, although the film stress is small. For this reason, when an SOG film is used as an interlayer insulating film, if heat of 250 ° C or higher is applied in the subsequent process, the moisture in the SOG film reaches the ferroelectric capacitor, and the characteristics of the ferroelectric capacitor are It is thought that it will deteriorate.
[0139] このような表面に段差や傾斜が生じている下地上に形成されたバリア膜に対して、 本実施形態による半導体装置における平坦化された絶縁膜上に形成された平坦な ノリア膜は被覆性が極めて良好である。したがって、このような平坦なノリア膜により 水素及び水分を確実にバリアし、水素及び水分が強誘電体キャパシタの強誘電体膜 に達するのを防止することができる。  [0139] In contrast to the barrier film formed on the base having such a step or inclination on the surface, the flat noria film formed on the flattened insulating film in the semiconductor device according to the present embodiment is Coverability is very good. Therefore, hydrogen and moisture can be reliably blocked by such a flat noria film, and hydrogen and moisture can be prevented from reaching the ferroelectric film of the ferroelectric capacitor.
[0140] し力しながら、強誘電体キャパシタの上方に、単に 1層の平坦なバリア膜を形成した 場合には、 PTHS試験において不良が発生する等、過酷な環境下において水素に 対する耐性や耐湿性を充分に確保することができないことがあった。これは、平坦な ノ リア膜の下地層となる層間絶縁膜を CMP法等により平坦ィ匕する際に層間絶縁膜 の表面に生じたマイクロ 'スクラッチによる段差が影響して 、ると考えられる。すなわち 、層間絶縁膜の表面に生じたマイクロ 'スクラッチによる段差のために平坦なノリア膜 においても被覆性があまり良好でない欠陥部分が生じており、このような欠陥部分が 、平坦なバリア膜によっても水素に対する耐性や耐湿性を充分に確保することができ ない場合がある原因の一つとなっていると考えられる。実際には、マイクロ 'スクラッチ による段差を考慮して、 CMP法等による下地層の平坦化後に、例えば膜厚 lOOnm のシリコン酸ィ匕膜を形成している力 このような手法を用いても、マイクロ 'スクラッチに よる影響を完全に回避することはできていな力つた。 [0141] 図 17は、強誘電体キャパシタを有する半導体装置において形成された平坦なバリ ァ膜に生じる欠陥部分を示す断面図である。なお、図 17に示す半導体装置では、本 実施形態による半導体装置とは異なり、平坦なバリア膜として 1層のバリア膜 78のみ が形成されており、ノリア膜 62は形成されて ヽな ヽ。 [0140] However, if a single flat barrier film is formed above the ferroelectric capacitor, the resistance to hydrogen in a harsh environment, such as failure in the PTHS test, may occur. In some cases, sufficient moisture resistance could not be ensured. This is thought to be due to the effect of the micro-scratch level created on the surface of the interlayer insulating film when the interlayer insulating film serving as the underlying layer of the flat noor film is flattened by CMP or the like. That is, due to a step due to micro scratches generated on the surface of the interlayer insulating film, a defective portion with poor coverage is generated even in a flat noria film, and such a defective portion is also formed by a flat barrier film. This is considered to be one of the reasons why sufficient resistance to hydrogen and moisture resistance may not be ensured. Actually, considering the step due to micro scratches, the force of forming a silicon oxide film with a thickness of lOOnm, for example, after planarizing the underlayer by CMP or the like, Micro 'scratch's influence could not be completely avoided. [0141] FIG. 17 is a cross-sectional view showing a defect portion generated in a flat barrier film formed in a semiconductor device having a ferroelectric capacitor. In the semiconductor device shown in FIG. 17, unlike the semiconductor device according to the present embodiment, only one barrier film 78 is formed as a flat barrier film, and the noria film 62 is formed.
[0142] 図 17に示すように、平坦なノリア膜 78においても、その下層の絶縁膜の表面に生 じて 、るマイクロ ·スクラッチによる段差等により、被覆性のあまり良好でな 、欠陥部分 110が生じて 、ると考えられる。  [0142] As shown in FIG. 17, even in the flat noria film 78, the defect portion 110 has a poor coverage due to a step caused by micro scratches generated on the surface of the underlying insulating film. Is considered to occur.
[0143] したがって、半導体装置がおかれる環境下によつては、平坦なノリア膜 78の欠陥 部分 110を介して半導体装置の内部に水素や水分が侵入してしまうと考えられる。  Therefore, under circumstances where the semiconductor device is placed, it is considered that hydrogen and moisture enter the semiconductor device through the defective portion 110 of the flat noria film 78.
[0144] さらに、図 17に示す半導体装置のように、単に 1層の平坦なバリア膜が形成されて いるのみでは、欠陥部分 110を介して半導体装置の内部に侵入した水素や水分が 強誘電体キャパシタ 42に達するのを充分に防止することが困難となる。この結果、平 坦なノリア膜が強誘電体キャパシタの上方に形成されている場合であっても、単に 1 層の平坦なバリア膜が形成されて!、るのみでは、強誘電体キャパシタの電気的特性 が劣化してしまうことがあると考えられる。  [0144] Furthermore, as in the semiconductor device shown in FIG. 17, simply by forming a single flat barrier film, hydrogen and moisture that have penetrated into the semiconductor device through the defective portion 110 are ferroelectric. It is difficult to sufficiently prevent the body capacitor 42 from being reached. As a result, even when the flat noria film is formed above the ferroelectric capacitor, a single flat barrier film is formed! It is considered that the physical characteristics may deteriorate.
[0145] これに対し、本実施形態による半導体装置では、 2層の平坦なバリア膜、すなわち、 強誘電体キャパシタ 42の上方に形成された第 1金属配線層 56と第 2金属配線層 72 との間に形成された平坦なバリア膜 62と、第 2金属配線層 72と第 3金属配線層 88と の間に形成された平坦なノリア膜 78とが形成されて ヽる。  In contrast, in the semiconductor device according to the present embodiment, two flat barrier films, that is, the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42, A flat barrier film 62 formed between the first metal wiring layer 72 and a flat noria film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed.
[0146] 本実施形態による半導体装置においても、図 18及び図 19に示すように、 2層の平 坦なバリア膜 62、 78に、被覆性があまり良好でない欠陥部分 110が生じている場合 が想定される。なお、図 18は本実施形態による半導体装置の構造を示す断面図で あり、図 19 (b)は図 19 (a)に示すパッド部 314を含む領域を拡大して示した平面図 である。図 18及び図 19 (b)において、 2層の平坦なバリア膜 62、 78に生じている欠 陥部分 110を概略的に示して 、る。  Also in the semiconductor device according to the present embodiment, as shown in FIGS. 18 and 19, there may be a case where a defective portion 110 with poor coverage is generated in the two-layer flat barrier films 62 and 78. is assumed. FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 19B is an enlarged plan view showing a region including the pad portion 314 shown in FIG. 19A. In FIG. 18 and FIG. 19 (b), the notch 110 formed in the two flat barrier films 62 and 78 is schematically shown.
[0147] しかし、図 18に示すように、平坦なバリア膜 62、 78において、互いにほぼ同じ平面 位置に欠陥部分 110が生じる確率は極めて小さいといえる。したがって、本実施形態 による半導体装置では、上層に位置する平坦なバリア膜 78に生じている欠陥部分 1 10を介して水素や水分が半導体装置の内部に侵入したとしても、下層に位置する平 坦なバリア膜 62により、侵入した水素や水分が強誘電体キャパシタ 42に達するのを 確実に遮断することができる。 However, as shown in FIG. 18, in the flat barrier films 62 and 78, it can be said that the probability that the defective portion 110 is generated at substantially the same plane position is very small. Therefore, in the semiconductor device according to the present embodiment, the defective portion 1 generated in the flat barrier film 78 positioned in the upper layer 1. Even if hydrogen or moisture penetrates into the semiconductor device via 10, the flat barrier film 62 located in the lower layer can reliably block the penetrated hydrogen and moisture from reaching the ferroelectric capacitor 42. Can do.
[0148] また、詳細なメカニズムは不明である力 2層のバリア膜 62、 78が形成されているこ とにより、 2層のバリア膜 62、 78の間に、層間絶縁膜中に存在する残留水素が封止さ れ、強誘電体キャパシタ 42上の残留水素が強誘電体キャパシタ 42に達するのが防 止されると考えられる。このような他の要因によっても、強誘電体キャパシタ 42の電気 的特性の劣化が防止され、 PTHS特性を向上することができると考えられる。  [0148] Further, the detailed mechanism is unknown. Since the two-layer barrier films 62 and 78 are formed, the residual film existing in the interlayer insulating film is present between the two-layer barrier films 62 and 78. It is considered that hydrogen is sealed, and residual hydrogen on the ferroelectric capacitor 42 is prevented from reaching the ferroelectric capacitor 42. Such other factors are also considered to prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 and improve the PTHS characteristics.
[0149] すなわち、図 20に示すように、平坦なノリア膜として 1層のバリア膜 78のみが形成 されており、ノリア膜 62は形成されていない場合においては、強誘電体キャパシタ 4 2上の残留水素が容易に強誘電体キャパシタ 42に達することができる。したがって、 この場合には、強誘電体キャパシタ 42の電気的特性の劣化を十分に防止することは 困難であると考えられる。  That is, as shown in FIG. 20, only one barrier film 78 is formed as a flat noria film, and no noria film 62 is formed. Residual hydrogen can easily reach the ferroelectric capacitor 42. Therefore, in this case, it is considered difficult to sufficiently prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42.
[0150] 他方、図 21に示す本実施形態による半導体装置のように、 2層のバリア膜 62、 78 が形成されている場合、層間絶縁膜中の残留水素は、 2層のノリア膜 62、 78の間に 封止されることとなる。このため、強誘電体キャパシタ 42上の残留水素が強誘電体キ ャパシタ 42に達するのが防止される。この結果、強誘電体キャパシタ 42の電気的特 性の劣化が防止され、 PTHS特性を向上することができると考えられる。  On the other hand, when the two-layer barrier films 62 and 78 are formed as in the semiconductor device according to the present embodiment shown in FIG. 21, the residual hydrogen in the interlayer insulating film It will be sealed during 78. This prevents residual hydrogen on the ferroelectric capacitor 42 from reaching the ferroelectric capacitor 42. As a result, it is considered that the deterioration of the electrical characteristics of the ferroelectric capacitor 42 can be prevented and the PTHS characteristics can be improved.
[0151] また、本実施形態による半導体装置は、バリア膜 62、 78が、 FeRAMチップ領域 3 02及びスクライブ部 304にわたつて形成されているとともに、隣接する FeRAMチッ プ領域 302にまでわたって形成されていることにも主たる特徴がある。  [0151] In the semiconductor device according to the present embodiment, the barrier films 62 and 78 are formed over the FeRAM chip region 302 and the scribe part 304, and are formed over the adjacent FeRAM chip region 302. The main characteristic is that
[0152] これに対して、例えば特許文献 7に記載された半導体装置にぉ 、ては、 FeRAMセ ル部にのみ水素ノリア層が形成されているだけである。このため、特許文献 7に記載 された半導体装置では、 FeRAMセル部の上方或いは側方力 水素及び水分が Fe RAMセル部に侵入し、強誘電体キャパシタに達するのを防止することは困難である と考えられる。このため、例えば高湿度の環境下に長時間放置すると、強誘電体キヤ パシタの特性は劣化してしまうと考えられる。  [0152] On the other hand, for example, in the semiconductor device described in Patent Document 7, only the hydrogen noria layer is formed only in the FeRAM cell portion. For this reason, in the semiconductor device described in Patent Document 7, it is difficult to prevent hydrogen and moisture from entering the Fe RAM cell part from reaching the ferroelectric capacitor above or laterally from the FeRAM cell part. it is conceivable that. For this reason, for example, it is considered that the characteristics of the ferroelectric capacitor deteriorate when left in a high humidity environment for a long time.
[0153] 本実施形態による半導体装置では、バリア膜 62、 78力 FeRAMチップ領域 302 及びスクライブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領 域 302にまでわたって形成されているため、 FeRAMセル部 306の上方或いは側方 力 水素及び水分力 SFeRAMセル部 306に侵入するのを確実に防止することができ る。したがって、例えば高湿度の環境下における長時間放置による強誘電体キャパ シタ 42の電気的特性の劣化も確実に防止することができる。 In the semiconductor device according to the present embodiment, the barrier film 62, 78 force FeRAM chip region 302 And the scribe part 304, and also extends to the adjacent FeRAM chip area 302, so that the hydrogen or moisture force above the FeRAM cell part 306 or lateral force enters the SFeRAM cell part 306. This can be surely prevented. Therefore, for example, it is possible to reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42 caused by leaving it for a long time in a high humidity environment.
[0154] また、本実施形態による半導体装置では、バリア膜 62、 78の被覆性を確保するた めにバリア膜 62、 78を比較的厚く形成する必要がなぐバリア膜 62、 78を比較的薄 く形成することができる。したがって、バリア膜 62、 78を含む層間絶縁膜 66、 82にコ ンタクトホールを形成する際に、 FeRAMチップ領域 306における各部において、ェ ツチシフトを 70nm以下に抑制することができる。これにより、コンタクト抵抗の上昇を 抑制することができる。また、微細なコンタクトホールを確実に形成することを可能とし 、半導体装置の微細化に寄与することができる。  [0154] In addition, in the semiconductor device according to the present embodiment, the barrier films 62 and 78 which are not required to be formed relatively thick in order to ensure the coverage of the barrier films 62 and 78 are relatively thin. Can be formed. Therefore, when contact holes are formed in the interlayer insulating films 66 and 82 including the barrier films 62 and 78, the etch shift can be suppressed to 70 nm or less in each part in the FeRAM chip region 306. Thereby, an increase in contact resistance can be suppressed. In addition, it is possible to reliably form fine contact holes and contribute to miniaturization of semiconductor devices.
[0155] 上述のように、本実施形態による半導体装置では、強誘電体キャパシタ 42の上方 に形成された第 1金属配線層 56と第 2金属配線層 72との間に形成された平坦なバリ ァ膜 62と、第 2金属配線層 72と第 3金属配線層 88との間に形成された平坦なバリア 膜 78とが形成されているので、水素及び水分を確実にノリアし、水素及び水分が強 誘電体キャパシタ 42の強誘電体膜 38に達するのを確実に防止することができる。こ れにより、水素及び水分による強誘電体キャパシタ 42の電気的特性の劣化を確実に 防止することができ、強誘電体キャパシタを有する半導体装置の PTHS特性を大幅 に向上することができる。  As described above, in the semiconductor device according to the present embodiment, the flat variability formed between the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42. And the flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed, so that hydrogen and moisture can be surely removed, and hydrogen and moisture can be removed. Can be reliably prevented from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
[0156] さらに、本実施形態による半導体装置では、平坦なバリア膜 62、 78が、スクライブ 部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路部 310、口 ジック回路の周辺回路部 312、パッド部 314、これらの境界部であるスクライブ部'パ ッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界部 320にわたつて形成されているので、水素及び水分による強誘電体キャパシタ 42の 電気的特性の劣化を更に確実に防止することができる。  Furthermore, in the semiconductor device according to the present embodiment, the flat barrier films 62 and 78 include the scribe part 304, the FeRAM cell part 306, the peripheral circuit part 308 of the FeRAM, the logic circuit part 310, and the peripheral circuit part of the mouth circuit. 312, pad part 314, scribe part which is a boundary part between them, pad part boundary part 316, pad part / circuit part boundary part 318, and circuit part / circuit part boundary part 320. Therefore, it is possible to more reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture.
[0157] なお、バリア膜 62、 78の膜厚は、以下に述べる観点から、例えば、 50nm以上 100 nm未満、より好ましくは 50nm以上 80nm以下に設定することが望まし 、。 [0158] まず、バリア膜 62、 78の膜厚は、導体プラグに欠損が発生するのを防止する観点 からは、例えば、 40nm以上 lOOnm未満、より好ましくは 40nm以上 80nm以下に設 定することが望ま U、。この点につ!、て図 22及び図 23を用いて説明する。 [0157] The thickness of the barrier films 62 and 78 is preferably set to, for example, 50 nm or more and less than 100 nm, more preferably 50 nm or more and 80 nm or less, from the viewpoint described below. [0158] First, the thickness of the barrier films 62 and 78 may be set to, for example, 40 nm or more and less than lOOnm, and more preferably 40 nm or more and 80 nm or less, from the viewpoint of preventing defects in the conductor plug. Hope U ,. This point will be described with reference to FIGS. 22 and 23. FIG.
[0159] 図 22は、バリア膜を含む層間絶縁膜に埋め込まれた導体プラグに生じる欠損を説 明する断面図である。図 22 (a)はバリア膜が比較的薄い場合を示し、図 22 (b)はバリ ァ膜が比較的厚い場合を示している。図 23は、ノリア膜を含む層間絶縁膜に埋め込 まれた導体プラグに生じた欠損を観察した透過型電子顕微鏡写真である。  FIG. 22 is a cross-sectional view illustrating a defect occurring in a conductor plug embedded in an interlayer insulating film including a barrier film. FIG. 22 (a) shows the case where the barrier film is relatively thin, and FIG. 22 (b) shows the case where the barrier film is relatively thick. FIG. 23 is a transmission electron micrograph observing defects generated in the conductor plug embedded in the interlayer insulating film including the noria film.
[0160] 図 22 (a)及び図 22 (b)に示すように、層間絶縁膜 324上に、配線層 326が形成さ れている。配線層 326が形成された層間絶縁膜 324上には、平坦なノリア膜 328を 含む層間絶縁膜 330が形成されている。層間絶縁膜 330には、配線層 326に達する コンタクトホール 332が形成されている。コンタクトホール 332内には、タングステンよ りなる導体プラグ 334が埋め込まれている。導体プラグ 334が埋め込まれた層間絶縁 膜 330上には、配線層 336が形成されている。  As shown in FIGS. 22A and 22B, a wiring layer 326 is formed on the interlayer insulating film 324. An interlayer insulating film 330 including a flat noria film 328 is formed on the interlayer insulating film 324 on which the wiring layer 326 is formed. A contact hole 332 reaching the wiring layer 326 is formed in the interlayer insulating film 330. A conductor plug 334 made of tungsten is embedded in the contact hole 332. A wiring layer 336 is formed on the interlayer insulating film 330 in which the conductor plug 334 is embedded.
[0161] 酸ィ匕アルミニウム膜よりなるノリア膜 328の膜厚が 80nm以下の場合には、図 22 (a )に示すように、導体プラグ 334はコンタクトホール 332内に十分に埋め込まれ、導体 プラグ 334に欠損は生じな 、。  [0161] When the thickness of the noria film 328 made of an acid aluminum film is 80 nm or less, the conductor plug 334 is sufficiently embedded in the contact hole 332 as shown in FIG. There is no defect in 334.
[0162] 他方、酸ィ匕アルミニウム膜よりなるバリア膜 328の膜厚が 80nmを超えた場合には、 図 22 (b)に示すように、導体プラグ 334がコンタクトホール 332内に十分に埋め込ま れずに、導体プラグ 334に欠損 338が生じる。図 23 (a)及び図 23 (b)は、それぞれ ノリア膜を含む層間絶縁膜に埋め込まれた導体プラグに生じた欠損を観察した透過 型電子顕微鏡写真である。このような欠損 338は、ノリア膜の膜厚力 SlOOnm以上に なると高 、頻度で発生することが確認されて 、る。  [0162] On the other hand, when the thickness of the barrier film 328 made of an oxide aluminum film exceeds 80 nm, the conductor plug 334 is not sufficiently embedded in the contact hole 332 as shown in FIG. In addition, a defect 338 occurs in the conductor plug 334. FIG. 23 (a) and FIG. 23 (b) are transmission electron micrographs observing defects generated in a conductor plug embedded in an interlayer insulating film including a noria film. It has been confirmed that such defects 338 occur at a high frequency when the film thickness force of the noria film becomes more than SlOOnm.
[0163] したがって、バリア膜 62、 78の膜厚は、導体プラグに欠損が発生するのを防止する 観点からは、例えば、 40nm以上 lOOnm未満、より好ましくは 40nm以上 80nm以下 に設定することが望ましい。  [0163] Accordingly, the thickness of the barrier films 62 and 78 is desirably set to, for example, 40 nm or more and less than lOOnm, and more preferably 40 nm or more and 80 nm or less, from the viewpoint of preventing defects in the conductor plug. .
[0164] 他方、バリア膜 62、 78に水素及び水分の拡散防止機能を十分に発揮させるため には、バリア膜 62、 78の膜厚は例えば 50nm以上に設定することが望ましい。  On the other hand, in order for the barrier films 62 and 78 to fully exhibit the function of preventing the diffusion of hydrogen and moisture, the film thickness of the barrier films 62 and 78 is preferably set to 50 nm or more, for example.
[0165] 以上のことから、バリア膜 62、 78の膜厚は、例えば、 50nm以上 lOOnm未満、より 好ましくは 50nm以上 80nm以下に設定することが望ましい。 [0165] From the above, the film thicknesses of the barrier films 62 and 78 are, for example, 50 nm or more and less than lOOnm. Preferably, it is set to 50 nm or more and 80 nm or less.
[0166] (半導体装置の製造方法） [0166] (Method for Manufacturing Semiconductor Device)
次に、本実施形態による半導体装置の製造方法について図 24乃至図 39を用いて 説明する。なお、以下では、基本的に、図 3に示す半導体装置の断面構造に対応す る工程断面図を用いて説明する力 ロジック回路部 310、周辺回路部 308、 312等に おけるトランジスタ、配線等は、通常の半導体装置の製造プロセスを用いて形成する ことができる。  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. In the following, the transistors, wirings, etc. in the power logic circuit part 310, the peripheral circuit parts 308, 312, etc., which are basically explained using the process cross-sectional view corresponding to the cross-sectional structure of the semiconductor device shown in FIG. It can be formed using a normal semiconductor device manufacturing process.
[0167] まず、例えばシリコンよりなる半導体基板 10に、例えば LOCOS (LOCal Oxidation of Silicon)法により、素子領域を画定する素子分離領域 12を形成する。  First, the element isolation region 12 that defines the element region is formed on the semiconductor substrate 10 made of, for example, silicon by, for example, the LOCOS (LOCal Oxidation of Silicon) method.
[0168] 次いで、イオン注入法により、ドーパント不純物を導入することにより、ゥエル 14a、 1 4bを形成する。  [0168] Next, dopants are introduced by ion implantation to form the wells 14a and 14b.
[0169] 次いで、通常のトランジスタの形成方法を用いて、素子領域に、ゲート電極 (ゲート 配線） 18とソース Zドレイン拡散層 22とを有するトランジスタ 24を形成する（図 24 (a) を参照)。  [0169] Next, a transistor 24 having a gate electrode (gate wiring) 18 and a source Z drain diffusion layer 22 is formed in the element region by using a normal transistor formation method (see FIG. 24A). .
[0170] 次!、で、全面に、例えばプラズマ CVD (Chemical Vapor Deposition)法により、例え ば膜厚 200nmの SiON膜 25を形成する。  Next, for example, a 200 nm-thickness SiON film 25 is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition).
[0171] 次いで、全面に、プラズマ TEOSCVD法により、例えば例えば膜厚 600nmのシリ コン酸化膜 26を形成する（図 24 (b)を参照)。 Next, for example, a silicon oxide film 26 of, eg, a 600 nm-thickness is formed on the entire surface by a plasma TEOSCVD method (see FIG. 24B).
[0172] こうして、 SiON膜 25とシリコン酸ィ匕膜 26とにより層間絶縁膜 27が構成される。 Thus, the interlayer insulating film 27 is constituted by the SiON film 25 and the silicon oxide film 26.
[0173] 次いで、例えば CMP法により、層間絶縁膜 27の表面を平坦ィ匕する（図 24 (c)を参 照)。 Next, the surface of the interlayer insulating film 27 is planarized by, eg, CMP (see FIG. 24 (c)).
[0174] 次いで、一酸化二窒素（N O)又は窒素（N )雰囲気にて、例えば 650°C、 30分間  [0174] Next, in a dinitrogen monoxide (N 2 O) or nitrogen (N 2) atmosphere, for example, 650 ° C, 30 minutes
2 2  twenty two
の熱処理を行う。  The heat treatment is performed.
[0175] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 34を形成する（図 25 (a)を参照)。  Next, a silicon oxide film 34 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 25 (a)).
[0176] 次!、で、 N Oガスを用いて発生させたプラズマ雰囲気にて、例えば 350°C、 2分間 [0176] Next !, in a plasma atmosphere generated using N 2 O gas, for example, at 350 ° C for 2 minutes
2  2
の熱処理を行う。  The heat treatment is performed.
[0177] 次いで、全面に、例えばスパッタ法又は CVD法により、例えば膜厚 20〜50nmの 酸ィ匕アルミニウム膜 36aを形成する。 [0177] Next, on the entire surface, for example, with a film thickness of 20 to 50 nm by, for example, sputtering or CVD. An aluminum oxide film 36a is formed.
[0178] 次いで、例えば RTA(Rapid Thermal Annealing)法により、酸素雰囲気中にて熱処 理を行う。熱処理温度は例えば 650°Cとし、熱処理時間は例えば 1〜2分とする。 [0178] Next, heat treatment is performed in an oxygen atmosphere by, for example, RTA (Rapid Thermal Annealing). The heat treatment temperature is, for example, 650 ° C., and the heat treatment time is, for example, 1-2 minutes.
[0179] 次いで、全面に、例えばスパッタ法により、例えば膜厚 100〜200nmの Pt膜 36bを 形成する。 [0179] Next, a Pt film 36b having a thickness of 100 to 200 nm, for example, is formed on the entire surface by, eg, sputtering.
[0180] こうして、酸ィ匕アルミニウム膜 36aと Pt膜 36bとからなる積層膜 36が形成される。積 層膜 36は、強誘電体キャパシタ 42の下部電極となるものである。  Thus, a laminated film 36 composed of the aluminum oxide film 36a and the Pt film 36b is formed. The multilayer film 36 becomes a lower electrode of the ferroelectric capacitor 42.
[0181] 次 、で、全面に、例えばスパッタ法により、強誘電体膜 38を形成する。強誘電体膜 38としては、例えば膜厚 100〜250nmの PZT膜を形成する。  Next, a ferroelectric film 38 is formed on the entire surface by, eg, sputtering. As the ferroelectric film 38, for example, a PZT film having a thickness of 100 to 250 nm is formed.
[0182] なお、ここでは、強誘電体膜 38をスパッタ法により形成する場合を例に説明したが 、強誘電体膜の形成方法はスパッタ法に限定されるものではない。例えば、ゾル 'ゲ ル法、 MOD (Metal Organic Deposition)法、 MOCVD法等により強誘電体膜を形成 してちよい。  Here, the case where the ferroelectric film 38 is formed by the sputtering method has been described as an example, but the method of forming the ferroelectric film is not limited to the sputtering method. For example, the ferroelectric film may be formed by a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD method, or the like.
[0183] 次 、で、例えば RTA法により、酸素雰囲気中にて熱処理を行う。熱処理温度は例 えば 550〜600°Cとし、熱処理時間は例えば 60〜120秒とする。  Next, heat treatment is performed in an oxygen atmosphere by, for example, the RTA method. The heat treatment temperature is, for example, 550 to 600 ° C, and the heat treatment time is, for example, 60 to 120 seconds.
[0184] 次いで、例えばスパッタ法又は MOCVD法により、例えば膜厚 25〜75nmの IrO [0184] Next, for example, IrO having a film thickness of 25 to 75 nm is formed by sputtering or MOCVD.
X  X
膜 40aを形成する。  A film 40a is formed.
[0185] 次いで、アルゴン及び酸素雰囲気にて、例えば 600〜800°C、 10〜： LOO秒間の熱 処理を行う。  [0185] Next, heat treatment is performed in an atmosphere of argon and oxygen, for example, 600 to 800 ° C, 10 to: LOO seconds.
[0186] 次いで、例えばスパッタ法又は MOCVD法により、例えば膜厚 150〜250nmの Ir O膜 40bを形成する。この際、 IrO膜 40bの酸素の組成比 Y力 IrO膜 40aの酸素 Next, an Ir 2 O film 40b having a thickness of 150 to 250 nm, for example, is formed by, eg, sputtering or MOCVD. At this time, the oxygen composition ratio of the IrO film 40b Y force The oxygen of the IrO film 40a
Y Y X Y Y X
の組成比 Xより高くなるように、 IrO膜 40bを形成する。  The IrO film 40b is formed so as to be higher than the composition ratio X.
Y  Y
[0187] こうして、 IrO膜 40aと IrO膜 40bとからなる積層膜 40が形成される（図 25 (b)を参  [0187] Thus, the laminated film 40 including the IrO film 40a and the IrO film 40b is formed (see FIG. 25B).
X Y  X Y
照)。積層膜 40は、強誘電体キャパシタ 42の上部電極となるものである。  See). The laminated film 40 becomes an upper electrode of the ferroelectric capacitor 42.
[0188] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 98を形成する。 [0188] Next, a photoresist film 98 is formed on the entire surface by, eg, spin coating.
[0189] 次いで、フォトリソグラフィ一により、フォトレジスト膜 98を強誘電体キャパシタ 42の 上部電極 40の平面形状にパターユングする。 Next, the photoresist film 98 is patterned into the planar shape of the upper electrode 40 of the ferroelectric capacitor 42 by photolithography.
[0190] 次!、で、フォトレジスト膜 98をマスクとして、積層膜 40をエッチングする。エッチング ガスとしては、例えば Arガスと C1ガスとを用いる。こうして、積層膜よりなる上部電極 4 Next, the stacked film 40 is etched using the photoresist film 98 as a mask. etching For example, Ar gas and C1 gas are used as the gas. Thus, the upper electrode made of a laminated film 4
2  2
0が形成される（図 25 (c)を参照)。この後、フォトレジスト膜 98を剥離する。  0 is formed (see FIG. 25 (c)). Thereafter, the photoresist film 98 is peeled off.
[0191] 次いで、例えば酸素雰囲気にて、例えば 400〜700°C、 30〜120分間の熱処理を 行う。この熱処理は、上部電極 40の表面に異常が生ずるのを防止するためのもので ある。 [0191] Next, for example, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 700 ° C for 30 to 120 minutes. This heat treatment is intended to prevent the surface of the upper electrode 40 from becoming abnormal.
[0192] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 100を形成する。  [0192] Next, a photoresist film 100 is formed on the entire surface by, eg, spin coating.
[0193] 次いで、フォトリソグラフィ一により、フォトレジスト膜 100を強誘電体キャパシタ 42の 強誘電体膜 38の平面形状にパターユングする。 [0193] Next, the photoresist film 100 is patterned into the planar shape of the ferroelectric film 38 of the ferroelectric capacitor 42 by photolithography.
[0194] 次いで、フォトレジスト膜 100をマスクとして、強誘電体膜 38をエッチングする（図 26 Next, the ferroelectric film 38 is etched using the photoresist film 100 as a mask (FIG. 26).
(a)を参照)。この後、フォトレジスト膜 100を剥離する。  (See (a)). Thereafter, the photoresist film 100 is peeled off.
[0195] 次いで、酸素雰囲気にて、例えば 300〜400°C、 30〜 120分間の熱処理を行う。 [0195] Next, heat treatment is performed in an oxygen atmosphere, for example, at 300 to 400 ° C for 30 to 120 minutes.
[0196] 次いで、例えばスノッタ法又は CVD法により、ノリア膜 44を形成する（図 26 (b)を 参照)。ノリア膜 44としては、例えば膜厚 20〜50nmの酸ィ匕アルミニウム膜を形成す る。 [0196] Next, the noria film 44 is formed by, for example, the snotter method or the CVD method (see FIG. 26B). As the noria film 44, for example, an aluminum oxide film having a thickness of 20 to 50 nm is formed.
[0197] 次いで、酸素雰囲気にて、例えば 400〜600°C、 30〜 120分間の熱処理を行う。  [0197] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
[0198] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 102を形成する。 [0198] Next, a photoresist film 102 is formed on the entire surface by, eg, spin coating.
[0199] 次いで、フォトリソグラフィ一により、フォトレジスト膜 102を強誘電体キャパシタ 42の 下部電極 36の平面形状にパターユングする。 Next, the photoresist film 102 is patterned into the planar shape of the lower electrode 36 of the ferroelectric capacitor 42 by photolithography.
[0200] 次 、で、フォトレジスト膜 102をマスクとして、ノリア膜 44及び積層膜 36をエツチン グする（図 26 (c)を参照)。こうして、積層膜よりなる下部電極 36が形成される。また、 ノリア膜 44が、上部電極 40及び強誘電体膜 38を覆うように残存する。この後、フォト レジスト膜 102を剥離する。 Next, using the photoresist film 102 as a mask, the noria film 44 and the laminated film 36 are etched (see FIG. 26C). Thus, the lower electrode 36 made of a laminated film is formed. Further, the noria film 44 remains so as to cover the upper electrode 40 and the ferroelectric film 38. Thereafter, the photoresist film 102 is peeled off.
[0201] 次いで、酸素雰囲気にて、例えば 400〜600°C、 30〜 120分間の熱処理を行う。 [0201] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
[0202] 次いで、全面に、例えばスパッタ法又は CVD法により、バリア膜 46を形成する。ノ リア膜 46としては、例えば膜厚 20〜： LOOnmの酸ィ匕アルミニウム膜を形成する（図 27[0202] Next, the barrier film 46 is formed on the entire surface by, eg, sputtering or CVD. As the noria film 46, for example, an oxide aluminum film having a film thickness of 20 to: LOOnm is formed (FIG. 27).
(a)を参照)。こうして、バリア膜 44により覆われた強誘電体キャパシタ 42を更に覆う ようにノリア膜 46が形成される。 (See (a)). Thus, the noria film 46 is formed so as to further cover the ferroelectric capacitor 42 covered with the barrier film 44.
[0203] 次いで、酸素雰囲気にて、例えば 500〜700°C、 30〜 120分間の熱処理を行う。 [0204] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 1500nmのシリ コン酸ィ匕膜よりなるシリコン酸ィ匕膜 48を形成する（図 27 (b)を参照)。 [0203] Next, heat treatment is performed in an oxygen atmosphere, for example, at 500 to 700 ° C for 30 to 120 minutes. Next, a silicon oxide film 48 made of a silicon oxide film having a thickness of, eg, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 27B).
[0205] 次いで、例えば CMP法により、シリコン酸ィ匕膜 48の表面を平坦ィ匕する（図 27 (c)を 参照)。  [0205] Next, the surface of the silicon oxide film 48 is flattened by, eg, CMP (see FIG. 27C).
[0206] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0206] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 48中の水分を除去する とともに、シリコン酸ィ匕膜 48の膜質を変化させ、シリコン酸ィ匕膜 48中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 48の表面は窒化され、シ リコン酸ィ匕膜 48の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 48 and changing the film quality of the silicon oxide film 48 so that the moisture does not easily enter the silicon oxide film 48. By this heat treatment, the surface of the silicon oxide film 48 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 48.
[0207] 次いで、フォトリソグラフィー及びエッチングにより、シリコン酸ィ匕膜 48、バリア膜 46、 シリコン酸ィ匕膜 34、及び層間絶縁膜 27に、ソース/ドレイン拡散層 22に達するコン タクトホール 50a、 50bを形成する（図 28 (a)を参照）。  [0207] Next, contact holes 50a, 50b reaching the source / drain diffusion layer 22 are formed in the silicon oxide film 48, the barrier film 46, the silicon oxide film 34, and the interlayer insulating film 27 by photolithography and etching. (See FIG. 28 (a)).
[0208] 次 、で、全面に、例えばスパッタ法により、例えば膜厚 20nmの Ti膜を形成する。  [0208] Next, a Ti film of, eg, a 20 nm-thickness is formed on the entire surface by, eg, sputtering.
続いて、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。こ うして、 Ti膜と TiN膜とによりバリアメタル膜 (図示せず)が構成される。  Subsequently, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering. Thus, the Ti film and the TiN film constitute a barrier metal film (not shown).
[0209] 次 、で、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0210] 次いで、例えば CMP法により、シリコン酸ィ匕膜 48の表面が露出するまで、タンダス テン膜及びバリアメタル膜を研磨する。こうして、コンタクトホール 50a、 50b内に、タン ダステンよりなる導体プラグ 54a、 54bがそれぞれ埋め込まれる（図 28 (b)を参照)。  [0210] Next, the tungsten film and the barrier metal film are polished by, for example, CMP until the surface of the silicon oxide film 48 is exposed. Thus, the conductor plugs 54a and 54b made of tungsten are embedded in the contact holes 50a and 50b, respectively (see FIG. 28B).
[0211] 次いで、例えばアルゴンガスを用いたプラズマ洗浄を行う。これにより、導体プラグ 5 4a、 54b表面に存在する自然酸ィ匕膜等が除去される。  [0211] Next, plasma cleaning is performed using, for example, argon gas. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 54a and 54b are removed.
[0212] 次いで、全面に、例えば CVD法により、例えば膜厚 lOOnmの SiON膜 104を形成 する。  [0212] Next, a SiON film 104 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD.
[0213] 次いで、フォトリソグラフィー及びドライエッチングにより、 SiON膜 104、シリコン酸 化膜 48、バリア膜 46、及びバリア膜 44に、強誘電体キャパシタ 42の上部電極 40に 達するコンタクトホール 52aと、強誘電体キャパシタ 42の下部電極 36に達するコンタ タトホール 52aとを形成する（図 28 (c)を参照)。 [0214] 次いで、酸素雰囲気にて、例えば 400〜600°C、 30〜 120分間の熱処理を行う。 この熱処理は、強誘電体キャパシタ 42の強誘電体膜 38に酸素を供給し、強誘電体 キャパシタ 42の電気的特性を回復するためのものである。なお、ここでは酸素雰囲気 中にて熱処理を行う場合を例に説明したが、オゾン雰囲気中にて熱処理を行っても よい。オゾン雰囲気中にて熱処理を行った場合にも、キャパシタの強誘電体膜 38に 酸素を供給することができ、強誘電体キャパシタ 42の電気的特性を回復することが 可能である。 [0213] Next, by photolithography and dry etching, the contact hole 52a reaching the upper electrode 40 of the ferroelectric capacitor 42 and the ferroelectric film are formed in the SiON film 104, the silicon oxide film 48, the barrier film 46, and the barrier film 44. A contact hole 52a reaching the lower electrode 36 of the body capacitor 42 is formed (see FIG. 28 (c)). [0214] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42. Note that here, the case where the heat treatment is performed in an oxygen atmosphere has been described as an example, but the heat treatment may be performed in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen can be supplied to the ferroelectric film 38 of the capacitor, and the electrical characteristics of the ferroelectric capacitor 42 can be recovered.
[0215] 次いで、エッチングにより SiON膜 104を除去する。  [0215] Next, the SiON film 104 is removed by etching.
[0216] 次!、で、全面に、例えば膜厚 150nmの TiN膜と、例えば膜厚 550nmの AlCu合金 膜と、例えば膜厚 5nmの Ti膜と、膜厚 150nmの TiN膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と Ti膜と TiN膜とを順次積層してなる導体膜が形成される。  Next, for example, a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially stacked on the entire surface. . Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
[0217] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターユングする 。これにより、第 1金属配線層 56、すなわち強誘電体キャパシタ 42の上部電極 40と 導体プラグ 54aとに電気的に接続された配線 56a、強誘電体キャパシタ 42の下部電 極 36に電気的に接続された配線 56b、及び導体プラグ 54bに電気的に接続された 配線 56cが形成される（図 29 (a)を参照)。  Next, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 56, that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected. The wiring 56b thus formed and the wiring 56c electrically connected to the conductor plug 54b are formed (see FIG. 29 (a)).
[0218] 次いで、酸素雰囲気にて、例えば 350°C、 30分間の熱処理を行う。  [0218] Next, heat treatment is performed in an oxygen atmosphere, for example, at 350 ° C for 30 minutes.
[0219] 次いで、全面に、例えばスパッタ法又は CVD法により、バリア膜 58を形成する。ノ リア膜 58としては、例えば膜厚 20〜70nmの酸ィ匕アルミニウム膜を形成する（図 29 ( b)を参照)。ここでは、ノリア膜 58として、膜厚 20nmの酸ィ匕アルミニウム膜を形成す る。こうして、配線 56a、 56b、 56cの上面及び側面を覆うようにバリア膜 58が形成さ れる。  [0219] Next, a barrier film 58 is formed on the entire surface by, eg, sputtering or CVD. As the noria film 58, for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed (see FIG. 29B). Here, as the noria film 58, an aluminum oxide film having a thickness of 20 nm is formed. In this way, the barrier film 58 is formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, and 56c.
[0220] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 2600nmのシリ コン酸化膜 60を形成する（図 30 (a)を参照)。  Next, a silicon oxide film 60 of, eg, a 2600 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 30A).
[0221] 次いで、例えば CMP法により、シリコン酸ィ匕膜 60の表面を平坦ィ匕する（図 30 (b)を 参照)。 Next, the surface of the silicon oxide film 60 is flattened by, eg, CMP (see FIG. 30B).
[0222] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0222] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 60中の水分を除去する とともに、シリコン酸ィ匕膜 60の膜質を変化させ、シリコン酸ィ匕膜 60中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 60の表面は窒化され、シ リコン酸ィ匕膜 60の表面には SiON膜 (図示せず)が形成される。 Perform heat treatment at 0 ° C for 4 minutes. This heat treatment removes moisture in the silicon oxide film 60. At the same time, the film quality of the silicon oxide film 60 is changed to make it difficult for moisture to enter the silicon oxide film 60. By this heat treatment, the surface of the silicon oxide film 60 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 60.
[0223] 次いで、平坦化されたシリコン酸化膜 60上に、例えばプラズマ TEOSCVD法によ り、例えば膜厚 lOOnmのシリコン酸ィ匕膜 61を形成する。平坦化されたシリコン酸ィ匕 膜 60上にシリコン酸ィ匕膜 61を形成するため、シリコン酸ィ匕膜 61は平坦となる。  Next, a silicon oxide film 61 having a thickness of, for example, lOOnm is formed on the planarized silicon oxide film 60 by, eg, plasma TEOSCVD. Since the silicon oxide film 61 is formed on the planarized silicon oxide film 60, the silicon oxide film 61 becomes flat.
[0224] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0224] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 61中の水分を除去する とともに、シリコン酸ィ匕膜 61の膜質を変化させ、シリコン酸ィ匕膜 61中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 61の表面は窒化され、シ リコン酸ィ匕膜 61の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 61 and changing the film quality of the silicon oxide film 61 so that moisture does not easily enter the silicon oxide film 61. By this heat treatment, the surface of the silicon oxide film 61 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 61.
[0225] 次いで、平坦なシリコン酸ィ匕膜 61上に、例えばスパッタ法又は CVD法により、バリ ァ膜 62を形成する。ノ リア膜 62としては、例えば膜厚 20〜70nmの酸ィ匕アルミ-ゥ ム膜を形成する。ここでは、ノ リア膜 62として、膜厚 50nmの酸ィ匕アルミニウム膜を形 成する。平坦なシリコン酸ィ匕膜 61上にバリア膜 62を形成するため、ノ リア膜 62は平 坦となる。また、 CMP法により表面が平坦ィ匕されたシリコン酸ィ匕膜 60上にシリコン酸 化膜 61を介してノ リア膜 62を形成している。このため、マイクロ 'スクラッチによってシ リコン酸ィ匕膜 60の表面に生じた段差等によりバリア膜 62に欠陥部分が発生するのを 抑帘 Uすることができる。 [0225] Next, a barrier film 62 is formed on the flat silicon oxide film 61 by, for example, sputtering or CVD. As the noria film 62, for example, an acid aluminum film having a thickness of 20 to 70 nm is formed. Here, an oxide aluminum film having a thickness of 50 nm is formed as the noor film 62. Since the barrier film 62 is formed on the flat silicon oxide film 61, the NOR film 62 becomes flat. In addition, a noria film 62 is formed on a silicon oxide film 60 whose surface is flattened by the CMP method via a silicon oxide film 61. For this reason, it is possible to suppress the occurrence of a defective portion in the barrier film 62 due to a step or the like generated on the surface of the silicon oxide film 60 by the micro scratch.
[0226] ノ リア膜 62は、図 31に示すように、 FeRAMチップ領域 302及びスクライブ部 304 にわたつて形成するとともに、隣接する FeRAMチップ領域 302にまでわたって形成 する。すなわち、ノ リア膜 62は、スクライブ部 304、 FeRAMセル部 306、 FeRAMの 周辺回路部 308、ロジック回路部 310、ロジック回路の周辺回路部 312、 ノ ッド部 31 4、これらの境界部であるスクライブ部'パッド部間境界部 316、パッド部，回路部間境 界部 318、及び回路部，回路部間境界部 320にわたつて形成する。  As shown in FIG. 31, the noor film 62 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304 and also to the adjacent FeRAM chip region 302. That is, the NORA film 62 is a scribe part 304, a FeRAM cell part 306, a peripheral circuit part 308 of the FeRAM, a logic circuit part 310, a peripheral circuit part 312 of the logic circuit, a node part 314, and a boundary part thereof. The scribe portion is formed across the pad portion boundary portion 316, the pad portion and the circuit portion boundary portion 318, and the circuit portion and circuit portion boundary portion 320.
[0227] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 64を形成する（図 32 (a)を参照)。  [0227] Next, a silicon oxide film 64 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 32A).
[0228] こうして、バリア膜 58、シリコン酸ィ匕膜 60、シリコン酸ィ匕膜 61、バリア膜 62、及びシリ コン酸ィ匕膜 64により層間絶縁膜 66が構成される。 [0228] Thus, the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon film An interlayer insulating film 66 is constituted by the conic acid film 64.
[0229] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0229] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 64中の水分を除去する とともに、シリコン酸ィ匕膜 64の膜質を変化させ、シリコン酸ィ匕膜 64中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 64の表面は窒化され、シ リコン酸ィ匕膜 64の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 64 and changing the film quality of the silicon oxide film 64 so that moisture does not easily enter the silicon oxide film 64. By this heat treatment, the surface of the silicon oxide film 64 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 64.
[0230] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸ィ匕膜 64、 ノ リア 膜 62、シリコン酸ィ匕膜 61、シリコン酸ィ匕膜 60、及びバリア膜 58に、配線 56cに達する コンタクトホール 68を形成する（図 32 (b)を参照）。  [0230] Next, contact holes reaching the wiring 56c are formed in the silicon oxide film 64, the noria film 62, the silicon oxide film 61, the silicon oxide film 60, and the barrier film 58 by photolithography and dry etching. 68 (see FIG. 32 (b)).
[0231] 次いで、 N雰囲気にて、例えば 350°C、 120分間の熱処理を行う。  [0231] Next, heat treatment is performed in an N atmosphere, for example, at 350 ° C for 120 minutes.
2  2
[0232] 次 、で、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。  [0232] Next, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
こうして、 TiN膜によりバリアメタル膜 (図示せず)が構成される。  Thus, a barrier metal film (not shown) is constituted by the TiN film.
[0233] 次 、で、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  [0233] Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0234] 次いで、例えば EB (エッチバック）法により、シリコン酸ィ匕膜 64の表面が露出するま で、タングステン膜をエッチバックする。こうして、コンタクトホール 68内に、タンダステ ンよりなる導体プラグ 70が埋め込まれる（図 33 (a)を参照)。  [0234] Next, the tungsten film is etched back until the surface of the silicon oxide film 64 is exposed, for example, by an EB (etch back) method. In this way, the conductor plug 70 made of tandastain is embedded in the contact hole 68 (see FIG. 33 (a)).
[0235] 次 、で、全面に、例えば膜厚 500nmの AlCu合金膜と、例えば膜厚 5nmの Ti膜と 、例えば膜厚 150nmの TiN膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と T i膜と TiN膜とを順次積層してなる導体膜が形成される。  Next, an AlCu alloy film having a thickness of, for example, 500 nm, a Ti film having a thickness of, for example, 5 nm, and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
[0236] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターユングする 。これにより、第 2金属配線層 72、すなわち配線 72a、及び導体プラグ 70に電気的に 接続された配線 72bが形成される（図 33 (b)を参照)。配線 72a、 72bを形成する際 のドライエッチングにおいては、シリコン酸ィ匕膜 64がエッチングのストッパ膜として機 能する。このシリコン酸ィ匕膜 64によりバリア膜 62が保護され、配線 72a、 72bを形成 する際のエッチングによりバリア膜 62の膜厚が減少し或いはノ リア膜 62が除去され てしまうのを防止することができる。これにより、ノ リア膜 62の水素及び水分の拡散機 能が劣化するのを防止することができる。 [0237] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 2200nmのシリ コン酸化膜 74を形成する（図 34 (a)を参照)。 [0236] Next, the conductor film is patterned by photolithography and dry etching. As a result, the second metal wiring layer 72, that is, the wiring 72a and the wiring 72b electrically connected to the conductor plug 70 are formed (see FIG. 33B). In the dry etching for forming the wirings 72a and 72b, the silicon oxide film 64 functions as an etching stopper film. The silicon oxide film 64 protects the barrier film 62, and prevents the thickness of the barrier film 62 from being reduced or the removal of the NOR film 62 by etching when the wirings 72a and 72b are formed. Can do. Thereby, it is possible to prevent the hydrogen and moisture diffusing function of the nore film 62 from being deteriorated. Next, a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 34 (a)).
[0238] 次いで、例えば CMP法により、シリコン酸ィ匕膜 74の表面を平坦ィ匕する（図 34 (b)を 参照)。 [0238] Next, the surface of the silicon oxide film 74 is flattened by, eg, CMP (see FIG. 34B).
[0239] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0239] In a plasma atmosphere generated using N 2 O gas or N gas, for example, 35!
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 74中の水分を除去する とともに、シリコン酸ィ匕膜 74の膜質を変化させ、シリコン酸ィ匕膜 74中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 74の表面は窒化され、シ リコン酸ィ匕膜 74の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 74 and changing the film quality of the silicon oxide film 74 so that the moisture does not easily enter the silicon oxide film 74. By this heat treatment, the surface of the silicon oxide film 74 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 74.
[0240] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸ィ匕膜 76を形成する。平坦化されたシリコン酸ィ匕膜 74上にシリコン酸ィ匕膜 76を 形成するため、シリコン酸ィ匕膜 76は平坦となる。  [0240] Next, a silicon oxide film 76 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD. Since the silicon oxide film 76 is formed on the planarized silicon oxide film 74, the silicon oxide film 76 becomes flat.
[0241] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0241] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 76中の水分を除去する とともに、シリコン酸ィ匕膜 76の膜質を変化させ、シリコン酸ィ匕膜 76中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 76の表面は窒化され、シ リコン酸ィ匕膜 76の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 76 and changing the film quality of the silicon oxide film 76 so that moisture does not easily enter the silicon oxide film 76. By this heat treatment, the surface of the silicon oxide film 76 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 76.
[0242] 次いで、平坦なシリコン酸ィ匕膜 76上に、例えばスパッタ法又は CVD法により、バリ ァ膜 78を形成する。ノ リア膜 78としては、例えば膜厚 20〜70nmの酸ィ匕アルミ-ゥ ム膜を形成する。ここでは、ノ リア膜 78として、膜厚 50nmの酸ィ匕アルミニウム膜を形 成する。平坦なシリコン酸ィ匕膜 76上にバリア膜 78を形成するため、ノ リア膜 78は平 坦となる。また、 CMP法により表面が平坦ィ匕されたシリコン酸ィ匕膜 74上にシリコン酸 化膜 76を介してノ リア膜 78を形成している。このため、マイクロ 'スクラッチによってシ リコン酸ィ匕膜 74の表面に生じた段差等によりバリア膜 78に欠陥部分が発生するのを 抑帘 Uすることができる。 Next, a barrier film 78 is formed on the flat silicon oxide film 76 by, eg, sputtering or CVD. As the NOR film 78, for example, an acid aluminum film having a film thickness of 20 to 70 nm is formed. Here, an oxide aluminum film having a thickness of 50 nm is formed as the noria film 78. Since the barrier film 78 is formed on the flat silicon oxide film 76, the NOR film 78 becomes flat. Further, a noor film 78 is formed on the silicon oxide film 74 whose surface is flattened by the CMP method via the silicon oxide film 76. For this reason, it is possible to suppress the occurrence of a defective portion in the barrier film 78 due to a step or the like generated on the surface of the silicon oxide film 74 by the micro scratch.
[0243] ノ リア膜 78は、図 35に示すように、 FeRAMチップ領域 302及びスクライブ部 304 にわたつて形成するとともに、隣接する FeRAMチップ領域 302にまでわたって形成 する。すなわち、ノ リア膜 78は、スクライブ部 304、 FeRAMセル部 306、 FeRAMの 周辺回路部 308、ロジック回路部 310、ロジック回路の周辺回路部 312、パッド部 31 4、これらの境界部であるスクライブ部'パッド部間境界部 316、パッド部，回路部間境 界部 318、及び回路部，回路部間境界部 320にわたつて形成する。 [0243] As shown in FIG. 35, the noria film 78 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304 and also to the adjacent FeRAM chip region 302. That is, the NORA film 78 is formed of the scribe portion 304, the FeRAM cell portion 306, and the FeRAM. Peripheral circuit part 308, logic circuit part 310, peripheral circuit part 312 of logic circuit, pad part 31 4, scribe part which is the boundary part between these parts' pad part boundary part 316, pad part, boundary part between circuit parts 318, And the circuit part and the boundary part 320 between the circuit parts.
[0244] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 80を形成する（図 36 (a)を参照)。  Next, a silicon oxide film 80 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 36A).
[0245] こうして、シリコン酸ィ匕膜 74、シリコン酸ィ匕膜 76、バリア膜 78、及びシリコン酸化膜 8 0により層間絶縁膜 82が構成される。  In this way, the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80 constitute the interlayer insulating film 82.
[0246] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0246] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 80中の水分を除去する とともに、シリコン酸ィ匕膜 76の膜質を変化させ、シリコン酸ィ匕膜 80中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 80の表面は窒化され、シ リコン酸ィ匕膜 80の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 80 and changing the film quality of the silicon oxide film 76 so that the moisture does not easily enter the silicon oxide film 80. By this heat treatment, the surface of the silicon oxide film 80 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 80.
[0247] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸ィ匕膜 80、バリア 膜 78、シリコン酸ィ匕膜 76、及びシリコン酸ィ匕膜 74に、配線 72a、 72bに達するコンタ タトホール 84a、 84bを形成する（図 36 (b)を参照）。  [0247] Next, contact holes 84a, 84b reaching the wirings 72a, 72b are formed on the silicon oxide film 80, the barrier film 78, the silicon oxide film 76, and the silicon oxide film 74 by photolithography and dry etching. (See Figure 36 (b)).
[0248] 次いで、 N雰囲気にて、例えば 350°C、 120分間の熱処理を行う。  [0248] Next, heat treatment is performed in an N atmosphere, for example, at 350 ° C for 120 minutes.
2  2
[0249] 次 、で、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。  [0249] Next, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
こうして、 TiN膜によりバリアメタル膜 (図示せず)が構成される。  Thus, a barrier metal film (not shown) is constituted by the TiN film.
[0250] 次 、で、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0251] 次いで、例えば EB法により、シリコン酸ィ匕膜 80の表面が露出するまで、タンダステ ン膜をエッチバックする。こうして、コンタクトホール 84a、 84b内〖こ、タングステンよりな る導体プラグ 86a、 86bがそれぞれ埋め込まれる（図 37 (a)を参照)。  Next, the tandastain film is etched back by, for example, the EB method until the surface of the silicon oxide film 80 is exposed. In this way, the inner surfaces of the contact holes 84a and 84b and the conductor plugs 86a and 86b made of tungsten are embedded (see FIG. 37 (a)).
[0252] 次いで、全面に、例えば膜厚 500nmの AlCu合金膜と、例えば膜厚 150nmの TiN 膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と TiN膜とを順次積層してなる 導体膜が形成される。  [0252] Next, an AlCu alloy film having a thickness of, for example, 500 nm and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, and a TiN film.
[0253] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターユングする 。これにより、第 3金属配線層 88、すなわち導体プラグ 86aに電気的に接続された配 線 88a、及び導体プラグ 86bに電気的に接続された配線 88bが形成される（図 37 (b )を参照)。配線 88a、 88bを形成する際のドライエッチングにおいては、シリコン酸ィ匕 膜 80がエッチングのストツバ膜として機能する。このシリコン酸ィ匕膜 80によりバリア膜 78が保護され、配線 88a、 88bを形成する際のエッチングによりバリア膜 78の膜厚が 減少し或いはノ リア膜 78が除去されてしまうのを防止することができる。これにより、 ノ リア膜 78の水素及び水分の拡散機能が劣化するのを防止することができる。 [0253] Next, the conductor film is patterned by photolithography and dry etching. As a result, the wiring electrically connected to the third metal wiring layer 88, that is, the conductor plug 86a. A line 88a and a wiring 88b electrically connected to the conductor plug 86b are formed (see FIG. 37 (b)). In dry etching when the wirings 88a and 88b are formed, the silicon oxide film 80 functions as an etching stover film. The silicon oxide film 80 protects the barrier film 78, and prevents the film thickness of the barrier film 78 from being reduced or removed from the etching when the wirings 88a and 88b are formed. Can do. As a result, it is possible to prevent the hydrogen and moisture diffusing functions of the NORA film 78 from deteriorating.
[0254] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 90を形成する。  [0254] Next, a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
[0255] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0255] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 90中の水分を除去する とともに、シリコン酸ィ匕膜 90の膜質を変化させ、シリコン酸ィ匕膜 90中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 90の表面は窒化され、シ リコン酸ィ匕膜 90の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing water in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that the water does not easily enter the silicon oxide film 90. By this heat treatment, the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
[0256] 次いで、例えば CVD法により、例えば膜厚 350nmのシリコン窒化膜 92を形成する Next, a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
(図 38 (a)を参照)。シリコン窒化膜 92は、水分を遮断し、水分により金属配線層 88、 (See Figure 38 (a)). The silicon nitride film 92 blocks moisture and the metal wiring layer 88,
72、 56等が腐食するのを防止するためのものである。 This is to prevent corrosion of 72, 56, etc.
[0257] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 106を形成する。 Next, a photoresist film 106 is formed on the entire surface by, eg, spin coating.
[0258] 次いで、フォトリソグラフィ一により、フォトレジスト膜 106に、配線 (ボンディングパッ ド） 88bに達する開口部をシリコン窒化膜 92及びシリコン酸ィ匕膜 90に形成する領域 を露出する開口部 108を形成する。 [0258] Next, by photolithography, an opening 108 is formed in the photoresist film 106 that exposes a region where an opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90. Form.
[0259] 次いで、フォトレジスト膜 106をマスクとして、シリコン窒化膜 92及びシリコン酸ィ匕膜Next, using the photoresist film 106 as a mask, the silicon nitride film 92 and the silicon oxide film
90をエッチングする。こうして、シリコン窒化膜 92及びシリコン酸ィ匕膜 90に、配線 (ボ ンデイングパッド) 88bに達する開口部 96aが形成される（図 38 (b)を参照)。この後、 フォトレジスト膜 106を剥離する。 Etch 90. Thus, an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90 (see FIG. 38B). Thereafter, the photoresist film 106 is peeled off.
[0260] 次 、で、例えばスピンコート法により、例えば膜厚 2〜6 μ mのポリイミド榭脂膜 94を 形成する（図 39 (a)を参照)。 Next, a polyimide resin film 94 having a film thickness of 2 to 6 μm, for example, is formed by, eg, spin coating (see FIG. 39 (a)).
[0261] 次いで、フォトリソグラフィ一により、ポリイミド榭脂膜 94に、配線 (ボンディングパッド[0261] Next, a wiring (bonding pad) is formed on the polyimide resin film 94 by photolithography.
) 88bに達する開口部 96bを形成する（図 39 (b)を参照)。 [0262] こうして、本実施形態による半導体装置が製造される。 ) Form an opening 96b that reaches 88b (see Figure 39 (b)). [0262] Thus, the semiconductor device according to the present embodiment is manufactured.
[0263] (評価結果）  [0263] (Evaluation result)
本実施形態による半導体装置について PTHS試験を行い、本実施形態による半導 体装置の PTHS特性を評価した結果について説明する。  The results of conducting a PTHS test on the semiconductor device according to the present embodiment and evaluating the PTHS characteristics of the semiconductor device according to the present embodiment will be described.
[0264] PTHS試験では、 2気圧、温度 121°C、湿度 100%の条件下で、本実施形態による 半導体装置の FeRAMチップを保管し、 168時間、 336時間、 504時間、 504時間、 及び 672時間経過した時点のそれぞれにおいて、同一ゥエーハを用いて形成された 5つのチップ試料毎に不良セルの発生の有無を確認した。 PTHS試験を行った本実 施形態による半導体装置では、バリア膜 58の膜厚を 20nm、平坦なバリア膜 62の膜 厚を 50nm、平坦なバリア膜 78の膜厚を 70nmとした。  [0264] In the PTHS test, the FeRAM chip of the semiconductor device according to the present embodiment was stored under conditions of 2 atm, temperature 121 ° C, and humidity 100%, and 168 hours, 336 hours, 504 hours, 504 hours, and 672 At each time point, the presence or absence of defective cells was confirmed for each of the five chip samples formed using the same wafer. In the semiconductor device according to the present embodiment in which the PTHS test was performed, the film thickness of the barrier film 58 was 20 nm, the film thickness of the flat barrier film 62 was 50 nm, and the film thickness of the flat barrier film 78 was 70 nm.
[0265] なお、比較例として、平坦なノリア膜 58が形成されていない場合、すなわち平坦な ノ リア膜が 1層のみ形成されている場合についても上記と同様の PTHS試験を行つ た。比較例 1による半導体装置では、バリア膜 58の膜厚を 70nm、平坦なバリア膜 78 の膜厚を 70nmとした。また、比較例 2による半導体装置では、ノリア膜 58の膜厚を 2 Onm、平坦なバリア膜 78の膜厚を 50nmとした。なお、比較例 1、 2による半導体装 置の構造は、平坦なバリア膜 58が形成されていない点を除いては、本実施形態によ る半導体装置と同様にした。  [0265] As a comparative example, the PTHS test similar to the above was performed when the flat noria film 58 was not formed, that is, when only one flat noria film was formed. In the semiconductor device according to Comparative Example 1, the thickness of the barrier film 58 was set to 70 nm, and the thickness of the flat barrier film 78 was set to 70 nm. In the semiconductor device according to Comparative Example 2, the thickness of the noria film 58 was 2 Onm, and the thickness of the flat barrier film 78 was 50 nm. The structure of the semiconductor device according to Comparative Examples 1 and 2 was the same as that of the semiconductor device according to the present embodiment except that the flat barrier film 58 was not formed.
[0266] PTHS試験の結果は以下の通りとなった。  [0266] The results of the PTHS test were as follows.
[0267] まず、本実施形態の場合、 5つのチップ試料のすべてについて、 168時間、 336時 間、 504時間、 504時間、及び 672時間経過した時点のいずれにおいても、不良セ ルが発生することはな力つた。  [0267] First, in the case of the present embodiment, defective cells occur at all of 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours for all five chip samples. Hana was strong.
[0268] 一方、比較例 1の場合、 5つのチップ試料のうち、あるチップ試料では、 168時間経 過した時点で 1個の不良セルが発生し、 336時間経過した時点で不良セルは 3個と なり、 504時間経過した時点で不良セルは 10個となり、 672時間経過した時点で不 良セルは 18個となった。また、他のチップ試料では、 168時間及び 336時間経過し た時点までは不良セルは発生しなかった力 504時間経過した時点で 1個の不良セ ルが発生し、 672時間経過した時点で不良セルは 26個となった。更に他のチップ試 料では、 168時間及び 336時間経過した時点までは不良セルは発生しなかったが、 504時間経過した時点で 22個の不良セルが発生し、 672時間経過した時点で不良 セノレは 62個となった。 5つのチップ試料のうち、 168時間、 336時間、 504時間、 504 時間、及び 672時間経過した時点の!/、ずれにお 、ても不良セルが発生しなかったの は、 2つのチップ試料のみであった。 [0268] On the other hand, in the case of Comparative Example 1, one of the five chip samples had one defective cell after 168 hours, and three defective cells after 336 hours. When 504 hours passed, there were 10 defective cells, and when 672 hours passed, there were 18 bad cells. In other chip samples, a defective cell was not generated until 168 hours and 336 hours passed.One defective cell was generated when 504 hours passed, and failed after 672 hours passed. There were 26 cells. In other chip samples, no defective cells were generated until 168 hours and 336 hours had passed. At the end of 504 hours, 22 defective cells were generated, and at the end of 672 hours, the number of defective senors reached 62. Of the five chip samples, only 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours have passed! /. Met.
[0269] また、比較例 2の場合、 5つのチップ試料のうち、あるチップ試料では、 168時間経 過した時点で 19個の不良セルが発生し、 336時間経過した時点で不良セルは 34個 となり、 504時間経過した時点で不良セルは 51個となり、 672時間経過した時点で不 良セルは 72個となった。また、他のチップ試料では、 168時間経過した時点では不 良セルは発生しなかった力 336時間経過した時点で 3個の不良セルが発生し、 50 4時間経過した時点で不良セルは 5個となり、 672時間経過した時点で不良セルは 7 個となった。更に他のチップ試料では、 168時間経過した時点では不良セルは発生 しなかった力 336時間経過した時点で 3個の不良セルが発生し、 504時間経過した 時点で不良セルは 113個となり、 672時間経過した時点で不良セルは 811個となつ た。更に他のチップ試料では、 168時間経過した時点で 106個の不良セルが発生し 、 336時間経過した時点で不良セルは 1690個となり、 504時間経過した時点で不良 セルは 3253個となり、 672時間経過した時点で不良セルは 5184個となった。 5つの チップ試料のうち、 168時間、 336時間、 504時間、 504時間、及び 672時間経過し た時点のいずれにおいても不良セルが発生しなかったのは、 1つのチップ試料のみ であった。 [0269] In the case of Comparative Example 2, in one chip sample among the five chip samples, 19 defective cells were generated after 168 hours, and 34 defective cells were reached after 336 hours. When 504 hours passed, there were 51 defective cells, and when 672 hours passed, there were 72 bad cells. In other chip samples, no defective cells were generated after 168 hours. Three defective cells were generated after 336 hours, and five defective cells were generated after 504 hours. When 672 hours passed, there were 7 defective cells. Furthermore, in other chip samples, when 168 hours passed, no defective cells were generated. When 336 hours passed, 3 defective cells were generated, and after 504 hours, 113 defective cells were obtained. At the end of time, there were 811 defective cells. In another chip sample, 106 defective cells were generated when 168 hours passed, 1690 defective cells were reached after 336 hours, and 3253 defective cells were reached after 504 hours, 672 hours. At that time, there were 5184 defective cells. Of the five chip samples, only one chip sample had no defective cells at any time after 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours.
[0270] 上記 PTHS試験の結果から、本実施形態によれば、強誘電体キャパシタを有する 半導体装置の PTHS特性を大幅に向上することができ、 FeRAMに関して PTHS試 験の量産認定レベルを充分に上回ることができることが確認された。  [0270] From the result of the PTHS test, according to the present embodiment, the PTHS characteristic of the semiconductor device having the ferroelectric capacitor can be greatly improved, and the mass production certification level of the PTHS test for FeRAM is sufficiently exceeded. It was confirmed that it was possible.
[0271] また、単に平坦なノリア膜を 1層形成しただけでは、充分な耐湿性を確保することが できず、強誘電体キャパシタを有する半導体装置の PTHS特性の向上を実現するこ とが困難であることが確認された。  [0271] Further, it is difficult to achieve sufficient moisture resistance simply by forming a single flat noria film, and it is difficult to improve the PTHS characteristics of a semiconductor device having a ferroelectric capacitor. It was confirmed that.
[0272] また、単に平坦なノリア膜を 1層形成して FeRAM部だけを覆った試料について P THS試験を行ったが、十分な耐湿性を確保することはできな力つた。  [0272] In addition, a P THS test was performed on a sample in which only a single flat noria film was formed to cover only the FeRAM part. However, it did not ensure sufficient moisture resistance.
[0273] 更に、単に平坦なノリア膜を 1層形成して FeRAM部及びロジック回路部を覆った 試料につ 、て PTHS試験を行った力 十分な耐湿性を確保することはできなカゝつた。 [0273] Furthermore, a single flat noria film was formed to cover the FeRAM part and the logic circuit part. The strength of the PTHS test on the sample It was not possible to ensure sufficient moisture resistance.
[0274] 更に、単に平坦なノリア膜を 1層形成して FeRAM部、ロジック回路部、及びパッド 部を覆った試料について PTHS試験を行った力 やや良好になるものの、十分な耐 湿性を確保することはできな力つた。  [0274] Furthermore, the PTHS test was performed on a sample that simply formed a flat noria film and covered the FeRAM part, logic circuit part, and pad part. I couldn't do it.
[0275] 更に、単に平坦なノリア膜を 1層形成して FeRAM部、ロジック回路部、パッド部、 及びスクライブ部を覆った試料にっ 、て PTHS試験を行った力 やや良好になるも のの、十分な耐湿度性を確保することはできな力つた。  [0275] In addition, a sample obtained by simply forming a single flat noria film and covering the FeRAM part, logic circuit part, pad part, and scribe part is slightly better than the PTHS test force. It was impossible to ensure sufficient humidity resistance.
[0276] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 ノリア膜 44、 46、 58にカ卩えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属配 線層 72と第 3金属配線層 88との間に形成された平坦なバリア膜 78とを有するので、 水素及び水分を確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強誘電 体膜 38に達するのを確実に防止することができる。これにより、水素及び水分による 強誘電体キャパシタ 42の電気的特性の劣化を確実に防止することができ、強誘電体 キャパシタを有する半導体装置の PTHS特性を大幅に向上することができる。  As described above, according to the present embodiment, the barrier film for preventing the diffusion of hydrogen and moisture is formed above the ferroelectric capacitor 42 in addition to the noria films 44, 46, and 58. (1) A flat barrier film 62 formed between the metal wiring layer 56 and the second metal wiring layer 72, and a flat barrier formed between the second metal wiring layer 72 and the third metal wiring layer 88. Since the film 78 is included, hydrogen and moisture can be reliably blocked, and hydrogen and moisture can be reliably prevented from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, the electrical characteristics of the ferroelectric capacitor 42 can be reliably prevented from being deteriorated by hydrogen and moisture, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
[0277] [第 2実施形態]  [0277] [Second Embodiment]
本発明の第 2実施形態による半導体装置及びその製造方法について図 40乃至図 46を用いて説明する。図 40及び図 41は本実施形態による半導体装置の構造を示 す断面図、図 42は本実施形態による半導体装置においてバリア膜が形成されてい る範囲を示す平面図、図 43乃至図 46は本実施形態による半導体装置の製造方法 を示す工程断面図である。なお、第 1実施形態による半導体装置及びその製造方法 と同様の構成要素には、同一の符号を付し説明を省略或いは簡略にする。  A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. 40 and 41 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment, FIG. 42 is a plan view showing the area where the barrier film is formed in the semiconductor device according to the present embodiment, and FIGS. It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment. The same components as those in the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.
[0278] (半導体装置）  [0278] (Semiconductor device)
本実施形態による半導体装置の基本的構成は、第 1実施形態による半導体装置と ほぼ同様である。本実施形態による半導体装置は、第 3金属配線層 88 (配線 88a、 8 8b)の上方に形成されたバリア膜 114を更に有する点で、第 1実施形態による半導体 装置と異なっている。  The basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that it further includes a barrier film 114 formed above the third metal wiring layer 88 (wirings 88a and 88b).
[0279] すなわち、図 40に示すように、層間絶縁膜 82上及び配線 88a、 88b上には、例え ば膜厚 1500nmのシリコン酸ィ匕膜 112が形成されて 、る。シリコン酸ィ匕膜 112の表面 は、その形成後に例えば CMP法により平坦ィ匕されており、配線 88b上のシリコン酸 化膜 112は例えば 350nmの膜厚で残存して 、る。 That is, as shown in FIG. 40, on the interlayer insulating film 82 and the wirings 88a and 88b, for example, In this case, a silicon oxide film 112 having a thickness of 1500 nm is formed. The surface of the silicon oxide film 112 is flattened by, for example, CMP after the formation thereof, and the silicon oxide film 112 on the wiring 88b remains with a film thickness of, for example, 350 nm.
[0280] 平坦化されたシリコン酸ィ匕膜 112上には、ノ リア膜 114が形成されている。バリア膜 114としては、例えば膜厚 20〜70nmの酸化アルミニウム膜が用いられている。平坦 ィ匕されたシリコン酸ィ匕膜 112上にバリア膜 114が形成されているため、バリア膜 114 は平坦となっている。 On the planarized silicon oxide film 112, a noor film 114 is formed. As the barrier film 114, for example, an aluminum oxide film having a thickness of 20 to 70 nm is used. Since the barrier film 114 is formed on the flattened silicon oxide film 112, the barrier film 114 is flat.
[0281] ノ リア膜 114は、バリア膜 44、 46、 58、 62、 78と同様に、水素及び水分の拡散を 防止する機能を有する膜である。さらに、ノ リア膜 114は、平坦化されたシリコン酸ィ匕 膜 112上に形成されているため平坦となっており、バリア膜 62、 78と同様に、ノ リア 膜 44、 46、 58と比較して、極めて良好な被覆性で形成されている。したがって、この ような平坦なバリア膜 114により、更に確実に水素及び水分の拡散を防止することが できる。なお、実際には、ノ リア膜 114は、バリア膜 62、 78と同様に、強誘電体キャパ シタ 42を有する複数のメモリセルが配列された FeRAMセル部 306のみならず、 Fe RAMチップ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接 する FeRAMチップ領域 302にまでわたって形成されている。この点については後述 する。  As with the barrier films 44, 46, 58, 62, and 78, the noria film 114 is a film that has a function of preventing the diffusion of hydrogen and moisture. Further, the NORA film 114 is flat because it is formed on the flattened silicon oxide film 112, and compared with the NORA films 44, 46, and 58, like the barrier films 62 and 78. Thus, it is formed with extremely good coverage. Accordingly, such a flat barrier film 114 can more reliably prevent hydrogen and moisture from diffusing. In practice, the NOR film 114 is not only the FeRAM cell part 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the Fe RAM chip region 302, like the barrier films 62 and 78. The scribe portion 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
[0282] ノ リア膜 114上には、例えば膜厚 50〜150nmのシリコン酸ィ匕膜 90が形成されて いる。シリコン酸ィ匕膜 90は、図示しない配線を形成する際のエッチングのストツバ膜と して機能する。このシリコン酸ィ匕膜 90によりバリア膜 114が保護され、配線層を形成 する際のエッチングによりバリア膜 114の膜厚が減少し或いはノ リア膜 114が除去さ れてしまうのを防止することができる。これにより、ノ リア膜 62の水素及び水分の拡散 機能が劣化するのを防止することができる。  [0282] A silicon oxide film 90 having a thickness of 50 to 150 nm, for example, is formed on the noria film 114. The silicon oxide film 90 functions as a stubbing film for etching when a wiring (not shown) is formed. The silicon oxide film 90 protects the barrier film 114, and prevents the film thickness of the barrier film 114 from being reduced or removed by etching during the formation of the wiring layer. it can. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 62 from being deteriorated.
[0283] シリコン酸ィ匕膜 90上には、例えば膜厚 350nmのシリコン窒化膜 92が形成されてい る。  [0283] On the silicon oxide film 90, for example, a silicon nitride film 92 having a thickness of 350 nm is formed.
[0284] シリコン窒化膜 92上には、例えば膜厚 3〜6 μ mのポリイミド榭脂膜 94が形成され ている。  [0284] On the silicon nitride film 92, for example, a polyimide resin film 94 having a film thickness of 3 to 6 μm is formed.
[0285] ポリイミド榭脂膜 94、シリコン窒化膜 92、シリコン酸ィ匕膜 90、 バリア膜 114、及びシリ コン酸ィ匕膜 112には、配線 (ボンディングパッド) 88bに達する開口部 96が形成され ている。すなわち、シリコン窒化膜 92、シリコン酸ィ匕膜 90、ノ リア膜 114、及びシリコ ン酸ィ匕膜 112には、配線 (ボンディングパッド） 88bに達する開口部 96aが形成されて いる。ポリイミド榭脂膜 94には、シリコン窒化膜 92、シリコン酸ィ匕膜 90、バリア膜 114 、及びシリコン酸化膜 112に形成された開口部 96aを含む領域に、開口部 96bが形 成されている。 [0285] Polyimide resin film 94, silicon nitride film 92, silicon oxide film 90, barrier film 114, and silicon An opening 96 reaching the wiring (bonding pad) 88b is formed in the conoxide film 112. That is, in the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112. .
[0286] ノリア膜 114は、ノリア膜 62、 78と同様に、図 41及び図 42に示すように、 FeRAM チップ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接する F eRAMチップ領域 302にまでわたって形成されている。すなわち、ノリア膜 114は、 スクライブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路 部 310、ロジック回路の周辺回路部 312、パッド部 314、これらの境界部であるスクラ イブ部，パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部，回路 部間境界部 320にわたつて形成されている。  As in the case of the noria films 62 and 78, the noria film 114 is formed across the FeRAM chip area 302 and the scribe section 304 as shown in FIGS. 41 and 42, and adjacent FeRAM chip areas. It is formed over 302. That is, the noria film 114 includes a scribe portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a pad portion 314, and a sliver portion that is a boundary portion thereof. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
[0287] このように、本実施形態による半導体装置は、水素及び水分の拡散を防止するバリ ァ膜として、バリア膜 44、 46、 58にカ卩えて、強誘電体キャパシタ 42の上方に形成さ れた第 1金属配線層 56 (配線 56a、 56b、 56c)と第 2金属配線層 72 (配線 72a、 72b )との間に形成された平坦なバリア膜 62と、第 2金属配線層 72 (配線 72a、 72b)と第 3金属配線層 88 (配線 88a、 88b)との間に形成された平坦なバリア膜 78と、第 3金 属配線層 88 (配線 88a、 88b)の上方に形成された平坦なバリア膜 114とを有するこ とに主たる特徴がある。  As described above, the semiconductor device according to the present embodiment is formed above the ferroelectric capacitor 42 over the barrier films 44, 46, 58 as a barrier film for preventing diffusion of hydrogen and moisture. A flat barrier film 62 formed between the first metal wiring layer 56 (wirings 56a, 56b, 56c) and the second metal wiring layer 72 (wirings 72a, 72b), and a second metal wiring layer 72 ( A flat barrier film 78 formed between the wirings 72a and 72b) and the third metal wiring layer 88 (wirings 88a and 88b), and the third metal wiring layer 88 (wirings 88a and 88b). And a flat barrier film 114.
[0288] 本実施形態による半導体装置では、第 1実施形態による半導体装置における平坦 なノリア膜 62、 78に加えて、第 3金属配線層 88の上方に平坦なノリア膜 114が形成 されているので、水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キ ャパシタ 42の強誘電体膜 38に達するのを更に確実に防止することができる。これに より、水素及び水分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に 防止することができ、強誘電体キャパシタを有する半導体装置の PTHS特性を更に 大幅に向上することができる。  [0288] In the semiconductor device according to the present embodiment, in addition to the flat noria films 62 and 78 in the semiconductor device according to the first embodiment, the flat noria film 114 is formed above the third metal wiring layer 88. In addition, hydrogen and moisture can be more reliably blocked, and hydrogen and moisture can be more reliably prevented from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved.
[0289] さらに、本実施形態による半導体装置では、平坦なバリア膜 62、 78、 114が、スクラ イブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路部 310 、ロジック回路の周辺回路部 312、ノッド部 314、これらの境界部であるスクライブ部- パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界 部 320にわたつて形成されているので、水素及び水分による強誘電体キャパシタ 42 の電気的特性の劣化を更に確実に防止することができる。 Furthermore, in the semiconductor device according to the present embodiment, the flat barrier films 62, 78, and 114 are Eve portion 304, FeRAM cell portion 306, FeRAM peripheral circuit portion 308, logic circuit portion 310, logic circuit peripheral circuit portion 312, nod portion 314, and a scribe portion-pad portion boundary portion 316 that is a boundary portion thereof, pad Since it is formed over the boundary part 318 between the circuit part and the circuit part and the boundary part 320 between the circuit part and the circuit part, the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be prevented more reliably. Can do.
[0290] (半導体装置の製造方法） [0290] (Method for Manufacturing Semiconductor Device)
次に、本実施形態による半導体装置の製造方法について図 43乃至図 46を用いて 説明する。  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0291] まず、図 24乃至図 37に示す第 1実施形態による半導体装置の製造方法と同様に して、第 3金属配線層（配線 88a、配線 88b)までを形成する。  First, the third metal wiring layer (wiring 88a, wiring 88b) is formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.
[0292] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 1500nmのシリ コン酸化膜 112を形成する（図 43 (a)を参照)。 Next, a silicon oxide film 112 of, eg, a 1500 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 43 (a)).
[0293] 次いで、例えば CMP法により、シリコン酸ィ匕膜 112の表面を平坦ィ匕する（図 43 (b) を参照)。 Next, the surface of the silicon oxide film 112 is flattened by, eg, CMP (see FIG. 43B).
[0294] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0294] Next !, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 112中の水分を除去する とともに、シリコン酸ィ匕膜 112の膜質を変化させ、シリコン酸ィ匕膜 112中に水分が入り に《するためのものである。この熱処理により、シリコン酸ィ匕膜 112の表面は窒化さ れ、シリコン酸ィ匕膜 112の表面には、 SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 112 and changing the film quality of the silicon oxide film 112 so that moisture enters the silicon oxide film 112. By this heat treatment, the surface of the silicon oxide film 112 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 112.
[0295] 次いで、平坦ィ匕されたシリコン酸ィ匕膜 112上に、例えばスパッタ法又は CVD法によ り、ノリア膜 114を形成する。ノリア膜 114としては、例えば膜厚 20〜70nmの酸ィ匕 アルミニウム膜を形成する。平坦化されたシリコン酸化膜 112上にバリア膜 114を形 成するため、ノリア膜 114は平坦となる。  [0295] Next, a noria film 114 is formed on the flattened silicon oxide film 112 by, for example, sputtering or CVD. As the noria film 114, for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the noria film 114 becomes flat.
[0296] ノリア膜 114は、図 44に示すように、 FeRAMチップ領域 302及びスクライブ部 30 4にわたつて形成するとともに、隣接する FeRAMチップ領域 302にまでわたって形 成する。すなわち、ノリア膜 114は、スクライブ部 304、 FeRAMセル部 306、 FeRA Mの周辺回路部 308、ロジック回路部 310、ロジック回路の周辺回路部 312、パッド 部 314、これらの境界部であるスクライブ部'パッド部間境界部 316、パッド部'回路 部間境界部 318、及び回路部，回路部間境界部 320にわたつて形成する。 As shown in FIG. 44, the noria film 114 is formed so as to extend over the FeRAM chip region 302 and the scribe portion 304, and also into the adjacent FeRAM chip region 302. That is, the noria film 114 includes a scribe part 304, a FeRAM cell part 306, a peripheral circuit part 308 of FeRAM, a logic circuit part 310, a peripheral circuit part 312 of a logic circuit, a pad part 314, and a scribe part that is a boundary part between them. Pad part boundary 316, pad part 'circuit It is formed over the inter-part boundary 318 and the circuit part / inter-circuit part boundary 320.
[0297] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 90を形成する。 [0297] Next, a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
[0298] 次!、で、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0298] In a plasma atmosphere generated using N 2 O gas or N gas, for example, 35!
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 90中の水分を除去する とともに、シリコン酸ィ匕膜 90の膜質を変化させ、シリコン酸ィ匕膜 90中に水分が入りにく くするためのものである。この熱処理により、シリコン酸ィ匕膜 90の表面は窒化され、シ リコン酸ィ匕膜 90の表面には SiON膜 (図示せず)が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing water in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that the water does not easily enter the silicon oxide film 90. By this heat treatment, the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
[0299] 次いで、例えば CVD法により、例えば膜厚 350nmのシリコン窒化膜 92を形成する  [0299] Next, a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD.
(図 45 (a)を参照)。シリコン窒化膜 92は、水分を遮断し、水分により金属配線層 88、 72、 56等が腐食するのを防止するためのものである。  (See Figure 45 (a)). The silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
[0300] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 106を形成する。  [0300] Next, a photoresist film 106 is formed on the entire surface by, eg, spin coating.
[0301] 次いで、フォトリソグラフィ一により、フォトレジスト膜 106に、配線 (ボンディングパッ ド） 88bに達する開口部をシリコン窒化膜 92、シリコン酸ィ匕膜 90、 ノリア膜 114、及び シリコン酸化膜 112に形成する領域を露出する開口部 108を形成する。  [0301] Next, by photolithography, the opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112 through the photoresist film 106. An opening 108 that exposes a region to be formed is formed.
[0302] 次いで、フォトレジスト膜 106をマスクとして、シリコン窒ィ匕膜 92、シリコン酸化膜 90 、 ノリア膜 114、及びシリコン酸ィ匕膜 112をエッチングする。こうして、シリコン窒化膜 9 2、シリコン酸ィ匕膜 90、 ノリア膜 114、及びシリコン酸ィ匕膜 112に、配線 (ボンディング パッド） 88bに達する開口部 96aが形成される（図 45 (b)を参照）。この後、フォトレジ スト膜 106を剥離する。  [0302] Next, using the photoresist film 106 as a mask, the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112 are etched. Thus, an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the noria film 114, and the silicon oxide film 112 (see FIG. 45 (b)). reference). Thereafter, the photoresist film 106 is peeled off.
[0303] 次 、で、例えばスピンコート法により、例えば膜厚 3〜6 μ mのポリイミド榭脂膜 94を 形成する（図 46 (a)を参照)。  Next, a polyimide resin film 94 having a film thickness of 3 to 6 μm, for example, is formed by, eg, spin coating (see FIG. 46 (a)).
[0304] 次いで、フォトリソグラフィ一により、ポリイミド榭脂膜 94に、開口部 96aを介して配線 [0304] Next, by photolithography, wiring is made to the polyimide resin film 94 through the opening 96a.
(ボンディングパッド) 88bに達する開口部 96bを形成する（図 46 (b)を参照)。  (Bonding pad) Opening 96b reaching 88b is formed (see FIG. 46 (b)).
[0305] こうして、本実施形態による半導体装置が製造される。 Thus, the semiconductor device according to the present embodiment is manufactured.
[0306] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 ノリア膜 44、 46、 58にカ卩えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属配 線層 72と第 3金属配線層 88との間に形成された平坦なバリア膜 78と、第 3金属配線 層 88の上方に形成された平坦なノリア膜 114とを有するので、水素及び水分を更に 確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強誘電体膜 38に達する のを更に確実に防止することができる。これにより、水素及び水分による強誘電体キ ャパシタ 42の電気的特性の劣化を更に確実に防止することができ、強誘電体キャパ シタを有する半導体装置の PTHS特性を更に大幅に向上することができる。 As described above, according to the present embodiment, the barrier film that prevents diffusion of hydrogen and moisture is used as the barrier film 44, 46, 58, and is formed above the ferroelectric capacitor 42. (1) A flat barrier film 62 formed between the metal wiring layer 56 and the second metal wiring layer 72 and the second metal wiring Since it has a flat barrier film 78 formed between the line layer 72 and the third metal wiring layer 88 and a flat noria film 114 formed above the third metal wiring layer 88, hydrogen and moisture can be removed. Further, the barrier can be surely prevented, and hydrogen and moisture can be prevented more reliably from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be further reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved. .
[0307] [第 3実施形態]  [Third Embodiment]
本発明の第 3実施形態による半導体装置及びその製造方法について図 47乃至図 52を用いて説明する。図 47及び図 48は本実施形態による半導体装置の構造を示 す断面図、図 49は本実施形態による半導体装置においてバリア膜が形成されてい る範囲を示す平面図、図 50乃至図 52は本実施形態による半導体装置の製造方法 を示す工程断面図である。なお、第 1実施形態による半導体装置及びその製造方法 と同様の構成要素については同一の符号を付し説明を省略し或いは簡略にする。  A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. 47 and 48 are cross-sectional views showing the structure of the semiconductor device according to the present embodiment, FIG. 49 is a plan view showing the area where the barrier film is formed in the semiconductor device according to the present embodiment, and FIGS. It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0308] (半導体装置）  [0308] (Semiconductor device)
本実施形態による半導体装置の基本的構成は、第 1実施形態による半導体装置と ほぼ同様である。本実施形態による半導体装置は、強誘電体キャパシタ 42と、第 1金 属配線層 56 (配線 56a、 56b、 56c)との間に、平坦なバリア膜 116を更に有する点 で、第 1実施形態による半導体装置と異なっている。  The basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. The semiconductor device according to the present embodiment is different from the first embodiment in that it further includes a flat barrier film 116 between the ferroelectric capacitor 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). This is different from the semiconductor device.
[0309] すなわち、図 47に示すように、導体プラグ 50a、 50bが埋め込まれたシリコン酸ィ匕膜 48上に、ノリア膜 116が形成されている。ノリア膜 116としては、例えば膜厚 20〜70 nmの酸ィ匕アルミニウム膜が用いられている。ここで、シリコン酸ィ匕膜 48は平坦ィ匕され ており、平坦ィ匕されたシリコン酸ィ匕膜 48上にノリア膜 116が形成されているため、バ リア膜 116は平坦となって ヽる。  That is, as shown in FIG. 47, the noria film 116 is formed on the silicon oxide film 48 in which the conductor plugs 50a and 50b are embedded. As the noria film 116, for example, an aluminum oxide film having a thickness of 20 to 70 nm is used. Here, since the silicon oxide film 48 is flattened, and the noria film 116 is formed on the flattened silicon oxide film 48, the barrier film 116 becomes flat. The
[0310] ノリア膜 116は、バリア膜 44、 46、 58、 62、 78と同様に、水素及び水分の拡散を 防止する機能を有する膜である。さらに、ノリア膜 116は、平坦化されたシリコン酸ィ匕 膜 48上に形成されているため平坦となっており、バリア膜 62、 78と同様に、バリア膜 44、 46、 58と比較して、極めて良好な被覆性で形成されている。したがって、このよ うな平坦なバリア膜 116により、更に確実に水素及び水分の拡散を防止することがで きる。なお、実際には、ノ リア膜 116は、バリア膜 62、 78と同様に、強誘電体キャパシ タ 42を有する複数のメモリセルが配列された FeRAMセル部 306のみならず、 FeRA Mチップ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領域 302にまでわたって形成されている。この点については後述する [0310] Like the barrier films 44, 46, 58, 62, and 78, the noria film 116 is a film having a function of preventing the diffusion of hydrogen and moisture. Further, the noria film 116 is flat because it is formed on the flattened silicon oxide film 48, and is similar to the barrier films 62, 78 in comparison with the barrier films 44, 46, 58. It is formed with very good coverage. Therefore, such a flat barrier film 116 can more reliably prevent the diffusion of hydrogen and moisture. wear. In practice, the NOR film 116 is not only the FeRAM cell section 306 in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the FeRA M chip region 302, as in the barrier films 62 and 78. The scribe portion 304 is formed over the adjacent FeRAM chip region 302. This point will be described later.
[0311] ノ リア膜 116上には、例えば膜厚 lOOnmのシリコン酸ィ匕膜 118が形成されている。 [0311] On the oxide film 116, for example, a silicon oxide film 118 having a thickness of lOOnm is formed.
シリコン酸ィ匕膜 118は、後述する配線 56a、 56b, 56cを形成する際のエッチングのス トツパ膜として機能する。このシリコン酸ィ匕膜 118によりバリア膜 116が保護され、配線 56a、 56b、 56cを形成する際のエッチングによりバリア膜 116の膜厚が減少し或い はノ リア膜 116が除去されてしまうのを防止することができる。これにより、ノ リア膜 11 6の水素及び水分の拡散機能が劣化するのを防止することができる。  The silicon oxide film 118 functions as an etching stopper film when forming wirings 56a, 56b, and 56c described later. The barrier film 116 is protected by the silicon oxide film 118, and the film thickness of the barrier film 116 is reduced or the NOR film 116 is removed by etching when forming the wirings 56a, 56b, 56c. Can be prevented. As a result, it is possible to prevent the hydrogen and moisture diffusing function of the NOR film 116 from deteriorating.
[0312] シリコン酸ィ匕膜 34、バリア膜 46、シリコン酸ィ匕膜 48、ノ リア膜 116、及びシリコン酸 化膜 118により層間絶縁膜 49が構成されて 、る。  [0312] The silicon oxide film 34, the barrier film 46, the silicon oxide film 48, the NOR film 116, and the silicon oxide film 118 constitute an interlayer insulating film 49.
[0313] シリコン酸ィ匕膜 118、ノ リア膜 116、シリコン酸ィ匕膜 48、バリア膜 46、及びバリア膜 4 4には、上部電極 40に達するコンタクトホール 52aが形成されている。また、シリコン 酸化膜 118、ノ リア膜 116、シリコン酸ィ匕膜 48、バリア膜 46、及びバリア膜 44には、 下部電極 36に達するコンタクトホール 52bが形成されて!、る。  [0313] A contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 118, the NORA film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44. Further, a contact hole 52b reaching the lower electrode 36 is formed in the silicon oxide film 118, the NORA film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44.
[0314] さらに、シリコン酸ィ匕膜 118及びバリア膜 116には、導体プラグ 54aに達するコンタ タトホール 120aが形成されている。また、シリコン酸ィ匕膜 118及びバリア膜 116には、 導体プラグ 54bに達するコンタクトホール 120bが形成されている。  [0314] Further, a contact hole 120a reaching the conductor plug 54a is formed in the silicon oxide film 118 and the barrier film 116. In addition, a contact hole 120b reaching the conductor plug 54b is formed in the silicon oxide film 118 and the barrier film 116.
[0315] シリコン酸化膜 118上、コンタクトホール 52a内、及びコンタクトホール 120a内には 、導体プラグ 54aと上部電極 40とに電気的に接続された配線 56aが形成されて 、る 。また、シリコン酸ィ匕膜 118上及びコンタクトホール 52b内には、下部電極 36に電気 的に接続された配線 56bが形成されている。また、シリコン酸ィ匕膜 118上及びコンタ タトホール 120b内には、導体プラグ 54bに電気的に接続された配線 56cが形成され ている。  [0315] A wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the silicon oxide film 118, in the contact hole 52a, and in the contact hole 120a. A wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 118 and in the contact hole 52b. Further, a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 118 and in the contact hole 120b.
[0316] ノ リア膜 116は、ノ リア膜 62、 78と同様に、図 48及び図 49に示すように、 FeRAM チップ領域 302及びスクライブ部 304にわたつて形成されているとともに、隣接する F eRAMチップ領域 302にまでわたって形成されている。すなわち、ノリア膜 116は、 スクライブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路 部 310、ロジック回路の周辺回路部 312、パッド部 314、これらの境界部であるスクラ イブ部，パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部，回路 部間境界部 320にわたつて形成されている。 As in the case of the nore films 62 and 78, the nore film 116 is formed over the FeRAM chip region 302 and the scribe part 304 as shown in FIGS. The eRAM chip region 302 is formed. That is, the noria film 116 includes a scribe portion 304, an FeRAM cell portion 306, an FeRAM peripheral circuit portion 308, a logic circuit portion 310, a logic circuit peripheral circuit portion 312, a pad portion 314, and a sliver portion that is a boundary portion thereof. It is formed across the pad part boundary part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320.
[0317] このように、本実施形態による半導体装置は、水素及び水分の拡散を防止するバリ ァ膜として、バリア膜 44、 46、 58にカ卩えて、強誘電体キャパシタ 42と強誘電体キャパ シタ 42の上方に形成された第 1金属配線層 56 (配線 56a、 56b、 56c)との間に形成 された平坦なノリア膜 116と、第 1金属配線層 56 (配線 56a、 56b、 56c)と第 2金属 配線層 72 (配線 72a、 72b)との間に形成された平坦なバリア膜 62と、第 2金属配線 層 72 (配線 72a、 72b)と第 3金属配線層 88 (配線 88a、 88b)の間に形成された平坦 なノリア膜 78とを有することに主たる特徴がある。  As described above, the semiconductor device according to the present embodiment covers the ferroelectric capacitors 42 and the ferroelectric capacitors as barrier films 44, 46, 58 as barrier films for preventing the diffusion of hydrogen and moisture. A flat noria film 116 formed between the first metal wiring layer 56 (wirings 56a, 56b, 56c) formed above the shita 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). And the second metal wiring layer 72 (wiring 72a, 72b), the second barrier layer 62 (wiring 72a, 72b) and the third metal wiring layer 88 (wiring 88a, The main feature is that it has a flat noria film 78 formed between the layers 88b).
[0318] 本実施形態による半導体装置では、第 1実施形態による半導体装置における平坦 なバリア膜 62、 78に加えて、強誘電体キャパシタ 42と強誘電体キャパシタ 42の上方 に形成された第 1金属配線層 56との間に平坦なノリア膜 116が形成されているので 、水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強 誘電体膜 38に達するのを更に確実に防止することができる。これにより、水素及び水 分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に防止することがで き、強誘電体キャパシタを有する半導体装置の PTHS特性を更に大幅に向上するこ とがでさる。  [0318] In the semiconductor device according to the present embodiment, the ferroelectric capacitor 42 and the first metal formed above the ferroelectric capacitor 42 in addition to the flat barrier films 62 and 78 in the semiconductor device according to the first embodiment. Since the flat noria film 116 is formed between the wiring layer 56 and the wiring layer 56, the hydrogen and moisture are further reliably blocked, and the hydrogen and moisture reach the ferroelectric film 38 of the ferroelectric capacitor 42 more reliably. Can be prevented. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. I'll do it.
[0319] さらに、本実施形態による半導体装置では、平坦なバリア膜 62、 78、 116が、スクラ イブ部 304、 FeRAMセル部 306、 FeRAMの周辺回路部 308、ロジック回路部 310 、ロジック回路の周辺回路部 312、ノッド部 314、これらの境界部であるスクライブ部- パッド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界 部 320にわたつて形成されているので、水素及び水分による強誘電体キャパシタ 42 の電気的特性の劣化を更に確実に防止することができる。  Furthermore, in the semiconductor device according to the present embodiment, the flat barrier films 62, 78, 116 include the sliver part 304, the FeRAM cell part 306, the FeRAM peripheral circuit part 308, the logic circuit part 310, and the periphery of the logic circuit. The circuit part 312, the nod part 314, and the boundary part between the scribe part and the pad part 316, the pad part / circuit part boundary part 318, and the circuit part / circuit part boundary part 320 are formed. Therefore, the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be prevented more reliably.
[0320] (半導体装置の製造方法）  [0320] (Manufacturing method of semiconductor device)
次に、本実施形態による半導体装置の製造方法について図 50乃至図 52を用いて 説明する。 Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. explain.
まず、図 24乃至図 27、図 28 (a)、及び図 28 (b)に示す第 1実施形態による半導体 装置の製造方法と同様にして、導体プラグ 54a、 54bまでを形成する（図 50 (a)を参 照)。  First, conductor plugs 54a and 54b are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 24 to 27, FIG. 28 (a), and FIG. see a)).
[0321] 次 、で、例えばアルゴンガスを用いたプラズマ洗浄を行う。これにより、導体プラグ 5 4a、 54b表面に存在する自然酸ィ匕膜等が除去される。  Next, plasma cleaning is performed using, for example, argon gas. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 54a and 54b are removed.
[0322] 次いで、導体プラグ 54a、 54bが埋め込まれたシリコン酸ィ匕膜 48上に、例えばスパ ッタ法又は CVD法により、ノリア膜 116を形成する。ノリア膜 114としては、例えば膜 厚 20〜70nmの酸ィ匕アルミニウム膜を形成する。シリコン酸ィ匕膜 48は平坦ィ匕されて おり、平坦化されたシリコン酸ィ匕膜 48上にバリア膜 116を形成するため、バリア膜 11 6は平坦となる。  [0322] Next, the noria film 116 is formed on the silicon oxide film 48 in which the conductor plugs 54a and 54b are embedded by, for example, a sputtering method or a CVD method. As the noria film 114, for example, an aluminum oxide film having a film thickness of 20 to 70 nm is formed. Since the silicon oxide film 48 is flattened and the barrier film 116 is formed on the flattened silicon oxide film 48, the barrier film 116 becomes flat.
[0323] ノリア膜 116は、図 51に示すように、 FeRAMチップ領域 302及びスクライブ部 30 4にわたつて形成するとともに、隣接する FeRAMチップ領域 302にまでわたって形 成する。すなわち、ノ リア膜 116は、スクライブ部 304、 FeRAMセル部 306、 FeRA Mの周辺回路部 308、ロジック回路部 310、ロジック回路の周辺回路部 312、パッド 部 314、これらの境界部であるスクライブ部'パッド部間境界部 316、パッド部'回路 部間境界部 318、及び回路部，回路部間境界部 320にわたつて形成する。  As shown in FIG. 51, the noria film 116 is formed so as to extend over the FeRAM chip region 302 and the scribe part 304, and also into the adjacent FeRAM chip region 302. In other words, the NORA film 116 is composed of the scribe part 304, the FeRAM cell part 306, the peripheral circuit part 308 of the FeRAM, the logic circuit part 310, the peripheral circuit part 312 of the logic circuit, the pad part 314, and the scribe part that is the boundary between them. It is formed over the 'pad portion boundary portion 316, the pad portion' circuit portion boundary portion 318, and the circuit portion / circuit portion boundary portion 320.
[0324] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 118を形成する（図 50 (b)を参照)。  Next, a silicon oxide film 118 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 50B).
[0325] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸ィ匕膜 118及びバ リ 膜 116【こ、導体プラグ 54a、 54b【こ達する =3ンタクトホーノレ 120a、 120bを形成す る（図 50 (c)を参照)。  [0325] Next, by photolithography and dry etching, the silicon oxide film 118 and the barrier film 116 are formed, and the conductor plugs 54a and 54b reach 3 = contact holes 120a and 120b (FIG. 50 (c) See).
[0326] 次いで、全面に、例えば CVD法により、例えば膜厚 lOOnmの SiON膜 122を形成 する（図 52 (a)を参照)。  Next, a SiON film 122 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD (see FIG. 52A).
[0327] 次いで、フォトリソグラフィー及びドライエッチングにより、 SiON膜 122、シリコン酸 化膜 118、 ノリア膜 116、シリコン酸ィ匕膜 48、 バリア膜 46、及びバリア膜 44に、強誘 電体キャパシタ 42の上部電極 40に達するコンタクトホール 52aと、強誘電体キャパシ タ 42の下部電極 36に達するコンタクトホール 52aとを形成する（図 52 (b)を参照）。 [0328] 次いで、酸素雰囲気にて、例えば 500°C、 60分間の熱処理を行う。この熱処理は、 強誘電体キャパシタ 42の強誘電体膜 38に酸素を供給し、強誘電体キャパシタ 42の 電気的特性を回復するためのものである。 Next, the strong dielectric capacitor 42 is formed on the SiON film 122, the silicon oxide film 118, the noria film 116, the silicon oxide film 48, the barrier film 46, and the barrier film 44 by photolithography and dry etching. A contact hole 52a reaching the upper electrode 40 and a contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 are formed (see FIG. 52 (b)). [0328] Next, heat treatment is performed in an oxygen atmosphere at, for example, 500 ° C for 60 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
[0329] 次いで、エッチングにより SiON膜 122を除去する。  Next, the SiON film 122 is removed by etching.
[0330] 次いで、全面に、例えば膜厚 150nmの TiN膜と、例えば膜厚 550nmの AlCu合金 膜と、例えば膜厚 5nmの Ti膜と、例えば膜厚 150nmの TiN膜とを順次積層する。こ うして、 TiN膜と AlCu合金膜と Ti膜と TiN膜とを順次積層してなる導体膜が形成され る。  [0330] Next, a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm, for example, are sequentially laminated on the entire surface. In this way, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
[0331] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターユングする 。これにより、第 1金属配線層 56、すなわち強誘電体キャパシタ 42の上部電極 40と 導体プラグ 54aとに電気的に接続された配線 56a、強誘電体キャパシタ 42の下部電 極 36に電気的に接続された配線 56b、及び導体プラグ 54bに電気的に接続された 配線 56cが形成される（図 52 (c)を参照)。配線 56a、 56b、 56cを形成する際のドラ ィエッチングにおいては、シリコン酸ィ匕膜 118がエッチングのストッパ膜として機能す る。このシリコン酸ィ匕膜 118によりバリア膜 118が保護され、配線 56a、 56b、 56cを形 成する際のエッチングによりバリア膜 118の膜厚が減少し或いはノリア膜 118が除去 されてしまうのを防止することができる。これにより、バリア膜 118の水素及び水分の 拡散機能が劣化するのを防止することができる。  [0331] Next, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 56, that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected. The wiring 56b thus formed and the wiring 56c electrically connected to the conductor plug 54b are formed (see FIG. 52 (c)). In dry etching for forming the wirings 56a, 56b, and 56c, the silicon oxide film 118 functions as an etching stopper film. The silicon oxide film 118 protects the barrier film 118, and prevents the thickness of the barrier film 118 from being reduced or the removal of the noria film 118 by etching when forming the wirings 56a, 56b, 56c. can do. Thereby, it is possible to prevent the hydrogen and moisture diffusion functions of the barrier film 118 from being deteriorated.
[0332] この後の工程は、図 29 (b)乃至図 39に示す第 1実施形態による半導体装置の製 造方法と同様であるので説明を省略する。  [0332] Subsequent steps are the same as those in the method for manufacturing the semiconductor device according to the first embodiment shown in FIGS.
[0333] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 ノリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42と強誘電体キャパシタ 42の上 方に形成された第 1金属配線層 56との間に形成された平坦なバリア膜 116と、第 1金 属配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属 配線層 72と第 3金属配線層 88の間に形成された平坦なバリア膜 78とを有するので、 水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強 誘電体膜 38に達するのを更に確実に防止することができる。これにより、水素及び水 分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に防止することがで き、強誘電体キャパシタを有する半導体装置の PTHS特性を更に大幅に向上するこ とがでさる。 As described above, according to the present embodiment, as a barrier film for preventing diffusion of hydrogen and moisture, in addition to the noria films 44, 46, 58, the ferroelectric capacitors 42 and the ferroelectric capacitors 42 are provided. A flat barrier film 116 formed between the first metal wiring layer 56 and the first metal wiring layer 56 formed on the opposite side, and a flat barrier film formed between the first metal wiring layer 56 and the second metal wiring layer 72. 62, and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88, so that hydrogen and moisture are more securely blocked, and the hydrogen and moisture are ferroelectric capacitors. Reaching the ferroelectric film 38 of 42 can be prevented more reliably. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water can be prevented more reliably. As a result, the PTHS characteristics of semiconductor devices with ferroelectric capacitors can be greatly improved.
[0334] なお、本実施形態では、導体プラグ 54a、 54bを形成した後に、ノリア膜 116を形 成する場合について説明したが、導体プラグ 54a、 54bを形成する前に、ノリア膜 11 6を形成してもよい。  In the present embodiment, the case where the noria film 116 is formed after the conductor plugs 54a and 54b are formed has been described. However, the noria film 116 is formed before the conductor plugs 54a and 54b are formed. May be.
[0335] 具体的には、まず、図 24乃至図 27 (c)に示す第 1実施形態による半導体装置の製 造方法と同様にして、 CMP法により表面が平坦化されたシリコン酸ィ匕膜 48までを形 成する。  [0335] Specifically, first, a silicon oxide film whose surface is planarized by a CMP method in the same manner as in the method for manufacturing the semiconductor device according to the first embodiment shown in FIGS. 24 to 27 (c). Form up to 48.
[0336] 次いで、 CMP法により表面が平坦ィ匕されたシリコン酸ィ匕膜 48上にノリア膜 116を 形成する。  Next, a noria film 116 is formed on the silicon oxide film 48 whose surface is flattened by the CMP method.
[0337] 次いで、ノリア膜 116上に、例えば膜厚 lOOnmのシリコン酸ィ匕膜を形成する。  [0337] Next, a silicon oxide film having a thickness of lOOnm, for example, is formed on the noria film 116.
[0338] 次いで、ノ リア膜 116上のシリコン酸ィ匕膜、ノ リア膜 116、シリコン酸ィ匕膜 48、 ノ リア 膜 46、シリコン酸ィ匕膜 34、及び層間絶縁膜 27に、ソース/ドレイン拡散層 22に達す るコンタクトホール 50a、 50bを形成する。 [0338] Next, the silicon oxide film on the noria film 116, the noria film 116, the silicon oxide film 48, the noria film 46, the silicon oxide film 34, and the interlayer insulating film 27 are supplied with the source / Contact holes 50a and 50b reaching the drain diffusion layer 22 are formed.
[0339] 次いで、コンタクトホール 50a、 50bに埋め込まれた導体プラグ 54a、 54bを形成す る。 [0339] Next, conductor plugs 54a and 54b embedded in the contact holes 50a and 50b are formed.
[0340] このように、導体プラグ 50a、 50bを形成する前に、ノリア膜 116を形成してもよ ヽ。  [0340] As described above, the noria film 116 may be formed before the conductor plugs 50a and 50b are formed.
[0341] [変形実施形態]  [0341] [Modified Embodiment]
本発明は上記実施形態に限らず種々の変形が可能である。  The present invention is not limited to the above embodiment, and various modifications can be made.
[0342] 例えば、上記実施形態では、強誘電体膜 38として PZT膜を用いる場合を例に説明 したが、強誘電体膜 38は PZT膜に限定されるものではなぐ他のあらゆる強誘電体 膜を適宜用いることができる。例えば、強誘電体膜 38として、 Pb La Zr Ti O  For example, in the above embodiment, the case where a PZT film is used as the ferroelectric film 38 has been described as an example. However, the ferroelectric film 38 is not limited to the PZT film, but any other ferroelectric film. Can be used as appropriate. For example, as the ferroelectric film 38, Pb La Zr Ti O
1 -X X 1 -Y Y 3 膜 (PLZT膜）、 SrBi (Ta Nb ) O膜、 Bi Ti O 膜等を用いてもよい。  1 -X X 1 -Y Y 3 film (PLZT film), SrBi (Ta Nb) O film, Bi Ti O film, or the like may be used.
2 X 1 -X 2 9 4 2 12  2 X 1 -X 2 9 4 2 12
[0343] また、上記実施形態では、酸ィ匕アルミニウム膜 36aと Pt膜 36bとの積層膜により下 部電極 36を構成したが、下部電極 36を構成する導体膜等の材料はカゝかる材料に限 定されるものではない。例えば、 Ir膜、 IrO膜、 Ru膜、 RuO膜、 SrRuO (ストロンチ  [0343] In the above embodiment, the lower electrode 36 is configured by the laminated film of the acid aluminum film 36a and the Pt film 36b. However, the material of the conductor film or the like that configures the lower electrode 36 is a material to be covered. It is not limited to. For example, Ir film, IrO film, Ru film, RuO film, SrRuO (Stront
2 2  twenty two
ゥムルテニウムオキサイド)膜 (SRO膜)、 Pd膜により下部電極 38を構成してもよい。  The lower electrode 38 may be formed of a (muruthenium oxide) film (SRO film) or a Pd film.
[0344] また、上記実施形態では、 IrO膜 40aと IrO膜 40bとの積層膜により上部電極 40 を構成したが、上部電極 40を構成する導体膜の材料はカゝかる材料に限定されるもの ではない。例えば、 Ir膜、 Ru膜、 RuO膜、 SRO膜、 Pd膜により上部電極 40を構成 [0344] In the above embodiment, the upper electrode 40 is formed of a laminated film of the IrO film 40a and the IrO film 40b. However, the material of the conductor film that constitutes the upper electrode 40 is not limited to the material to be covered. For example, the upper electrode 40 is composed of an Ir film, Ru film, RuO film, SRO film, and Pd film.
2  2
してちよい。  You can do it.
[0345] また、上記実施形態では、平坦なバリア膜について、第 1実施形態においては第 1 金属配線層 56と第 2金属配線層 72との間にバリア膜 62を形成し、第 2金属配線層7 2と第 3金属配線層 88との間にバリア膜 78を形成する場合について説明し、第 2実 施形態においてはノ リア膜 62、 78に加えて第 3金属配線層 88の上方にノ リア膜 11 4を形成する場合について説明し、第 3実施形態においてはノリア膜 62、 78に加え て強誘電体キャパシタ 42と第 1金属配線層 56との間にバリア膜 116を形成する場合 について説明した力 形成するバリア膜 62、 78、 114、 116の組合せは、上記実施 形態において説明した場合に限定されるものではない。平坦なノリア膜は、バリア膜 62、 78、 114、 116のうちの少なくとも 2層力形成されて!ヽれば、よく、ノリア膜 62、 78 、 114、 116のうちの 3層を形成してちょ!ヽし、或!/、 ίまノリア膜 62、 78、 114、 116の 4 層すベてを形成してもよい。また、半導体基板 10上に形成する金属配線層の層数等 に応じて、更に多くの平坦なノリア膜を形成してもよい。この場合において、平坦なバ リア膜の膜厚は、第 1実施形態において述べたように、例えば、 50nm以上 lOOnm 未満、より好ましくは 50nm以上 80nm以下に設定することが望ましい。 [0345] In the embodiment described above, for the flat barrier film, in the first embodiment, the barrier film 62 is formed between the first metal wiring layer 56 and the second metal wiring layer 72, and the second metal wiring is formed. It described the case of forming the barrier film 78 between the layer 7 2 and the third metal wiring layer 88, above the third metal interconnect layer 88 in addition to Bruno Riamaku 62, 78 in the second implementation embodiment In the third embodiment, a case where the barrier film 116 is formed between the ferroelectric capacitor 42 and the first metal wiring layer 56 in addition to the noria films 62 and 78 will be described. The combination of the barrier films 62, 78, 114 and 116 to be formed is not limited to the case described in the above embodiment. The flat noria film is formed by at least two layers of the barrier films 62, 78, 114, and 116! It is sufficient to form three layers of the noria films 62, 78, 114, and 116. It is also possible to form all of the four layers of 62, 78, 114, and 116. Further, more flat noria films may be formed according to the number of metal wiring layers formed on the semiconductor substrate 10 and the like. In this case, the thickness of the flat barrier film is desirably set to, for example, 50 nm or more and less than lOOnm, more preferably 50 nm or more and 80 nm or less, as described in the first embodiment.
[0346] なお、強誘電体キャパシタの電気的特性の劣化を効果的に防止する観点からは、 ボンディングパッドと、ボンディングパッド下の最上層の金属配線層との間に平坦な ノリア膜がまずは形成されており、他の金属配線層の間に他の平坦なバリア膜が形 成されて!/、ることが望まし!/、。  [0346] From the viewpoint of effectively preventing deterioration of the electrical characteristics of the ferroelectric capacitor, a flat noria film is first formed between the bonding pad and the uppermost metal wiring layer under the bonding pad. It is desirable that another flat barrier film be formed between other metal wiring layers! /.
[0347] また、上記実施形態では、ノリア膜として酸ィ匕アルミニウム膜を用いる場合を例に説 明したが、ノリア膜は酸ィ匕アルミニウム膜に限定されるものではない。水素又は水分 の拡散を防止する機能を有する膜を、ノリア膜として適宜用いることができる。ノリア 膜としては、例えば金属酸ィ匕物よりなる膜を適宜用いることができる。金属酸化物より なるバリア膜としては、例えば、タンタル酸ィ匕物やチタン酸ィ匕物等よりなる膜を用いる ことができる。また、バリア膜は、金属酸ィ匕物よりなる膜に限定されるものではない。例 えば、シリコン窒化膜 (Si N膜)やシリコン窒化酸ィ匕膜 (SiON膜)等をバリア膜として 用いることもできる。また、塗布型酸化膜、或いはポリイミド、ポリアリーレン、ポリアリー レンエーテル、ベンゾシクロブテン等よりなる榭脂膜のような吸湿性を有する有機膜を ノ リア膜として用いることができる。 [0347] In the above embodiment, the case where an acid aluminum film is used as the noria film has been described as an example. However, the noria film is not limited to the acid aluminum film. A film having a function of preventing diffusion of hydrogen or moisture can be appropriately used as the noria film. As the noria film, for example, a film made of a metal oxide can be used as appropriate. As the barrier film made of a metal oxide, for example, a film made of tantalate oxide, titanate oxide, or the like can be used. The barrier film is not limited to a film made of a metal oxide. For example, a silicon nitride film (SiN film) or silicon nitride oxide film (SiON film) is used as a barrier film. It can also be used. In addition, a coating type oxide film, or an organic film having a hygroscopic property such as a resin film made of polyimide, polyarylene, polyarylene ether, benzocyclobutene, or the like can be used as the NORA film.
[0348] また、上記実施形態では、形成するバリア膜のすべてに同一材料よりなるバリア膜 を用いる場合について説明したが、以下に述べるように、異なる材料よりなるバリア膜 を適宜用いることもできる。  [0348] In the above embodiment, the case where the barrier film made of the same material is used for all the barrier films to be formed has been described. However, as will be described below, barrier films made of different materials can be used as appropriate.
[0349] 例えば、第 1又は第 2実施形態による半導体装置において、平坦なバリア膜 62、 78 、 114のうちで最も強誘電体キャパシタ 42側に形成されているノ リア膜 62として酸ィ匕 アルミニウム膜を用いるとともに、バリア膜 62の上方に形成されているバリア膜 78又 はノ リア膜 114としてシリコン窒化膜を用いてもよい。また、例えば、酸ィ匕アルミニウム 膜上に、酸化チタン膜を形成してもよい。  [0349] For example, in the semiconductor device according to the first or second embodiment, among the flat barrier films 62, 78, and 114, the oxide film aluminum is used as the NORA film 62 that is formed closest to the ferroelectric capacitor 42 side. In addition to using a film, a silicon nitride film may be used as the barrier film 78 or the barrier film 114 formed above the barrier film 62. Further, for example, a titanium oxide film may be formed on the aluminum oxide film.
[0350] また、第 2実施形態による半導体装置において、第 3金属配線層 88の下方に形成 されて 、る平坦なノ リア膜 62、 78として酸ィ匕アルミニウム膜等の金属酸ィ匕物よりなる 膜やシリコン窒化膜等の無機膜を用いるとともに、第 3金属配線層 88の上方に形成 され、配線 (ボンディングパッド) 88bに達する開口部 96bが形成される平坦なノ リア 膜 114として、吸湿性を有する有機膜を形成してもよい。  [0350] In the semiconductor device according to the second embodiment, the flat metal films 62 and 78 formed below the third metal wiring layer 88 are made of a metal oxide such as an oxide aluminum film. As a flat nore film 114 formed above the third metal wiring layer 88 and having an opening 96b reaching the wiring (bonding pad) 88b, an inorganic film such as a film or a silicon nitride film is used. An organic film having properties may be formed.
[0351] また、上記実施形態では、層間絶縁膜を構成する絶縁膜として、シリコン酸ィ匕膜を 形成する場合を例に説明したが、シリコン酸ィ匕膜に代えて、種々の絶縁膜を形成す ることがでさる。  [0351] In the above-described embodiment, the case where a silicon oxide film is formed as the insulating film constituting the interlayer insulating film has been described as an example. However, various insulating films may be used instead of the silicon oxide film. It can be formed.
[0352] また、上記実施形態では、層間絶縁膜を構成する絶縁膜の表面を平坦化する方法 として CMP法を用いる場合を例に説明したが、絶縁膜の表面を平坦ィ匕する方法は、 CMP法に限定されるものではない。例えば、エッチングにより、絶縁膜の表面を平坦 化してもよい。エッチングガスとしては、例えば Arガスを用いることができる。  [0352] In the above-described embodiment, the case where the CMP method is used as a method for flattening the surface of the insulating film constituting the interlayer insulating film has been described as an example. However, the method for flattening the surface of the insulating film is described below. It is not limited to the CMP method. For example, the surface of the insulating film may be planarized by etching. As an etching gas, for example, Ar gas can be used.
[0353] また、上記実施形態では、第 1金属配線層 56、第 2金属配線層 72、及び第 3金属 配線層 88の 3層の金属配線層により半導体基板 10上に回路が構成される場合を例 に説明したが、半導体基板 10上の回路を構成する金属配線層の層数は 3層に限定 されるものではない。金属配線層の層数は、半導体基板 10上に構成する回路の設 計に応じて適宜設定することができる。 [0354] また、上記実施形態では、 1つのトランジスタ 24及び 1つの強誘電体キャパシタ 42 を有する 1T1C型のメモリセルが形成されている場合を例に説明した力 メモリセル の構成は 1T1C型に限定されるものではない。メモリセルの構成としては、 1T1C型 のほか、例えば 2つのトランジスタ及び 2つの強誘電体キャパシタを有する 2T2C型 等の種々の構成を用いることができる。 [0353] In the above embodiment, the circuit is formed on the semiconductor substrate 10 by the three metal wiring layers of the first metal wiring layer 56, the second metal wiring layer 72, and the third metal wiring layer 88. However, the number of metal wiring layers constituting the circuit on the semiconductor substrate 10 is not limited to three. The number of metal wiring layers can be appropriately set according to the design of the circuit configured on the semiconductor substrate 10. [0354] In the above embodiment, the configuration of the force memory cell described as an example in which a 1T1C type memory cell having one transistor 24 and one ferroelectric capacitor 42 is formed is limited to the 1T1C type. Is not to be done. As the configuration of the memory cell, in addition to the 1T1C type, various configurations such as a 2T2C type having two transistors and two ferroelectric capacitors can be used.
[0355] また、上記実施形態では、プレーナー型セルを有する FeRAM構造の半導体装置 について説明した力 本発明の適用範囲はこれに限定されるものではない。例えば、 本発明は、スタック型セルを有し、ゲート長が例えば 0. 18 μ mに設定された FeRA M構造の半導体装置にっ 、ても適用することができる。  Further, in the above embodiment, the force described for the FeRAM structure semiconductor device having the planar type cell is not limited to this. For example, the present invention can be applied even to a FeRAM structure semiconductor device having a stack type cell and a gate length set to, for example, 0.18 μm.
[0356] 図 53は、本発明を適用したスタック型セルを有する FeRAM構造の半導体装置の 構造を示す断面図である。なお、図 53においては、 FeRAMセル部 306以外の部分 につ 、ては、ノ リア膜以外の構造を省略して示して 、る。  FIG. 53 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having stacked cells to which the present invention is applied. In FIG. 53, the structure other than the FeRAM cell portion 306 is shown by omitting the structure other than the NORA film.
[0357] 図示するように、例えばシリコンよりなる半導体基板 210上には、素子領域を画定す る素子分離領域 212が形成されている。素子分離領域 212が形成された半導体基 板 210内には、ウエノレ 214a、 214b力 ^形成されている。  As shown in the drawing, an element isolation region 212 that defines an element region is formed on a semiconductor substrate 210 made of, for example, silicon. In the semiconductor substrate 210 in which the element isolation region 212 is formed, Wenore 214a and 214b forces are formed.
[0358] ゥエル 214a、 214bが形成された半導体基板 210上には、ゲート絶縁膜 216を介し てゲート電極 (ゲート配線） 218が形成されている。ゲート電極 218は、例えば、ポリシ リコン膜上に、トランジスタのゲート長等に応じてコバルトシリサイド膜、ニッケルシリサ イド膜、タングステンシリサイド膜等の金属シリサイド膜が積層されたポリサイド構造を 有している。ゲート電極 218上には、シリコン酸ィ匕膜 219が形成されている。ゲート電 極 218及びシリコン酸ィ匕膜 219の側壁部分には、サイドウォール絶縁膜 220が形成 されている。  A gate electrode (gate wiring) 218 is formed on the semiconductor substrate 210 on which the wells 214a and 214b are formed via a gate insulating film 216. The gate electrode 218 has, for example, a polycide structure in which a metal silicide film such as a cobalt silicide film, a nickel silicide film, or a tungsten silicide film is stacked on a polysilicon film in accordance with the gate length of the transistor. A silicon oxide film 219 is formed on the gate electrode 218. A sidewall insulating film 220 is formed on the side walls of the gate electrode 218 and the silicon oxide film 219.
[0359] サイドウォール絶縁膜 220が形成されたゲート電極 218の両側には、ソース/ドレイ ン拡散層 222が形成されている。こうして、ゲート電極 218とソース Zドレイン拡散層 2 22とを有するトランジスタ 224が構成されている。トランジスタ 224のゲート長は、例え ば 0. 18 mに設定されている。  [0359] A source / drain diffusion layer 222 is formed on both sides of the gate electrode 218 on which the sidewall insulating film 220 is formed. Thus, a transistor 224 having a gate electrode 218 and a source Z drain diffusion layer 222 is formed. The gate length of transistor 224 is set to 0.18 m, for example.
[0360] トランジスタ 224が形成された半導体基板 210上には、 SiON膜 225と、シリコン酸 化膜 226とを順次積層してなる層間絶縁膜 227が形成されている。層間絶縁膜 227 の表面は平坦ィ匕されて 、る。 [0360] On the semiconductor substrate 210 on which the transistor 224 is formed, an interlayer insulating film 227 formed by sequentially laminating a SiON film 225 and a silicon oxide film 226 is formed. Interlayer insulating film 227 The surface of the surface is flattened.
[0361] 層間絶縁膜 227上には、例えば酸ィ匕アルミニウム膜よりなるバリア膜 228が形成さ れている。  [0361] On the interlayer insulating film 227, a barrier film 228 made of, for example, an oxide aluminum film is formed.
[0362] ノ リア膜 228及び層間絶縁膜 227には、ソース/ドレイン拡散層 222に達するコン タク卜ホーノレ 230a、 230b力形成されて!ヽる。  [0362] The contact films Honor 230a and 230b reaching the source / drain diffusion layer 222 are formed in the noria film 228 and the interlayer insulating film 227.
[0363] コンタクトホール 230a、 230bには、 Ti膜と TiN膜とを順次積層してなるバリアメタル 膜 (図示せず)が形成されて！ヽる。 [0363] A barrier metal film (not shown) formed by sequentially stacking a Ti film and a TiN film is formed in the contact holes 230a and 230b! Speak.
[0364] ノ リアメタル膜が形成されたコンタクトホール 230a、 230b内には、タングステンより なる導体プラグ 232a、 232bが埋め込まれて!/、る。 [0364] Conductor plugs 232a and 232b made of tungsten are embedded in the contact holes 230a and 230b in which the rare metal film is formed.
[0365] ノ リア膜 228上には、導体プラグ 232aに電気的に接続された Ir膜 234が形成され ている。 [0365] An Ir film 234 electrically connected to the conductor plug 232a is formed on the noria film 228.
[0366] Ir膜 234上には、強誘電体キャパシタ 242の下部電極 236が形成されている。  On the Ir film 234, the lower electrode 236 of the ferroelectric capacitor 242 is formed.
[0367] 下部電極 236上には、強誘電体キャパシタ 242の強誘電体膜 238が形成されてい る。強誘電体膜 238としては、例えば PZT膜が用いられている。 On the lower electrode 236, a ferroelectric film 238 of the ferroelectric capacitor 242 is formed. As the ferroelectric film 238, for example, a PZT film is used.
[0368] 強誘電体膜 238上には、強誘電体キャパシタ 242の上部電極 240が形成されてい る。 [0368] On the ferroelectric film 238, the upper electrode 240 of the ferroelectric capacitor 242 is formed.
[0369] 積層されている上部電極 240、強誘電体膜 238、下部電極 236、及び Ir膜 234は、 エッチングにより一括してパターユングされ、互いにほぼ同じ平面形状を有している。  The upper electrode 240, the ferroelectric film 238, the lower electrode 236, and the Ir film 234 that are stacked are patterned together by etching and have substantially the same planar shape.
[0370] こうして、下部電極 236と強誘電体膜 238と上部電極 240とからなる強誘電体キヤ パシタ 242が構成されている。強誘電体キャパシタ 242の下部電極 236は、 Ir膜 234 を介して導体プラグ 232aに電気的に接続されている。 Thus, the ferroelectric capacitor 242 composed of the lower electrode 236, the ferroelectric film 238, and the upper electrode 240 is formed. The lower electrode 236 of the ferroelectric capacitor 242 is electrically connected to the conductor plug 232a via the Ir film 234.
[0371] 層間絶縁膜 227の Ir膜 234が形成されていない領域上には、 Ir膜 234と同程度の 膜厚或いは Ir膜 234よりも薄い膜厚の SiON膜 244が形成されている。なお、 SiON 膜 244に代えて、シリコン酸ィ匕膜を形成してもよい。 [0371] On the region of the interlayer insulating film 227 where the Ir film 234 is not formed, a SiON film 244 having a film thickness approximately the same as that of the Ir film 234 or thinner than the Ir film 234 is formed. In place of the SiON film 244, a silicon oxide film may be formed.
[0372] 強誘電体キャパシタ 242上及び SiON膜 244上には、水素及び水分の拡散を防止 する機能を有するバリア膜 246が形成されている。バリア膜 246としては、例えば酸 化アルミニウム膜が用いられて 、る。 A barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed on the ferroelectric capacitor 242 and the SiON film 244. As the barrier film 246, for example, an aluminum oxide film is used.
[0373] ノ リア膜 246上にはシリコン酸ィ匕膜 248が形成され、シリコン酸ィ匕膜 248により強誘 電体キャパシタ 242が埋め込まれて!/、る。シリコン酸化膜 248の表面は平坦ィ匕されて いる。 [0373] A silicon oxide film 248 is formed on the noria film 246 and is strongly attracted by the silicon oxide film 248. Electric capacitor 242 is embedded! The surface of the silicon oxide film 248 is flattened.
[0374] 平坦化されたシリコン酸ィ匕膜 248上には、水素及び水分の拡散を防止する機能を 有する平坦なノ リア膜 250が形成されている。ノ リア膜 250としては、例えば酸化ァ ルミ-ゥム膜が用いられている。バリア膜 250は、 FeRAMチップ領域 302及びスクラ イブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領域 302に までわたって形成されている。すなわち、ノ リア膜 250は、スクライブ部 304、 FeRA Mセル部 306、 FeRAMの周辺回路部（図示せず）、ロジック回路部 310、ロジック回 路の周辺回路部（図示せず）、パッド部 314、これらの境界部であるスクライブ部'パッ ド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界部 3 20にわたつて形成されている。  [0374] On the flattened silicon oxide film 248, a flat noria film 250 having a function of preventing the diffusion of hydrogen and moisture is formed. As the noria film 250, for example, an aluminum oxide film is used. The barrier film 250 is formed over the FeRAM chip region 302 and the sliver portion 304, and is formed over the adjacent FeRAM chip region 302. That is, the NORA film 250 includes a scribe part 304, a FeRA M cell part 306, a peripheral circuit part (not shown) of the FeRAM, a logic circuit part 310, a peripheral circuit part (not shown) of the logic circuit, and a pad part 314. The boundary portion 316 between the scribe portion and the pad portion, the boundary portion 318 between the pad portion and the circuit portion, and the boundary portion 320 between the circuit portion and the circuit portion are formed.
[0375] ノ リア膜 250上には、シリコン酸ィ匕膜 252が形成されている。  A silicon oxide film 252 is formed on the noria film 250.
[0376] こうして、 SiON膜 244、 ノ リア膜 246、シリコン酸化膜 248、 ノ リア膜 250、及びシリ コン酸ィ匕膜 252により層間絶縁膜 253が構成されている。  Thus, the SiON film 244, the noria film 246, the silicon oxide film 248, the noria film 250, and the silicon oxide film 252 constitute the interlayer insulating film 253.
[0377] シリコン酸ィ匕膜 252、 ノ リア膜 250、シリコン酸ィ匕膜 248及びバリア膜 246には、強 誘電体キャパシタ 242の上部電極 240に達するコンタクトホール 254aが形成されて いる。また、シリコン酸ィ匕膜 252、 ノ リア膜 250、シリコン酸ィ匕膜 248、 ノ リア膜 246、 及び SiON膜 244には、導体プラグ 232bに達するコンタクトホール 254bが形成され ている。  [0377] A contact hole 254a reaching the upper electrode 240 of the ferroelectric capacitor 242 is formed in the silicon oxide film 252, the NORA film 250, the silicon oxide film 248, and the barrier film 246. In addition, a contact hole 254b reaching the conductor plug 232b is formed in the silicon oxide film 252, the noria film 250, the silicon oxide film 248, the noria film 246, and the SiON film 244.
[0378] コンタクトホール 254a、 254b内には、 Ti膜と TiN膜とを順次積層してなるバリアメタ ル膜 (図示せず)が形成されている。なお、ノ リアメタル膜として、 Ti膜を形成せずに [0378] A barrier metal film (not shown) is formed in the contact holes 254a and 254b by sequentially stacking a Ti film and a TiN film. In addition, without forming the Ti film as the rare metal film
、 TiN膜よりなるバリアメタル膜を形成してもよい。 A barrier metal film made of a TiN film may be formed.
[0379] ノ リアメタル膜が形成されたコンタクトホール 254a、 254b内には、タングステンより なる導体プラグ 256a、 256bがそれぞれ埋め込まれて!/、る。 [0379] Conductor plugs 256a and 256b made of tungsten are embedded in the contact holes 254a and 254b in which the nore metal film is formed!
[0380] シリコン酸ィ匕膜 252上には、導体プラグ 256aに電気的に接続された配線 258aと、 導体プラグ 256bに電気的に接続された配線 258bとが形成されている。 [0380] On the silicon oxide film 252 are formed a wiring 258a electrically connected to the conductor plug 256a and a wiring 258b electrically connected to the conductor plug 256b.
[0381] 配線 258a、 258bが形成されたシリコン酸ィ匕膜 252上にはシリコン酸ィ匕膜 260が形 成され、シリコン酸ィ匕膜 260により配線 258a、 258bが埋め込まれている。シリコン酸 化膜 260の表面は平坦ィ匕されて 、る。 [0381] A silicon oxide film 260 is formed on the silicon oxide film 252 on which the wirings 258a and 258b are formed, and the wirings 258a and 258b are embedded by the silicon oxide film 260. Silicon acid The surface of the oxide film 260 is flattened.
[0382] 平坦化されたシリコン酸ィ匕膜 260上には、水素及び水分の拡散を防止する機能を 有する平坦なノ リア膜 262が形成されている。ノ リア膜 262としては、例えば酸化ァ ルミ-ゥム膜が用いられている。ノ リア膜 262は、 FeRAMチップ領域 302及びスクラ イブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領域 302に までわたって形成されている。すなわち、ノ リア膜 262は、スクライブ部 304、 FeRA Mセル部 306、 FeRAMの周辺回路部（図示せず）、ロジック回路部 310、ロジック回 路の周辺回路部（図示せず）、パッド部 314、これらの境界部であるスクライブ部'パッ ド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界部 3 20にわたつて形成されている。  [0382] On the flattened silicon oxide film 260, a flat noria film 262 having a function of preventing the diffusion of hydrogen and moisture is formed. As the noria film 262, for example, an aluminum oxide film is used. The noria film 262 is formed over the FeRAM chip region 302 and the sliver portion 304, and is formed over the adjacent FeRAM chip region 302. That is, the NORA film 262 includes the scribe part 304, the FeRA M cell part 306, the peripheral circuit part (not shown) of the FeRAM, the logic circuit part 310, the peripheral circuit part (not shown) of the logic circuit, and the pad part 314. The boundary portion 316 between the scribe portion and the pad portion, the boundary portion 318 between the pad portion and the circuit portion, and the boundary portion 320 between the circuit portion and the circuit portion are formed.
[0383] ノ リア膜 262上には、シリコン酸ィ匕膜 264が形成されている。  A silicon oxide film 264 is formed on the noria film 262.
[0384] こうして、シリコン酸ィ匕膜 260、 ノ リア膜 262、及びシリコン酸ィ匕膜 264により層間絶 縁膜 265が構成されている。  Thus, the interlayer insulating film 265 is constituted by the silicon oxide film 260, the noria film 262, and the silicon oxide film 264.
[0385] シリコン酸ィ匕膜 264、 ノ リア膜 262、及びシリコン酸ィ匕膜 260には、配線 258bに達 するコンタクトホール 268が形成されて!、る。  [0385] In the silicon oxide film 264, the NORA film 262, and the silicon oxide film 260, a contact hole 268 reaching the wiring 258b is formed!
[0386] コンタクトホール 268内には、 Ti膜と TiN膜とを順次積層してなるノ リアメタル膜（図 示せず）が形成されている。  [0386] In the contact hole 268, a rare metal film (not shown) formed by sequentially laminating a Ti film and a TiN film is formed.
[0387] ノ リアメタル膜が形成されたコンタクトホール 268内には、タングステンよりなる導体 プラグ 270が埋め込まれて!/、る。  [0387] A conductor plug 270 made of tungsten is embedded in the contact hole 268 in which the noria metal film is formed!
[0388] シリコン酸ィ匕膜 264上には、導体プラグ 268に電気的に接続された配線 272が形 成されている。  [0388] On the silicon oxide film 264, a wiring 272 electrically connected to the conductor plug 268 is formed.
[0389] 配線 272が形成されたシリコン酸ィ匕膜 264上にはシリコン酸ィ匕膜 274が形成され、 シリコン酸ィ匕膜 274により配線 272が埋め込まれて 、る。シリコン酸ィ匕膜 274の表面 は平坦ィ匕されている。  A silicon oxide film 274 is formed on the silicon oxide film 264 on which the wiring 272 is formed, and the wiring 272 is embedded by the silicon oxide film 274. The surface of the silicon oxide film 274 is flat.
[0390] 平坦化されたシリコン酸ィ匕膜 274上には、水素及び水分の拡散を防止する機能を 有する平坦なノ リア膜 276が形成されている。ノ リア膜 276としては、例えば酸化ァ ルミ-ゥム膜が用いられている。ノ リア膜 276は、 FeRAMチップ領域 302及びスクラ イブ部 304にわたつて形成されているとともに、隣接する FeRAMチップ領域 302に までわたって形成されている。すなわち、ノリア膜 276は、スクライブ部 304、 FeRA Mセル部 306、 FeRAMの周辺回路部（図示せず）、ロジック回路部 310、ロジック回 路の周辺回路部（図示せず）、パッド部 314、これらの境界部であるスクライブ部'パッ ド部間境界部 316、パッド部 ·回路部間境界部 318、及び回路部 ·回路部間境界部 3 20にわたつて形成されている。 [0390] On the flattened silicon oxide film 274, a flat noria film 276 having a function of preventing the diffusion of hydrogen and moisture is formed. As the noria film 276, for example, an aluminum oxide film is used. The noria film 276 is formed over the FeRAM chip region 302 and the sliver portion 304, and is formed in the adjacent FeRAM chip region 302. It is formed all the way. That is, the noria film 276 includes a scribe part 304, a FeRA M cell part 306, a peripheral circuit part (not shown) of FeRAM, a logic circuit part 310, a peripheral circuit part (not shown) of a logic circuit, a pad part 314, These boundary portions are formed across a scribe portion'pad portion boundary portion 316, a pad portion / circuit portion boundary portion 318, and a circuit portion / circuit portion boundary portion 320.
[0391] ノリア膜 276上には、シリコン酸ィ匕膜 278が形成されている。  On the noria film 276, a silicon oxide film 278 is formed.
[0392] なお、シリコン酸ィ匕膜 278から上部は図示しないが、回路設計に応じて、シリコン酸 化膜等により構成される層間絶縁膜に埋め込まれた配線が適宜形成されている。  [0392] Although the upper portion from the silicon oxide film 278 is not shown, wirings embedded in an interlayer insulating film made of a silicon oxide film or the like are appropriately formed according to the circuit design.
[0393] 上述のように、スタック型セルを有する FeRAM構造の半導体装置にお!、ても、上 記実施形態と同様に、水素及び水分の拡散を防止する平坦なバリア膜 250、 262、 276を形成することにより、水素及び水分による強誘電体キャパシタ 242の電気的特 性の劣化を確実に防止することができ、 PTHS特性を大幅に向上することができる。 なお、この場合においても、水素及び水分の拡散を防止する平坦なノリア膜は、少 なくとも 2層形成されていればよぐノリア膜 250、 262、 276の 3層すべてが形成され ていなくてもよい。また、必要に応じて、更に多くの平坦なノリア膜を形成してもよい。  [0393] As described above, in the FeRAM structure semiconductor device having a stack type cell !, however, as in the above embodiment, the flat barrier films 250, 262, 276 that prevent the diffusion of hydrogen and moisture are used. As a result, the deterioration of the electrical characteristics of the ferroelectric capacitor 242 due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics can be greatly improved. Even in this case, the flat noria film for preventing the diffusion of hydrogen and moisture is not necessarily formed in all three layers of the noria films 250, 262, and 276 as long as at least two layers are formed. Also good. Further, more flat noria films may be formed as necessary.
[0394] 上記実施形態では、 A1を主体とする配線を形成する場合を例に説明したが、配線 は、 A1を主体とする配線に限定されるものではなぐ例えばダマシン法等により Cuを 主体とする配線を形成してもよ ヽ。  [0394] In the above embodiment, the case where the wiring mainly composed of A1 is formed has been described as an example. However, the wiring is not limited to the wiring mainly composed of A1, and Cu is mainly composed by the damascene method or the like. You can also form wiring to be used.
[0395] Cuを主体とする配線を用いた場合について図 54及び図 55を用いて説明する。図 54は図 53に示す半導体装置にお 、て Cu配線を用 V、た場合の構造を示す断面図、 図 55は Cu配線を用いた場合におけるボンディングパッドの構造を示す断面図であ る。なお、図 54は、図 53と同様に、スタック型セルを有する FeRAM構造の半導体装 置の構造を示している。図 53に示す半導体装置と同様の構成要素については同様 の符号を付し説明を省略し或いは簡略にする。  [0395] The case where wiring mainly composed of Cu is used will be described with reference to FIGS. 54 and 55. FIG. FIG. 54 is a cross-sectional view showing the structure of the semiconductor device shown in FIG. 53 when Cu wiring is used, and FIG. 55 is a cross-sectional view showing the structure of the bonding pad when Cu wiring is used. Note that FIG. 54 shows the structure of a FeRAM semiconductor device having a stack type cell as in FIG. The same components as those of the semiconductor device illustrated in FIG. 53 are denoted by the same reference numerals, and description thereof will be omitted or simplified.
[0396] 図 54に示すように、タングステンよりなる導体プラグ 256a、 256bが埋め込まれた層 間絶縁膜 253上には、シリコン酸ィ匕膜 260aが形成されている。  As shown in FIG. 54, a silicon oxide film 260a is formed on the interlayer insulating film 253 in which the conductor plugs 256a and 256b made of tungsten are embedded.
[0397] シリコン酸ィ匕膜 260aには、配線溝 280a、 280bが形成されている。  [0397] Wiring grooves 280a and 280b are formed in the silicon oxide film 260a.
[0398] 配線溝 280aには、導体プラグ 256aに電気的に接続された Cu配線 282aが埋め込 まれている。配線溝 280bには、導体プラグ 256bに電気的に接続された Cu配線 282 bが埋め込まれている。 [0398] Cu wiring 282a electrically connected to conductor plug 256a is embedded in wiring groove 280a. It is rare. Cu wiring 282b electrically connected to the conductor plug 256b is embedded in the wiring groove 280b.
[0399] Cu配線 282a、 282bが埋め込まれたシリコン酸化膜 260a上には、シリコン酸化膜 [0399] On the silicon oxide film 260a in which the Cu wirings 282a and 282b are embedded, the silicon oxide film
260bが形成されて!、る。シリコン酸化膜 260bの表面は平坦ィ匕されて!、る。 260b is formed! The surface of the silicon oxide film 260b is flattened!
[0400] 平坦化されたシリコン酸ィ匕膜 260上には、水素及び水分の拡散を防止する機能を 有する平坦なノ リア膜 262が形成されて ヽる。 [0400] On the flattened silicon oxide film 260, a flat noria film 262 having a function of preventing diffusion of hydrogen and moisture is formed.
[0401] ノ リア膜 262上には、シリコン酸ィ匕膜 264が形成されている。 [0401] A silicon oxide film 264 is formed on the noria film 262.
[0402] こうして、シリコン酸ィ匕膜 260、 ノ リア膜 262、及びシリコン酸ィ匕膜 264により層間絶 縁膜 265が構成されている。 Thus, the interlayer insulating film 265 is constituted by the silicon oxide film 260, the noria film 262, and the silicon oxide film 264.
[0403] シリコン酸ィ匕膜 264、 ノ リア膜 262、及びシリコン酸ィ匕膜 260bには、 Cu配線 282b に達するコンタクトホール 268が形成されて!、る。 [0403] A contact hole 268 reaching the Cu wiring 282b is formed in the silicon oxide film 264, the NORA film 262, and the silicon oxide film 260b.
[0404] コンタクトホール 268内には、例えば膜厚 15nmの Ta膜と、例えば膜厚 130nmの C u膜とを順次積層してなる膜が形成されている。こうして、 Ta膜よりなるバリアメタル膜[0404] In the contact hole 268, a film is formed by sequentially stacking, for example, a Ta film with a thickness of 15 nm and a Cu film with a thickness of 130 nm, for example. Thus, a barrier metal film made of Ta film
(図示せず）が形成されたコンタクトホール 268内には、 Cuよりなる導体プラグ 270が 埋め込まれている。 A conductor plug 270 made of Cu is embedded in the contact hole 268 in which (not shown) is formed.
[0405] 上述のように Cu配線を用いた場合にぉ 、て、ボンディングパッドは、 AlCu合金膜 等の A1を主体とする金属膜により構成される。  [0405] When Cu wiring is used as described above, the bonding pad is made of a metal film mainly composed of A1, such as an AlCu alloy film.
[0406] 図 55に示すように、シリコン酸ィ匕膜よりなる層間絶縁膜 284には、配線溝 285が形 成されている。 [0406] As shown in FIG. 55, a wiring trench 285 is formed in the interlayer insulating film 284 made of a silicon oxide film.
[0407] 配線溝 285には、 Cu配線 286が埋め込まれている。  [0407] Cu wiring 286 is embedded in the wiring groove 285.
[0408] Cu配線 286が埋め込まれた層間絶縁膜 284上には、シリコン酸ィ匕膜よりなる層間 絶縁膜 288が形成されている。層間絶縁膜 288を構成するシリコン酸ィ匕膜は、例え ばプラズマ TEOSCVD法により形成されたものである。  [0408] An interlayer insulating film 288 made of a silicon oxide film is formed on the interlayer insulating film 284 in which the Cu wiring 286 is embedded. The silicon oxide film constituting the interlayer insulating film 288 is formed by, for example, a plasma TEOSCVD method.
[0409] 層間絶縁膜 288には、 Cu配線 286に達するコンタクトホール 289が形成されている  [0409] In the interlayer insulating film 288, a contact hole 289 reaching the Cu wiring 286 is formed.
[0410] コンタクトホール 268内には、タングステンよりなる導体プラグ 290が埋め込まれて いる。 [0410] In the contact hole 268, a conductor plug 290 made of tungsten is embedded.
[0411] 導体プラグ 290が埋め込まれた層間絶縁膜 288上には、導体プラグ 290に電気的 に接続されたボンディングパッド 292が形成されて!、る。ボンディングパッド 292は、[0411] On the interlayer insulating film 288 in which the conductor plug 290 is embedded, the conductor plug 290 is electrically connected. A bonding pad 292 connected to the substrate is formed! Bonding pad 292
AlCu合金膜により構成されて 、る。 It is composed of an AlCu alloy film.
[0412] なお、 Cu配線 286とボンディングパッド 292との間に、水素及び水分の拡散を防止 するバリア膜を形成してもよ 、。 [0412] A barrier film that prevents diffusion of hydrogen and moisture may be formed between the Cu wiring 286 and the bonding pad 292.
[0413] 層間絶縁膜 288上及びボンディングパッド 292上には、シリコン酸ィ匕膜 294が形成 されている。シリコン酸化膜 294は、例えばプラズマ TEOSCVD法により形成された ものである。 [0413] A silicon oxide film 294 is formed on the interlayer insulating film 288 and the bonding pad 292. The silicon oxide film 294 is formed by plasma TEOSCVD, for example.
[0414] シリコン酸ィ匕膜 294上には、シリコン窒化膜 296が形成されている。  [0414] On the silicon oxide film 294, a silicon nitride film 296 is formed.
[0415] シリコン窒化膜 296上には、ポリイミド榭脂膜 298が形成されている。 [0415] On the silicon nitride film 296, a polyimide resin film 298 is formed.
[0416] ポリイミド榭脂膜 298、シリコン窒化膜 296、及びシリコン酸ィ匕膜 294には、ボンディ ングパッド 292に達する開口部 299が形成されている。すなわち、シリコン窒化膜 29 6及びシリコン酸ィ匕膜 294には、ボンディングパッド 292に達する開口部 299aが形成 されている。ポリイミド榭脂膜 298には、シリコン窒化膜 296及びシリコン酸ィ匕膜 294 に形成された開口部 299aを含む領域に、開口部 299bが形成されている。 [0416] In the polyimide resin film 298, the silicon nitride film 296, and the silicon oxide film 294, an opening 299 reaching the bonding pad 292 is formed. That is, an opening 299 a reaching the bonding pad 292 is formed in the silicon nitride film 296 and the silicon oxide film 294. In the polyimide resin film 298, an opening 299b is formed in a region including the opening 299a formed in the silicon nitride film 296 and the silicon oxide film 294.
[0417] ボンディングパッド 292には、開口部 299を介して、外部回路（図示せず）が電気的 に接続される。 [0417] An external circuit (not shown) is electrically connected to the bonding pad 292 through the opening 299.
[0418] このように、 A1を主体とする配線に代えて Cuを主体とする配線を用いてもょ 、。  [0418] In this way, instead of the wiring mainly composed of A1, the wiring mainly composed of Cu may be used.
[0419] 図 53に示すようにスタック型セルを有する FeRAM構造の半導体装置にお 、て Cu 配線を用いた場合においては、例えば、強誘電体キャパシタと、強誘電体キャパシタ 上の第 1層目の Cu配線との間にまず 1層目の平坦なノリア膜を形成し、ボンディング ノッドと、ボンディングパッド下の最上層の Cu配線との間に 2層目の平坦なノリア膜 を形成すればよい。このような 2層の平坦なノリア膜に加えて、他の Cu配線の間に平 坦なノリア膜を更に形成することにより、耐湿性を更に向上することができる。 [0419] In the case of using a Cu wiring in a FeRAM structure semiconductor device having a stack type cell as shown in FIG. 53, for example, a ferroelectric capacitor and a first layer on the ferroelectric capacitor. First, a first flat noria film should be formed between the Cu wiring and the second flat noria film should be formed between the bonding node and the uppermost Cu wiring under the bonding pad. . In addition to such a two-layer flat noria film, moisture resistance can be further improved by further forming a flat noria film between other Cu wirings.
産業上の利用可能性  Industrial applicability
[0420] 本発明による半導体装置及びその製造方法は、強誘電体キャパシタを有する半導 体装置の信頼性を向上するのに有用である。 The semiconductor device and the manufacturing method thereof according to the present invention are useful for improving the reliability of a semiconductor device having a ferroelectric capacitor.

Claims

請求の範囲 The scope of the claims
[1] 半導体基板上に形成され、下部電極と、前記下部電極上に形成された強誘電体 膜と、前記強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタと、 前記半導体基板上及び前記強誘電体キャパシタ上に形成され、表面が平坦化さ れた第 1の絶縁膜と、  [1] A ferroelectric capacitor formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film; A first insulating film formed on a semiconductor substrate and on the ferroelectric capacitor and having a planarized surface;
前記第 1の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 1のバ リア膜と、  A flat first barrier film formed on the first insulating film and preventing diffusion of hydrogen or moisture;
前記第 1のバリア膜上に形成され、表面が平坦化された第 2の絶縁膜と、 前記第 2の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 2のバ リア膜と  A second insulating film formed on the first barrier film and having a planarized surface; and a flat second barrier film formed on the second insulating film and preventing diffusion of hydrogen or moisture. With membrane
を有することを特徴とする半導体装置。  A semiconductor device comprising:
[2] 請求の範囲第 1項記載の半導体装置において、 [2] In the semiconductor device according to claim 1,
前記半導体基板に設けられたチップ領域と、  A chip region provided on the semiconductor substrate;
前記半導体基板に、前記チップ領域に隣接して設けられたスクライブ部と、 前記チップ領域内に設けられ、前記強誘電体キャパシタを有するメモリセルが形成 されたメモリセル部と、  A scribe portion provided in the semiconductor substrate adjacent to the chip region; a memory cell portion provided in the chip region and formed with a memory cell having the ferroelectric capacitor;
前記チップ領域内に設けられ、ロジック回路が形成されたロジック回路部と、 前記チップ領域内に設けられ、ボンディングパッドが形成されたパッド部とを更に有 し、  A logic circuit part provided in the chip area and having a logic circuit formed thereon; and a pad part provided in the chip area and having a bonding pad formed thereon.
前記第 1のバリア膜及び前記第 2のバリア膜の少なくともいずれかは、前記メモリセ ル部、前記ロジック回路部、及び前記パッド部にわたって形成されている  At least one of the first barrier film and the second barrier film is formed over the memory cell portion, the logic circuit portion, and the pad portion.
ことを特徴とする半導体装置。  A semiconductor device.
[3] 請求の範囲第 2項記載の半導体装置にお 、て、 [3] In the semiconductor device according to claim 2,
前記前記第 1のバリア膜及び前記第 2のバリア膜の少なくともいずれかは、前記メモ リセル部、前記ロジック回路部、前記パッド部、及びスクライブ部にわたって形成され ている  At least one of the first barrier film and the second barrier film is formed over the memory cell portion, the logic circuit portion, the pad portion, and the scribe portion.
ことを特徴とする半導体装置。  A semiconductor device.
[4] 請求の範囲第 1項乃至第 3項のいずれ力 1項に記載の半導体装置において、 前記強誘電体キャパシタの前記下部電極又は前記上部電極に電気的に接続され た第 1の配線と、 [4] In the semiconductor device according to any one of claims 1 to 3, A first wiring electrically connected to the lower electrode or the upper electrode of the ferroelectric capacitor;
前記第 1の配線上に形成された第 2の配線と、  A second wiring formed on the first wiring;
前記第 2の配線上に形成され、外部回路が電気的に接続される第 3の配線とを更 に有する  And a third wiring formed on the second wiring and electrically connected to an external circuit.
ことを特徴とする半導体装置。  A semiconductor device.
[5] 請求の範囲第 4項記載の半導体装置において、 [5] In the semiconductor device according to claim 4,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the second wiring and the third wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[6] 請求の範囲第 4項記載の半導体装置において、 [6] In the semiconductor device according to claim 4,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記第 1の配線と前記第 2の配線と の間に形成されている  The first insulating film and the first barrier film are formed between the first wiring and the second wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[7] 請求の範囲第 6項記載の半導体装置において、 [7] In the semiconductor device according to claim 6,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the second wiring and the third wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[8] 請求の範囲第 7項記載の半導体装置において、 [8] In the semiconductor device according to claim 7,
前記第 3の配線上に形成され、表面が平坦化された第 3の絶縁膜と、  A third insulating film formed on the third wiring and having a planarized surface;
前記第 3の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 3のバ リア膜とを更に有し、  A flat third barrier film formed on the third insulating film and preventing diffusion of hydrogen or moisture;
前記第 3の絶縁膜及び前記第 3のバリア膜には、前記第 3の配線に達する開口部 が形成されている  An opening reaching the third wiring is formed in the third insulating film and the third barrier film.
ことを特徴とする半導体装置。  A semiconductor device.
[9] 請求の範囲第 6項記載の半導体装置において、 [9] In the semiconductor device according to claim 6,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている The second insulating film and the second barrier film are formed on the third wiring. An opening reaching the third wiring is formed in the second insulating film and the second barrier film.
ことを特徴とする半導体装置。  A semiconductor device.
[10] 請求の範囲第 4項記載の半導体装置において、 [10] In the semiconductor device according to claim 4,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されており、  The first insulating film and the first barrier film are formed between the second wiring and the third wiring;
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている  The second insulating film and the second barrier film are formed on the third wiring, and the second insulating film and the second barrier film have an opening reaching the third wiring. Part is formed
ことを特徴とする半導体装置。  A semiconductor device.
[11] 請求の範囲第 4項記載の半導体装置において、 [11] In the semiconductor device according to claim 4,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記強誘電体キャパシタと前記第 1 の配線との間に形成されている  The first insulating film and the first barrier film are formed between the ferroelectric capacitor and the first wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[12] 請求の範囲第 11項記載の半導体装置において、 [12] In the semiconductor device according to claim 11,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 1の配線と前記第 2の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the first wiring and the second wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[13] 請求の範囲第 12項記載の半導体装置において、 [13] In the semiconductor device according to claim 12,
前記第 2の配線と前記第 3の配線との間に形成され、表面が平坦化された第 3の絶 縁膜と、  A third insulating film formed between the second wiring and the third wiring and having a planarized surface;
前記第 3の配線下、前記第 3の絶縁膜上に形成され、水素又は水分の拡散を防止 する平坦な第 3のバリア膜とを更に有する  A flat third barrier film that is formed on the third insulating film under the third wiring and prevents diffusion of hydrogen or moisture.
ことを特徴とする半導体装置。  A semiconductor device.
[14] 請求の範囲第 13項記載の半導体装置において、 [14] In the semiconductor device according to claim 13,
前記第 3の配線上に形成され、表面が平坦化された第 4の絶縁膜と、  A fourth insulating film formed on the third wiring and having a planarized surface;
前記第 4の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 4のバ リア膜とを更に有し、 A flat fourth buffer formed on the fourth insulating film and preventing diffusion of hydrogen or moisture. A rear film,
前記第 4の絶縁膜及び前記第 4のバリア膜には、前記第 3の配線に達する開口部 が形成されている  An opening reaching the third wiring is formed in the fourth insulating film and the fourth barrier film.
ことを特徴とする半導体装置。  A semiconductor device.
[15] 請求の範囲第 11項記載の半導体装置において、 [15] In the semiconductor device according to claim 11,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the second wiring and the third wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[16] 請求の範囲第 11項記載の半導体装置において、 [16] In the semiconductor device according to claim 11,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている  The second insulating film and the second barrier film are formed on the third wiring, and the second insulating film and the second barrier film have an opening reaching the third wiring. Part is formed
ことを特徴とする半導体装置。  A semiconductor device.
[17] 請求の範囲第 1項乃至第 16項のいずれ力 1項に記載の半導体装置において、 前記第 1のバリア膜及び前記第 2のバリア膜の少なくともいずれかは、前記半導体 基板の全面にわたって形成されている 17. The semiconductor device according to claim 1, wherein at least one of the first barrier film and the second barrier film extends over the entire surface of the semiconductor substrate. Formed
ことを特徴とする半導体装置。  A semiconductor device.
[18] 請求の範囲第 4項乃至第 16項のいずれ力 1項に記載の半導体装置において、 前記第 1の配線を覆うように形成され、水素又は水分の拡散を防止する第 5のバリ ァ膜を更に有する [18] The semiconductor device according to any one of [4] to [16], wherein the fifth barrier is formed so as to cover the first wiring and prevents diffusion of hydrogen or moisture. Further having a membrane
ことを特徴とする半導体装置。  A semiconductor device.
[19] 請求の範囲第 1項乃至第 18項のいずれ力 1項に記載の半導体装置において、 前記強誘電体キャパシタを覆うように形成され、水素又は水分の拡散を防止する第 6のノ リア膜を更に有する [19] The semiconductor device according to any one of [1] to [18], wherein the sixth capacitor is formed so as to cover the ferroelectric capacitor and prevents diffusion of hydrogen or moisture. Further having a membrane
ことを特徴とする半導体装置。  A semiconductor device.
[20] 請求の範囲第 1項乃至第 19項のいずれ力 1項に記載の半導体装置において、 前記第 1のバリア膜又は前記第 2のバリア膜は、金属酸化物よりなる ことを特徴とする半導体装置。 [20] The semiconductor device according to any one of [1] to [19], wherein the first barrier film or the second barrier film is made of a metal oxide. A semiconductor device.
[21] 請求の範囲第 20項記載の半導体装置において、  [21] In the semiconductor device according to claim 20,
前記金属酸化物は、酸ィ匕アルミニウム、酸化チタン、又は酸ィ匕タンタルである ことを特徴とする半導体装置。  The semiconductor device is characterized in that the metal oxide is acid aluminum, titanium oxide, or acid tantalum.
[22] 請求の範囲第 1項乃至第 19項のいずれ力 1項に記載の半導体装置において、 前記第 1のノリア膜又は前記第 2のノリア膜は、シリコン窒化膜又はシリコン窒化酸 化膜である [22] The semiconductor device according to any one of [1] to [19], wherein the first noria film or the second noria film is a silicon nitride film or a silicon nitride oxide film. is there
ことを特徴とする半導体装置。  A semiconductor device.
[23] 請求の範囲第 1項乃至第 19項のいずれ力 1項に記載の半導体装置において、 前記第 1のバリア膜は、酸ィ匕アルミニウム膜であり、 [23] The semiconductor device according to any one of [1] to [19], wherein the first barrier film is an aluminum oxide film,
前記第 2のバリア膜は、シリコン窒化膜である  The second barrier film is a silicon nitride film
ことを特徴とする半導体装置。  A semiconductor device.
[24] 請求の範囲第 1項乃至第 19項のいずれ力 1項に記載の半導体装置において、 前記第 1のバリア膜は、酸ィ匕アルミニウム膜であり、 [24] The semiconductor device according to any one of [1] to [19], wherein the first barrier film is an aluminum oxide film,
前記第 2のバリア膜は、吸湿性を有する有機膜である  The second barrier film is a hygroscopic organic film
ことを特徴とする半導体装置。  A semiconductor device.
[25] 請求の範囲第 1項乃至第 24項のいずれ力 1項に記載の半導体装置において、 前記第 1のノリア膜の膜厚及び前記第 2のノリア膜の膜厚は、 50nm以上 lOOnm 未満である [25] The semiconductor device according to any one of [1] to [24], wherein the film thickness of the first noria film and the film thickness of the second noria film are 50 nm or more and less than lOOnm. Is
ことを特徴とする半導体装置。  A semiconductor device.
[26] 請求の範囲第 25項記載の半導体装置において、 [26] In the semiconductor device according to claim 25,
前記第 1のノリア膜の膜厚及び前記第 2のノリア膜の膜厚は、 50nm以上 80nm以 下である  The film thickness of the first noria film and the film thickness of the second noria film are 50 nm or more and 80 nm or less.
ことを特徴とする半導体装置。  A semiconductor device.
[27] 請求の範囲第 1項乃至第 26項のいずれ力 1項に記載の半導体装置において、 前記第 1のバリア膜の直上及び前記第 2のバリア膜の直上の少なくともいずれかに 形成され、エッチングのストツバとなる絶縁膜を更に有する [27] The semiconductor device according to any one of [1] to [26], wherein the force is formed at least one directly above the first barrier film and immediately above the second barrier film, It further has an insulating film that serves as an etching stopper
ことを特徴とする半導体装置。 A semiconductor device.
[28] 請求の範囲第 1項乃至第 27項のいずれ力 1項に記載の半導体装置において、 前記強誘電体膜は、 PbZr Ti O膜、 Pb La Zr Ti O膜、 SrBi (Ta Nb l -X X 3 1 -X X 1 -Y Y 3 2 X 1[28] The semiconductor device according to any one of [1] to [27], wherein the ferroelectric film includes a PbZrTiO film, a PbLaZrTiO film, an SrBi (Ta Nb l − XX 3 1 -XX 1 -YY 3 2 X 1
) O膜、又は Bi Ti O 膜である ) O film or Bi Ti O film
-X 2 9 4 2 12  -X 2 9 4 2 12
ことを特徴とする半導体装置。  A semiconductor device.
[29] 半導体基板上に形成され、下部電極と、前記下部電極上に形成された強誘電体 膜と、前記強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタと、 前記半導体基板上及び前記強誘電体キャパシタ上に形成され、表面が平坦化され た第 1の絶縁膜と、前記第 1の絶縁膜上に形成され、水素又は水分の拡散を防止す る平坦な第 1のバリア膜と、前記第 1のバリア膜上に形成され、表面が平坦化された 第 2の絶縁膜と、前記第 2の絶縁膜上に形成され、水素又は水分の拡散を防止する 平坦な第 2のバリア膜とを有するメモリセル部と、 [29] A ferroelectric capacitor formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film; A first insulating film formed on a semiconductor substrate and on the ferroelectric capacitor and having a flat surface, and a flat first film formed on the first insulating film and preventing diffusion of hydrogen or moisture. 1 barrier film, a second insulating film formed on the first barrier film and having a planarized surface, and formed on the second insulating film to prevent diffusion of hydrogen or moisture. A memory cell portion having a second barrier film;
ボンディッグパッドが形成されたパッド部とを有し、  And a pad portion on which a bonding pad is formed,
前記第 1のバリア膜及び前記第 2のバリア膜の少なくともいずれかは、前記メモリセ ル部及び前記パッド部にわたって形成されている  At least one of the first barrier film and the second barrier film is formed over the memory cell portion and the pad portion.
ことを特徴とする半導体装置。  A semiconductor device.
[30] 半導体基板上に形成され、下部電極と、前記下部電極上に形成された強誘電体 膜と、前記強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタと、 前記半導体基板上及び前記強誘電体キャパシタ上に形成され、表面が平坦化され た第 1の絶縁膜と、前記第 1の絶縁膜上に形成され、水素又は水分の拡散を防止す る平坦な第 1のバリア膜と、前記第 1のバリア膜上に形成され、表面が平坦化された 第 2の絶縁膜と、前記第 2の絶縁膜上に形成され、水素又は水分の拡散を防止する 平坦な第 2のバリア膜とを有するチップ領域と、 [30] A ferroelectric capacitor formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film; A first insulating film formed on a semiconductor substrate and on the ferroelectric capacitor and having a flat surface, and a flat first film formed on the first insulating film and preventing diffusion of hydrogen or moisture. 1 barrier film, a second insulating film formed on the first barrier film and having a planarized surface, and formed on the second insulating film to prevent diffusion of hydrogen or moisture. A chip region having a second barrier film;
前記半導体基板に、前記チップ領域に隣接して設けられたスクライブ部とを有し、 前記第 1のノリア膜及び前記第 2のノリア膜の少なくともいずれかは、前記チップ領 域及び前記スクライブ部にわたつて形成されて 、る  A scribing portion provided adjacent to the chip region on the semiconductor substrate, wherein at least one of the first noria film and the second noria film is provided on the chip region and the scribe portion. Formed
ことを特徴とする半導体装置。  A semiconductor device.
[31] 半導体基板上に、下部電極と、前記下部電極上に形成された強誘電体膜と、前記 強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタを形成する工程 と、 [31] A step of forming a ferroelectric capacitor having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film on a semiconductor substrate. When,
前記半導体基板上及び前記強誘電体キャパシタ上に、第 1の絶縁膜を形成するェ 程と、  Forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor;
前記第 1の絶縁膜の表面を平坦化する工程と、  Planarizing the surface of the first insulating film;
前記第 1の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 1のバリア膜を 形成する工程と、  Forming a flat first barrier film for preventing diffusion of hydrogen or moisture on the first insulating film;
前記第 1のバリア膜上に、第 2の絶縁膜を形成する工程と、  Forming a second insulating film on the first barrier film;
前記第 2の絶縁膜の表面を平坦化する工程と、  Planarizing the surface of the second insulating film;
前記第 2の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 2のバリア膜を 形成する工程と  Forming a flat second barrier film for preventing diffusion of hydrogen or moisture on the second insulating film;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
[32] 請求の範囲第 31項記載の半導体装置の製造方法において、 [32] In the method of manufacturing a semiconductor device according to claim 31,
前記第 1の絶縁膜の表面を平坦化する工程の後、前記第 1のバリア膜を形成する 工程の前に、第 1の熱処理を行う工程を更に有する  A step of performing a first heat treatment after the step of planarizing the surface of the first insulating film and before the step of forming the first barrier film;
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[33] 請求の範囲第 32項記載の半導体装置の製造方法において、 [33] In the method of manufacturing a semiconductor device according to claim 32,
前記第 1の熱処理を行う工程では、少なくとも窒素ガスを用いて発生させたプラズマ 雰囲気にて第 1の熱処理を行うことにより、前記第 1の絶縁膜の表面を窒化する ことを特徴とする半導体装置の製造方法。  In the step of performing the first heat treatment, the surface of the first insulating film is nitrided by performing the first heat treatment in a plasma atmosphere generated using at least nitrogen gas. Manufacturing method.
[34] 請求の範囲第 31項乃至第 33項のいずれか 1項に記載の半導体装置の製造方法 において、 [34] The method for manufacturing a semiconductor device according to any one of claims 31 to 33,
前記第 2の絶縁膜の表面を平坦化する工程の後、前記第 2のバリア膜を形成する 工程の前に、第 2の熱処理を行う工程を更に有する  After the step of planarizing the surface of the second insulating film, the method further includes a step of performing a second heat treatment before the step of forming the second barrier film.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[35] 請求の範囲第 34項記載の半導体装置の製造方法において、 [35] In the method for manufacturing a semiconductor device according to claim 34,
前記第 2の熱処理を行う工程では、少なくとも窒素ガスを用いて発生させたプラズマ 雰囲気にて第 2の熱処理を行うことにより、前記第 2の絶縁膜の表面を窒化する ことを特徴とする半導体装置の製造方法。 In the step of performing the second heat treatment, the surface of the second insulating film is nitrided by performing the second heat treatment in a plasma atmosphere generated using at least nitrogen gas. Manufacturing method.
[36] 請求の範囲第 31項乃至第 35項のいずれか 1項に記載の半導体装置の製造方法 において、 [36] In the method of manufacturing a semiconductor device according to any one of claims 31 to 35,
前記第 1の絶縁膜の表面を平坦化する工程では、 CMP法により前記第 1の絶縁膜 の表面を研磨することにより、前記第 1の絶縁膜の表面を平坦化する  In the step of planarizing the surface of the first insulating film, the surface of the first insulating film is planarized by polishing the surface of the first insulating film by a CMP method.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[37] 請求の範囲第 36項記載の半導体装置の製造方法において、 [37] In the method for manufacturing a semiconductor device according to claim 36,
前記第 1の絶縁膜の表面を平坦化する工程の後、前記第 1のバリア膜を形成する 工程の前に、平坦化された前記第 1の絶縁膜の直上に、平坦な第 3の絶縁膜を形成 する工程を更に有し、  After the step of flattening the surface of the first insulating film, and before the step of forming the first barrier film, a flat third insulating film is formed directly on the flattened first insulating film. A step of forming a film;
前記第 1のバリア膜を形成する工程では、前記第 3の絶縁膜上に前記第 1のバリア 膜を形成する  In the step of forming the first barrier film, the first barrier film is formed on the third insulating film.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[38] 請求の範囲第 31項乃至第 37項のいずれか 1項に記載の半導体装置の製造方法 において、 [38] The method of manufacturing a semiconductor device according to any one of claims 31 to 37,
前記第 2の絶縁膜の表面を平坦化する工程では、 CMP法により前記第 2の絶縁膜 の表面を研磨することにより、前記第 2の絶縁膜の表面を平坦化する  In the step of planarizing the surface of the second insulating film, the surface of the second insulating film is planarized by polishing the surface of the second insulating film by CMP.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[39] 請求の範囲第 38項記載の半導体装置の製造方法において、 [39] In the method for manufacturing a semiconductor device according to claim 38,
前記第 2の絶縁膜の表面を平坦化する工程の後、前記第 2のバリア膜を形成する 工程の前に、平坦化された前記第 2の絶縁膜の直上に、平坦な第 4の絶縁膜を形成 する工程を更に有し、  After the step of planarizing the surface of the second insulating film and before the step of forming the second barrier film, a flat fourth insulating layer is formed directly on the planarized second insulating film. A step of forming a film;
前記第 2のバリア膜を形成する工程では、前記第 4の絶縁膜上に前記第 2のバリア 膜を形成する  In the step of forming the second barrier film, the second barrier film is formed on the fourth insulating film.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[40] 請求の範囲第 31項乃至第 39項のいずれか 1項に記載の半導体装置の製造方法 において、 [40] In the method of manufacturing a semiconductor device according to any one of claims 31 to 39,
前記第 1のノリア膜を形成する工程の後、前記第 1のノリア膜上に、エッチングのス トツパ膜となる第 5の絶縁膜を形成する工程を更に有する ことを特徴とする半導体装置の製造方法。 After the step of forming the first noria film, the method further includes a step of forming a fifth insulating film serving as an etching stopper film on the first noria film. A method for manufacturing a semiconductor device.
請求の範囲第 31項乃至第 40項のいずれか 1項に記載の半導体装置の製造方法 において、  The method for manufacturing a semiconductor device according to any one of claims 31 to 40, wherein:
前記第 2のノ リア膜を形成する工程の後、前記第 2のノ リア膜上に、エッチングのス トツパ膜となる第 6の絶縁膜を形成する工程を更に有する  After the step of forming the second noor film, the method further includes a step of forming a sixth insulating film serving as an etching stopper film on the second noria film.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
PCT/JP2005/011955 2004-07-02 2005-06-29 Semiconductor device and method for manufacturing same WO2006003940A1 (en)

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