CN1993828A - Semiconductor device and method for manufacturing same - Google Patents
Semiconductor device and method for manufacturing same Download PDFInfo
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- CN1993828A CN1993828A CNA2005800266413A CN200580026641A CN1993828A CN 1993828 A CN1993828 A CN 1993828A CN A2005800266413 A CNA2005800266413 A CN A2005800266413A CN 200580026641 A CN200580026641 A CN 200580026641A CN 1993828 A CN1993828 A CN 1993828A
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- 239000010936 titanium Substances 0.000 claims description 27
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- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
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- 238000003475 lamination Methods 0.000 description 28
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- 230000008569 process Effects 0.000 description 22
- 238000004544 sputter deposition Methods 0.000 description 20
- 238000001259 photo etching Methods 0.000 description 19
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- 229910052721 tungsten Inorganic materials 0.000 description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 18
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- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical compound Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Disclosed is a semiconductor device comprising a ferroelectric capacitor (42) formed on a semiconductor substrate (10) and having a lower electrode (36), a ferroelectric film (38) formed on the lower electrode (36) and an upper electrode (40) formed on the ferroelectric film (38); a silicon oxide film (60) formed over the semiconductor substrate (10) and the ferroelectric capacitor (42) and having a planarized surface; a flat barrier film (62) formed on the silicon oxide film (60) via a silicon oxide film (61) for preventing diffusion of hydrogen or moisture; a silicon oxide film (74) formed on the barrier film (62) and having a planarized surface; and a flat barrier film (78) formed on the silicon oxide film (74) via a silicon oxide film (76) for preventing diffusion of hydrogen or moisture.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially relate to a kind of semiconductor device and manufacture method thereof with ferroelectric condenser.
Background technology
In recent years, as the dielectric film of capacitor and use ferroelectric film (ferroelectric film) extremely to gaze at.Used this ferroelectric condenser ferroelectric memory (FeRAM:Ferroelectric RandomAccess Memory: the ferroelectric random memory) be a kind of have can carry out high speed motion, consumed power low, write/read the nonvolatile memory of features such as durability is outstanding, and prediction will have further development from now on.
But ferroelectric condenser has its characteristic easily by from the hydrogen of outside and the character of moisture deterioration.Specifically, the ferroelectric condenser of the FeRAM of the lower electrode that forms by the Pt film for lamination successively, the ferroelectric film that forms by the PZT film, the upper electrode that forms by the Pt film and the standard that constitutes, as everyone knows, if in hydrogen partial pressure is environment about 40Pa (0.3Torr), substrate is heated to temperature about 200 ℃, then almost loses PbZr
1-XTi
XO
3The strong dielectricity of film (PZT film).In addition, well-known, if the state of ferroelectric condenser adsorption moisture or moisture be present in ferroelectric condenser near state under heat-treat, then the strong dielectricity of the ferroelectric film of ferroelectric condenser is by remarkable deterioration.
Because ferroelectric condenser has this character, therefore, in the manufacturing process of FeRAM,, select moisture to produce less as far as possible and the technology of low temperature as the technology that has formed after the ferroelectric condenser.In addition, as the technology of interlayer dielectric being carried out film forming, and select to utilize CVD (the Chemical Vapor Deposition: the chemical vapour deposition (CVD)) film-forming process of method etc. of the few relatively unstrpped gas of the generation that for example used hydrogen.
And then, as preventing that ferroelectric film from being proposed by the technology of hydrogen and moisture deterioration: the technology that forms pellumina in the mode that covers ferroelectric condenser; On the interlayer dielectric that is formed on the ferroelectric condenser, form the technology of pellumina.Pellumina has the function of the diffusion that prevents hydrogen and moisture.Therefore, if according to the technology that proposes, can prevent that then hydrogen and moisture from arriving ferroelectric film, thereby can prevent that ferroelectric condenser is by hydrogen and moisture deterioration.This technology for example is recorded in the patent documentation 1～7.
Patent documentation 1:JP spy opens the 2003-197878 communique
Patent documentation 2:JP spy opens the 2001-68639 communique
Patent documentation 3:JP spy opens the 2003-174145 communique
Patent documentation 4:JP spy opens the 2002-176149 communique
Patent documentation 5:JP spy opens the 2003-100994 communique
Patent documentation 6:JP spy opens the 2001-36026 communique
Patent documentation 7:JP spy opens the 2001-15703 communique
Disclosure of an invention
As mentioned above, ferroelectric condenser has its characteristic easily by from the hydrogen of outside and the character of moisture deterioration.Therefore, in PTHS (the Pressure Temperature HumidityStress) test as one of accelerated life test, FeRAM in the past is difficult to obtain good result of the test.
Usually, PTHS test is based on JEDEC (Joint Electron Device Engineering Council: specification etc. U.S. electronic engineering designs associating association), and be that 135 ℃, humidity are to carry out under 85% the condition in for example temperature.In this PTHS test, if fully do not guarantee the patience and the moisture-proof of the relative hydrogen of FeRAM, then ferroelectric condenser is taken place bad by deterioration.
Up to the present, though propose to have to prevent that ferroelectric condenser is by the technology of the deterioration of hydrogen and moisture, but want to improve FeRAM with ferroelectric condenser etc. semiconductor device the PTHS characteristic and in the PTHS test, obtain fully to be higher than the good result of the test that standards are assert in a large amount of productions, then abundant not enough by present technology.
The objective of the invention is to, provide a kind of patience and moisture-proof to hydrogen outstanding and can suppress the deterioration of ferroelectric condenser characteristic fully and can improve the semiconductor device and the manufacture method thereof of PTHS characteristic.
If according to a viewpoint of the present invention, a kind of semiconductor device then is provided, it has: ferroelectric condenser, and it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film; First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevents the diffusion of hydrogen or moisture.
In addition, if according to other viewpoints of the present invention, a kind of semiconductor device then is provided, it has: memory cell portion, this memory cell portion has: ferroelectric condenser, it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film; First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevents the diffusion of hydrogen or moisture, pad portion, it is formed with joint sheet, and at least one in above-mentioned first barrier film and above-mentioned second barrier film is formed on said memory cells portion and above-mentioned pad portion.
In addition, if according to other other viewpoints of the present invention, a kind of semiconductor device then is provided, it has: chip area, this chip area has: ferroelectric condenser, it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film; First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevent the diffusion of hydrogen or moisture, scribing portion, its adjacent said chip zone and be arranged at above-mentioned semiconductor substrate, in above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on the regional and above-mentioned scribing of said chip portion.
In addition, if according to other other viewpoints of the present invention, a kind of manufacture method of semiconductor device then is provided, and it has: have lower electrode, be formed on ferroelectric film on the above-mentioned lower electrode, be formed on the operation of the ferroelectric condenser of the upper electrode on the above-mentioned ferroelectric film forming on the semiconductor substrate; Reaching the operation that forms first dielectric film on the above-mentioned ferroelectric condenser on the above-mentioned semiconductor substrate; The surface of above-mentioned first dielectric film is carried out the operation of planarization; On above-mentioned first dielectric film, form the operation of the first smooth barrier film of the diffusion that prevents hydrogen or moisture; On above-mentioned first barrier film, form the operation of second dielectric film; The surface of above-mentioned second dielectric film is carried out the operation of planarization; On above-mentioned second dielectric film, form the diffusion prevent hydrogen or moisture the second smooth barrier film operation.
In addition, in " on the substrate " in the application's specification, put down in writing, " on the ferroelectric condenser ", " on the dielectric film ", " on the wiring layer " etc. " on ", except " directly over " the meaning, also comprise the meaning of " top ".
If according to the present invention, then be formed on the semiconductor substrate and have lower electrode, be formed on ferroelectric film on the above-mentioned lower electrode, be formed in the semiconductor device of ferroelectric condenser of the upper electrode on the ferroelectric film having, be formed with: first dielectric film, it is formed on the semiconductor substrate and reaches on the ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on first dielectric film, and prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on second dielectric film, and prevents the diffusion of hydrogen or moisture, therefore, can stop hydrogen and moisture reliably, thereby can prevent reliably that hydrogen and moisture from arriving the ferroelectric film of ferroelectric condenser.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser that causes by hydrogen and moisture can be prevented reliably, thereby the PTHS characteristic of semiconductor device can be improved significantly with ferroelectric condenser.
The simple declaration of accompanying drawing
Fig. 1 is the vertical view of chip structure of the semiconductor device of expression first execution mode of the present invention.
Fig. 2 is the vertical view of regional structure on chip top layer of the semiconductor device of expression first execution mode of the present invention.
Fig. 3 is the cutaway view (one) of structure of the semiconductor device of expression first execution mode of the present invention.
Fig. 4 is the cutaway view (its two) of structure of the semiconductor device of expression first execution mode of the present invention.
Fig. 5 is formed with the vertical view (one) of the scope of barrier film in the semiconductor device of expression first execution mode of the present invention.
Fig. 6 is formed with the vertical view (its two) of the scope of barrier film in the semiconductor device of expression first execution mode of the present invention.
Fig. 7 is the transmission electron microscope photo of observed result of the sog film section of the embedding ferroelectric condenser of expression.
Fig. 8 is the transmission electron microscope photo that expression is formed on the observed result of the pellumina section on the section difference that is produced by ferroelectric condenser.
Fig. 9 is the operation cutaway view (one) that the defective when having formed barrier film on the coating-type dielectric film describes.
Figure 10 is the operation cutaway view (its two) that the defective when having formed barrier film on the coating-type dielectric film describes.
Figure 11 is the operation cutaway view (one) that the other defect when having formed barrier film on the coating-type dielectric film describes.
Figure 12 is the operation cutaway view (its two) that the other defect when having formed barrier film on the coating-type dielectric film describes.
Figure 11 is the operation cutaway view (its three) that the other defect when having formed barrier film on the coating-type dielectric film describes.
Figure 12 is the operation cutaway view (its four) that the other defect when having formed barrier film on the coating-type dielectric film describes.
Figure 15 is the curve chart of expression by the evaluation result of the barrier film of thermal desorption analysis (Thermal Desorption Spectroscopy) method.
Figure 16 is the figure that describes for the defective when forming barrier film in thick relatively mode.
Figure 17 is the figure (one) that the effect for the semiconductor device of first execution mode of the present invention describes.
Figure 18 is the figure (its two) that the effect for the semiconductor device of first execution mode of the present invention describes.
Figure 19 is the figure (its two) that the effect for the semiconductor device of first execution mode of the present invention describes.
Figure 20 is the figure (its three) that the effect for the semiconductor device of first execution mode of the present invention describes.
Figure 21 is the figure (its four) that the effect for the semiconductor device of first execution mode of the present invention describes.
Figure 22 is for the damaged cutaway view that describes that is taken place on the conductor plug that is embedded in the interlayer dielectric that comprises barrier film.
Figure 23 is for the damaged transmission electron microscope photo of observing that is taken place on the conductor plug that is embedded in the interlayer dielectric that comprises barrier film.
Figure 24 is the operation cutaway view (one) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 25 is the operation cutaway view (its two) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 26 is the operation cutaway view (its three) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 27 is the operation cutaway view (its four) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 28 is the operation cutaway view (its five) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 29 is the operation cutaway view (its six) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 30 is the operation cutaway view (its seven) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 31 is the operation cutaway view (its eight) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 32 is the operation cutaway view (its nine) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 33 is the operation cutaway view (its ten) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 34 is the operation cutaway view (its 11) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 35 is the operation cutaway view (its 12) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 36 is the operation cutaway view (its 13) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 37 is the operation cutaway view (its 14) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 38 is the operation cutaway view (its 15) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 39 is the operation cutaway view (its 16) of manufacture method of the semiconductor device of expression first execution mode of the present invention.
Figure 40 is the cutaway view (one) of structure of the semiconductor device of expression second execution mode of the present invention.
Figure 41 is the cutaway view (its two) of structure of the semiconductor device of expression second execution mode of the present invention.
Figure 42 is formed with the vertical view of the scope of barrier film in the semiconductor device of expression second execution mode of the present invention.
Figure 43 is the operation cutaway view (one) of manufacture method of the semiconductor device of expression second execution mode of the present invention.
Figure 44 is the operation cutaway view (its two) of manufacture method of the semiconductor device of expression second execution mode of the present invention.
Figure 45 is the operation cutaway view (its three) of manufacture method of the semiconductor device of expression second execution mode of the present invention.
Figure 46 is the operation cutaway view (its four) of manufacture method of the semiconductor device of expression second execution mode of the present invention.
Figure 47 is the cutaway view (one) of structure of the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 48 is the cutaway view (its two) of structure of the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 49 is formed with the vertical view of the scope of barrier film in the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 50 is the operation cutaway view (one) of manufacture method of the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 51 is the operation cutaway view (its two) of manufacture method of the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 52 is the operation cutaway view (its three) of manufacture method of the semiconductor device of expression the 3rd execution mode of the present invention.
Figure 53 is the cutaway view (one) of structure that expression has the semiconductor device of the FeRAM structure that has been suitable for stacked of the present invention (stack-type) unit.
Figure 54 is the cutaway view (its two) of structure that expression has the semiconductor device of the FeRAM structure that has been suitable for stacked of the present invention unit.
Figure 55 is the cutaway view that is illustrated in the structure of the joint sheet (Bonding pad) when having used the Cu distribution.
The explanation of Reference numeral
10: semiconductor substrate
12: the element separated region
14a, 14b: trap
16: gate insulating film
18: gate electrode
19: dielectric film
20: side wall insulating film
22: source
24: transistor
The 25:SiON film
26: silicon oxide film
27: interlayer dielectric
34: silicon oxide film
36: lower electrode
36a: pellumina
The 36b:Pt film
38: ferroelectric film
40: upper electrode
40a:IrO
XFilm
40b:IrO
YFilm
42: ferroelectric condenser
44: barrier film
46: barrier film
48: silicon oxide film
49: interlayer dielectric
50a, 50b: contact hole
52a, 52b: contact hole
54a, 54b: conductor plug
56: the first metallic wiring layer
56a, 56b, 56c: distribution
58: barrier film
60: silicon oxide film
61: silicon oxide film
62: barrier film
64: silicon oxide film
66: interlayer dielectric
68: contact hole
70: conductor plug
72: the second metallic wiring layer
72a, 72b: distribution
74: silicon oxide film
76: silicon oxide film
78: barrier film
80: silicon oxide film
82: interlayer dielectric
84a, 84b: contact hole
86a, 86b: conductor plug
88: the three metallic wiring layer
88a, 88b: distribution
90: silicon oxide film
92: silicon nitride film
93: stacked film
94: polyimide resin film
96,96a, 96a: peristome
98: photoresist
100: photoresist
102: photoresist
The 104:SiON film
106: photoresist
108: peristome
110: defect part
112: silicon oxide film
114: barrier film
116: barrier film
118: silicon oxide film
120a, 120b: contact hole
The 122:SiON film
210: semiconductor substrate
212: the element separated region
214a, 214b: trap
216: gate insulating film
218: gate electrode
219: silicon oxide film
220: side wall insulating film
222: source
224: transistor
The 225:SiON film
226: silicon oxide film
227: interlayer dielectric
228: barrier film
230a, 230b: contact hole
232a, 232b: conductor plug
The 234:Ir film
236: lower electrode
238: ferroelectric film
240: upper electrode
242: ferroelectric condenser
The 244:SiON film
246: barrier film
248: silicon oxide film
250: barrier film
252: silicon oxide film
253: interlayer dielectric
254a, 54b: contact hole
256a, 256b: conductor plug
258a, 258b: distribution
260,260a, 260b: silicon oxide film
262: barrier film
264: silicon oxide film
265: interlayer dielectric
268: contact hole
270: conductor plug
272: distribution
274: silicon oxide film
276: barrier film
278: silicon oxide film
280a, 280b: distribution trough
282a, 282b:Cu distribution
284: interlayer dielectric
285: distribution trough
The 286:Cu distribution
288: silicon oxide film
289: contact hole
290: conductor plug
292: joint sheet
294: silicon oxide film
296: silicon nitride film
298: polyimide resin film
299,299a, 299b: peristome
300: single exposure zone (Shot)
The 302:FeRAM chip area
304: scribing (scribe) portion
306:FeRAM unit portion
The peripheral circuit portion of 308:FeRAM
310: logical circuit portion
312: the peripheral circuit portion of logical circuit
314: pad (pad) portion
316: boundary portion between scribing portion and pad portion
318: boundary portion between pad portion and circuit part
320: boundary portion between circuit part and circuit part
322: the moisture-proof ring
324: interlayer dielectric
326: wiring layer
328: barrier film
330: interlayer dielectric
332: contact hole
334: conductor plug
336: wiring layer
338: the damaged portion of conductor plug
400: interlayer dielectric
402: lower electrode
404: ferroelectric film
406: upper electrode
408: ferroelectric condenser
The 410:SOG film
412: distribution
414: pellumina
416: interlayer dielectric
418: barrier film
420: photoresist
422a, 422b: contact hole
424: metal film
426: photoresist
428a, 428b: distribution
430: conductor plug
432: interlayer dielectric
434: distribution
436: interlayer dielectric
438: barrier film
440: barrier film
The 442:Al distribution
444: conductor plug
446: contact hole
The best mode that is used to carry out an invention
[first execution mode]
Utilize Fig. 1 to Figure 39, the semiconductor device and the manufacture method thereof of first execution mode of the present invention described.
(semiconductor device)
At first, utilize Fig. 1 to Figure 23, the semiconductor device of present embodiment is described.
At first, the chip structure at the semiconductor device of present embodiment utilizes Fig. 1 and Fig. 2 to describe.Fig. 1 is the vertical view of chip structure of the semiconductor device of expression present embodiment, and Fig. 2 is the vertical view of regional structure on chip top layer of the semiconductor device of expression present embodiment.Fig. 1 (b) is the vertical view of the FeRAM chip area in 1 single exposure zone of expression, and Fig. 1 (a) is the vertical view that amplifies the FeRAM chip area in the presentation graphs 1 (b).Fig. 2 (a) is the vertical view of expression along the regional structure on the chip top layer of the X-X ' line of Fig. 1 (a), and Fig. 2 (b) is the vertical view of expression along the regional structure on the chip top layer of the Y-Y ' line of Fig. 1 (a).
As shown in Figure 1, on semiconductor substrate 10, each single exposure zone 300 is formed with a plurality of FeRAM chip areas 302.Be provided with scribing portion 304 between adjacent FeRAM chip area 302, this scribing portion 304 is divided into the cut-out zone of independent F eRAM chip respectively with each FeRAM chip area 302 a kind of being used for.
In FeRAM chip area 302, the peripheral circuit portion 312 that be respectively arranged with the FeRAM unit portion 306 that is formed with the FeRAM unit, the peripheral circuit portion 308 that is formed with the peripheral circuit of FeRAM, is formed with the logical circuit portion 310 of logical circuit and is formed with the peripheral circuit of logical circuit.In addition, the circumference at FeRAM chip area 302 is provided with the pad portion 314 that is formed with the joint sheet (Bonding Pad) that is used to connect chip circuit and external circuit.In addition,, pad portion 314 can be formed along all limits of FeRAM chip area 302 circumferences of square shape according to the kind of the encapsulation of FeRAM etc., also can only be formed on relatively to one group of limit on.
Shown in Fig. 2 (a), the regional structure on the chip top layer of the X-X ' line in Fig. 1 (a) is: be followed successively by between scribing portion 304, scribing portion and pad portion between boundary portion 316, pad portion 314, pad portion and circuit part between boundary portion 318, FeRAM unit portion 306, circuit part and circuit part between boundary portion 320, logical circuit portion 310, pad portion and circuit part boundary portion 316, scribing portion 304 between boundary portion 318, pad portion 314, scribing portion and pad portion from X side direction X ' side.
Shown in Fig. 2 (b), the regional structure on the chip top layer of the Y-Y ' line in Fig. 1 (a) is: be followed successively by between scribing portion 304, scribing portion and pad portion between boundary portion 316, pad portion 314, pad portion and circuit part between boundary portion 318, FeRAM unit portion 306, circuit part and circuit part between peripheral circuit portion 308, circuit part and the circuit part of boundary portion 320, FeRAM between peripheral circuit portion 312, pad portion and the circuit part of boundary portion 320, logical circuit boundary portion 316, scribing portion 304 between boundary portion 318, pad portion 314, scribing portion and pad portion from Y side direction Y ' side.
Then, at the structure of the semiconductor device of present embodiment, utilize Fig. 3 to Fig. 6 to describe.Fig. 3 and Fig. 4 are the cutaway views of structure of the semiconductor device of expression present embodiment, and Fig. 5 and Fig. 6 are the vertical views that is formed with the scope of barrier film in the semiconductor device of expression present embodiment.In addition, in Fig. 4, direct representation the entire profile structure of FeRAM chip area 302 and scribing portion 304, but in Fig. 3, for convenience of explanation, concentrate and to have represented cross-section structure that the FeRAM chip section 306, peripheral circuit portion 308, the pad portion 314 that constitute FeRAM chip area 302 simplified.
As shown in Figure 3, on the semiconductor substrate 10 that constitutes by for example silicon, be formed with the element separated region 12 of dividing element area.In the semiconductor substrate 10 that is formed with element separated region 12, be formed with trap 14a, 14b.
On the semiconductor substrate 10 that is formed with trap 14a, 14b, clip gate insulating film 16 and be formed with gate electrode (gate wirings) 18.Gate electrode 18 for example has polycrystalline metal silicide (Polycide) structure that on polysilicon film lamination has metal silicide films such as tungsten silicide (tungsten silicide) film.On gate electrode 18, be formed with the dielectric film 19 that forms by silicon oxide film.Sidewall sections at gate electrode 18 and dielectric film 19 is formed with side wall insulating film 20.
Both sides at the gate electrode 18 that is formed with side wall insulating film 20 are formed with source 22.So constitute transistor 24 with gate electrode 18 and source 22.The grid of transistor 24 is long for example to be set to 0.35 μ m, or for example is set to 0.11～0.18 μ m.
On the semiconductor substrate 10 that is formed with transistor 24, thickness is for example arranged is that the SiON film 25 of 200nm is the silicon oxide film 26 of 600nm with for example thickness to lamination successively.So be formed with the interlayer dielectric 27 that lamination SiON film successively 25 and silicon oxide film 26 form.The surface of interlayer dielectric 27 is flattened.
For example being formed with on interlayer dielectric 27, thickness is the silicon oxide film 34 of 100nm.Owing to be formed with silicon oxide film 34 on the interlayer dielectric 27 that is flattened, so silicon oxide film 34 becomes smooth.
On silicon oxide film 34, be formed with the lower electrode 36 of ferroelectric condenser 42.Lower electrode 36 by lamination successively for example thickness be that 20～50nm pellumina 36a and thickness are that the stacked film that the Pt film 36b of 100～200nm forms constitutes.At this, the thickness of Pt film 36b is set to 165nm.
On lower electrode 36, be formed with the ferroelectric film 38 of ferroelectric condenser 42.For example adopting as ferroelectric film 38, thickness is the PbZr of 100～250nm
1-XTi
XO
3Film (PZT film).At this, it is the PZT film of 150nm that ferroelectric film 38 adopts thickness.
On ferroelectric film 38, be formed with the upper electrode 40 of ferroelectric condenser 42.Upper electrode 40 by lamination successively for example thickness be the IrO of 25～75nm
XFilm 40a and thickness are the IrO of 150～250nm
YThe stacked film that film 40b forms constitutes.Herein, IrO
XThe thickness of film 40a is set to 50nm, IrO
YThe thickness of film 40b is set to 200nm.In addition, IrO
YThe ratio of components Y of the oxygen of film 40b is set to and compares IrO
XThe ratio of components X of film 40a is higher.
So constituted the ferroelectric condenser 42 that forms by lower electrode 36, ferroelectric film 38, upper electrode 40.
On the ferroelectric film 38 and on the upper electrode 40, be formed with barrier film 44 to cover the ferroelectric film 38 and the upper surface of upper electrode 40 and the mode of side.As barrier film 44, for example can adopt the aluminium oxide (Al of 20～100nm
2O
3) film.
On the ferroelectric condenser 42 that is covered by barrier film 44 and on the silicon oxide film 34, be formed with barrier film 46.For example adopting as barrier film 46, thickness is the pellumina of 20～100nm.
For example being formed with on barrier film 46, thickness is the silicon oxide film 48 of 1500nm.The surface of silicon oxide film 48 is flattened.Silicon oxide film 48 is for example by formed films of chemical vapour deposition such as CVD method, mocvd methods.
By silicon oxide film 34, barrier film 46, and silicon oxide film 48 constitute interlayer dielectric 49.
At silicon oxide film 48, barrier film 46, silicon oxide film 34, and interlayer dielectric 27, be formed with the contact hole 50a, the 50b that extend to source 22 respectively.In addition, at silicon oxide film 48, barrier film 46, and barrier film 44, be formed with the contact hole 52a that extends to upper electrode 40.In addition, at silicon oxide film 48, barrier film 46, and barrier film 44, be formed with the contact hole 52b that extends to lower electrode 36.
In contact hole 50a, 50b, be formed with lamination successively for example thickness be that Ti film and, for example thickness of 20nm is the barrier metal film (not shown) that the TiN film of 50nm forms.In barrier metal film, the Ti film is to be formed in order to reduce contact resistance, and the TiN film is to be formed for the diffusion of the tungsten that prevents the conductor plug material.Be formed on the barrier metal film of each contact hole described later, also be formed for same purpose.
In being formed with contact hole 50a, the 50b of barrier metal film, embedding respectively have conductor plug 54a, a 54b that is made of tungsten.
On silicon oxide film 48 and in the contact hole 52a, be formed with the distribution 56a that is electrically connected with conductor plug 54a and upper electrode 40.In addition, on silicon oxide film 48 and in the contact hole 52b, be formed with the distribution 56b that is electrically connected with lower electrode 36.In addition, on silicon oxide film 48, be formed with the distribution 56c that is electrically connected with conductor plug 54b.The stacked film that the TiN film that distribution 56a, 56b, 56c (first metallic wiring layer 56) for example are 150nm by lamination thickness successively is the TiN film of 150nm, AlCu alloy film that thickness is 550nm, thickness is 5nm Ti film and thickness forms constitutes.
So, the source 22 of transistor 24 and the upper electrode 40 of ferroelectric condenser 42, be electrically connected by conductor plug 54a and distribution 56a, thereby formation has the 1T1C type memory cell of the FeRAM of a transistor 24 and a ferroelectric condenser 42.In fact, a plurality of memory cell is arranged in the memory cell region of FeRAM chip.
On the silicon oxide film 48 that is formed with distribution 56a, 56b, 56c, be formed with barrier film 58 to cover distribution 56a, the upper surface of 56b, 56c and the mode of side.Adopt for example pellumina of 20nm as barrier film 58.
For example being formed with on barrier film 58, thickness is the silicon oxide film 60 of 2600nm.
The surface of silicon oxide film 60 is flattened.The silicon oxide film 60 that has been flattened remains on distribution 56a, 56b, the 56c with the thickness of for example 1000nm.
For example being formed with on silicon oxide film 60, thickness is the silicon oxide film 61 of 100nm.Because silicon oxide film 61 is formed on the silicon oxide film 60 that has been flattened, so silicon oxide film 61 becomes smooth.
On silicon oxide film 61, be formed with barrier film 62.For example adopting as barrier film 62, thickness is the pellumina of 20～70nm.At this, adopting thickness as barrier film 62 is the pellumina of 50nm.Because barrier film 62 is formed on the smooth silicon oxide film 61, so barrier film 62 becomes smooth.
For example being formed with on barrier film 62, thickness is the silicon oxide film 64 of 50～100nm.At this, the thickness of silicon oxide film 64 is set at 100nm.Etching when silicon oxide film 64 conducts form distribution 72a described later, 72b stops (stopper) film and brings into play function.Barrier film 62 is subjected to the protection of this silicon oxide film 64, and can prevent the etching when forming distribution 72a, 72b and cause the thickness of barrier film 62 to reduce or barrier film 62 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 62.
So, constitute interlayer dielectric 66 by barrier film 58, silicon oxide film 60, silicon oxide film 61, barrier film 62 and silicon oxide film 64.
Be formed with the contact hole 68 that extends to distribution 56c at interlayer dielectric 66.
In contact hole 68, be formed with lamination successively for example thickness be that Ti film and, for example thickness of 20nm is the barrier metal film (not shown) that the TiN film of 50nm forms.In addition, do not form the Ti film and form the barrier metal film that forms by the TiN film and can yet.
In the contact hole 68 that is formed with barrier metal film, embedding have a conductor plug 70 that is made of tungsten.
On interlayer dielectric 66, be formed with distribution 72a.In addition, be formed with the distribution 72b that is electrically connected with conductor plug 70 on the interlayer dielectric 66.The stacked film that the TiN film that distribution 72a, 72b (second metallic wiring layer 72) are 150nm by Ti film that for example thickness is the TiN film of 50nm, AlCu alloy film that thickness is 500nm, thickness is 5nm of lamination successively and thickness forms constitutes.Also can not form the TiN film under the AlCu alloy film.
On the interlayer dielectric 66 and on distribution 72a, the 72b, for example being formed with, thickness is the silicon oxide film 74 of 2200nm.The surface of silicon oxide film 74 is flattened.
For example being formed with on silicon oxide film 74, thickness is the silicon oxide film 76 of 100nm.Owing on the silicon oxide film 74 that is flattened, be formed with silicon oxide film 76, so silicon oxide film 76 becomes smooth.
On silicon oxide film 76, be formed with barrier film 78.For example adopting as barrier film 78, thickness is the pellumina of 20～100nm.At this, adopting thickness as barrier film 78 is the pellumina of 50nm.Because barrier film 78 is formed on the smooth silicon oxide film 76, so barrier film 78 becomes smooth.
For example being formed with on barrier film 78, thickness is the silicon oxide film 80 of 50～100nm.At this, the thickness of silicon oxide film 80 is set at 100nm.Silicon oxide film 80 when forming distribution 88a described later, 88b the etching block film and bring into play function.Barrier film 78 is subjected to the protection of this silicon oxide film 80, and can prevent the etching when forming distribution 88a, 88b and cause barrier film 78 to reduce or barrier film 62 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 78.
So, constitute interlayer dielectric 82 by silicon oxide film 74, silicon oxide film 76, barrier film 78 and silicon oxide film 80.
At interlayer dielectric 82, be formed with the contact hole 84a, the 84b that extend to distribution 72a, 72b respectively.
In contact hole 84a, 84b, be formed with lamination successively for example thickness be that Ti film and, for example thickness of 20nm is the barrier metal film (not shown) that the TiN film of 50nm forms.In addition, do not form the Ti film and form the barrier metal film that forms by the TiN film and can yet.
In being formed with contact hole 84a, the 84b of barrier metal film, embedding conductor plug 86a, the 86b that is made of tungsten that have distributes.
On the embedding interlayer dielectric 82 that conductor plug 86a, 86b arranged.Distribution (joint sheet) 88b that is formed with the distribution 88a that is electrically connected with conductor plug 86a and is electrically connected with conductor plug 86b.Distribution 88a, 88b (the 3rd metallic wiring layer 88) by lamination successively for example thickness be that the stacked film that TiN film that the TiN film of 50nm, AlCu alloy film that thickness is 500nm and thickness are 150nm forms constitutes.In addition, also can not form TiN film under the AlCu alloy film.
On the interlayer dielectric 88 and on distribution 88a, the 88b, for example being formed with, thickness is the silicon oxide film 90 of 100～300nm.At this, the thickness of silicon oxide film 90 is set at 100nm.
For example being formed with on silicon oxide film 90, thickness is the silicon nitride film 92 of 350nm.
So, on the interlayer dielectric 82 and on distribution 88a, the 88b, be formed with the stacked film 93 that lamination silicon oxide film successively 90 and silicon nitride film 92 form.
For example being formed with on silicon nitride film 92, thickness is the polyimide resin film 94 of 2～6 μ m.
On polyimide resin film 94, silicon nitride film 92 and silicon oxide film 90, be formed with the peristome 96 that extends to distribution (joint sheet) 88b.That is, be formed with the peristome 96a that extends to distribution (joint sheet) 88b at silicon nitride film 92 and silicon oxide film 90.Be formed at the zone of the peristome 96a of silicon nitride film 92 and silicon oxide film 90 in comprising of polyimide resin film 94, be formed with peristome 96b.
At distribution (joint sheet) 88b, be electrically connected with external circuit (not shown) by peristome 96.
At this,, utilize Fig. 4 to Fig. 6 to be described in detail at the barrier film in the semiconductor device of present embodiment 62,78.Fig. 4 is that expression is corresponding with the regional structure shown in Fig. 2 (a), the cutaway view of the structure of the semiconductor device of present embodiment.Fig. 5 and Fig. 6 are formed with the vertical view of the scope of barrier film 62,78 in the semiconductor device of expression present embodiment.
As shown in Figure 4, on semiconductor substrate 10 and in FeRAM unit portion 306, logical circuit portion 310, be formed with transistor 24.
On the semiconductor substrate 10 that is formed with transistor 24, be formed with interlayer dielectric 27 all sidedly.
On interlayer dielectric 27 and in FeRAM unit portion 306, be formed with ferroelectric condenser 42.
On the interlayer dielectric 27 that is formed with ferroelectric condenser 42, be formed with interlayer dielectric 49 all sidedly.
On interlayer dielectric 49 and in FeRAM unit portion 306, logical circuit portion 310 and pad portion 314, be formed with first metallic wiring layer 56.First metallic wiring layer 56 in the FeRAM unit portion 306 suitably is electrically connected with upper electrode 40, lower electrode 36 or the transistor 24 of ferroelectric condenser 42 by conductor plug.First metallic wiring layer 56 in the logical circuit portion 310 suitably is electrically connected with transistor 24 by conductor plug.
On the interlayer dielectric 49 that is formed with first metallic wiring layer 56, be formed with interlayer dielectric 66 all sidedly.
As Fig. 4 and shown in Figure 5, when the barrier film 62 that constitutes interlayer dielectric 66 is formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302.That is, barrier film 62 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
On the interlayer dielectric 66 and in FeRAM unit portion 306, logical circuit portion 310 and pad portion 3 14, be formed with second metallic wiring layer 72.Second metallic wiring layer 72 suitably is electrically connected with first metallic wiring layer 56 by conductor plug.
On the interlayer dielectric 66 that is formed with second metallic wiring layer 72, be formed with interlayer dielectric 82 all sidedly.
As Fig. 4 and shown in Figure 6, when the barrier film 78 that constitutes interlayer dielectric 82 is formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302.That is, barrier film 78 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
On the interlayer dielectric 82 and in FeRAM unit portion 306, logical circuit portion 310 and pad portion 314, be formed with the 3rd metallic wiring layer 88.The 3rd metallic wiring layer 88 in the pad portion 314 is joint sheet 88b.The 3rd metallic wiring layer 88 suitably is electrically connected with second metallic wiring layer 72 by conductor plug.
On the interlayer dielectric 82 that is formed with the 3rd metallic wiring layer 88, be formed with stacked film 93.
On stacked film 93, be formed with polyimide resin film 94.
Between scribing portion and pad portion in the interlayer dielectric 27,49,66,82,93 of boundary portion 316, be formed with and be used to suppress the moisture-proof ring 322 of humidity the influence of FeRAM chip.Moisture-proof ring 322 is by being formed on metallic wiring layer in the interlayer dielectric 27,49,82,93, constituting with the same metal level of conductor plug etc.Moisture-proof ring 322 with FeRAM chip area 302 in the mode of not short circuits such as distribution constitute.
So constitute the semiconductor device of present embodiment.
The semiconductor device of present embodiment, be primarily characterized in that, barrier film as the diffusion that prevents hydrogen and moisture, except barrier film 44,46,58, also have: be formed at ferroelectric condenser 42 above first metallic wiring layer 56 ( distribution 56a, 56b, 56c) and second metallic wiring layer 72 ( distribution 72a, 72b) between formed smooth barrier film 62; Formed smooth barrier film 78 between second metallic wiring layer 72 ( distribution 72a, 72b) and the 3rd metallic wiring layer 88 ( distribution 88a, 88b).
In having the semiconductor device of ferroelectric condenser, as the effective means of the deterioration of the electrical characteristic of the ferroelectric condenser that prevents to cause, and can expect above ferroelectric condenser, forming the barrier film that constitutes by the aluminium oxide of the diffusion that prevents hydrogen and moisture etc. by hydrogen and moisture.
At this, when having formed barrier film in the substrates such as interlayer dielectric of the section of having difference or inclination from the teeth outwards, because the spreadability of barrier film is not so good, so can't utilize barrier film fully to prevent the diffusion of hydrogen and moisture.If hydrogen and moisture arrive the ferroelectric film of ferroelectric condenser, then the strong dielectricity of ferroelectric film is reduced or disappear, thereby the electrical characteristic that causes ferroelectric condenser is by deterioration because of hydrogen and moisture.
Defective when being formed with barrier film in the substrate at difference of the section of having from the teeth outwards or the interlayer dielectric that tilts utilizes Fig. 7 to Figure 16 to describe in detail.
For example, as described in patent documentation 1, comprising on the concavo-convex surface that produces owing to wiring layer and ferroelectric condenser etc., forming organic insulating film or SOG (Spin On Glass: spin coated glass) during coating-type dielectric film such as film, be difficult to make the surface of coating-type dielectric film to become smooth.Therefore, can the section of having difference and inclination on the surface of coating-type dielectric film.
Fig. 7 is the transmission electron microscope photo of observed result of the sog film section of the embedding ferroelectric condenser of expression.On the interlayer dielectric 400 of transmission electron microscope photo shown in Figure 7, be formed with the ferroelectric condenser 408 that constitutes by lower electrode 402, ferroelectric film 404, upper electrode 406.Ferroelectric condenser 408 is embedded in sog film 410.On sog film 410, be formed with the distribution 412 that is electrically connected with upper electrode 406.
Can know clearly that from transmission electron microscope photo shown in Figure 7 the air spots of sog film 410 is smooth, and have the section of mitigation poor.
So, when having formed the barrier film that is made of pellumina in the substrate of the surface section of having difference or inclination, the thickness of barrier film becomes inhomogeneous.
For example, Fig. 8 is the transmission electron microscope photo that expression is formed on observed result on the section difference that is produced by ferroelectric condenser, the pellumina section.
Can know clearly at transmission electron microscope photo shown in Figure 8, on the face of upper electrode 406 approximate horizontal, roughly be formed uniformly the pellumina 414 of 50nm.On the other hand, interval on the inclined plane of the side end of upper electrode 406, that clamped with arrow among the figure, more to the below, it is thin more that the thickness of pellumina 414 becomes along the inclined plane.
As mentioned above, when for example having formed barrier film on coating-type dielectric films such as organic insulating film or sog film as described in the patent documentation 1, the inequality of thickness takes place on the thickness of barrier film.The defective of the following stated can take place in this case.
Fig. 9 and Figure 10 are the operation cutaway views that the defective when having formed barrier film on the coating-type dielectric film describes.
At first, on interlayer dielectric 400, form the ferroelectric condenser 408 (with reference to Fig. 9 (a)) that constitutes by lower electrode 402, ferroelectric film 404, upper electrode 406.
Then, on the interlayer dielectric 400 that is formed with ferroelectric condenser 408, form the interlayer dielectric 416 (with reference to Fig. 9 (b)) that constitutes by coating-type dielectric films such as organic insulating film and sog films.Interlayer dielectric 416 is smooth inadequately, and in the surface of interlayer dielectric 416 section of having difference or inclination.
Then, on interlayer dielectric 416, form the barrier film 418 (with reference to Fig. 9 (c)) that constitutes by pellumina or oxidation titanium film etc.If barrier film 418 forms by the method beyond the mocvd method, then compare the thickness attenuation of the barrier film of locating on the inclined plane of interlayer dielectric 416 418 with the horizontal plane of interlayer dielectric 416.
Then, form the formation presumptive area of exposing the contact hole that extends to upper electrode 406, lower electrode 402 by photoetching process and cover other regional photoresists 420 (with reference to Fig. 9 (d)).
Then, photoresist 420 as mask, and is carried out etching to barrier film 418 and interlayer dielectric 416.So, at barrier film 418 and interlayer dielectric 416, form the contact hole 422b (with reference to Figure 10 (a)) that extends to the contact hole 422a of upper electrode 406 and extend to lower electrode 402 respectively.
Then, on whole, be formed for forming the metal film 424 (with reference to Figure 10 (b)) of distribution.
Then, form the formation presumptive area that covers the distribution that is connected with upper electrode 406, lower electrode 402 and expose other regional photoresists 426 (with reference to Fig. 9 (c)) by photoetching process.
Then, photoresist 426 as mask, and is carried out etching to metal film 424.So form: the distribution 428a that constitutes and be connected by metal film 424 with upper electrode 406; And the distribution 428b (with reference to Figure 10 (d)) that constitutes and be connected by metal film 424 with lower electrode 402.
When in order to form distribution 428a, 428b metal film 424 being carried out etching, barrier film 418 also is utilized as the etching block film.Therefore, barrier film 418 is also etched, and its thickness can reduce.At this moment, if because the section difference of substrate or tilt and became uneven is arranged on the thickness of barrier film 418, then the part that approaches at thickness makes the remarkable attenuation of its thickness by etching, and then the situation that barrier film 418 is removed can take place.Its result, barrier film 418 can't be given full play to the function of the diffusion that prevents hydrogen and moisture.
For example, when the thickness of barrier film is set at 100nm, on horizontal plane, be removed the thickness of 50nm by etching, thereby the thickness of barrier film reduces to 50nm, relative therewith, on the inclined plane, take place barrier film by etching be removed damaged.In addition, when the thickness setting of barrier film is 200nm, on horizontal plane, be removed the thickness of 50nm by etching, thereby the thickness of barrier film reduces to 150nm, and is relative therewith, on the inclined plane, thickness reduces to 0～50nm by etching, thus local take place that barrier film has been removed damaged.
In addition, except above-mentioned defective, for example as described in the patent documentation 1, when having formed barrier film on coating-type dielectric films such as organic insulating film or sog film, the defective of the following stated can take place also.
Figure 11 to Figure 14 is the operation cutaway view that the other defect when having formed barrier film on the coating-type dielectric film describes.It is the situation of the barrier film of 50nm that Figure 11 and Figure 12 have represented to form thickness, and it is the situation of the barrier film of 100nm that Figure 13 and Figure 14 have represented to form thickness.
At first, be the situation of the barrier film of 50nm at having formed thickness, utilize Figure 11 and Figure 12 to describe.
At first, on the embedding interlayer dielectric 432 that conductor plug 430 arranged, form distribution 434 (with reference to Figure 11 (a)).
Then, on the interlayer dielectric 432 that is formed with distribution 434, form the interlayer dielectric 436 (with reference to Figure 11 (b)) that constitutes by coating-type dielectric films such as organic insulating film or sog films.The surface of interlayer dielectric 436 is smooth inadequately, thereby in the surperficial segment occurred difference or the inclination of interlayer dielectric 436.
Then, forming thickness on interlayer dielectric 436 is the barrier film 438 (with reference to Figure 11 (c)) of 50nm.
Then, on barrier layer 438, form interlayer dielectric 440 (with reference to Figure 11 (d)).
Figure 12 is the cutaway view that amplifies the barrier film 438 shown in expression Figure 11 (c).As shown in the figure, on the horizontal H of interlayer dielectric 436, the thickness of barrier film 438 is 50nm.On the other hand, at the inclined plane of interlayer dielectric 436 S, in fact the thickness of barrier film 438 becomes below the 20nm.So, when having formed thickness and be the barrier film 438 of 50nm, the spreadability variation, thus become can local attenuation for the thickness of barrier film 438.Therefore, barrier film 438 can't be given full play to the function of the diffusion that prevents hydrogen and moisture.
Then, be the situation of the barrier film of 100nm at having formed thickness, utilize Figure 13 and Figure 14 to describe.
At first, on the embedding interlayer dielectric 432 that conductor plug 430 arranged, form distribution 434 (with reference to Figure 13 (a)).
Then, on the interlayer dielectric 432 that is formed with distribution 434, form the interlayer dielectric 436 (with reference to Figure 13 (b)) that constitutes by coating-type dielectric films such as organic insulating film or sog films.The surface of interlayer dielectric 436 is smooth inadequately, thereby in the surface of interlayer dielectric 436 section of having difference or inclination.
Then, forming thickness on interlayer dielectric 436 is the barrier film 438 (with reference to Figure 13 (c)) of 100nm.
Then, on barrier layer 438, form interlayer dielectric 440 (with reference to Figure 13 (d)).
Figure 14 is the cutaway view that amplifies the barrier film 438 shown in expression Figure 13 (c).As shown in the figure, on the horizontal H of interlayer dielectric 436, the thickness of barrier film 438 is 100nm.On the other hand, in the major part of the inclined plane of interlayer dielectric 436 S, in fact the thickness of barrier film 438 becomes 20～50nm.But, the most precipitous part in the S of inclined plane, the thickness of barrier film 438 becomes below the 20nm.
So, when having formed thickness and be the barrier film 438 of 100nm, be that the situation of 50nm is compared with thickness, spreadability becomes well.But, still exist the thickness of barrier film 438 to become 20nm part following, the thickness attenuation.Therefore, barrier film 438 can't be given full play to the function of the diffusion that prevents hydrogen and moisture.
As mentioned above, if the thickness of barrier film is set at 100nm, though then the thickness on the horizontal plane is 100nm, the damaged of barrier film takes place not form in the part on the inclined plane.In addition, if the thickness of barrier film is set at 200nm, though then the thickness on the horizontal plane is 200nm, the thickness on the inclined plane becomes 50～100nm.
Form situation, and the comparative result between the situation that has formed barrier film in the substrate that has an even surface of barrier film in the substrate at the section difference that exist to relax from the teeth outwards, utilized Figure 15 to describe.Figure 15 is the curve chart of expression by the evaluation result of the barrier film of thermal desorption analysis (Thermal Desorption Spectroscopy, TDS) method.In Figure 15, transverse axis is represented substrate temperature, and the longitudinal axis is represented the hydrionic amount of separating out from test portion.In addition, the figure place of the longitudinal axis of the figure place of the longitudinal axis of Figure 15 (a) and Figure 15 (b) is not both because the size of the area of the test portion of resolving by TDS causes.
There is the situation that has formed barrier film in section poor substrate that relaxes from the teeth outwards in Figure 15 (a) expression.Adopt the test portion of process following steps as test portion: on silicon substrate, form sog film, by sputtering method, on whole, form pellumina then as barrier film by coating process.In Figure 15 (a), mark ● expression does not form the situation of pellumina.Mark △ represents that the thickness of pellumina is the situation of 20nm.Mark represents that the thickness of pellumina is the situation of 50nm.Mark ◇ represents that the thickness of pellumina is the situation of 100nm.
The situation of Figure 15 (b) expression as the barrier layer in the semiconductor device of present embodiment 62,78, in the substrate that has an even surface, formation barrier film.Adopt the test portion of process following steps as test portion: on silicon substrate, form silicon oxide film, by sputtering method, on whole, form pellumina then as barrier film by plasma TEOSCVD method.In Figure 15 (b), mark ● expression does not form the situation of pellumina.Mark △ represents that the thickness of pellumina is the situation of 10nm.Mark represents that the thickness of pellumina is the situation of 20nm.Mark ◇ represents that the thickness of pellumina is the situation of 50nm.Mark zero expression has only the situation of silicon substrate.
Can know clearly from Figure 15 (a), exist from the teeth outwards when having formed barrier film in section poor substrate that relaxes, can't obtain sufficient barrier properties, thereby can't utilize barrier film to prevent the diffusion of hydrogen hydrogen.
Relative therewith, can know clearly from Figure 15 (b), when in the substrate that has an even surface, having formed barrier film, be that the hydrionic amount of separating out under arbitrary situation of 10nm, 20nm, 50nm all significantly is less than the hydrionic amount of separating out when not forming barrier film at thickness.Hence one can see that, when having formed barrier film in the substrate that is having an even surface as the semiconductor device of present embodiment, can obtain the sufficient barrier properties to hydrogen, thereby can utilize barrier film to prevent the diffusion of hydrogen reliably
In addition, to the barrier properties of moisture basically with barrier properties interlock to hydrogen, under the situation that can't obtain, and then also can't obtain barrier properties to moisture to the barrier properties of hydrogen.Though not shown, at by TDS, about the evaluation result that barrier properties carried out to moisture, also obtained with above-mentioned about the same result of evaluation result the barrier properties of hydrogen.In addition, on the viewpoint of the size of material,, therefore,, and need in fully smooth substrate, form barrier film for both all obtain sufficient barrier properties to hydrogen and moisture then because hydrogen is the material littler than water.
When having formed barrier film in the substrate of segment occurred difference or inclination from the teeth outwards, in order to obtain sufficient barrier properties, and need form barrier film with thick relatively thickness to hydrogen and hydrogen.But if form barrier film thick relatively, for example thickness is more than the 100nm, the etching that then can the be used to form contact hole defective of difficulty that becomes.Below, utilize Figure 16 that defective under the situation that forms barrier film thick relatively is described.
Shown in Figure 16 (a), when forming the upper electrode 406 of ferroelectric condenser 408, form barrier film in the interlayer dielectric between upper electrode 406 and Al distribution 442 with conductor plug 444 that Al distribution 442 is connected.At this moment, if the thickness of barrier film is thick relatively, when then being used to form the etching of contact hole 446 of embedding conductor plug 444, the narrowed width of the bottom of contact hole 446, thus contact resistance rises or comes in contact bad.
Figure 16 (b) is the embedding cutaway view that the contact hole 446 of conductor plug 444 is arranged of expression.The width on contact hole 446 tops of Al distribution 442 sides is made as W
t, the width of contact hole 446 bottoms that upper electrode 406 is exposed is made as W
b, with both poor W
t-W
bBe defined as etching skew (etch-shift).When having formed thickness as barrier film and being the pellumina of 100nm, the etching skew becomes 150nm, and contact resistance rises.In addition, when having formed thickness as barrier film and being the pellumina of 200nm, the etching skew becomes 300nm, and loose contact has taken place.
Be described in detail as above institute, for example as described in the patent documentation 1, when on coating-type dielectric films such as organic insulating film or sog film, having formed barrier film, when promptly having formed barrier film in the substrate of segment occurred difference or inclination from the teeth outwards, no matter be to make the thickness relative thin of barrier film or thick relatively, different defectives has all taken place.
And then well-known, usually, the membrane stress of sog film is little, but the residual moisture in the film is very many.Therefore, when adopting sog film as interlayer dielectric, as if the heat that applies in the operation of back more than 250 ℃, then the moisture in the sog film arrives ferroelectric condenser, thereby makes the deterioration in characteristics of ferroelectric condenser.
With respect to formed barrier film in the substrate of this difference of segment occurred from the teeth outwards or inclination, in the semiconductor device of present embodiment, the spreadability of formed barrier film is extremely good on the dielectric film that is flattened.Thereby, utilize this smooth barrier film to stop hydrogen and moisture reliably, thereby can prevent that hydrogen and moisture from arriving the ferroelectric film of ferroelectric condenser.
But, bad etc. when above ferroelectric condenser, only having formed the smooth barrier film of one deck as in the PTHS test, taking place, in rugged environment, can't fully guarantee patience and moisture-proof sometimes to hydrogen.Think this be because: by CMP (Chemical Mechanical Polishing: when cmp) method waits the interlayer dielectric that comes the basalis that becomes smooth barrier film to carry out planarization, section influence that differs from that the little cut (micro scratch) that is subjected to being taken place on the surface owing to interlayer dielectric takes place.Promptly, because it is poor by the section that lip-deep little cut caused that occurs in interlayer dielectric, so the not too good defect part of spreadability also can be arranged on smooth barrier film, utilize smooth barrier film also also can't guarantee fully sometimes to one of the patience of hydrogen and reason of moisture-proof even if think that this defect part just becomes.In fact, it is poor to consider by the section that little cut caused, and thickness is the silicon oxide film of 100nm and for example form after by CMP method etc. basalis being carried out planarization, still, even adopt this method, also can't avoid the influence that is caused by little cut fully.
Figure 17 is the cutaway view that expression has the defect part that is taken place on the formed smooth barrier film in the semiconductor device of ferroelectric condenser.In addition, different with the semiconductor device of present embodiment, in semiconductor device shown in Figure 17, only be formed with the barrier film 78 of one deck as smooth barrier film, and do not form barrier film 62.
As shown in figure 17, on smooth barrier film 78,, and the not too good defect part of spreadability 110 is arranged also because by in the section difference that little cut that the surface took place caused of the dielectric film of its lower floor etc.
Thereby according to the residing environment of semiconductor device, hydrogen and moisture invade the inside of semiconductor device via smooth barrier film 78 defect parts 110.
And then semiconductor device as shown in figure 17 if only be formed with merely the smooth barrier film of one deck, is difficult to then to prevent fully that the hydrogen and the moisture that invade the inside of semiconductor device via defect part 110 from arriving ferroelectric condenser 42.Its result, even smooth barrier film is formed under the situation of top of ferroelectric condenser, if only be formed with the smooth barrier film of one deck merely, then the electrical characteristic of ferroelectric condenser also can deterioration.
Relative therewith, in the semiconductor device of present embodiment, be formed with two-layer smooth barrier film, that is: be formed at ferroelectric condenser 42 above first metallic wiring layer 56 and second metallic wiring layer 72 between formed smooth barrier film 62; Formed smooth barrier film 88 between second metallic wiring layer 72 and the 3rd metallic wiring layer 88.
As Figure 18 and shown in Figure 19, supposing also has the situation that the not too good defect part 110 of spreadability takes place at two-layer smooth barrier film 62,78 in the semiconductor device of present embodiment.In addition, Figure 18 is the cutaway view of structure of the semiconductor device of expression present embodiment, and Figure 19 (b) amplifies the vertical view that expression comprises the zone of the pad portion 314 shown in Figure 19 (a).Be shown schematically in two-layer smooth barrier film 62,78 defect parts that taken place 110 at Figure 18 and Figure 19 (b).
But as shown in figure 18, the probability that defect part 110 takes place on the mutual roughly the same plan position approach of smooth barrier film 62,78 is minimum.Therefore, in the semiconductor device of present embodiment, even hydrogen and moisture invade the inside of semiconductor device via the defect part 110 that occurs in the smooth barrier film 78 that is positioned at the upper strata, hydrogen that also can utilize the smooth barrier film 62 that is positioned at lower floor to interdict reliably to be invaded and moisture arrive ferroelectric condenser 42.
In addition, though detailed mechanism is not clear, but think: by being formed with two- layer barrier film 62,78, thereby the remaining hydrogen that is present in the interlayer dielectric is closed between the two- layer barrier layer 62,78, and can prevent that the remaining hydrogen on the ferroelectric condenser 42 from arriving ferroelectric condenser 42.By this other major reason, also can prevent the deterioration of the electrical characteristic of ferroelectric condenser 42, thereby can improve the PTHS characteristic.
That is, as shown in figure 20, when only being formed with the barrier film 78 of one deck and not forming barrier film 62 as smooth barrier film, the remaining hydrogen on the ferroelectric condenser 42 can arrive ferroelectric condenser 42 easily.Thereby, the very difficult at this moment deterioration that prevents the electrical characteristic of ferroelectric condenser 42 fully.
On the other hand, the semiconductor device of present embodiment as shown in Figure 21 was formed with two-layer barrier film like that at 62,78 o'clock, and the remaining hydrogen in the interlayer dielectric is enclosed between the two-layer barrier film 62,78.Therefore, can prevent that the remaining hydrogen on the ferroelectric condenser 42 from arriving ferroelectric condenser 42.Its result can prevent the deterioration of the electrical characteristic of ferroelectric condenser 42, thereby can improve the PTHS characteristic.
In addition, the principal character of the semiconductor device of present embodiment is that barrier film 62,78 not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.
Relative therewith, in the semiconductor device of in as patent documentation 7, being put down in writing, only be formed with hydrogen barrier layer in FeRAM unit portion.Therefore, in the semiconductor device of in patent documentation 7, being put down in writing, be difficult to prevent that hydrogen and moisture from invading FeRAM unit portion and arriving ferroelectric condenser from the top or the side of FeRAM unit portion.Therefore, if place for a long time in the environment of for example high humility, then the characteristic of ferroelectric condenser is by deterioration.
In the semiconductor device of present embodiment, barrier film 62,78 not only is formed on FeRAM chip area 302 and scribing portion 304, also be formed on simultaneously adjacent FeRAM chip area 302, can prevent reliably that therefore hydrogen and moisture from invading FeRAM unit portion 306 from the top or the side of FeRAM unit portion 306.Thereby, also can prevent reliably owing to long-time deterioration of placing the electrical characteristic of the ferroelectric condenser 42 that causes in the environment of for example high humility.
In addition, in the semiconductor device of present embodiment, be not required to be the spreadability of guaranteeing barrier film 62,78 and relatively heavy back form barrier film 62,78, and can form barrier film 62,78 in relative thin ground.Thereby, when the interlayer dielectric 66,82 that comprises barrier film 62,78 forms contact holes, can the each several part of FeRAM chip area 306 with the etching shift suppression below 70nm.Thus, can suppress the rising of contact resistance.In addition, the reliable formation of fine contact hole is become possibility, thereby can contribute for the miniaturization of semiconductor device.
As mentioned above, in the semiconductor device of present embodiment, since be formed be formed at ferroelectric condenser 42 above first metallic wiring layer 56 and second metallic wiring layer 72 between formed smooth barrier film 62 and between second metallic wiring layer 72 and the 3rd metallic wiring layer 88 formed smooth barrier film 78, therefore can stop hydrogen and moisture reliably, thereby can prevent reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented reliably, thereby the PTHS characteristic of semiconductor device can be improved significantly with ferroelectric condenser.
And then, in the semiconductor device of present embodiment, since smooth barrier film 62,78 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part, therefore can prevent the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture more reliably.
In addition, from the viewpoint of the following stated, it is above and less than 100nm that the thickness of barrier film 62,78 for example should be set at 50nm, and it is above and below the 80nm to be preferably set to 50nm.
At first, from preventing at conductor plug damaged viewpoint to take place, it is above and less than 100nm that the thickness of barrier film 62,78 for example should be set at 40nm, and it is above and below the 80nm to be preferably set to 40nm.At this point, utilize Figure 22 and Figure 23 to describe.
Figure 22 is for the damaged cutaway view that describes that is taken place on the conductor plug that is embedded in the interlayer dielectric that comprises barrier film.The situation of Figure 22 (a) expression barrier film relative thin, the thick relatively situation of Figure 22 (b) expression barrier film.Figure 23 is for the damaged transmission electron microscope photo of observing that is taken place on the conductor plug that is embedded in the interlayer dielectric that comprises barrier film.
Shown in Figure 22 (a) and Figure 22 (b), on interlayer dielectric 324, be formed with wiring layer 326.On the interlayer dielectric 324 that is formed with wiring layer 326, be formed with the interlayer dielectric 330 that comprises smooth barrier film 328.Be formed with at interlayer dielectric 330 and extend to wiring layer 326 contact holes 332.Be embedded with the conductor plug 334 that constitutes by tungsten at contact hole 332.On the embedding interlayer dielectric 330 that conductor plug 334 arranged, be formed with wiring layer 336.
Under the thickness of the barrier film 328 that is made of pellumina was situation below the 80nm, shown in Figure 22 (a), conductor plug 334 was embedded in the contact hole 332 fully, thereby can not take place damaged at conductor plug 334.
On the other hand, surpass under the situation of 80nm at the thickness of the barrier film 328 that is made of pellumina, shown in Figure 22 (b), conductor plug 334 is not embedded in the contact hole 332 fully, thereby takes place damaged at conductor plug 334.Figure 23 (a) and Figure 23 (b) are respectively for the damaged transmission electron microscope photo of observing that is taken place on the conductor plug that is embedded in the interlayer dielectric that comprises barrier film.Confirm following situation:, then have this damaged 338 with high frequency if the thickness of barrier film becomes more than the 100nm.
Therefore, from preventing at conductor plug damaged viewpoint to take place, it is above and less than 100nm that the thickness of barrier film 62,78 for example should be set at 40nm, and it is above and below the 80nm to be preferably set to 40nm.
On the other hand, give full play to the function of the diffusion that prevents hydrogen and moisture in order to make barrier film 62,78, preferably the thickness with barrier film 62,78 is set at for example more than the 50nm.
From as can be known above, it is above and less than 100nm that the thickness of barrier film 62,78 for example should be set at 50nm, and it is above and below the 80nm to be preferably set to 50nm.
(manufacture method of semiconductor device)
Then, at the manufacture method of the semiconductor device of present embodiment, utilize Figure 24 to Figure 39 to describe.In addition, basically utilize the operation cutaway view corresponding to describe below, but also can utilize the manufacturing process of common semiconductor device to be formed on transistor among logical circuitry 310, peripheral circuit Figure 30 8,312 etc., distribution etc. with the cross-section structure of semiconductor device shown in Figure 3.
At first, (LOCal Oxidation of Silicon: method local oxidation of silicon) forms the element separated region 12 of dividing element area on the semiconductor substrate 10 that is made of for example silicon by for example LOCOS.
Then, import dopant impurities, thereby form trap 14a, 14b by ion implantation.
Then, by common transistorized formation method, on element area, form transistor 24 (with reference to Figure 24 (a)) with gate electrode (gate wirings) 18 and source 22.
Then, for example (Chemical Vapor Deposition: chemical vapour deposition (CVD)) method, for example forming on whole, thickness is the SiON film 25 of 200nm by plasma CVD.
Then, by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 26 (with reference to Figure 24 (b)) of 600nm.
So, constitute interlayer dielectric 27 by SiON film 25 and silicon oxide film 26.
Then, by for example CMP method, planarization (with reference to Figure 24 (c)) is carried out on the surface of interlayer dielectric 27.
Then, at nitrous oxide (N
2O) or nitrogen (N
2) environment in carry out for example 650 ℃, 30 minutes heat treatment.
Then, by for example plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 34 (with reference to Figure 25 (a)) of 100nm.
Then, adopting N
2In the isoionic environment that O gas generates, carry out for example 350 ℃, 2 minutes heat treatment.
Then, by for example sputtering method or CVD method, for example forming on whole, thickness is the pellumina 36a of 20～50nm.
Then, by for example RTA (Rapid Thermal Annealing: method rapid thermal annealing), in oxygen atmosphere, heat-treat.Heat treatment temperature for example is made as 650 ℃, and heat treatment time for example was made as 1～2 minute.
Then, by for example sputtering method, for example forming on whole, thickness is the Pt film 36b of 100～200nm.
So, form the stacked film 36 that constitutes by pellumina 36a and Pt film 36b.Stacked film 36 will become the lower electrode of ferroelectric condenser 42.
Then, by for example sputtering method, on whole, form ferroelectric film 38.For example forming as ferroelectric film 38, thickness is the PZT film of 100～250nm.
In addition, at this situation that forms ferroelectric film 38 by sputtering method has been described for example, still, the formation method of ferroelectric film not only is defined in sputtering method.For example, also can wait and form ferroelectric film by sol-gel process (sol-gelmethod), MOD (Metal Organic Deposition) method, mocvd method.
Then, by for example RTA method, in oxygen atmosphere, heat-treat.Heat treatment temperature for example is made as 550～600 ℃, and heat treatment time for example was made as for 60～120 seconds.
Then, for example by sputtering method or mocvd method, for example forming, thickness is the IrO of 25～75nm
XFilm 40a.
Then, in argon and oxygen atmosphere, carry out for example 600～800 ℃, the heat treatment in 10～100 seconds.
Then, for example by sputtering method or mocvd method, for example forming, thickness is the IrO of 150～250nm
YFilm 40b.At this moment, with IrO
YThe ratio of components Y of the oxygen of film 40b is higher than IrO
XThe mode of the ratio of components X of the oxygen of film 40a forms IrO
YFilm 40b.
So, form by IrO
XFilm 40a and IrO
YThe stacked film 40 (with reference to Figure 25 (b)) that film 40b constitutes.Stacked film 40 will become the upper electrode of ferroelectric condenser 42.
Then, for example, on whole, for example form photoresist 98 by spin-coating method.
Then, by photoetching process, photoresist 98 is portrayed as the flat shape of the upper electrode 40 of ferroelectric condenser 42.
Then, photoresist 98 as mask, is carried out etching to stacked film 40.As etching gas, for example adopt Ar gas and Cl
2Gas.So form the upper electrode 40 (with reference to Figure 25 (c)) that constitutes by stacked film.Then, peel off photoresist 98.
Then, for example in oxygen atmosphere, carry out for example 400～700 ℃, 30～120 minutes heat treatment.This heat treatment is to be used to prevent that the surface at upper electrode 40 from unusual heat treatment taking place.
Then, for example by spin-coating method, on whole, form photoresist 100.
Then, by photoetching process, photoresist 100 is portrayed as the flat shape of the ferroelectric film 38 of ferroelectric condenser 42.
Then, photoresist 100 as mask, is carried out etching (with reference to Figure 26 (a)) to ferroelectric film 38.Then, peel off photoresist 100.
Then, in oxygen atmosphere, carry out for example 300～400 ℃, 30～120 minutes heat treatment.
Then, for example form barrier film 44 (Figure 26 (b)) by sputtering method or CVD method.For example forming as barrier film 44, thickness is the pellumina of 20～50nm.
Then, in oxygen atmosphere, carry out for example 400～600 ℃, 30～120 minutes heat treatment.
Then, for example by spin-coating method, on whole, form photoresist 102.
Then, by photoetching process, photoresist 102 is portrayed as the flat shape of the lower electrode 36 of ferroelectric condenser 42.
Then, photoresist 102 as mask, is carried out etching (Figure 26 (c)) to stacked film 44 and stacked film 36.So form the lower electrode 36 that constitutes by stacked film.In addition, barrier film 44 left behind in the mode that covers upper electrode 40 and ferroelectric film 38.Then, peel off photoresist 102.
Then, in oxygen atmosphere, carry out for example 400～600 ℃, 30～120 minutes heat treatment.
Then, for example by sputtering method or CVD method, on whole, form barrier film 46.For example forming as barrier film 46, thickness is the pellumina (with reference to 27 (a)) of 20～100nm.So, the mode of the ferroelectric condenser 42 that is covered by barrier film 44 with further covering forms barrier film 46.
Then, in oxygen atmosphere, carry out for example 500～700 ℃, 30～120 minutes heat treatment.
Then, for example by plasma TEOSCVD method, on whole, form thickness for example and be the silicon oxide film 48 (with reference to Figure 27 (b)) that constitutes by silicon oxide film of 1500nm.
Then, for example, planarization (with reference to Figure 27 (c)) is carried out on the surface of silicon oxide film 48 by the CMP method.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the isoionic environment that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 48, make the membranous variation of silicon oxide film 48 and be difficult for making moisture to enter into the processing of silicon oxide film 48.By this heat treatment, the surface of silicon oxide film 48 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 48.
Then, at silicon oxide film 48, barrier film 46, silicon oxide film 34 and interlayer dielectric 27, form contact hole 50a, the 50b (with reference to Figure 28 (a)) that extends to source 22 by photoetching process and etching.
Then, for example by sputtering method, for example forming on whole, thickness is the Ti film of 20nm.And then, for example by sputtering method, for example forming on whole, thickness is the TiN film of 50nm.So, constitute barrier metal film (not shown) by Ti film and TiN film.
Then, for example by the CVD method, for example forming on whole, thickness is the tungsten film of 500nm.
Then, for example, tungsten film and barrier metal film are ground, till the surface of exposing silicon oxide film 48 by the CMP method.So, conductor plug 54a, the 54b that is made of tungsten is embedded in (with reference to Figure 28 (b)) in contact hole 50a, the 50b respectively.
Then, for example utilizing argon gas to carry out plasma cleans.So, remove and be present in conductor plug 54a, the lip-deep natural oxide film of 54b etc.
Then, for example by the CVD method, for example forming on whole, thickness is the SiON film 104 of 100nm.
Then, by photoetching process and dry ecthing, form the contact hole 52a of the upper electrode 40 that extends to ferroelectric condenser 42 and extend to the contact hole 52a (with reference to Figure 28 (c)) of the lower electrode 36 of ferroelectric condenser 42 at SiON film 104, silicon oxide film 48, barrier film 46 and barrier film 44.
Then, in oxygen atmosphere, carry out for example 400～600 ℃, 30～120 minutes heat treatment.This heat treatment is a kind of being used for to supply with oxygen and the processing that recovers the electrical characteristic of ferroelectric condenser 42 to the ferroelectric film 38 of ferroelectric condenser 42.In addition, though the situation of heat-treating has been described for example in oxygen atmosphere, also can in ozone environment, heat-treat at this.That heat-treats in ozone environment is following, supplies with oxygen also can for the ferroelectric film 38 of capacitor, thereby can recover the electrical characteristic of ferroelectric condenser 42.
Then, remove SiON film 104 by etching.
Then, on whole successively lamination for example thickness be the TiN film of 150nm, the AlCu alloy film that for example thickness is 550nm, the Ti film that for example thickness is 5nm, the TiN film that thickness is 150nm.So, form the electrically conductive film that lamination TiN film, AlCu alloy film, Ti film, TiN film successively form.
Then, by photoetching process and dry ecthing, electrically conductive film is portrayed.The distribution 56c (with reference to Figure 29 (a)) that forms first metallic wiring layer 56, the distribution 56a that promptly is electrically connected, the distribution 56b that is electrically connected with the lower electrode 36 of ferroelectric condenser 42 and be electrically connected like this with conductor plug 54b with the upper electrode 40 and the conductor plug 54a of ferroelectric condenser 42.
Then, in oxygen atmosphere, carry out for example 350 ℃, 30 minutes heat treatment.
Then, for example by sputtering method or CVD method, on whole, form barrier film 58.For example forming as barrier film 58, thickness is the pellumina (with reference to 29 (b)) of 20～70nm.At this, forming thickness as barrier film 58 is the pellumina of 20nm.So, form barrier film 58 to cover distribution 56a, the upper surface of 56b, 56c and the mode of side.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 60 (with reference to Figure 30 (a)) of 2600nm.
Then, for example, planarization (with reference to Figure 30 (b)) is carried out on the surface of silicon oxide film 60 by the CMP method.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 4 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 60, make the membranous variation of silicon oxide film 60 and be difficult for making moisture to enter into the processing of silicon oxide film 60.By this heat treatment, the surface of silicon oxide film 60 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 60.
Then, for example by plasma TEOSCVD method, for example forming on the silicon oxide film 60 that is flattened, thickness is the silicon oxide film 61 of 100nm.Owing to silicon oxide film 61 is formed on the silicon oxide film 60 that has been flattened, so silicon oxide film 61 becomes smooth.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 61, make the membranous variation of silicon oxide film 61 and be difficult for making moisture to enter into the processing of silicon oxide film 61.By this heat treatment, the surface of silicon oxide film 61 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 61.
Then, for example by sputtering method or CVD method, on smooth silicon oxide film 61, form barrier film 62.For example forming as barrier film 62, thickness is the pellumina of 20～70nm.At this, forming thickness as barrier film 62 is the pellumina of 50nm.Owing to barrier film 62 is formed on the smooth silicon oxide film 61, so barrier film 62 becomes smooth.In addition, on the silicon oxide film 60 that the surface has been flattened by the CMP method, sandwich silicon oxide film 61 and form barrier film 62.Thereby, can suppress:, and defect parts take place at barrier film 62 because occur in the lip-deep section difference etc. of silicon oxide film 60 by little cut.
As shown in figure 31, barrier film 62 not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.That is, barrier film 62 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 64 (with reference to Figure 32 (a)) of 100nm.
So, constitute interlayer dielectric 66 by barrier film 58, silicon oxide film 60, silicon oxide film 61, barrier film 62 and silicon oxide film 64.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 4 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 64, make the membranous variation of silicon oxide film 64 and be difficult for making moisture to enter into the processing of silicon oxide film 64.By this heat treatment, the surface of silicon oxide film 64 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 64.
Then, by photoetching process and dry ecthing,, form the contact hole 68 (with reference to Figure 32 (b)) that extends to distribution 56c at silicon oxide film 64, barrier film 62, silicon oxide film 61, silicon oxide film 60 and barrier film 58.
Then, at N
2Carry out for example 350 ℃, 120 minutes heat treatment in the environment.
Then, for example by sputtering method, for example forming on whole, thickness is the TiN film of 50nm.So, constitute barrier metal film (not shown) by the TiN film.
Then, for example by the CVD method, for example forming on whole, thickness is the tungsten film of 500nm.
Then, for example come tungsten film is carried out etching, till the surface of exposing silicon oxide film 64 by EB (Etch Back: eat-back) method.So, the conductor plug 70 that is made of tungsten is embedded in the contact hole 68 (with reference to Figure 33 (a)).
Then, on whole successively lamination for example thickness be the AlCu alloy film of 500nm, the Ti film that for example thickness is 5nm, the TiN film that for example thickness is 150nm.So, form the electrically conductive film that lamination TiN film, AlCu alloy film, Ti film, TiN film successively form.
Then, by photoetching process and dry ecthing, electrically conductive film is portrayed.Thus, form second metallic wiring layer 72, be distribution 72a and the distribution 72b (with reference to Figure 33 (b)) that is electrically connected with conductor plug 70.In the dry ecthing when forming distribution 72a, 72b, silicon oxide film 64 is brought into play function as the etching block film.Barrier film 62 is subjected to the protection of this silicon oxide film 64, and can prevent that etching owing to forming distribution 72a, 72b from reduce the thickness of barrier film 62 or barrier film 62 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 62.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 74 (with reference to Figure 34 (a)) of 2200nm.
Then, for example, planarization (with reference to Figure 34 (b)) is carried out on the surface of silicon oxide film 74 by the CMP method.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 4 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 74, make the membranous variation of silicon oxide film 74 and be difficult for making moisture to enter into the processing of silicon oxide film 74.By this heat treatment, the surface of silicon oxide film 74 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 74.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 76 of 100nm.Owing to silicon oxide film 76 is formed on the silicon oxide film 74 that has been flattened, so silicon oxide film 76 becomes smooth.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 76, make the membranous variation of silicon oxide film 76 and be difficult for making moisture to enter into the processing of silicon oxide film 76.By this heat treatment, the surface of silicon oxide film 76 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 76.
Then, for example by sputtering method or CVD method, on smooth silicon oxide film 76, form barrier film 78.For example forming as barrier film 78, thickness is the pellumina of 20～70nm.At this, forming thickness as barrier film 78 is the pellumina of 50nm.Owing to barrier layer 78 is formed on the smooth silicon oxide film 76, so barrier film 78 becomes smooth.In addition, on the silicon oxide film 74 that the surface has been flattened by the CMP method, sandwich silicon oxide film 76 and form barrier film 78.Thereby, can suppress: because because little cut occurs in the lip-deep section difference etc. of silicon oxide film 74, and at barrier film 78 generation defect parts.
As shown in figure 35, barrier film 78 not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.That is, barrier film 78 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 80 (with reference to Figure 36 (a)) of 100nm.
So, constitute interlayer dielectric 82 by silicon oxide film 74, silicon oxide film 76, barrier film 78 and silicon oxide film 80.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 80, make the membranous variation of silicon oxide film 76 and be difficult for making moisture to enter into the film of silicon oxide film 80.By this heat treatment, the surface of silicon oxide film 80 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 80.
Then, by photoetching process and dry ecthing,, form contact hole 84a, the 84b (with reference to Figure 36 (b)) that extend to distribution 72a, 72b at silicon oxide film 80, barrier film 78, silicon oxide film 76 and silicon oxide film 74.
Then, at N
2Carry out for example 350 ℃, 120 minutes heat treatment in the environment.
Then, for example by sputtering method, for example forming on whole, thickness is the TiN film of 50nm.So, constitute barrier metal film (not shown) by the TiN film.
Then, for example by the CVD method, for example forming on whole, thickness is the tungsten film of 500nm.
Then, for example come tungsten film is carried out etching, till the surface of exposing silicon oxide film 80 by the EB method.So, conductor plug 86a, the 86b that is made of tungsten is embedded in (with reference to Figure 37 (a)) in contact hole 84a, the 84b respectively.
Then, on whole successively lamination for example thickness be the AlCu alloy film of 500nm, the TiN film that for example thickness is 150nm.So, form the electrically conductive film that lamination TiN film, AlCu alloy film, TiN film successively form.
Then, by photoetching process and dry ecthing, electrically conductive film is portrayed.Thus, the distribution 88b (with reference to Figure 37 (b)) that forms the 3rd metallic wiring layer 88, the distribution 88a that promptly is electrically connected and be electrically connected with conductor plug 86b with conductor plug 86a.In the dry ecthing when forming distribution 88a, 88b, silicon oxide film 80 is brought into play function as the etching block film.Barrier film 78 is subjected to the protection of this silicon oxide film 80, and can prevent that etching owing to forming distribution 88a, 88b from reduce the thickness of barrier film 78 or barrier film 78 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 78.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 90 of 100nm.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 90, make the membranous variation of silicon oxide film 90 and be difficult for making moisture to enter into the processing of silicon oxide film 90.By this heat treatment, the surface of silicon oxide film 90 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 90.
Then, for example by the CVD method, for example forming, thickness is the silicon nitride film 92 (with reference to Figure 38 (a)) of 350nm.Silicon nitride film 92 is a kind ofly to be used for blocks moisture and to prevent the film that metallic wiring layer 88,72,56 etc. is corroded by moisture.
Then, for example by spin-coating method, on whole, form photoresist 106.
Then, by photoetching process, form peristome 108 on photoresist 106, this peristome 108 is used to expose the zone that forms the peristome that extends to distribution (joint sheet) 88b at silicon nitride film 92 and silicon oxide film 90.
Then, photoresist 106 as mask, is carried out etching to silicon nitride film 92 and silicon oxide film 90.So, form the peristome 96a (with reference to Figure 38 (b)) that extends to distribution (joint sheet) 88b at silicon nitride film 92 and silicon oxide film 90.Then, peel off photoresist 106.
Then, for example for example forming by spin-coating method, thickness is the polyimide resin film 94 (with reference to Figure 39 (a)) of 2～6 μ m.
Then, by photoetching process, on polyimide resin film 94, form the peristome 96b (with reference to Figure 39 (b)) that extends to distribution (joint sheet) 88b.
So, make the semiconductor device of present embodiment.
(evaluation result)
Carry out PTHS test and estimated the result of PTHS characteristic of the semiconductor device of present embodiment at semiconductor device, describe present embodiment.
In the PTHS test, the FeRAM chip of the semiconductor device of keeping present embodiment under two atmospheric pressure, 121 ℃ the condition of temperature, 100% humidity, and passing through each time point of 168 hours, 336 hours, 504 hours, 504 hours and 672 hours, utilize formed 5 the chip test portions of identical wafer to confirm to have or not the generation bad element to each.In the semiconductor device of the present embodiment of having carried out the PTHS test, the thickness of barrier film 58 is made as 20nm, the thickness of smooth barrier film 62 is made as 50nm, the thickness of smooth barrier film 78 is made as 70nm.
In addition, as a comparative example,, also carried out and above-mentioned same PTHS test for the situation that does not form smooth barrier film 58, promptly for the situation that only is formed with the smooth barrier film of one deck.In the semiconductor device of first comparative example, the thickness of barrier film 58 is made as 70nm, the thickness of smooth barrier film 78 is made as 70nm.In addition, in the semiconductor device of second comparative example, the thickness of barrier film 58 is made as 20nm, the thickness of smooth barrier film 78 is made as 50nm.In addition, the structure of the semiconductor device in first comparative example 1,2 is except this point that does not form smooth barrier film 58, identical with the semiconductor device of present embodiment.
The result of PTHS test is as follows.
At first, in 5 of present embodiment all chip test portions, bad element does not all take place in any test portion for having passed through 168 hours, 336 hours, 504 hours, 504 hours and 672 hours.
On the other hand, in a certain chip test portion in 5 chip test portions of first comparative example, 1 bad element has taken place at the time point that passed through 168 hours, at the time point that has passed through 336 hours, bad element becomes 3, and at the time point that has passed through 504 hours, bad element becomes 10, at the time point that has passed through 672 hours, bad element becomes 18.In addition, in other chip test portion, at the time point that has passed through 168 hours and 336 hours bad element does not take place, but, at the time point that passed through 504 hours 1 bad element has taken place, at the time point that has passed through 672 hours, bad element becomes 26.In other chip test portion, to the time point that has passed through 168 hours and 336 hours bad element not taking place, still, at the time point that passed through 504 hours 22 bad elements have taken place, at the time point that has passed through 672 hours, bad element becomes 62.In 5 chip test portions, even passed through 168 hours, 336 hours, 504 hours, 504 hours and chip test portion that bad element all do not take place in 672 hours has only two.
In addition, in a certain chip test portion in 5 chip test portions of second comparative example, 19 bad elements have taken place at the time point that passed through 168 hours, at the time point that has passed through 336 hours, bad element becomes 34, and at the time point that has passed through 504 hours, bad element becomes 51, at the time point that has passed through 672 hours, bad element becomes 72.In addition, in other chip test portion, bad element does not take place at the time point that passed through 168 hours, but, at the time point that passed through 336 hours 3 bad elements have taken place, at the time point that has passed through 504 hours, bad element becomes 5, at the time point that has passed through 672 hours, bad element becomes 7.In other chip test portion, bad element did not take place in 168 hours having passed through, but, 3 bad elements have taken place at the time point that passed through 336 hours, at the time point that has passed through 504 hours, bad element becomes 113, and at the time point that has passed through 672 hours, bad element becomes 811.In other chip test portion, 106 bad elements have taken place at the time point that passed through 168 hours, at the time point that has passed through 336 hours, bad element becomes 1690, at the time point that has passed through 504 hours, bad element becomes 3253, and at the time point that has passed through 672 hours, bad element becomes 5184.In 5 chip test portions, even passed through 168 hours, 336 hours, 504 hours, 504 hours and chip test portion that bad element all do not take place in 672 hours has only 1.
Can confirm from the result of above-mentioned PTHS test: if according to present embodiment, then can increase substantially the PTHS characteristic of semiconductor device, thereby can fully be higher than a large amount of productions identification standards of PTHS test about FeRAM with ferroelectric condenser.
Confirm in addition: if only form the smooth barrier film of one deck, then can't guarantee sufficient moisture-proof, thereby be difficult to realize to have the raising of PTHS characteristic of the semiconductor device of ferroelectric condenser.
In addition, the test portion that only covers FeRAM portion for only forming the smooth barrier film of one deck has carried out the PTHS test, its result, and it fails to guarantee sufficient moisture-proof.
And then the test portion that covers FeRAM portion and logical circuit portion for only forming the smooth barrier film of one deck has carried out the PTHS test, its result, and it fails to guarantee sufficient moisture-proof.
And then the test portion that covers FeRAM portion, logical circuit portion and pad portion for only forming the smooth barrier film of one deck has carried out the PTHS test, its result, though become a little well, it fails to guarantee sufficient moisture-proof.
And then the test portion that covers FeRAM portion, logical circuit portion, pad portion and scribing portion for only forming the smooth barrier film of one deck has carried out the PTHS test, its result, though become a little well, it fails to guarantee sufficient moisture-proof.
So, if according to present embodiment, then, except barrier film 44,46,58, also have as preventing the barrier film of the diffusion of hydrogen and moisture: be formed at ferroelectric condenser 42 above first metallic wiring layer 56 and second metallic wiring layer 72 between formed smooth barrier film 62; Therefore formed smooth barrier film 78 between second metallic wiring layer 72 and the 3rd metallic wiring layer 88, can stop hydrogen and moisture reliably, thereby can prevent reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented reliably, thereby the PTHS characteristic of semiconductor device can be improved significantly with ferroelectric condenser.
[second execution mode]
At the semiconductor device and the manufacture method thereof of second execution mode of the present invention, utilize Figure 40 to Figure 46 to describe.Figure 40 and Figure 41 are the cutaway views of structure of the semiconductor device of expression present embodiment, Figure 42 is formed with the vertical view of the scope of barrier film in the semiconductor device of expression present embodiment, and Figure 43 to Figure 46 is the operation cutaway view of manufacture method of the semiconductor device of expression present embodiment.In addition, for putting on identical Reference numeral, and omit or simply its explanation with the same inscape of the semiconductor device of first execution mode and manufacture method thereof.
(semiconductor device)
The semiconductor device of the basic structure of the semiconductor device of present embodiment and first execution mode is roughly the same.The semiconductor device of present embodiment is different at following point with the semiconductor device of first execution mode: the semiconductor device of present embodiment also has at the formed barrier film 114 in the top of the 3rd metallic wiring layer 88 ( distribution 88a, 88b).
That is, as shown in figure 40, on the interlayer dielectric 82 and on distribution 88a, the 88b, for example being formed with, thickness is the silicon oxide film 112 of 1500nm.The surface of silicon oxide film 112 for example is flattened by the CMP method after it forms, and the silicon oxide film 112 on distribution 88b is the thickness of residual 350nm for example.
On the silicon oxide film 112 that has been flattened, be formed with barrier film 114.For example adopting as barrier film 114, thickness is the pellumina of 20～70nm.Because barrier film 114 is formed on the silicon oxide film 112 that has been flattened, so that barrier film 114 becomes is smooth.
Same with barrier film 44,46,58,62,78, barrier film 114 is a kind of films with function of the diffusion that prevents hydrogen and moisture.And then barrier film 114 becomes smoothly owing to being formed on the silicon oxide film 112 that has been flattened, and same and barrier film 44,46,58 is compared with barrier film 62,78, is formed with extremely good spreadability.Thereby, utilize this smooth barrier film 114 and can prevent the diffusion of hydrogen and moisture more reliably.In addition, in fact, barrier film 114 is same with barrier film 62,78, not only has been formed on assortment and has had a FeRAM unit portion 306 of a plurality of memory cell of ferroelectric condenser 42, and be formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302 simultaneously.For this point, narration more later on.
For example being formed with on barrier film 114, thickness is the silicon oxide film 90 of 50～150nm.Silicon oxide film 90 when forming not shown distribution the etching block film and bring into play function.Barrier film 114 is subjected to the protection of this silicon oxide film 90, and can prevent that etching owing to forming distribution from reduce the thickness of barrier film 114 or barrier film 114 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 62.
For example being formed with on silicon oxide film 90, thickness is the silicon nitride film 92 of 350nm.
For example being formed with on silicon nitride film 92, thickness is the polyimide resin film 94 of 3～6 μ m.
At polyimide resin film 94, silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112, be formed with the peristome 96 that extends to distribution (joint sheet) 88b.That is,, be formed with the peristome 96a that extends to distribution (joint sheet) 88b at silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112.Be formed at the zone of the peristome 96a of silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112 in comprising of polyimide resin film 94, be formed with peristome 96b.
As Figure 41 and shown in Figure 42, barrier film 114 is same with barrier film 62,78, not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.That is, barrier film 114 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
So, the semiconductor device of present embodiment, be primarily characterized in that, barrier film as the diffusion that prevents hydrogen and moisture, except barrier film 44,46,58, also have: be formed at ferroelectric condenser 42 above first metallic wiring layer 56 ( distribution 56a, 56b, 56c) and second metallic wiring layer 72 ( distribution 72a, 72b) between formed smooth barrier film 62; Formed smooth barrier film 78 between second metallic wiring layer 72 ( distribution 72a, 72b) and the 3rd metallic wiring layer 88 ( distribution 88a, 88b); At the formed smooth barrier film 114 in the top of the 3rd metallic wiring layer 88 ( distribution 88a, 88b).
In the semiconductor device of present embodiment, on except being formed with the smooth barrier film 62,78 in the semiconductor device of first execution mode, also above the 3rd metallic wiring layer 88, be formed with smooth barrier film 114, therefore can stop hydrogen and moisture more reliably, thereby can prevent more reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented more reliably, thereby the PTHS characteristic of semiconductor device can be improved significantly with ferroelectric condenser.
And then, in the semiconductor device of present embodiment, since smooth barrier film 62,78,114 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part, therefore can prevent the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture more reliably.
(manufacture method of semiconductor device)
Then, at the manufacture method of the semiconductor device of present embodiment, utilize Figure 43 to Figure 46 to describe.
At first, carrying out to the same mode of the manufacture method of the semiconductor device of first execution mode shown in Figure 37, be formed into the structure till the 3rd metallic wiring layer ( distribution 88a, 88b) with Figure 24.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 112 (with reference to Figure 43 (a)) of 1500nm.
Then, for example, planarization (with reference to Figure 43 (b)) is carried out on the surface of silicon oxide film 112 by the CMP method.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 4 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 112, make the membranous variation of silicon oxide film 112 and be difficult for making moisture to enter into the processing of silicon oxide film 112.By this heat treatment, the surface of silicon oxide film 112 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 112.
Then, for example by sputtering method or CVD method, on the silicon oxide film 112 that has been flattened, form barrier film 114.For example forming as barrier film 114, thickness is the pellumina of 20～70nm.Owing to barrier film 114 is formed on the silicon oxide film 112 that has been flattened, so barrier film 114 becomes smooth.
As shown in figure 44, barrier film 114 not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.That is, barrier film 114 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 90 of 100nm.
Then, using N
2O gas or N
2Carry out for example 350 ℃, 2 minutes heat treatment in the plasma ambient that gas takes place.When this heat treatment is a kind of moisture that is used for removing silicon oxide film 90, make the membranous variation of silicon oxide film 90 and be difficult for making moisture to enter into the processing of silicon oxide film 90.By this heat treatment, the surface of silicon oxide film 90 is by nitrogenize, thereby formed SiON film (not shown) on the surface of silicon oxide film 90.
Then, for example by the CVD method, for example forming, thickness is the silicon nitride film 92 (with reference to Figure 45 (a)) of 350nm.Silicon nitride film 92 is a kind ofly to be used for blocks moisture and to prevent the film that metallic wiring layer 88,72,56 etc. is corroded by moisture.
Then, for example, on whole, for example form photoresist 106 by spin-coating method.
Then, pass through photoetching process, form peristome 108 on photoresist 106, this peristome 108 is used to expose the zone that forms the peristome that extends to distribution (joint sheet) 88b at silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112.
Then, photoresist 106 as mask, is carried out etching to silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112.So, form the peristome 96a (with reference to Figure 45 (b)) that extends to distribution (joint sheet) 88b at silicon nitride film 92, silicon oxide film 90, barrier film 114 and silicon oxide film 112.Then, peel off photoresist 106.
Then, for example by spin-coating method, for example forming, thickness is the polyimide resin film 94 (with reference to Figure 46 (a)) of 3～6 μ m.
Then, by photoetching process, on polyimide resin film 94, form the peristome 96b (with reference to Figure 46 (b)) that extends to distribution (joint sheet) 88b via peristome 96a.
So, make the described semiconductor device of present embodiment.
So, if according to present embodiment, then, except barrier film 44,46,58, also have as preventing the barrier film of the diffusion of hydrogen and moisture: be formed at ferroelectric condenser 42 above first metallic wiring layer 56 and second metallic wiring layer 72 between formed smooth barrier film 62; Formed smooth barrier film 78 between second metallic wiring layer 72 and the 3rd metallic wiring layer 88; Therefore formed smooth barrier film 114 above the 3rd metallic wiring layer 88, can stop hydrogen and moisture more reliably, thereby can prevent reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented more reliably, thereby the PTHS characteristic of semiconductor device can be improved more significantly with ferroelectric condenser.
[the 3rd execution mode]
At the semiconductor device and the manufacture method thereof of the 3rd execution mode of the present invention, utilize Figure 47 to Figure 52 to describe.Figure 47 and Figure 48 are the cutaway views of structure of the semiconductor device of expression present embodiment, Figure 49 is formed with the vertical view of the scope of barrier film in the semiconductor device of expression present embodiment, and Figure 50 to Figure 52 is the operation cutaway view of manufacture method of the semiconductor device of expression present embodiment.In addition, for putting on identical Reference numeral, and omit or simply its explanation with the same inscape of the semiconductor device of first execution mode and manufacture method thereof.
(semiconductor device)
The semiconductor device of the basic structure of the semiconductor device of present embodiment and first execution mode is roughly the same.The semiconductor device of present embodiment is different at following point with the semiconductor device of first execution mode: between ferroelectric condenser 42 and first metallic wiring layer 56 ( distribution 56a, 56b, 56c), the semiconductor device of present embodiment also has smooth barrier film 116.
That is, as shown in figure 47, on the embedding silicon oxide film 48 that conductor plug 50a, 50b arranged, be formed with barrier film 1 16.For example adopting as barrier film 116, thickness is the pellumina of 20～70nm.At this, silicon oxide film 48 is flattened, and barrier film 116 is formed on the silicon oxide film 48 that has been flattened, so barrier film 116 becomes smooth.
Same with barrier film 44,46,58,62,78, barrier film 116 is a kind of films with function of the diffusion that prevents hydrogen and moisture.And then barrier film 116 becomes smoothly owing to being formed on the silicon oxide film 48 that has been flattened, and therefore, same and barrier film 44,46,58 is compared with barrier film 62,78, is formed with extremely good spreadability.Thereby, utilize this smooth barrier film 116 can prevent the diffusion of hydrogen and moisture more reliably.In addition, in fact, barrier film 116 is same with barrier film 62,78, not only has been formed on assortment and has had a FeRAM unit portion 306 of a plurality of memory cell of ferroelectric condenser 42, and be formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302 simultaneously.For this point, narration more later on.
For example being formed with on barrier film 116, thickness is the silicon oxide film 118 of 100nm.Silicon oxide film 118 when forming distribution 56a described later, 56b, 56c the etching block film and bring into play function.Barrier film 116 is subjected to the protection of this silicon oxide film 118, and can prevent that etching owing to forming distribution 56a, 56b, 56c from reduce the thickness of barrier film 116 or barrier film 116 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 116.
By silicon oxide film 34, barrier film 46, and silicon oxide film 48, barrier film 116 and silicon oxide film 118 constituted interlayer dielectric 49.
At silicon oxide film 118, barrier film 116, silicon oxide film 48, barrier film 46 and barrier film 44, be formed with the contact hole 52a that extends to upper electrode 40.In addition, at silicon oxide film 118, barrier film 116, silicon oxide film 48, barrier film 46, and barrier film 44, be formed with the contact hole 52b that extends to lower electrode 36.
And then, at silicon oxide film 118 and barrier film 116, be formed with the contact hole 120a that extends to conductor plug 54a.In addition, at silicon oxide film 118 and barrier film 116, be formed with the contact hole 120b that extends to conductor plug 54b.
On silicon oxide film 118 and in the contact hole 52a and in the contact hole 120a, be formed with the distribution 56a that is electrically connected with conductor plug 54a and upper electrode 40.In addition, on silicon oxide film 118 and in the contact hole 52b, be formed with the distribution 56b that is electrically connected with lower electrode 36.In addition, on silicon oxide film 118 and in the contact hole 120b, be formed with the distribution 56c that is electrically connected with conductor plug 54b.
As Figure 48 and shown in Figure 49, barrier film 116 is same with barrier film 62,78, when not only being formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302.That is, barrier film 116 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 3 16, pad portion and circuit part.
So, the semiconductor device of present embodiment, be primarily characterized in that, barrier film as the diffusion that prevents hydrogen and moisture, except barrier film 44,46,58, also have: ferroelectric condenser 42 and be formed at ferroelectric condenser 42 above first metallic wiring layer 56 ( distribution 56a, 56b, 56c) between formed smooth barrier film 116; Formed smooth barrier film 62 between first metallic wiring layer 56 ( distribution 56a, 56b, 56c) and second metallic wiring layer 72 ( distribution 72a, 72b); Formed smooth barrier film 78 between second metallic wiring layer 72 ( distribution 72a, 72b) and the 3rd metallic wiring layer 88 ( distribution 88a, 88b).
In the semiconductor device of present embodiment, the smooth barrier film 62,78 in the semiconductor device that is formed with first execution mode, also ferroelectric condenser 42 and be formed at ferroelectric condenser 42 above first metallic wiring layer 56 between be formed with smooth barrier film 116, therefore, can stop hydrogen and moisture more reliably, thereby can prevent more reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented more reliably, thereby the PTHS characteristic of semiconductor device can be improved more significantly with ferroelectric condenser.
And then, in the semiconductor device of present embodiment, since smooth barrier film 62,78,116 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part, therefore can prevent the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture more reliably.
(manufacture method of semiconductor device)
Then, at the manufacture method of the semiconductor device of present embodiment, utilize Figure 50 to Figure 52 to describe.
At first, carrying out, be formed into the structure (with reference to Figure 50 (a)) till conductor plug 54a, the 54b with the same mode of the manufacture method of the semiconductor device of first execution mode shown in Figure 24 to Figure 27, Figure 28 (a) and Figure 28 (b).
Then, for example utilizing argon gas to carry out plasma cleans.So, remove and be present in conductor plug 54a, the lip-deep natural oxide film of 54b etc.
Then, for example by sputtering method or CVD method, on the embedding silicon oxide film 48 that conductor plug 54a, 54b arranged, form barrier film 116.For example forming as barrier film 114, thickness is the pellumina of 20～70nm.Silicon oxide film 48 is flattened, and barrier film 116 is formed on the silicon oxide film 48 that has been flattened, so barrier film 116 becomes smooth.
Shown in Figure 51, barrier film 116 not only is formed on FeRAM chip area 302 and scribing portion 304, also is formed on adjacent FeRAM chip area 302 simultaneously.That is, barrier film 116 be formed on peripheral circuit portion 308, logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion 312, pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
Then, for example by plasma TEOSCVD method, for example forming on whole, thickness is the silicon oxide film 118 (with reference to Figure 50 (b)) of 100nm.
Then, by photoetching process and dry ecthing, form contact hole 120a, the 120b (with reference to Figure 50 (c)) that extends to conductor plug 54a, 54b at silicon oxide film 118 and barrier film 116.
Then, for example by the CVD method, for example forming on whole, thickness is the SiON film 122 (with reference to Figure 52 (a)) of 100nm.
Then, by photoetching process and dry ecthing, form the contact hole 52a of the upper electrode 40 that extends to ferroelectric condenser 42 and extend to the contact hole 52a (with reference to Figure 52 (b)) of the lower electrode 36 of ferroelectric condenser 42 at SiON film 122, silicon oxide film 118, barrier film 116, silicon oxide film 48, barrier film 46 and barrier film 44.
Then, in oxygen atmosphere, carry out for example 500 ℃, 60 minutes heat treatment.This heat treatment is a kind of being used for to supply with oxygen and the processing that recovers the electrical characteristic of ferroelectric condenser 42 to the ferroelectric film 38 of ferroelectric condenser 42.
Then, remove SiON film 122 by etching.
Then, on whole successively lamination for example thickness be the TiN film of 150nm, the AlCu alloy film that for example thickness is 550nm, the Ti film that for example thickness is 5nm, the TiN film that for example thickness is 150nm.So, form the electrically conductive film that lamination TiN film, AlCu alloy film, Ti film, TiN film successively form.
Then, by photoetching process and dry ecthing, electrically conductive film is portrayed.The distribution 56c (with reference to Figure 52 (c)) that forms first metallic wiring layer 56, the distribution 56a that promptly is electrically connected, the distribution 56b that is electrically connected with the lower electrode 36 of ferroelectric condenser 42 and be electrically connected like this with conductor plug 54b with the upper electrode 40 and the conductor plug 54a of ferroelectric condenser 42.In the dry ecthing when forming distribution 56a, 56b, 56c, silicon oxide film 118 is brought into play function as the etching block film.Barrier film 118 is subjected to the protection of this silicon oxide film 118, and can prevent that etching owing to forming distribution 56a, 56b, 56c from reduce the thickness of barrier film 118 or barrier film 118 is removed.Thus, can prevent the diffusion function deterioration of the hydrogen and the moisture of barrier film 118.
After this operation is identical to the manufacture method of the semiconductor device of first execution mode shown in Figure 39 with Figure 29 (b), therefore omits its explanation.
So, if according to present embodiment, then, except barrier film 44,46,58, also have as preventing the barrier film of the diffusion of hydrogen and moisture: ferroelectric condenser 42 and be formed at ferroelectric condenser 42 above first metallic wiring layer 56 between formed smooth barrier film 116; Formed smooth barrier film 62 between first metallic wiring layer 56 and second metallic wiring layer 72; Therefore formed smooth barrier film 78 between second metallic wiring layer 72 and the 3rd metallic wiring layer 88, can stop hydrogen and moisture more reliably, thereby can prevent more reliably that hydrogen and moisture from arriving the ferroelectric film 38 of ferroelectric condenser 42.Thus, the deterioration of the electrical characteristic of the ferroelectric condenser 42 that causes by hydrogen and moisture can be prevented more reliably, thereby the PTHS characteristic of semiconductor device can be improved more significantly with ferroelectric condenser.
In addition, in the present embodiment, the situation that forms barrier film 116 after forming conductor plug 54a, 54b again has been described, but also can before forming conductor plug 54a, 54b, have formed barrier film 116.
Specifically, at first, with the same mode of manufacture method of the semiconductor device of first execution mode shown in Figure 24 to Figure 27 (c), be formed into the structure till the silicon oxide film 48 that by CMP method surface has been flattened.
Then, form barrier film 116 on the silicon oxide film 48 that has been flattened on the surface by the CMP method.
Then, for example forming on barrier film 116, thickness is the silicon oxide film of 100nm.
Then, on the silicon oxide film on the barrier film 116, barrier film 116, silicon oxide film 48, barrier film 46, silicon oxide film 34 and interlayer dielectric 27, form the contact hole 50a, the 50b that extend to source 22.
Then, form conductor plug 54a, the 54b that is embedded in contact hole 50a, 50b.
So, can before forming conductor plug 50a, 50b, form barrier film 116.
[distortion execution mode]
The present invention not only is defined in above-mentioned execution mode, and can carry out various distortion.
For example, in the above-described embodiment, for example understand the situation that adopts the PZT film as ferroelectric film 38, but ferroelectric film 38 not only is defined in the PZT film, and also can suitably adopts other all ferroelectric film.For example, as ferroelectric film 38, also can adopt Pb
1-XLa
XZr
1-YTi
YO
3Film (plzt film), SrBi
2(Ta
XNb
1-X)
2O
9Film, Bi
4Ti
2O
12Film etc.
In addition, in the above-described embodiment, constitute lower electrode 36, but the material that constitutes the conductor mould etc. of lower electrode 36 not only is defined in this material by the stacked film of pellumina 36a and Pt film 36b.For example, also can be by Ir film, IrO
2Film, Ru film, RuO
2Film, SrRuO (Strontium RutheniumOxide) film (sro film), Pd film constitute lower electrode 38.
In addition, in the above-described embodiment, though by IrO
XFilm 40a and IrO
YThe stacked film of film 40b constitutes upper electrode 40, but the material of the conductor mould of formation upper electrode 40 not only is defined in this material.For example, also can be by Ir film, Ru film, RuO
2Film, sro film, Pd film constitute upper electrode 40.
In addition, in the above-described embodiment, about smooth barrier film, in the first embodiment, at between first metallic wiring layer 56 and second metallic wiring layer 72, forming barrier film 62, and the situation that forms barrier film 78 between second metallic wiring layer 72 and the 3rd metallic wiring layer 88 is illustrated, and, in second execution mode, at except barrier film 62, the situation that also forms barrier film 114 outside 78 above the 3rd metallic wiring layer 88 is illustrated, and, in the 3rd execution mode, except barrier film 62, the situation that also forms barrier film 116 outside 78 between the ferroelectric condenser 42 and first metallic wiring layer 56 is illustrated, still, formed barrier film 62,78,114,116 combination not only is defined in illustrated in the above-described embodiment situation.About smooth barrier film, as long as be formed with two-layer at least in the barrier film 62,78,114,116, also can form 3 layers in the barrier film 62,78,114,116, or form in the barrier film 62,78,114,116 all 4 layers.In addition, also can be according to the number of plies of formed metallic wiring layer on semiconductor substrate 10 etc., and form more smooth barrier film.At this moment, as described in the first embodiment, it is above and less than 100nm that the thickness of smooth barrier film for example will be set at 50nm, and it is above and below the 80nm to be preferably set to 50nm.
In addition, viewpoint from the deterioration of the electrical characteristic that prevents ferroelectric condenser effectively, preferably, at first should between the metallic wiring layer of the superiors under joint sheet and the joint sheet, be formed with smooth barrier film, and between other metallic wiring layer, be formed with other smooth barrier film.
In addition, in the above-described embodiment, for example understand the situation that adopts pellumina as barrier film, but barrier film not only is defined in pellumina.Can suitably adopt the function with the diffusion that prevents hydrogen or moisture film and as barrier film.As barrier film, can suitably adopt the film that for example constitutes by metal oxide.As the barrier film that constitutes by metal oxide, can adopt the film that for example constitutes by tantalum oxide or titanium oxide etc.In addition, barrier film not only is defined in the film that is made of metal oxide.For example, also can adopt silicon nitride film (Si
3N
4Film) or silicon oxynitride film (SiON film) etc. and as barrier film.In addition, also can adopt to have hygroscopic organic membrane and, as coating-type oxide-film or the resin molding that constitutes by polyimides, poly-arylene (PolyArylene), polyarylether (PolyArylene Ethers), benzocyclobutene etc. as barrier film.
In addition, in the above-described embodiment, illustrated that formed all barrier films adopt the situation of the barrier film that is made of same material, but as described below, also can suitably adopt the barrier film that constitutes by different materials.
For example, in the semiconductor device of first or second execution mode, the barrier film 62 that forms as the most close ferroelectric condenser 42 sides in smooth barrier film 62,78,114, and when can adopt pellumina, as formed barrier film 78 or barrier film 114 above barrier film 62, and also can adopt silicon nitride film.In addition, also can for example on pellumina, form oxidation titanium film.
In addition, in the semiconductor device of second execution mode, as formed smooth barrier film 62,78 below the 3rd metallic wiring layer 88, and when can adopt inoranic membranes such as the film that constitutes by metal oxides such as pelluminas or silicon nitride film, as the top that is formed on the 3rd metallic wiring layer 88 and be formed with the smooth barrier film 114 of the peristome 96b that extends to distribution (joint sheet) 88b, has hygroscopic organic membrane and also can adopt.
In addition, in the above-described embodiment, for example understand the situation that forms silicon oxide film as the dielectric film that constitutes interlayer dielectric, still, also can replace silicon oxide film and form various dielectric films.
In addition, in the above-described embodiment, for example understand the situation of utilizing the CMP method as the method for planarization is carried out on the surface of the dielectric film that constitutes interlayer dielectric, still, the method to planarization is carried out on the surface of dielectric film not only is defined in the CMP method.For example, also can come planarization is carried out on the surface of dielectric film by etching.As etching gas, can adopt for example Ar gas.
In addition, in the above-described embodiment, for example understand the situation of the 3 layers of metallic wiring layer forming circuit on semiconductor substrate 10 that utilizes first metallic wiring layer 56, second metallic wiring layer 72 and the 3rd metallic wiring layer 88, but the number of plies that constitutes the metallic wiring layer of the circuit on the semiconductor substrate 10 not only is defined in 3 layers.According to the design of the circuit that on semiconductor substrate 10, constitutes, also can suitably set the number of plies of metallic wiring layer.
In addition, in the above-described embodiment, for example understand the situation of the memory cell that is formed with 1T1C type, but the structure of memory cell not only is defined in the 1T1C type with a transistor 24 and a ferroelectric condenser 42.As the structure of memory cell, except the 1T1C type, can also adopt the various structures of 2T2C type of for example having two transistors and two ferroelectric condensers etc.
In addition, in the above-described embodiment, the semiconductor device of the FeRAM structure with plane unit has been described, but the scope of application of the present invention is not limited thereto.For example, the present invention also goes for having stacked unit and the long semiconductor device that for example is set to the FeRAM structure of 0.18 μ m of grid.
Figure 53 is the cutaway view of structure that expression has been suitable for the semiconductor device of FeRAM structure of the present invention, as to have the stacked unit.In addition, in Figure 53,, omit expression barrier film structure in addition for the part beyond the FeRAM unit portion 306.
As shown in the figure, on the semiconductor substrate 210 that constitutes by for example silicon, be formed with the element separated region 212 of dividing element area.In the semiconductor substrate 210 that is formed with element separated region 212, be formed with trap 214a, 214b.
On the semiconductor substrate 210 that is formed with trap 214a, 214b, sandwich gate insulating film 216 and be formed with gate electrode (gate wirings) 218.Gate electrode 218 for example have according to long grade of transistorized grid and on polysilicon film lamination the polycrystalline metal suicide structure of metal silicide films such as cobalt silicide film, nickel silicide film, tungsten silicide film is arranged.On gate electrode 218, be formed with silicon oxide film 219.Sidewall sections at gate electrode 218 and silicon oxide film 219 is formed with side wall insulating film 220.
Both sides at the gate electrode 218 that is formed with side wall insulating film 220 are formed with source 222.So constitute transistor 224 with gate electrode 218 and source 222.The long 0.18 μ m that for example is set to of the grid of transistor 224.
On the semiconductor substrate 210 that is formed with transistor 224, be formed with the interlayer dielectric 227 that lamination SiON film successively 225 and silicon oxide film 226 form.The surface of interlayer dielectric 227 is flattened.
On interlayer dielectric 227, be formed with the barrier film 228 that constitutes by for example pellumina.
At barrier film 228 and interlayer dielectric 227, be formed with the contact hole 230a, the 230b that extend to source 222.
At contact hole 230a, 230b, be formed with the barrier metal film (not shown) that lamination Ti film and TiN film successively form.
In being formed with contact hole 230a, the 230b of barrier metal film, embedding have conductor plug 232a, a 232b that is made of tungsten.
On barrier film 228, be formed with the Ir film 234 that is electrically connected with conductor plug 232a.
On Ir film 234, be formed with the lower electrode 236 of ferroelectric condenser 242.
On lower electrode 236, be formed with the ferroelectric film 238 of ferroelectric condenser 242.Adopt for example PZT film as ferroelectric film 238.
On ferroelectric film 238, be formed with the upper electrode 240 of ferroelectric condenser 242.
The upper electrode 240 of institute's lamination, ferroelectric film 238, lower electrode 236 and Ir film 234 are portrayed once by etching, thereby have roughly the same flat shape mutually.
So constitute the ferroelectric condenser 242 that forms by lower electrode 236, ferroelectric film 238, upper electrode 240.The lower electrode 236 of ferroelectric condenser 242 is electrically connected with conductor plug 232a by Ir film 234.
On the zone of the Ir film 234 that does not form interlayer dielectric 227, be formed with the SiON film 244 that has with the thickness of Ir film 234 same degree or the thickness thinner than Ir film 234.In addition, also can replace SiON film 244 and form silicon oxide film.
On the ferroelectric condenser 242 and on the SiON film 244, be formed with the barrier film 246 of function with the diffusion that prevents hydrogen and moisture.Adopting as barrier film 246 has for example pellumina.
Be formed with silicon oxide film 248 on barrier film 246, ferroelectric condenser 242 is embedded in silicon oxide film 248.The surface of silicon oxide film 248 is flattened.
On the silicon oxide film 248 that has been flattened, be formed with the smooth barrier film 250 of function with the diffusion that prevents hydrogen and moisture.Adopting as barrier film 250 has for example pellumina.When barrier film 250 is formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302.That is, barrier film 250 be formed on peripheral circuit portion (not shown), logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion (not shown), pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
On barrier film 250, be formed with silicon oxide film 252.
So, be formed with interlayer dielectric 253 by SiON film 244, barrier film 246, silicon oxide film 248, barrier film 250 and silicon oxide film 252.
At silicon oxide film 252, barrier film 250, silicon oxide film 248 and barrier film 246, be formed with the contact hole 254a of the upper electrode 240 that extends to ferroelectric condenser 242.In addition, at silicon oxide film 252, barrier film 250, silicon oxide film 248, barrier film 246, and SiON film 244, be formed with the contact hole 254b that extends to conductor plug 232b.
In contact hole 254a, 254b, be formed with the barrier metal film (not shown) that lamination Ti film and TiN film successively form.In addition, as barrier metal film, do not form the Ti film and form the barrier metal film that constitutes by the TiN film and can yet.
In being formed with contact hole 254a, the 254b of barrier metal film, embedding respectively have conductor plug 256a, a 256b that is made of tungsten.
On silicon oxide film 252, be formed with distribution 258a that is electrically connected with conductor plug 256a and the distribution 258b that is electrically connected with conductor plug 256b.
On the silicon oxide film 252 that is formed with distribution 258a, 258b, be formed with silicon oxide film 260, distribution 258a, 258b are embedded in silicon oxide film 260.The surface of silicon oxide film 260 is flattened.
On the silicon oxide film 260 that has been flattened, be formed with the smooth barrier film 262 of function with the diffusion that prevents hydrogen and moisture.Adopting as barrier film 262 has for example pellumina.When barrier film 262 is formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302.That is, barrier film 262 be formed on peripheral circuit portion (not shown), logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion (not shown), pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
On barrier film 262, be formed with silicon oxide film 264.
So, constitute interlayer dielectric 265 by silicon oxide film 260, barrier film 262 and silicon oxide film 264.
At silicon oxide film 264, barrier film 262 and silicon oxide film 260, be formed with the contact hole 268 that extends to distribution 258b.
In contact hole 268, be formed with the barrier metal film (not shown) that lamination Ti film and TiN film successively form.
In the contact hole 268 that is formed with barrier metal film, embedding have a conductor plug 270 that is made of tungsten.
On silicon oxide film 264, be formed with the distribution 272 that is electrically connected with conductor plug 268.
On the silicon oxide film 264 that is formed with distribution 272, be formed with silicon oxide film 274, distribution 272 is embedded in silicon oxide film 274.The surface of silicon oxide film 274 is flattened.
On the silicon oxide film 274 that has been flattened, be formed with the smooth barrier film 276 of function with the diffusion that prevents hydrogen and moisture.Adopting as barrier film 276 has for example pellumina.When barrier film 276 is formed on FeRAM chip area 302 and scribing portion 304, also be formed on adjacent FeRAM chip area 302.That is, barrier film 276 be formed on peripheral circuit portion (not shown), logical circuit portion 310, the logical circuit of scribing portion 304, FeRAM unit portion 306, FeRAM peripheral circuit portion (not shown), pad portion 314, as they the scribing portion of boundary portion and pad portion between boundary portion 320 between boundary portion 318 and circuit part and circuit part between boundary portion 316, pad portion and circuit part.
On barrier film 276, be formed with silicon oxide film 278.
In addition, though from silicon oxide film 278 to top diagram not, suitably be formed with the distribution that is embedded in the interlayer dielectric that constitutes by silicon oxide film etc. according to circuit design.
As mentioned above, in the semiconductor device of FeRAM structure with stacked unit, also same with above-mentioned execution mode, by forming the smooth barrier film 250,262,276 of the diffusion that can prevent hydrogen and moisture, and can prevent the deterioration of the electrical characteristic of the ferroelectric condenser 242 that causes by hydrogen and moisture reliably, thereby can improve the PTHS characteristic significantly.In addition, at this moment, about the smooth barrier film of the diffusion that prevents hydrogen and moisture, as long as also be formed with two-layer at least just can, can not and form all 3 layers of barrier film 250,262,276 yet.In addition, also can form more smooth barrier film as required.
In the above-described embodiment, for example understand situation about forming, but distribution not only is defined in the distribution based on Al, and for example also can waits the distribution that forms based on Cu by embedding (damascene) method based on the distribution of Al.
At situation about adopting, utilize Figure 54 and 55 to describe based on the distribution of Cu.Figure 54 is the cutaway view of structure that has used the situation of Cu distribution in the semiconductor device of expression shown in Figure 53, and Figure 55 is the cutaway view that is illustrated in the structure of the joint sheet when having used the Cu distribution.Figure 54 and Figure 53 are same, and expression has the structure of semiconductor device of the FeRAM structure of stacked unit.For putting on identical Reference numeral, and omit or simply its explanation with the same inscape of the semiconductor device shown in Figure 53.
Shown in Figure 54, on the embedding interlayer dielectric 253 that the conductor plug 256a, the 256b that are made of tungsten arranged, be formed with silicon oxide film 260a.
Be formed with distribution trough 280a, 280b at silicon oxide film 260a.
The Cu distribution 282a that is electrically connected with conductor plug 256a arranged in that distribution trough 280a is embedding.The Cu distribution 282b that is electrically connected with conductor plug 256b arranged in that distribution trough 280b is embedding.
On the embedding silicon oxide film 260a that Cu distribution 282a, 282b arranged, be formed with silicon oxide film 260b.The surface of silicon oxide film 260b is flattened.
On the silicon oxide film 260 that has been flattened, be formed with the smooth barrier film 262 of function with the diffusion that prevents hydrogen and moisture.
On barrier film 262, be formed with silicon oxide film 264.
So, constitute interlayer dielectric 265 by silicon oxide film 260, barrier film 262 and silicon oxide film 264.
At silicon oxide film 264, barrier film 262 and silicon oxide film 260b, be formed with the contact hole 268 that extends to Cu distribution 282b.
In contact hole 268, be formed with lamination successively for example thickness be that Ta film and, for example thickness of 15nm is the film that the Cu film of 130nm forms.So, in the contact hole 268 that is formed with the barrier metal film (not shown) that is made of the Ta film, embedding have a conductor plug 270 that is made of Cu.
As mentioned above, when adopting the Cu distribution, joint sheet is made of the metal film based on Al such as AlCu alloy film.
Shown in Figure 55, be formed with distribution trough 285 at the interlayer dielectric 284 that constitutes by silicon oxide film.
Cu distribution 286 arranged in that distribution trough 285 is embedding.
On the embedding interlayer dielectric 284 that Cu distribution 286 arranged, be formed with the interlayer dielectric 288 that constitutes by silicon oxide film.The silicon oxide film that constitutes interlayer dielectric 288 is a kind of for example by the formed film of plasma TEOSCVD method.
Be formed with the contact hole 289 that extends to Cu distribution 286 at interlayer dielectric 288.
In contact hole 268, embedding have a conductor plug 290 that is made of tungsten.
On the embedding interlayer dielectric 288 that conductor plug 290 arranged, be formed with the joint sheet 292 that is electrically connected with conductor plug 290.Joint sheet 292 is made of the AlCu alloy film.
In addition, between Cu distribution 286 and joint sheet 292, the barrier film that forms the diffusion that prevents hydrogen and moisture also can.
On the interlayer dielectric 288 and on the joint sheet 292, be formed with silicon oxide film 294.Silicon oxide film 294 is a kind of for example by the formed film of TEOSCVD method.
On silicon oxide film 294, be formed with silicon nitride film 296.
On silicon nitride film 296, be formed with polyimide resin film 298.
At polyimide resin film 298, silicon nitride film 296 and silicon oxide film 294, be formed with the peristome 299 that extends to joint sheet 292.That is,, be formed with the peristome 299a that extends to joint sheet 292 at silicon nitride film 296 and silicon oxide film 294.Be formed at the zone of the peristome 299a of silicon nitride film 296 and silicon oxide film 294 in comprising of polyimide resin film 298, be formed with peristome 299b.
At joint sheet 292, be electrically connected with external circuit (not shown) by peristome 299.
So, also can replace the distribution that adopts based on the distribution of Al based on Cu.
Shown in Figure 53, when in the semiconductor device of FeRAM structure, adopting the Cu distribution with stacked unit, for example, at first between the ground floor Cu distribution on ferroelectric condenser and the ferroelectric condenser, form the smooth barrier film of ground floor, between the undermost Cu distribution under joint sheet and the joint sheet, form the smooth barrier film of the second layer then and also can.Except this two-layer smooth barrier film, also between other Cu distribution, form smooth barrier film again, thereby can improve moisture-proof more.
Industrial utilizability
Semiconductor device of the present invention and manufacture method thereof are conducive to improve and have partly leading of ferroelectric condenser The reliability of body device.
Claims (41)
1. semiconductor device is characterized in that having:
Ferroelectric condenser, it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film;
First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened;
The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture;
Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened;
The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevents the diffusion of hydrogen or moisture.
2. semiconductor device as claimed in claim 1 is characterized in that also having:
Chip area, it is arranged at above-mentioned semiconductor substrate;
Scribing portion, its adjacent said chip zone and be arranged at above-mentioned semiconductor substrate;
Memory cell portion, it is arranged in the said chip zone, and is formed with the memory cell with above-mentioned ferroelectric condenser;
Logical circuit portion, it is arranged in the said chip zone, and is formed with logical circuit;
Pad portion, it is arranged in the said chip zone, and is formed with joint sheet,
In above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on said memory cells portion, above-mentioned logical circuit portion and above-mentioned pad portion.
3. semiconductor device as claimed in claim 2 is characterized in that,
In above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on said memory cells portion, above-mentioned logical circuit portion, above-mentioned pad portion and scribing portion.
4. as each described semiconductor device in the claim 1～3, it is characterized in that also having:
First distribution, it is electrically connected with the above-mentioned lower electrode or the above-mentioned upper electrode of above-mentioned ferroelectric condenser;
Second distribution, it is formed on above-mentioned first distribution;
The 3rd distribution, it is formed on above-mentioned second distribution, and is electrically connected with external circuit.
5. semiconductor device as claimed in claim 4 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed between above-mentioned second distribution and above-mentioned the 3rd distribution.
6. semiconductor device as claimed in claim 4 is characterized in that,
Above-mentioned first dielectric film and above-mentioned first barrier film are formed between above-mentioned first distribution and above-mentioned second distribution.
7. semiconductor device as claimed in claim 6 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed between above-mentioned second distribution and above-mentioned the 3rd distribution.
8. semiconductor device as claimed in claim 7 is characterized in that also having:
The 3rd dielectric film, it is formed on above-mentioned the 3rd distribution, and the surface is flattened;
The 3rd smooth barrier film, it is formed on above-mentioned the 3rd dielectric film, prevents the diffusion of hydrogen or moisture,
At above-mentioned the 3rd dielectric film and above-mentioned the 3rd barrier film, be formed with the peristome that extends to above-mentioned the 3rd distribution.
9. semiconductor device as claimed in claim 6 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed on above-mentioned the 3rd distribution,
At above-mentioned second dielectric film and above-mentioned second barrier film, be formed with the peristome that extends to above-mentioned the 3rd distribution.
10. semiconductor device as claimed in claim 4 is characterized in that,
Above-mentioned first dielectric film and above-mentioned first barrier film are formed between above-mentioned second distribution and above-mentioned the 3rd distribution,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed on above-mentioned the 3rd distribution,
At above-mentioned second dielectric film and above-mentioned second barrier film, be formed with the peristome that extends to above-mentioned the 3rd distribution.
11. semiconductor device as claimed in claim 4 is characterized in that,
Above-mentioned first dielectric film and above-mentioned first barrier film are formed between above-mentioned ferroelectric condenser and above-mentioned first distribution.
12. semiconductor device as claimed in claim 11 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed between above-mentioned first distribution and above-mentioned second distribution.
13. semiconductor device as claimed in claim 12 is characterized in that, also has:
The 3rd dielectric film, it is formed between above-mentioned second distribution and above-mentioned the 3rd distribution, and the surface is flattened;
The 3rd smooth barrier film, it is formed on, and above-mentioned the 3rd distribution is upper and lower to be stated on the 3rd dielectric film, prevents the diffusion of hydrogen or moisture.
14. semiconductor device as claimed in claim 13 is characterized in that, also has:
The 4th dielectric film, it is formed on above-mentioned the 3rd distribution, and the surface is flattened;
The 4th smooth barrier film, it is formed on above-mentioned the 4th dielectric film, prevents the diffusion of hydrogen or moisture,
At above-mentioned the 4th dielectric film and above-mentioned the 4th barrier film, be formed with the peristome that extends to above-mentioned the 3rd distribution.
15. semiconductor device as claimed in claim 11 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed between above-mentioned second distribution and above-mentioned the 3rd distribution.
16. semiconductor device as claimed in claim 11 is characterized in that,
Above-mentioned second dielectric film and above-mentioned second barrier film are formed on above-mentioned the 3rd distribution,
At above-mentioned second dielectric film and above-mentioned second barrier film, be formed with the peristome that extends to above-mentioned the 3rd distribution.
17. as each described semiconductor device in the claim 1～16, it is characterized in that,
In above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on whole of above-mentioned semiconductor substrate.
18. as each described semiconductor device in the claim 4～16, it is characterized in that,
Also have the 5th barrier film, the 5th barrier film forms in the mode that covers above-mentioned first distribution, prevents the diffusion of hydrogen or moisture.
19. as each described semiconductor device in the claim 1～18, it is characterized in that,
Also have the 6th barrier film, the 6th barrier film forms in the mode that covers above-mentioned ferroelectric condenser, prevents the diffusion of hydrogen or moisture.
20. as each described semiconductor device in the claim 1～19, it is characterized in that,
Above-mentioned first barrier film or above-mentioned second barrier film are made of metal oxide.
21. semiconductor device as claimed in claim 20 is characterized in that,
Above-mentioned metal oxide is aluminium oxide, titanium oxide or tantalum oxide.
22. as each described semiconductor device in the claim 1～19, it is characterized in that,
Above-mentioned first barrier film or above-mentioned second barrier film are silicon nitride film or silicon oxynitride film.
23. as each described semiconductor device in the claim 1～19, it is characterized in that,
Above-mentioned first barrier film is a pellumina,
Above-mentioned second barrier film is a silicon nitride film.
24. as each described semiconductor device in the claim 1～19, it is characterized in that,
Above-mentioned first barrier film is a pellumina,
Above-mentioned second barrier film is for having hygroscopic organic membrane.
25. as each described semiconductor device in the claim 1～24, it is characterized in that,
The thickness of the thickness of above-mentioned first barrier film and above-mentioned second barrier film is more than the 50nm and less than 100nm.
26. semiconductor device as claimed in claim 25 is characterized in that,
The thickness of the thickness of above-mentioned first barrier film and above-mentioned second barrier film is more than the 50nm and below the 80nm.
27. as each described semiconductor device in the claim 1～26, it is characterized in that,
Also have dielectric film, this dielectric film be formed on above-mentioned first barrier film directly over and above-mentioned second barrier film directly at least one side, and become etched block film.
28. as each described semiconductor device in the claim 1～27, it is characterized in that,
Above-mentioned ferroelectric film is PbZr
1-XTi
XO
3Film, Pb
1-XLa
XZr
1-YTi
YO
3Film, SrBi
2(Ta
XNb
1-X)
2O
9Film or Bi
4Ti
2O
12Film.
29. a semiconductor device is characterized in that having:
Memory cell portion, this memory cell portion has: ferroelectric condenser, it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film; First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevents the diffusion of hydrogen or moisture;
Pad portion, it is formed with joint sheet,
In above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on said memory cells portion and above-mentioned pad portion.
30. a semiconductor device is characterized in that having:
Chip area, this chip area has: ferroelectric condenser, it is formed on the semiconductor substrate, and has lower electrode, is formed on ferroelectric film on the above-mentioned lower electrode, is formed on the upper electrode on the above-mentioned ferroelectric film; First dielectric film, it is formed on the above-mentioned semiconductor substrate and reaches on the above-mentioned ferroelectric condenser, and the surface is flattened; The first smooth barrier film, it is formed on above-mentioned first dielectric film, prevents the diffusion of hydrogen or moisture; Second dielectric film, it is formed on above-mentioned first barrier film, and the surface is flattened; The second smooth barrier film, it is formed on above-mentioned second dielectric film, prevents the diffusion of hydrogen or moisture;
Scribing portion, its adjacent said chip zone and be arranged at above-mentioned semiconductor substrate,
In above-mentioned first barrier film and above-mentioned second barrier film at least one is formed on the regional and above-mentioned scribing of said chip portion.
31. the manufacture method of a semiconductor device is characterized in that, has:
Have lower electrode, be formed on ferroelectric film on the above-mentioned lower electrode, be formed on the operation of the ferroelectric condenser of the upper electrode on the above-mentioned ferroelectric film forming on the semiconductor substrate;
Reaching the operation that forms first dielectric film on the above-mentioned ferroelectric condenser on the above-mentioned semiconductor substrate;
The surface of above-mentioned first dielectric film is carried out the operation of planarization;
On above-mentioned first dielectric film, form the operation of the first smooth barrier film of the diffusion that prevents hydrogen or moisture;
On above-mentioned first barrier film, form the operation of second dielectric film;
The surface of above-mentioned second dielectric film is carried out the operation of planarization;
On above-mentioned second dielectric film, form the operation of the second smooth barrier film of the diffusion that prevents hydrogen or moisture.
32. the manufacture method of semiconductor device as claimed in claim 31 is characterized in that,
After the operation of the surface of above-mentioned first dielectric film being carried out planarization and before the operation that forms above-mentioned first barrier film, also have and carry out the first heat treated operation.
33. the manufacture method of semiconductor device as claimed in claim 32 is characterized in that,
In carrying out the above-mentioned first heat treated operation, in the plasma ambient of using nitrogen gas generation at least, carry out first heat treatment, thereby nitrogenize is carried out on the surface of above-mentioned first dielectric film.
34. the manufacture method as each described semiconductor device in the claim 31～33 is characterized in that,
After the operation of the surface of above-mentioned second dielectric film being carried out planarization and before the operation that forms above-mentioned second barrier film, also have and carry out the second heat treated operation.
35. the manufacture method of semiconductor device as claimed in claim 34 is characterized in that,
In carrying out the above-mentioned second heat treated operation, in the plasma ambient of using nitrogen gas generation at least, carry out second heat treatment, thereby nitrogenize is carried out on the surface of above-mentioned second dielectric film.
36. the manufacture method as each described semiconductor device in the claim 31～35 is characterized in that,
The surface of above-mentioned first dielectric film is being carried out in the operation of planarization, coming the surface of above-mentioned first dielectric film is ground, thereby planarization is being carried out on the surface of above-mentioned first dielectric film by chemical mechanical milling method.
37. the manufacture method of semiconductor device as claimed in claim 36 is characterized in that,
After the operation of the surface of above-mentioned first dielectric film being carried out planarization and before forming the operation of above-mentioned first barrier film, also have the operation that directly over above-mentioned first dielectric film that has been flattened, forms the 3rd smooth dielectric film,
In the operation that forms above-mentioned first barrier film, on above-mentioned the 3rd dielectric film, form above-mentioned first barrier film.
38. the manufacture method as each described semiconductor device in the claim 31～37 is characterized in that,
The surface of above-mentioned second dielectric film is being carried out in the operation of planarization, coming the surface of above-mentioned second dielectric film is ground, thereby planarization is being carried out on the surface of above-mentioned second dielectric film by chemical mechanical milling method.
39. the manufacture method of semiconductor device as claimed in claim 38 is characterized in that,
After the operation of the surface of above-mentioned second dielectric film being carried out planarization and before forming the operation of above-mentioned second barrier film, also have the operation that directly over above-mentioned second dielectric film that has been flattened, forms the 4th smooth dielectric film,
In the operation that forms above-mentioned second barrier film, on above-mentioned the 4th dielectric film, form above-mentioned second barrier film.
40. the manufacture method as each described semiconductor device in the claim 31～39 is characterized in that,
After the operation that forms above-mentioned first barrier film, also has the operation that on above-mentioned first barrier film, becomes the pentasyllabic quatrain velum of etched block film.
41. the manufacture method as each described semiconductor device in the claim 31～40 is characterized in that,
After the operation that forms above-mentioned second barrier film, also has the operation that on above-mentioned second barrier film, becomes the 6th dielectric film of etched block film.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPPCT/JP2004/009429 | 2004-07-02 | ||
| PCT/JP2004/009429 WO2006003707A1 (en) | 2004-07-02 | 2004-07-02 | Semiconductor device and process for fabricating the same |
| PCT/JP2005/011955 WO2006003940A1 (en) | 2004-07-02 | 2005-06-29 | Semiconductor device and method for manufacturing same |
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| CN1993828B CN1993828B (en) | 2012-02-08 |
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| JP3114710B2 (en) * | 1998-11-30 | 2000-12-04 | 日本電気株式会社 | Ferroelectric memory and method of manufacturing the same |
| JP3331334B2 (en) * | 1999-05-14 | 2002-10-07 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JP3260737B2 (en) * | 1999-06-17 | 2002-02-25 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JP2001015696A (en) * | 1999-06-29 | 2001-01-19 | Nec Corp | Hydrogen barrier layer and semiconductor device |
| JP2002110932A (en) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | Semiconductor device and its manufacturing method |
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| JP3466174B2 (en) * | 2001-09-27 | 2003-11-10 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP2003197878A (en) * | 2001-10-15 | 2003-07-11 | Hitachi Ltd | Memory semiconductor device and its manufacturing method |
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| WO2006003707A1 (en) | 2006-01-12 |
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