WO2006003707A1 - Semiconductor device and process for fabricating the same - Google Patents

Semiconductor device and process for fabricating the same Download PDF

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Publication number
WO2006003707A1
WO2006003707A1 PCT/JP2004/009429 JP2004009429W WO2006003707A1 WO 2006003707 A1 WO2006003707 A1 WO 2006003707A1 JP 2004009429 W JP2004009429 W JP 2004009429W WO 2006003707 A1 WO2006003707 A1 WO 2006003707A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
insulating film
barrier
wiring
Prior art date
Application number
PCT/JP2004/009429
Other languages
French (fr)
Japanese (ja)
Inventor
Kouichi Nagai
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2004/009429 priority Critical patent/WO2006003707A1/en
Priority to JP2006528750A priority patent/JP5202846B2/en
Priority to KR1020067027308A priority patent/KR100985793B1/en
Priority to PCT/JP2005/011955 priority patent/WO2006003940A1/en
Priority to CN2005800266413A priority patent/CN1993828B/en
Publication of WO2006003707A1 publication Critical patent/WO2006003707A1/en
Priority to US11/647,198 priority patent/US8552484B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.
  • Ferroelectric Random Access Memory using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, and excellent write / read durability. It is a non-volatile memory with features, and further development is expected in the future.
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside.
  • a standard FeRAM ferroelectric capacitor in which a lower electrode made of a Pt film, a ferroelectric film made of a PZT film, and an upper electrode made of a Pt film are sequentially stacked,
  • the substrate is heated to a temperature of about 200 ° C in an atmosphere with a partial pressure of 40 Pa (0.3 Torr)
  • the ferroelectricity of the PbZr Ti O film PZT film
  • a film forming process by the Deposition method or the like is selected.
  • Patent Document 1 JP 2003-197878 A
  • Patent Document 2 JP 2001-68639 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2003-174145
  • Patent Document 4 Japanese Patent Laid-Open No. 2002-176149
  • Patent Document 5 Japanese Patent Laid-Open No. 2003-100994
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. For this reason, it has been difficult for conventional FeRAMs to obtain good test results for the PTHS (Pressure Temperature Humidity Stress) test, which is one of the accelerated life tests.
  • PTHS Pressure Temperature Humidity Stress
  • the PTHS test is performed under conditions of, for example, a temperature of 135 ° C and a humidity of 85% based on the JEDEC (Joint Electron Device Engineering Council) standard. PTH like this
  • An object of the present invention is to provide a semiconductor device that is excellent in resistance to hydrogen gas and moisture resistance, sufficiently suppresses deterioration of characteristics of a ferroelectric capacitor, and can improve PTHS characteristics, and a method for manufacturing the same. is there.
  • a ferroelectric capacitor comprising: a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film; Is formed on the flat first barrier film for preventing the diffusion of moisture, the second barrier film having a planarized surface, and the second insulating film formed on the first barrier film.
  • a semiconductor device having a flat second barrier film that prevents diffusion of hydrogen or moisture.
  • a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film on a semiconductor substrate Forming a ferroelectric capacitor having: a step of forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor; and planarizing a surface of the first insulating film. Forming a flat first barrier film for preventing diffusion of hydrogen or moisture on the first insulating film; and forming a second insulating film on the first barrier film. A step of planarizing the surface of the second insulating film, and a step of forming a flat second barrier film for preventing diffusion of hydrogen or water on the second insulating film. A method for manufacturing a semiconductor device is provided.
  • a semiconductor device having a body capacitor a first insulating film formed on a semiconductor substrate and a ferroelectric capacitor and having a flattened surface and a first insulating film are formed.
  • a flat second barrier film that prevents the diffusion of hydrogen is formed, so that hydrogen and moisture are securely blocked, and hydrogen and moisture are prevented from reaching the ferroelectric film of the ferroelectric capacitor. can do.
  • deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram (part 1) for explaining an effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a view (No. 2) for explaining the effect of the semiconductor device according to the first embodiment of the invention.
  • FIG. 4 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 5 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 6 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 8 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 9 is a process cross-sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 10 is a process sectional view (No. 7) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 11 is a process cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 12 is a process cross-sectional view (No. 9) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 13 is a process cross-sectional view (No. 10) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 14 is a process cross-sectional view (No. 11) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 15 is a process sectional view (No. 12) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 16 is a process cross-sectional view (No. 13) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 17 is a process sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 19 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention
  • FIG. 21 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
  • FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 23 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 24 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
  • FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having stacked cells to which the present invention is applied.
  • FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment
  • FIGS. 2 and 3 are views for explaining the effects of the semiconductor device according to the present embodiment
  • FIGS. 4 to 17 are methods for manufacturing the semiconductor device according to the present embodiment. It is process sectional drawing which shows these.
  • an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon.
  • Semiconductor substrate on which element isolation region 12 is formed In FIG. 10, there are formed Uenoles 14a and 14b.
  • a gate electrode (gate wiring) 18 is formed via a gate insulating film 16 on the semiconductor substrate 10 on which the wells 14a and 14b are formed.
  • the gate electrode 18 has, for example, a polycide structure in which a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • an insulating film 19 made of a silicon oxide film is formed on the gate electrode 18.
  • Sidewall insulating films 20 are formed on the side walls of the gate electrode 18 and the insulating film 19.
  • a source Z drain diffusion layer 22 is formed on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed.
  • the transistor 24 having the gate electrode 18 and the source Z drain diffusion layer 22 is formed.
  • the gate length of the transistor 24 is set to 0.35 zm, for example, or 0.11 to 0.18 xm, for example.
  • a SiON film 25 having a thickness of, for example, 200 nm and a silicon oxide film 26 having a thickness of, for example, 600 nm are sequentially stacked.
  • an interlayer insulating film 27 formed by sequentially laminating the Si ON film 25 and the silicon oxide film 26 is formed.
  • the surface of the interlayer insulating film 27 is flat.
  • a silicon oxide film 34 having a film thickness of lOOnm is formed on the interlayer insulating film 27, for example. Since the silicon oxide film 34 is formed on the flattened interlayer insulating film 27, the silicon oxide film 34 is flat.
  • a lower electrode 36 of the ferroelectric capacitor 42 is formed on the silicon oxide film 34.
  • the lower electrode 36 is composed of, for example, a laminated film in which an oxide aluminum film 36a having a thickness of 20 to 50 nm and a Pt film 36b having a thickness of 100 to 200 nm are sequentially laminated.
  • the film thickness of the Pt film 36b is set to 165 nm.
  • a ferroelectric film 38 of the ferroelectric capacitor 42 is formed on the lower electrode 36.
  • ferroelectric film 38 for example, a PbZr TiO film (PZT film) having a film thickness of 100 250 nm is used.
  • ferroelectric film 38 a 150 nm thick film is used for the ferroelectric film 38.
  • An upper electrode 40 of the ferroelectric capacitor 42 is formed on the ferroelectric film 38.
  • the upper electrode 40 includes an IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm. It is composed of a laminated film obtained by sequentially laminating the film 40b.
  • Ir ⁇ film 40a IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm. It is composed of a laminated film obtained by sequentially laminating the film 40b.
  • the film thickness is set to 50 nm, and the film thickness of the IrO film 40b is set to 200 nm.
  • the oxygen composition ratio Y of the O film 40b is set higher than the oxygen composition ratio X of the IrO film 40a.
  • the ferroelectric capacitor 42 including the lower electrode 36, the ferroelectric film 38, and the upper electrode 40 is configured.
  • a barrier film 44 is formed on the ferroelectric film 38 and the upper electrode 40 so as to cover the upper and side surfaces of the ferroelectric film 38 and the upper electrode 40.
  • a 20-lOOnm aluminum oxide (Al 2 O 3) film is used as the noria film 44.
  • the barrier film 44 is a film having a function of preventing diffusion of hydrogen and moisture.
  • the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor 42 are reduced. Will deteriorate.
  • the barrier film 44 By forming the barrier film 44 so as to cover the upper surface and the side surfaces of the ferroelectric film 38 and the upper electrode 40, it is possible to suppress hydrogen and moisture from reaching the ferroelectric film 38. It is possible to suppress the deterioration of the electrical characteristics of the.
  • a barrier film 46 is formed on the ferroelectric capacitor 42 and the silicon oxide film 34 covered with the barrier film 44.
  • the barrier film 46 for example, an aluminum oxide film having a thickness of 20-lOOnm is used.
  • the barrier film 46 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier film 44.
  • an interlayer insulating film 48 made of, for example, a silicon oxide film having a thickness of 1500 nm is formed on the barrier film 46.
  • the surface of the interlayer insulating film 48 is planarized.
  • contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed, respectively. Further, in the interlayer insulating film 48, the barrier film 46, and the barrier film 44, a contact hole 52a reaching the upper electrode 40 is formed. A contact hole 52b reaching the lower electrode 36 is formed in the interlayer insulating film 48, the barrier film 46, and the barrier film 44.
  • a barrier metal film (not shown) is formed by sequentially laminating TiN films.
  • the Ti film is formed to reduce contact resistance, and the TiN film is formed to prevent diffusion of tungsten, which is a conductor plug material.
  • the barrier metal film formed on each contact hole to be described later is also formed for the same purpose.
  • Conductor plugs 54a and 54b made of tungsten are respectively carried in the contact holes 50a and 50b in which the barrier metal film is formed.
  • a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the interlayer insulating film 48 and in the contact hole 52a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the interlayer insulating film 48 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the interlayer insulating film 48.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially formed. It is comprised by the laminated film formed by laminating
  • the source / drain diffusion layer 22 of the transistor 24 and the upper electrode 40 of the ferroelectric capacitor 42 are electrically connected via the conductor plug 54a and the wiring 56a, so that one transistor 24 and 1 A FeRAM 1T1C type memory cell having two ferroelectric capacitors 42 is formed.
  • multiple memory cells are arranged in the memory cell area of the FeRAM chip.
  • a barrier film 58 is formed on the interlayer insulating film 48 on which the wirings 56a, 56b, 56c are formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, 56c.
  • a 20 nm aluminum oxide film is used as the barrier film 58.
  • the barrier film 58 is a film having a function of preventing the diffusion of hydrogen and moisture similarly to the barrier films 44 and 46.
  • the barrier film 58 is also used to suppress damage caused by plasma.
  • a silicon oxide film 60 having a thickness of 2600 nm is formed on the barrier film 58.
  • the surface of the silicon oxide film 60 is planarized.
  • the planarized silicon oxide film 60 is left and deposited on the self-spring 56a, 56b, 56c with a film thickness of, for example, lOOOnm.
  • a silicon oxide film 61 having a film thickness of lOOnm is formed on the silicon oxide film 60. Since the silicon oxide film 61 is formed on the flattened silicon oxide film 60, the silicon oxide film 61 is flat.
  • a noor film 62 is formed on the silicon oxide film 61.
  • the barrier film 62 for example, an aluminum oxide film having a thickness of 20 to 70 nm is used.
  • an aluminum oxide film having a thickness of 50 nm is used as the noria film 62. Since the NORA film 62 is formed on the flat silicon oxide film 61, the barrier film 62 is flat.
  • the barrier film 62 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44, 46, and 58. Further, the barrier film 62 is flat because it is formed on the flat silicon oxide film 61, and is formed with extremely good coverage as compared with the barrier films 44, 46, and 58. Therefore, such a flat barrier film 62 can more reliably prevent hydrogen and moisture from diffusing. In practice, the barrier film 62 is formed not only on the memory cell region of the FeRAM chip on which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also on the entire surface of the FeRAM chip including the peripheral circuit region. ing.
  • a silicon oxide film 64 having a film thickness of 50-lOOnm is formed on the barrier film 62.
  • the thickness of the silicon oxide film 64 is set to lOOnm.
  • the interlayer insulating film 66 is constituted by the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64.
  • a contact hole 68 reaching the wiring 56c is formed.
  • a barrier metal film (not shown) is formed by sequentially stacking, for example, a Ti film having a thickness of 20 nm and a TiN film having a thickness of 50 nm, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • a conductor plug 70 made of tungsten is carried in the contact hole 68 in which the barrier metal film is formed.
  • a wiring 72 a is formed on the interlayer insulating film 66. On the interlayer insulating film 66, a wiring 72b electrically connected to the conductor plug 70 is formed. Wiring 72a, 72b (first
  • the metal wiring layer 72 includes, for example, a TiN film with a thickness of 50 nm, an AlCu alloy film with a thickness of 500 nm, It consists of a laminated film consisting of a 5nm thick Ti film and a 150nm thick TiN film.
  • a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the interlayer insulating film 66 and on the wirings 72a and 72b.
  • the surface of the silicon oxide film 74 is planarized.
  • a silicon oxide film 76 having a film thickness of lOOnm is formed on the silicon oxide film 74. Since the silicon oxide film 76 is formed on the flattened silicon oxide film 74, the silicon oxide film 76 is flat.
  • a noria film 78 is formed on the silicon oxide film 76.
  • the barrier film 78 for example, an aluminum oxide film having a film thickness of 20-lOOnm is used.
  • the barrier film 78 an aluminum oxide film having a thickness of 50 nm is used. Since the NORA film 78 is formed on the flat silicon oxide film 76, the barrier film 78 is flat.
  • the barrier film 78 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 78 is formed on the flat silicon oxide film 61, it is flat. Like the barrier film 62, the barrier film 78 has an extremely good coverage as compared with the barrier films 44, 46, and 58. It is formed with. Therefore, diffusion of hydrogen and moisture can be prevented more reliably by using such a flat NOR film 62. Actually, the barrier film 78 includes not only the memory cell region of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit region and the like, like the barrier film 62. It is formed over the entire surface of the FeRAM chip.
  • a silicon oxide film 80 having a film thickness of lOOnm is formed on the barrier film 78.
  • the interlayer insulating film 82 is configured by the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80.
  • contact holes 84a and 84b reaching the wirings 72a and 72b are formed, respectively.
  • a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm thick Ti film and a 50 nm thick TiN film, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • the contact holes 84a and 84b in which the barrier metal film is formed are made of tungsten. Conductor plugs 86a and 86b are respectively carried.
  • the wiring 88a electrically connected to the conductor plug 86a and the wiring electrically connected to the conductor plug 86b (bon Ding pad) 88b is formed on the interlayer insulating film 82 in which the conductor plugs 86a and 86b are carried.
  • the wirings 88a and 88b (third metal wiring layer 88) are composed of, for example, a laminated film in which a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, and a 150 nm thick TiN film are sequentially laminated. ing.
  • a silicon oxide film 90 having a thickness of 100 to 300 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b.
  • the thickness of the silicon oxide film 90 is set to lOOnm.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed on the silicon oxide film 90.
  • a polyimide resin film 94 with a film thickness of 26 ⁇ m is formed on the silicon nitride film 92.
  • an opening 96 reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94, the silicon nitride film 92, and the silicon oxide film 90. That is, in the silicon nitride film 92 and the silicon oxide film 90, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92 and the silicon oxide film 90.
  • An external circuit (not shown) is electrically connected to the wiring (bonding pad) 88b through the opening 96.
  • the semiconductor device according to the present embodiment is configured.
  • the main feature is that it has a flat barrier film 78 formed between the third metal wiring layer 88 (wirings 88a and 88b).
  • a ferroelectric key caused by hydrogen or moisture is used.
  • a barrier film made of aluminum oxide or the like for preventing diffusion of hydrogen or moisture is formed above the ferroelectric capacitor.
  • the barrier film when a barrier film is formed on an interlayer insulating film or the like having a step on the surface, the barrier film is not so well covered, so that diffusion of hydrogen and moisture in the barrier film is difficult. Cannot be sufficiently prevented.
  • hydrogen or moisture reaches the ferroelectric film of the ferroelectric capacitor, the ferroelectric properties of the ferroelectric film are reduced or lost by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor are deteriorated. It becomes.
  • FIG. 2 is a cross-sectional view showing a defect portion generated in a flat barrier film formed in a semiconductor device having a ferroelectric capacitor.
  • the semiconductor device shown in FIG. 2 unlike the semiconductor device according to the present embodiment, only the single-layer film 78 is formed as a flat barrier film, and the barrier film 62 is not formed.
  • the barrier film 62 is not formed.
  • FIG. 2 even in the flat knitted rear film 78, a defective portion 110 having a poor coverage is formed due to a step caused by micro scratches generated on the surface of the insulating film underneath. It is thought that it occurs.
  • two flat barrier films that is, the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42, A flat barrier film 62 formed between the second metal wiring layer 72 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed.
  • FIG. 3A is a plan view showing the structure of the semiconductor device according to the present embodiment
  • FIG. 3B is a cross-sectional view of the semiconductor device according to the present embodiment corresponding to FIG. FIG. 2 schematically shows a defect portion 110 generated in two flat barrier films 62 and 78.
  • FIG. 3A is a plan view showing the structure of the semiconductor device according to the present embodiment
  • FIG. 3B is a cross-sectional view of the semiconductor device according to the present embodiment corresponding to FIG.
  • FIG. 2 schematically shows a defect portion 110 generated in two flat barrier films 62 and 78.
  • the probability that the defective portion 110 is generated at substantially the same plane position is very small. Therefore, in the semiconductor device according to the present embodiment, even if hydrogen or moisture enters the inside of the semiconductor device through the defect portion 110 generated in the flat barrier film 78 located in the upper layer, the flat device located in the lower layer is used.
  • the barrier film 62 can reliably block the intruding hydrogen and moisture from reaching the ferroelectric capacitor 42.
  • film 62 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 are formed, so that hydrogen and moisture are securely barriered, and hydrogen and moisture are strong.
  • Reaching the ferroelectric film 38 of the dielectric capacitor 42 can be reliably prevented.
  • an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon by, for example, a LOCOS (LOCal Oxidation of Silicon) method.
  • LOCOS LOCal Oxidation of Silicon
  • the dopants 14a and 14b are formed by introducing dopant impurities by ion implantation.
  • a transistor 24 having a gate electrode (gate wiring) 18 and a source / drain diffusion layer 22 is formed in the element region by using a normal transistor formation method (see FIG. 4A). .
  • an SiON film 25 of, eg, a 200 nm-thickness is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition).
  • a silicon oxide film 26 of, eg, a 600 nm-thickness is formed on the entire surface by a plasma TEOSCVD method (see FIG. 4B).
  • the interlayer insulating film 27 is constituted by the SiON film 25 and the silicon oxide film 26.
  • the surface of the interlayer insulating film 27 is flattened by, eg, CMP (see FIG. 4C).
  • the heat treatment is performed.
  • a silicon oxide film 34 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 5A).
  • heat treatment is performed in an oxygen atmosphere by, eg, RTA (Rapid Thermal Annealing).
  • the heat treatment temperature is, for example, 650 ° C
  • the heat treatment time is, for example, 1-12 minutes.
  • a laminated film 36 composed of the aluminum oxide film 36a and the Pt film 36b is formed.
  • the multilayer film 36 becomes a lower electrode of the ferroelectric capacitor 42.
  • ferroelectric film 38 is formed on the entire surface by, eg, sputtering.
  • a PZT film having a thickness of 100 to 250 nm is formed.
  • the ferroelectric film 38 is formed by the sputtering method has been described as an example, but the method of forming the ferroelectric film is not limited to the sputtering method.
  • the ferroelectric film may be formed by a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD method, or the like.
  • heat treatment is performed in an oxygen atmosphere by, for example, the RTA method.
  • the heat treatment temperature is, for example, 550-600 ° C
  • the heat treatment time is, for example, 60-120 seconds.
  • IrO having a film thickness of, for example, 25 to 75 nm is formed by, for example, sputtering or MOCVD.
  • a film 40a is formed.
  • heat treatment is performed, for example, at 600 to 800 ° C for 10 to 100 seconds in an argon and oxygen atmosphere.
  • the IrO film 40b is formed so as to be higher than the composition ratio X.
  • a laminated film 40 composed of the IrO film 40a and the IrO film 40b is formed (see FIG. 5B).
  • the laminated film 40 becomes an upper electrode of the ferroelectric capacitor 42.
  • a photoresist film 98 is formed on the entire surface by, eg, spin coating.
  • a photoresist film 98 is formed on the ferroelectric capacitor 42 by photolithography. Pattern in the planar shape of the upper electrode 40.
  • the laminated film 40 is etched using the photoresist film 98 as a mask.
  • Ar gas and C1 gas are used as the etching gas.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 700 ° C for 30 to 120 minutes. This heat treatment is intended to prevent the surface of the upper electrode 40 from becoming abnormal.
  • a photoresist film 100 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 100 is patterned into a planar shape of the ferroelectric film 38 of the ferroelectric capacitor 42 by photolithography.
  • the ferroelectric film 38 is etched using the photoresist film 100 as a mask (see FIG. 6A). Thereafter, the photoresist film 100 is peeled off.
  • heat treatment is performed in an oxygen atmosphere, for example, at 300 to 400 ° C for 30 to 120 minutes.
  • a barrier film 44 is formed by, eg, sputtering or CVD (see FIG. 6B).
  • the barrier film 44 for example, an aluminum oxide film having a thickness of 20 to 50 nm is formed.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • a photoresist film 102 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 102 is patterned into the planar shape of the lower electrode 36 of the ferroelectric capacitor 42 by photolithography.
  • the barrier film 44 and the laminated film 36 are etched (see FIG. 6C).
  • the lower electrode 36 made of a laminated film is formed.
  • the barrier film 44 remains so as to cover the upper electrode 40 and the ferroelectric film 38. Thereafter, the photoresist film 102 is peeled off.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 600 ° C for 30 to 120 minutes.
  • the noor film 46 is formed on the entire surface by, eg, sputtering or CVD.
  • the barrier film 46 for example, an aluminum oxide film having a thickness of 20 lOOnm is formed (see FIG. 7A).
  • the ferroelectric capacitor 42 covered with the barrier film 44 is further covered.
  • the barrier film 46 is formed.
  • heat treatment is performed in an oxygen atmosphere, for example, at 500 to 700 ° C for 30 to 120 minutes.
  • an interlayer insulating film 48 made of a silicon oxide film having a thickness of, eg, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 7B).
  • the surface of the interlayer insulating film 48 is planarized by, eg, CMP (see FIG. 7C).
  • This heat treatment is for removing moisture in the interlayer insulating film 48 and changing the film quality of the interlayer insulating film 48 so that moisture enters the interlayer insulating film 48.
  • the surface of the interlayer insulating film 48 is nitrided, and a SiON film (not shown) is formed on the surface of the interlayer insulating film 48.
  • contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed in the interlayer insulating film 48, the NORA film 46, the silicon oxide film 34, and the interlayer insulating film 27 by photolithography and etching. (See Figure 8 (a)).
  • a Ti film of, eg, a 20 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • the Ti film and the TiN film constitute a barrier metal film (not shown).
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tandastain film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 48 is exposed.
  • the conductor plugs 54a and 54b made of tungsten are loaded in the contact holes 50a and 50b, respectively (see FIG. 8 (b)).
  • a SiON film 104 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD.
  • the upper electrode 40 of the ferroelectric capacitor 42 is reached in the SiON film 104, the interlayer insulating film 48, the barrier film 46, and the barrier film 44 by photolithography and dry etching.
  • the contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 is formed (see FIG. 8 (c)).
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the heat treatment may be performed in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen can be supplied to the ferroelectric film 38 of the capacitor, and the electrical characteristics of the ferroelectric capacitor 42 can be recovered.
  • the SiON film 104 is removed by etching.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • a silicon film 58 is formed on the entire surface by, eg, sputtering or CVD.
  • the barrier film 58 for example, an aluminum oxide film having a film thickness of 20 to 70 nm is formed (see FIG. 9B).
  • the barrier film 58 an aluminum oxide film having a thickness of 20 nm is formed.
  • the barrier film 58 is formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, and 56c.
  • a silicon oxide film 60 of, eg, a 2600 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 10A).
  • the surface of the silicon oxide film 60 is planarized by, eg, CMP (see FIG. 10B).
  • CMP see FIG. 10B.
  • This heat treatment is for removing moisture in the silicon oxide film 60 and changing the film quality of the silicon oxide film 60 so that moisture does not easily enter the silicon oxide film 60.
  • the surface of the silicon oxide film 60 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 60.
  • a silicon oxide film 61 having a thickness of, for example, lOOnm is formed on the planarized silicon oxide film 60 by, eg, plasma TEOSCVD. Since the silicon oxide film 61 is formed on the planarized silicon oxide film 60, the silicon oxide film 61 becomes flat.
  • This heat treatment is for removing moisture in the silicon oxide film 61 and changing the film quality of the silicon oxide film 61 so that moisture does not easily enter the silicon oxide film 61.
  • the surface of the silicon oxide film 61 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 61.
  • the barrier film 62 is formed on the flat silicon oxide film 61 by, eg, sputtering or CVD.
  • the barrier film 62 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed.
  • an aluminum oxide film having a thickness of 50 nm is formed as the noble film 62. Since the barrier film 62 is formed on the flat silicon oxide film 61, the barrier film 62 becomes flat.
  • a silicon oxide film 64 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 11A).
  • the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64 constitute the interlayer insulating film 66.
  • This heat treatment is for removing moisture in the silicon oxide film 64 and changing the film quality of the silicon oxide film 64 so that moisture does not easily enter the silicon oxide film 64.
  • the surface of the silicon oxide film 64 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 64.
  • the silicon oxide film 64 and the barrier are formed by photolithography and dry etching.
  • a contact hole 68 reaching the wiring 56c is formed in the film 62, the silicon oxide film 61, the silicon oxide film 60, and the silicon film 58 (see FIG. 11B).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film is etched back by, for example, the EB (etch back) method until the surface of the TiN film is exposed.
  • the conductor plug 70 made of tungsten is loaded in the contact hole 68 (see FIG. 12A).
  • an AlCu alloy film having a thickness of 500 nm, and a Ti film having a thickness of 5 nm for example,
  • a TiN film having a thickness of 150 nm is sequentially stacked.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the second metal wiring layer 72 that is, the wiring 72a and the wiring 72b electrically connected to the conductor plug 70 are formed (see FIG. 12B).
  • a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 13A).
  • the surface of the silicon oxide film 74 is flattened by, eg, CMP (see FIG. 13B).
  • This heat treatment is for removing water in the silicon oxide film 74 and changing the film quality of the silicon oxide film 74 so that the water does not easily enter the silicon oxide film 74.
  • the surface of the silicon oxide film 74 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 74.
  • a silicon oxide film 76 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD. Since the silicon oxide film 76 is formed on the planarized silicon oxide film 74, the silicon oxide film 76 becomes flat. [0151] Next, in a plasma atmosphere generated using NO gas or N gas, for example, 35
  • This heat treatment is for removing moisture in the silicon oxide film 76 and changing the film quality of the silicon oxide film 76 to make it difficult for moisture to enter the silicon oxide film 76.
  • the surface of the silicon oxide film 76 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 76.
  • a barrier film 78 is formed on the flat silicon oxide film 76 by, eg, sputtering or CVD.
  • the barrier film 78 for example, an aluminum oxide film having a thickness of 2070 nm is formed.
  • an aluminum oxide film having a thickness of 50 nm is formed as the noor film 78. Since the barrier film 78 is formed on the flat silicon oxide film 76, the barrier film 78 becomes flat.
  • a silicon oxide film 80 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 14 (a)).
  • the interlayer insulating film 82 is constituted by zero.
  • This heat treatment is for removing moisture in the silicon oxide film 80 and changing the film quality of the silicon oxide film 76 so that moisture does not easily enter the silicon oxide film 80.
  • the surface of the silicon oxide film 80 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 80.
  • contact horns 84a and 84b reaching the wirings 72a and 72b are formed in the silicon oxide film 80, the barrier film 78, the silicon oxide film 76, and the silicon oxide film 74 by photolithography and dry etching (FIG. 14). (See (b)).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film is etched until the surface of the TiN film is exposed, for example, by the EB method. Chibak back. In this way, the conductor plugs 86a and 86b made of tungsten are loaded in the contact holes 84a and 84b, respectively (see FIG. 15 (a)).
  • an AlCu alloy film having a thickness of, for example, 500 nm and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the third metal wiring layer 88 that is, the wiring 88a electrically connected to the conductor plug 86a and the wiring 88b electrically connected to the conductor plug 88b are formed (see FIG. 15 (b)). ).
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • This heat treatment is for removing moisture in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that moisture does not easily enter the silicon oxide film 90.
  • the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
  • the silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • an opening 108 is formed in the photoresist film 106 to expose a region where the opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90. .
  • Etch 90 an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90 (see FIG. 16B). Thereafter, the photoresist film 106 is peeled off.
  • a polyimide resin film 94 having a film thickness of 2 to 6 ⁇ m is formed by spin coating, for example. (See Fig. 17 (a)).
  • an opening 96b reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94 by photolithography (see FIG. 17B).
  • the semiconductor device according to the present embodiment is manufactured.
  • a PTHS test is performed on the semiconductor device according to the present embodiment, and the results of evaluating the PTHS characteristics of the semiconductor device according to the present embodiment are described.
  • the FeRAM chip of the semiconductor device according to the present embodiment was stored under conditions of 2 atm, temperature of 121 ° C, and humidity of 100%, and 168 hours, 336 hours, 504 hours, 504 hours, and 672 At each time point, the presence or absence of defective cells was confirmed for each of the five chip samples formed using the same woofer.
  • the thickness of the barrier film 58 was set to 20 nm
  • the thickness of the flat barrier film 62 was set to 50 nm
  • the monthly thickness of the flat rear film 78 was set to 70 nm.
  • the PTHS test similar to the above was performed when the flat barrier film 58 was not formed, that is, when only one flat barrier film was formed.
  • the thickness of the barrier film 58 was set to 70 nm
  • the thickness of the flat barrier film 78 was set to 70 nm.
  • the thickness of the barrier film 58 was 2 Onm
  • the thickness of the flat barrier film 78 was 50 nm.
  • the structure of the semiconductor device according to Comparative Examples 1 and 2 was the same as that of the semiconductor device according to the present embodiment except that the flat barrier film 58 was not formed.
  • defective cells occur at all of 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours for all five chip samples. There was no.
  • one of the five chip samples had one defective cell after 168 hours, and three defective cells after 336 hours. When 504 hours passed, there were 10 defective cells, and when 672 hours passed, there were 18 bad cells. For other chip samples, 168 hours and 336 hours have passed. No defective cells were generated up to the time point, but one defective cell was generated after 504 hours, and 26 defective cells were reached after 672 hours. Furthermore, in other chip samples, no defective cells were generated until 168 hours and 336 hours passed, but 22 defective cells were generated after 504 hours and failed after 672 hours passed. There were 62 Senores. Of the five chip samples, only two chip samples had no defective cells at any time after 168 days temple, 3363 temples, 504 days temple, 504 hours, and 672 hours. there were.
  • the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved, and the mass production certification level of the PTHS test for FeRAM is sufficiently exceeded. It was confirmed that it was possible.
  • the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided.
  • the electrical characteristics of the ferroelectric capacitor 42 can be reliably prevented from being deteriorated by hydrogen and moisture, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • FIG. 18 is a sectional view showing the structure of the semiconductor device according to the present embodiment.
  • FIGS. 19 to 21 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the present embodiment further includes a NOR film 114 formed above the third metal wiring layer 88 (wirings 88a and 88b).
  • a silicon oxide film 112 having a thickness of, eg, 1500 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b.
  • the surface of the silicon oxide film 112 is flattened by, for example, CMP after the formation thereof, and the silicon oxide film 112 on the wiring 88b remains, for example, with a film thickness of 350 nm.
  • a silicon film 114 is formed on the flattened silicon oxide film 112.
  • the barrier film 114 for example, an aluminum oxide film having a thickness of 2070 nm is used. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the barrier film 114 is flat.
  • the barrier film 114 like the barrier films 44, 46, 58, 62, 78, diffuses hydrogen and moisture. It is a film having a function to prevent. Further, since the barrier film 114 is formed on the flattened silicon oxide film 112, it is flat, and in the same way as the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, the barrier film 114 is extremely flat. It is formed with good coverage. Accordingly, such a flat barrier film 114 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 114 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit area, etc. It is formed over the entire surface of the FeRAM chip including
  • a silicon oxide film 90 having a thickness of 50 to 150 nm is formed on the barrier film 114.
  • a silicon nitride film 92 having a thickness of 350 nm is formed on the silicon oxide film 90.
  • a polyimide resin film 94 with a film thickness of 36 ⁇ m is formed on the silicon nitride film 92.
  • the polyimide resin film 94, the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 have an opening 96 reaching the wiring (bonding pad) 88b. That is, in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112.
  • the semiconductor device according to the present embodiment is formed above the ferroelectric capacitor 42 in addition to the barrier films 44, 46, and 58 as a barrier film for preventing diffusion of hydrogen and moisture.
  • the main feature is that it has a flat barrier film 114.
  • the semiconductor device according to the present embodiment is flat in the semiconductor device according to the first embodiment.
  • the flat barrier film 114 is formed above the third metal wiring layer 88, so that the hydrogen and moisture are more securely barriered, and the hydrogen and moisture are ferroelectric capacitors. Reaching the ferroelectric film 38 of 42 can be prevented more reliably. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved.
  • the third metal wiring layer (wiring 88a, wiring 88b) is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS.
  • a silicon oxide film 112 of, eg, a 1500 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 19A).
  • the surface of the silicon oxide film 112 is planarized by, eg, CMP (see FIG. 19B).
  • This heat treatment is for removing moisture in the silicon oxide film 112 and changing the film quality of the silicon oxide film 112 so that the moisture does not easily enter the silicon oxide film 112.
  • the surface of the silicon oxide film 112 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 112.
  • a barrier film 114 is formed on the flattened silicon oxide film 112 by, eg, sputtering or CVD.
  • the nore film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the NOR film 114 becomes flat.
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
  • the silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • an opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 in the photoresist film 106 by photolithography.
  • An opening 108 exposing the region is formed.
  • the photoresist film 106 is peeled off.
  • the semiconductor device according to the present embodiment is manufactured.
  • the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided.
  • the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the ferroelectric capacitor 42 can be prevented.
  • the PTHS characteristics of a semiconductor device having a shita can be further greatly improved.
  • FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment.
  • FIGS. 23 and 24 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the first embodiment in that it further includes a flat barrier film 116 between the ferroelectric capacitor 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). This is different from the semiconductor device.
  • the rear film 116 is formed on the interlayer insulating film 48 on which the conductor plugs 50a and 50b are carried.
  • the barrier film 116 for example, an aluminum oxide film having a thickness of 20 to 70 ⁇ m is used.
  • the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 is flat.
  • the barrier film 116 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 116 is formed on the flattened silicon oxide film 48, it is flat, and, like the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, It is formed with good coverage. Therefore, such a flat barrier film 116 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 116 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, as in the barrier films 62 and 78, but also the peripheral circuit area. Etc. are formed over the entire surface of the FeRAM chip.
  • a silicon oxide film 118 having a thickness of lOOnm is formed on the barrier film 116.
  • a contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the barrier film 44. Also silicon acid A contact hole 52b reaching the lower electrode 36 is formed in the oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44.
  • a contact hole 120a reaching the conductor plug 54a is formed in the silicon oxide film 118 and the barrier film 116. Further, a contact hole 120b reaching the conductor plug 54b is formed in the silicon oxide film 118 and the barrier film 116.
  • a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the silicon oxide film 118, in the contact hole 52a, and in the contact hole 120a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 118 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 118 and in the contact hole 120b.
  • the ferroelectric film 42 and the ferroelectric capacitor are used as the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, and 58.
  • the ferroelectric capacitor 42 and the first metal formed above the ferroelectric capacitor 42 in addition to the flat barrier films 62 and 78 in the semiconductor device according to the first embodiment. Since the flat barrier film 116 is formed between the wiring layer 56 and the barrier layer 116, hydrogen and moisture are more securely blocked, and the hydrogen and moisture reach the ferroelectric film 38 of the ferroelectric capacitor 42 more reliably. Can be prevented. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
  • the conductor plugs 54a and 54b are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 4 to 7, FIG. 8A, and FIG. see a)).
  • NOR film 116 is formed by, for example, sputtering or CVD.
  • the noria film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 becomes flat.
  • a silicon oxide film 118 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 23B).
  • contact holes 120a and 120b reaching the conductor plugs 54a and 54b are formed in the silicon oxide film 118 and the barrier film 116 by photolithography and dry etching (see FIG. 23C).
  • an SiON film 122 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD (see FIG. 24A).
  • the upper portion of the ferroelectric capacitor 42 is formed on the SiONfl layer 122, the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44 by photolithography and dry etching.
  • a contact hole 52a reaching the electrode 40 and a contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 are formed (see FIG. 24B).
  • heat treatment is performed in an oxygen atmosphere, for example, at 500 ° C for 60 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the SiON film 122 is removed by etching.
  • a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm, for example, are sequentially laminated on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • the barrier films 44, 46, and 58 are used as barrier films for preventing the diffusion of hydrogen and moisture, and the ferroelectric capacitors 42 and the ferroelectric capacitors 42 are formed.
  • the capacitor 42 can be further reliably prevented from reaching the ferroelectric film 38. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
  • ferroelectric film 38 is not limited to the PZT film, but is any other ferroelectric film. Can be used as appropriate.
  • ferroelectric film 38 Pb La Zr Ti O
  • a 1-X X 1-Y Y 3 film (PLZT film), an SrBi (Ta Nb) O film, a BiTi O film, or the like may be used.
  • the lower electrode 36 is composed of the laminated film of the aluminum oxide film 36a and the Pt film 36b.
  • the material of the conductor film or the like that constitutes the lower electrode 36 is limited to the force and the material. It ’s not something that ’s fixed.
  • Ir film, IrO film, Ru film, RuO film, SrRuO stront
  • the lower electrode 38 may be composed of a (muruthenium oxide) film (SR film) or a Pd film.
  • SR film a (muruthenium oxide) film
  • Pd film a film that is laminated film of the IrO film 40a and the IrO film 40b.
  • upper electrode 40 is composed of Ir film, Ru film, RuO film, SRO film, Pd film
  • the barrier film 62 is formed between the first metal wiring layer 56 and the second metal wiring layer 72, and the second metal wiring is formed.
  • the case where the barrier film 78 is formed between the layer 72 and the third metal wiring layer 88 will be described.
  • the barrier film 62, 78 and the barrier above the third metal wiring layer 88 are described.
  • the case where the film 114 is formed will be described.
  • the case where the barrier film 116 is formed between the ferroelectric capacitor 42 and the first metal wiring layer 56 in addition to the barrier films 62 and 78 will be described.
  • the flat barrier film may be formed by forming at least two layers of the barrier films 62, 78, 114, and 116, and / or three layers of the rear layers 62, 78, 114, and 116. Alternatively, all four layers of 62, 78, 114, and 116 may be formed. Further, more flat barrier films may be formed according to the number of metal wiring layers formed on the semiconductor substrate 10.
  • the noria film is not limited to the aluminum oxide film.
  • a film having a function of preventing diffusion of hydrogen or moisture can be appropriately used as the barrier film.
  • the silicon film for example, a film made of a metal oxide can be used as appropriate.
  • the barrier film made of a metal oxide for example, tantalum oxide or titanium oxide can be used.
  • the barrier film is not limited to a film made of a metal oxide.
  • silicon nitride film (SiN film) or silicon nitride oxide film (SiON film) should be used as the barrier film.
  • a coating type oxide film or an organic film having a hygroscopic property such as a resin film made of polyimide, polyarylene, polyarylene ether, benzocyclobutene, or the like can be used as the barrier film.
  • barrier film made of the same material is used for all the barrier films to be formed.
  • the barrier film made of different materials Can also be used as appropriate.
  • an aluminum oxide film is used as the barrier film 62 formed closest to the ferroelectric capacitor 42 among the flat barrier films 62, 78, 114.
  • a silicon nitride film may be used as the barrier film 78 or the barrier film 114 formed above the noria film 62.
  • a film made of a metal oxide such as an aluminum oxide film or a silicon nitride film As a flat barrier film 114 formed above the third metal wiring layer 88 and having an opening 96b reaching the wiring (bonding pad) 88b, an organic material having a hygroscopic property is used. You can also form a film.
  • the case where the CMP method is used as a method for planarizing the surface of the insulating film constituting the interlayer insulating film has been described as an example. It is not limited to the law.
  • the surface of the insulating film may be flattened by etching.
  • As an etching gas for example, Ar gas can be used.
  • the circuit is formed on the semiconductor substrate 10 by the three metal wiring layers of the first metal wiring layer 56, the second metal wiring layer 72, and the third metal wiring layer 88.
  • the number of metal wiring layers constituting the circuit on the semiconductor substrate 10 is not limited to three. The number of metal wiring layers can be appropriately set according to the design of the circuit configured on the semiconductor substrate 10.
  • a case where a 1T1 C type memory cell having one transistor 24 and one ferroelectric capacitor 42 is formed has been described as an example, but the configuration of the memory cell is It is not limited to 1T1C type.
  • the configuration of the memory cell in addition to the 1T1C type, various configurations such as a 2T2C type having two transistors and two ferroelectric capacitors can be used.
  • a FeRAM structure semiconductor device having a planar type cell In the above-described embodiment, a FeRAM structure semiconductor device having a planar type cell.
  • the scope of the present invention is not limited to this.
  • the present invention can also be applied to a FeRA M structure semiconductor device having a stack type cell and having a gate length set to, for example, 0.18 ⁇ m.
  • FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having a stack type cell to which the present invention is applied.
  • an element isolation region 212 that defines an element region is formed on a semiconductor substrate 210 made of, for example, silicon.
  • Uenoles 214a and 214b are formed in the semiconductor substrate 210 in which the element isolation region 212 is formed.
  • a gate electrode (gate wiring) 218 is formed on the semiconductor substrate 210 on which the wells 214a and 214b are formed via a gate insulating film 216.
  • the gate electrode 218 has, for example, a polycide structure in which a metal silicide film such as a cobalt silicide film, a nickel silicide film, or a tungsten silicide film is stacked on a polysilicon film in accordance with the gate length of the transistor.
  • a silicon oxide film 219 is formed on the gate electrode 218.
  • Sidewall insulating films 220 are formed on the side walls of the gate electrode 218 and the silicon oxide film 219.
  • a source / drain diffusion layer 222 is formed on both sides of the gate electrode 218 on which the sidewall insulating film 220 is formed.
  • the transistor 224 having the gate electrode 218 and the source / drain diffusion layer 222 is formed.
  • the gate length of the transistor 224 is set to, for example, 0.18 / im.
  • an interlayer insulating film 227 formed by sequentially laminating a SiON film 225 and a silicon oxide film 226 is formed on the semiconductor substrate 210 on which the transistor 224 is formed.
  • the surface of the interlayer insulating film 227 is planarized.
  • a barrier film 228 made of, for example, an aluminum oxide film is formed on the interlayer insulating film 227.
  • Contact barriers 230a and 230b force S reaching the source / drain diffusion layer 222 are formed in the barrier film 228 and the interlayer insulating film 227, and are reduced.
  • Barrier methanol films (not shown) formed by sequentially laminating Ti films and TiN films are formed in the contact holes 230a and 230b.
  • Conductor plugs 232a and 232b made of tungsten are buried in the contact holes 230a and 230b in which the barrier metal film is formed.
  • an Ir film 234 electrically connected to the conductor plug 232a is formed on the barrier film 228, an Ir film 234 electrically connected to the conductor plug 232a is formed.
  • a ferroelectric film 238 of the ferroelectric capacitor 242 is formed on the lower electrode 236.
  • the upper electrode 240 of the ferroelectric capacitor 242 is formed.
  • the upper electrode 240, the ferroelectric film 238, the lower electrode 236, and the Ir film 234 that are laminated are patterned together by etching and have substantially the same planar shape.
  • a ferroelectric capacitor 242 composed of the lower electrode 236, the ferroelectric film 238, and the upper electrode 240 is formed.
  • the lower electrode 236 of the ferroelectric capacitor 242 is electrically connected to the conductor plug 232a via the Ir film 234.
  • a SiON film 244 having a film thickness comparable to or thinner than the Ir film 234 is formed on the region of the interlayer insulating film 227 where the Ir film 234 is not formed.
  • a silicon oxide film may be formed on the region of the interlayer insulating film 227 where the Ir film 234 is not formed.
  • a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed on the ferroelectric capacitor 242 and the SiON film 244.
  • a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • a silicon oxide film 248 is formed on the barrier film 246, and the strong dielectric capacitor 242 is embedded by the silicon oxide film 248.
  • the surface of the silicon oxide film 248 is planarized.
  • a flat barrier film 250 having a function of preventing the diffusion of hydrogen and moisture is formed on the planarized silicon oxide film 248, a flat barrier film 250 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • the nore film 250 for example, an anolymium oxide film is used.
  • a silicon oxide film 252 is formed on the barrier film 250.
  • An interlayer insulating film 253 is constituted by the con oxide film 252.
  • a contact hole 254a reaching the upper electrode 240 of the ferroelectric capacitor 242 is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, and the barrier film 246.
  • a contact hole 254b reaching the conductor plug 232b is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, the noria film 246, and the SiON film 244.
  • a barrier metal film (not shown) formed by sequentially stacking a Ti film and a TiN film is formed. As a barrier metal film, without forming a Ti film
  • a barrier metal film made of a TiN film may be formed.
  • Conductive plugs 256a and 256b made of tungsten are respectively carried in the contact holes 254a and 254b in which the barrier metal film is formed.
  • a wiring 258a electrically connected to the conductor plug 256a and a wiring 258b electrically connected to the conductor plug 256b are formed.
  • a silicon oxide film 260 is formed on the silicon oxide film 252 on which the wirings 258a and 258b are formed, and the self-insulating lines 258a and 258b are applied by the silicon oxide film 260.
  • the surface of the silicon oxide film 260 is flattened.
  • a flat barrier film 262 having a function of preventing the diffusion of hydrogen and moisture is formed on the flattened silicon oxide film 260.
  • the noria film 262 for example, an anolymium oxide film is used.
  • a silicon oxide film 264 is formed on the barrier film 262.
  • the interlayer insulating film 265 is constituted by the silicon oxide film 260, the silicon rear film 262, and the silicon oxide film 264.
  • a contact hole 268 reaching the wiring 258b is formed in the silicon oxide film 264, the barrier film 262, and the silicon oxide film 260.
  • a barrier metal film (not shown) is formed by sequentially stacking a Ti film and a TiN film.
  • a conductor plug 270 made of tungsten is loaded in the contact hole 268 in which the barrier metal film is formed.
  • a wiring 272 electrically connected to the conductor plug 268 is formed on the silicon oxide film 264.
  • a silicon oxide film 274 is formed on the silicon oxide film 264 on which the wiring 272 is formed, and the wiring 272 is embedded by the silicon oxide film 274.
  • the surface of the silicon oxide film 274 is flattened.
  • a flat barrier film 276 having a function of preventing the diffusion of hydrogen and moisture is formed on the planarized silicon oxide film 274.
  • a flat barrier film 276 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • a silicon oxide film 278 is formed on the barrier film 276.
  • the flat barrier films 250, 262, and 276 that prevent the diffusion of hydrogen and moisture are formed as in the above-described embodiment.
  • the flat barrier film for preventing the diffusion of hydrogen and moisture is sufficient if at least two layers are formed, and all three layers of the rear films 250, 262, and 276 are formed. It does not have to be. Further, if necessary, a larger number of flat rear films may be formed.
  • the semiconductor device and the manufacturing method thereof according to the present invention are useful for improving the reliability of a semiconductor device having a ferroelectric capacitor.

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Abstract

A semiconductor device comprising a ferroelectric capacitor (42) formed on a semiconductor substrate (10) and having a lower electrode (36), a ferroelectric film (38) formed on the lower electrode (36), and an upper electrode (40) formed on the ferroelectric film (38), a silicon oxide film (60) formed on the semiconductor substrate (10) and the ferroelectric capacitor (42) and having a planarized surface, a planar barrier film (62) formed on the silicon oxide film (60) via a silicon oxide film (61) and preventing diffusion of hydrogen or moisture, a silicon oxide film (74) formed on the barrier film (62) and having a planarized surface, and a planar barrier film (78) formed on the silicon oxide film (74) via a silicon oxide film (76) and preventing diffusion of hydrogen or moisture.

Description

明 細 書  Specification
半導体装置及びその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、半導体装置及びその製造方法に係り、特に強誘電体キャパシタを有す る半導体装置及びその製造方法に関する。  TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.
背景技術  Background art
[0002] 近時、キャパシタの誘電体膜として強誘電体膜を用いることが注目されている。この ような強誘電体キャパシタを用いた強誘電体メモリ（FeRAM： Ferroelectric Random Access Memory)は、高速動作が可能である、低消費電力である、書き込み/読み出 し耐久性に優れている等の特徴を有する不揮発性メモリであり、今後の更なる発展が 見込まれている。  Recently, attention has been focused on the use of a ferroelectric film as a dielectric film of a capacitor. Ferroelectric Random Access Memory (FeRAM) using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, and excellent write / read durability. It is a non-volatile memory with features, and further development is expected in the future.
[0003] し力しながら、強誘電体キャパシタは、外部からの水素ガスや水分により容易にそ の特性が劣化するという性質を有している。具体的には、 Pt膜よりなる下部電極と、 P ZT膜よりなる強誘電体膜と、 Pt膜よりなる上部電極とが順次積層されてなる標準的 な FeRAMの強誘電体キャパシタの場合、水素分圧 40Pa (0. 3Torr)程度の雰囲 気にて 200°C程度の温度に基板を加熱すると、 PbZr Ti O膜 (PZT膜）の強誘電  [0003] However, the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. Specifically, in the case of a standard FeRAM ferroelectric capacitor in which a lower electrode made of a Pt film, a ferroelectric film made of a PZT film, and an upper electrode made of a Pt film are sequentially stacked, When the substrate is heated to a temperature of about 200 ° C in an atmosphere with a partial pressure of 40 Pa (0.3 Torr), the ferroelectricity of the PbZr Ti O film (PZT film)
1— X X 3  1—X X 3
性はほぼ失われてしまうことが知られている。また、強誘電体キャパシタが水分を吸着 した状態、或いは水分が強誘電体キャパシタの近傍に存在する状態にて熱処理を行 うと、強誘電体キャパシタの強誘電体膜の強誘電性は、著しく劣化してしまうことが知 られている。  It is known that sex is almost lost. In addition, if the heat treatment is performed with the ferroelectric capacitor adsorbing moisture or in the vicinity of the ferroelectric capacitor, the ferroelectricity of the ferroelectric film of the ferroelectric capacitor is significantly deteriorated. It is known to end up.
[0004] このような強誘電体キャパシタの性質のため、 FeRAMの製造工程においては、強 誘電体膜を形成した後のプロセスとして、可能な限り、水分の発生が少なぐ且つ低 温のプロセスが選択されている。また、層間絶縁膜を成膜するプロセスには、例えば 、水素の発生量の比較的少ない原料ガスを用いた CVD (Chemical Vapor  [0004] Due to the properties of such a ferroelectric capacitor, in the manufacturing process of FeRAM, as a process after forming a ferroelectric film, a process that generates as little moisture as possible and has a low temperature is possible. Is selected. In the process of forming an interlayer insulating film, for example, CVD (Chemical Vapor using a source gas with a relatively small amount of hydrogen generation)
Deposition)法等による成膜プロセスが選択されている。  A film forming process by the Deposition method or the like is selected.
[0005] さらには、水素や水分による強誘電体膜の劣化を防止する技術として、強誘電体キ ャパシタを覆うように酸化アルミニウム膜を形成する技術や、強誘電体キャパシタ上に 形成された層間絶縁膜上に酸化アルミニウム膜を形成する技術が提案されている。 酸化アルミニウム膜は、水素や水分の拡散を防止する機能を有している。このため、 提案されている技術によれば、水素や水分が強誘電体膜に達するのを防止すること ができ、水素や水分による強誘電体膜の劣化を防止することが可能となる。このような 技術は、例えば特許文献 1一 5に記載されている。 [0005] Furthermore, as a technique for preventing the deterioration of the ferroelectric film due to hydrogen or moisture, a technique for forming an aluminum oxide film so as to cover the ferroelectric capacitor, or a technique for forming a ferroelectric capacitor on the ferroelectric capacitor. A technique for forming an aluminum oxide film on the formed interlayer insulating film has been proposed. The aluminum oxide film has a function of preventing diffusion of hydrogen and moisture. Therefore, according to the proposed technique, it is possible to prevent hydrogen and moisture from reaching the ferroelectric film, and it is possible to prevent the ferroelectric film from being deteriorated by hydrogen and moisture. Such a technique is described in, for example, Patent Documents 1-15.
特許文献 1 :特開 2003 - 197878号公報  Patent Document 1: JP 2003-197878 A
特許文献 2 :特開 2001— 68639号公報  Patent Document 2: JP 2001-68639 A
特許文献 3 :特開 2003 - 174145号公報  Patent Document 3: Japanese Patent Laid-Open No. 2003-174145
特許文献 4 :特開 2002— 176149号公報  Patent Document 4: Japanese Patent Laid-Open No. 2002-176149
特許文献 5：特開 2003 - 100994号公報  Patent Document 5: Japanese Patent Laid-Open No. 2003-100994
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] 上述のように、強誘電体キャパシタは外部からの水素ガスや水分により容易にその 特性が劣化するという性質を有している。このため、従来の FeRAMは、加速寿命試 験の一つである PTHS (Pressure Temperature Humidity Stress)試験について良好 な試験結果を得ることが困難であった。 [0006] As described above, the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. For this reason, it has been difficult for conventional FeRAMs to obtain good test results for the PTHS (Pressure Temperature Humidity Stress) test, which is one of the accelerated life tests.
[0007] 通常、 PTHS試験は、 JEDEC (Joint Electron Device Engineering Council)規格等 に基づき、例えば温度 135°C、湿度 85%の条件下で行われている。このような PTH[0007] Normally, the PTHS test is performed under conditions of, for example, a temperature of 135 ° C and a humidity of 85% based on the JEDEC (Joint Electron Device Engineering Council) standard. PTH like this
S試験では、 FeRAMの水素に対する耐性や耐湿性が充分に確保されていないと、 強誘電体キャパシタが劣化し、不良が発生してしまう。 In the S test, if the resistance and moisture resistance of FeRAM are not sufficiently secured, the ferroelectric capacitor deteriorates and a defect occurs.
[0008] これまでに、水素や水分による強誘電体膜の劣化を防止する技術が提案されては いるものの、強誘電体キャパシタを有する FeRAM等の半導体装置の PTHS特性を 向上し、 PTHS試験について量産認定レベルを充分に上回るような良好な試験結果 を得ることを可能とするには、これまでの技術は充分なものではなかった。 [0008] Although techniques for preventing deterioration of the ferroelectric film due to hydrogen and moisture have been proposed so far, the PTHS characteristics of semiconductor devices such as FeRAM with ferroelectric capacitors have been improved and PTHS tests have been conducted. Previous technologies have not been sufficient to make it possible to obtain good test results well above the mass production certification level.
[0009] 本発明の目的は、水素ガスに対する耐性及び耐湿性に優れ、強誘電体キャパシタ の特性の劣化を充分に抑制し、 PTHS特性を向上しうる半導体装置及びその製造 方法を提供することにある。 An object of the present invention is to provide a semiconductor device that is excellent in resistance to hydrogen gas and moisture resistance, sufficiently suppresses deterioration of characteristics of a ferroelectric capacitor, and can improve PTHS characteristics, and a method for manufacturing the same. is there.
課題を解決するための手段 [0010] 本発明の一観点によれば、半導体基板上に形成され、下部電極と、前記下部電極 上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極とを有する 強誘電体キャパシタと、前記半導体基板上及び前記強誘電体キャパシタ上に形成さ れ、表面が平坦化された第 1の絶縁膜と、前記第 1の絶縁膜上に形成され、水素又 は水分の拡散を防止する平坦な第 1のバリア膜と、前記第 1のバリア膜上に形成され 、表面が平坦化された第 2の絶縁膜と、前記第 2の絶縁膜上に形成され、水素又は 水分の拡散を防止する平坦な第 2のバリア膜とを有する半導体装置が提供される。 Means for solving the problem According to an aspect of the present invention, a lower electrode formed on a semiconductor substrate, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, A ferroelectric capacitor comprising: a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film; Is formed on the flat first barrier film for preventing the diffusion of moisture, the second barrier film having a planarized surface, and the second insulating film formed on the first barrier film. There is provided a semiconductor device having a flat second barrier film that prevents diffusion of hydrogen or moisture.
[0011] また、本発明の他の観点によれば、半導体基板上に、下部電極と、前記下部電極 上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極とを有する 強誘電体キャパシタを形成する工程と、前記半導体基板上及び前記強誘電体キヤ パシタ上に、第 1の絶縁膜を形成する工程と、前記第 1の絶縁膜の表面を平坦化す る工程と、前記第 1の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 1のバ リア膜を形成する工程と、前記第 1のバリア膜上に、第 2の絶縁膜を形成する工程と、 前記第 2の絶縁膜の表面を平坦化する工程と、前記第 2の絶縁膜上に、水素又は水 分の拡散を防止する平坦な第 2のバリア膜を形成する工程とを有する半導体装置の 製造方法が提供される。 [0011] According to another aspect of the present invention, a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film on a semiconductor substrate. Forming a ferroelectric capacitor having: a step of forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor; and planarizing a surface of the first insulating film. Forming a flat first barrier film for preventing diffusion of hydrogen or moisture on the first insulating film; and forming a second insulating film on the first barrier film. A step of planarizing the surface of the second insulating film, and a step of forming a flat second barrier film for preventing diffusion of hydrogen or water on the second insulating film. A method for manufacturing a semiconductor device is provided.
発明の効果  The invention's effect
[0012] 本発明によれば、半導体基板上に形成され、下部電極と、前記下部電極上に形成 された強誘電体膜と、強誘電体膜上に形成された上部電極とを有する強誘電体キヤ パシタを有する半導体装置において、半導体基板上及び強誘電体キャパシタ上に 形成され、表面が平坦化された第 1の絶縁膜と、第 1の絶縁膜上に形成され、水素又 は水分の拡散を防止する平坦な第 1のバリア膜と、第 1のバリア膜上に形成され、表 面が平坦化された第 2の絶縁膜と、第 2の絶縁膜上に形成され、水素又は水分の拡 散を防止する平坦な第 2のバリア膜とが形成されているので、水素及び水分を確実 にバリアし、水素及び水分が強誘電体キャパシタの強誘電体膜に達するのを確実に 防止することができる。これにより、水素及び水分による強誘電体キャパシタの電気 的特性の劣化を確実に防止することができ、強誘電体キャパシタを有する半導体装 置の PTHS特性を大幅に向上することができる。 図面の簡単な説明 According to the present invention, a ferroelectric formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. In a semiconductor device having a body capacitor, a first insulating film formed on a semiconductor substrate and a ferroelectric capacitor and having a flattened surface and a first insulating film are formed. A flat first barrier film that prevents diffusion, a second insulating film that is formed on the first barrier film and has a flattened surface, and a second insulating film that is formed on the second insulating film. A flat second barrier film that prevents the diffusion of hydrogen is formed, so that hydrogen and moisture are securely blocked, and hydrogen and moisture are prevented from reaching the ferroelectric film of the ferroelectric capacitor. can do. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved. Brief Description of Drawings
[図 1]図 1は、本発明の第 1実施形態による半導体装置の構造を示す断面図である。 FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
[図 2]図 2は、本発明の第 1実施形態による半導体装置の効果を説明する図（その 1) である。 FIG. 2 is a diagram (part 1) for explaining an effect of the semiconductor device according to the first embodiment of the present invention.
[図 3]図 3は、本発明の第 1実施形態による半導体装置の効果を説明する図（その 2) である。  FIG. 3 is a view (No. 2) for explaining the effect of the semiconductor device according to the first embodiment of the invention.
[図 4]図 4は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 1)である。  FIG. 4 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 5]図 5は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 2)である。  FIG. 5 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 6]図 6は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 3)である。  FIG. 6 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 7]図 7は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 4)である。  FIG. 7 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 8]図 8は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 5)である。  FIG. 8 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
[図 9]図 9は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断面 図（その 6)である。  FIG. 9 is a process cross-sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 10]図 10は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 7)である。  FIG. 10 is a process sectional view (No. 7) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
[図 11]図 11は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 8)である。  FIG. 11 is a process cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 12]図 12は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 9)である。  FIG. 12 is a process cross-sectional view (No. 9) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
[図 13]図 13は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 10)である。  FIG. 13 is a process cross-sectional view (No. 10) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
[図 14]図 14は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 11)である。 [図 15]図 15は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 12)である。 FIG. 14 is a process cross-sectional view (No. 11) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention. FIG. 15 is a process sectional view (No. 12) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 16]図 16は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 13)である。  FIG. 16 is a process cross-sectional view (No. 13) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 17]図 17は、本発明の第 1実施形態による半導体装置の製造方法を示す工程断 面図（その 14)である。  FIG. 17 is a process sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
[図 18]図 18は、本発明の第 2実施形態による半導体装置の構造を示す断面図であ る。  FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention.
[図 19]図 19は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 1)である。  FIG. 19 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
[図 20]図 20は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 2)である。  FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
[図 21]図 21は、本発明の第 2実施形態による半導体装置の製造方法を示す工程断 面図（その 3)である。  FIG. 21 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
[図 22]図 22は、本発明の第 3実施形態による半導体装置の構造を示す断面図であ る。  FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
[図 23]図 23は、本発明の第 3実施形態による半導体装置の製造方法を示す工程断 面図（その 1)である。  FIG. 23 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention;
[図 24]図 24は、本発明の第 3実施形態による半導体装置の製造方法を示す工程断 面図（その 2)である。  FIG. 24 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
[図 25]図 25は、本発明を適用したスタック型セルを有する FeRAM構造の半導体装 置の構造を示す断面図である。  FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having stacked cells to which the present invention is applied.
符号の説明 Explanation of symbols
10…半導体基板 10 ... Semiconductor substrate
12…素子分離領域  12 ... Element isolation region
14a、 14b…ゥエル 14a, 14b ... well
16…ゲート絶縁膜 16 ... Gate insulation film
18…ゲート電極 …絶縁膜 18 ... Gate electrode ... Insulating film
…サイドウォール絶縁膜 …ソース/ドレイン拡散層 …トランジスタ… Sidewall insulation film… Source / drain diffusion layer… Transistor
"-Si〇N膜 "-Si〇N film
…シリコン酸化膜 …層間絶縁膜 …シリコン酸化膜... Silicon oxide film ... Interlayer insulating film ... Silicon oxide film
···下部電極.... Lower electrode
a…酸化アルミニウム膜b"-Pt膜 a ... Aluminum oxide film b "-Pt film
…強誘電体膜 ... Ferroelectric film
…上部電極... Upper electrode
a- --IrO膜 a- --IrO film
X X
b- · -IrO膜 b- · -IrO film
Υ  Υ
…強誘電体キャパシタ···バリア膜 ... Ferroelectric capacitor ... Barrier film
…バリア膜 ... Barrier film
…層間絶縁膜... Interlayer insulation film
a、 50b…コンタクトホールa、 52b…コンタクトホールa、 54b…導体プラグ …第 1金属配線層ax 56b, 56c-'' ti線 …バリア膜 a, 50b ... contact hole a, 52b ... contact hole a, 54b ... conductor plug ... first metal wiring layer a x 56b, 56c- '' ti wire ... barrier film
…シリコン酸化膜 …シリコン酸化膜 …バリア膜 …シリコン酸化膜 …層間絶縁膜 …コンタクトホール …導体プラグ …第 2金属配線層a, 72b…配線 …シリコン酸化膜 …シリコン酸化膜 …バリア膜 …シリコン酸化膜 …層間絶縁膜a、 84b…コンタクトホa、 86b…導体プラグ …第 3金属配線層a, 88b…配線... Silicon oxide film ... Silicon oxide film ... Barrier film ... Silicon oxide film ... Interlayer insulation film ... Contact hole ... Conductor plug ... Second metal wiring layer a, 72b ... Wiring ... Silicon oxide film ... Silicon oxide film ... Barrier film ... Silicon oxide film ... Interlayer insulation film a, 84b ... Contact a, 86b ... Conductor plug ... Third metal wiring layer a, 88b ... Wiring
· · ·シリコン酸化膜· · ·シリコン ィ匕月莫 …ポリイミド樹脂膜 …開口部· · · Silicon oxide film · · · Silicon
a…開口部a… Opening
b…開口部 …フォトレジスト膜0…フォトレジスト膜2…フォトレジスト膜4 SiON膜b: Opening ... Photoresist film 0 ... Photoresist film 2 ... Photoresist film 4 SiON film
6…フォトレジスト膜8…開口部6 ... Photoresist film 8 ... Opening
0…欠陥部分 112…シリコン酸化膜 0 ... Defects 112 ... Silicon oxide film
114…バリア膜  114… Barrier film
116…バリア膜  116… Barrier film
118…シリコン酸化膜  118 ... Silicon oxide film
120a, 120b…コンタクトホーノレ 120a, 120b… Contact Honoré
122 SiON膜 122 SiON film
210…半導体基板  210 ... Semiconductor substrate
212…素子分離領域  212 ... Element isolation region
214a, 214b…ウエノレ  214a, 214b ... Uenore
216…ゲート絶縁膜  216 ... Gate insulation film
218…ゲート電極  218 ... Gate electrode
219…シリコン酸化膜  219 ... Silicon oxide film
220…サイドウォール絶縁膜 220… Side wall insulation film
222…ソース Zドレイン拡散層222… Source Z Drain diffusion layer
224…トランジスタ 224 ... transistor
225"'SiON膜  225 "'SiON film
226…シリコン酸化膜  226 ... Silicon oxide film
227…層間絶縁膜  227… Interlayer insulating film
228···ノ ジァ月莫  228 ..
230a, 230b…コンタクトホール 230a, 230b… Contact hole
232a, 232b…導体プラグ232a, 232b ... Conductor plug
234---Ir膜 234 --- Ir film
236…下部電極  236 ... Bottom electrode
238…強誘電体膜  238… Ferroelectric film
240…上部電極  240… Upper electrode
242…強誘電体キャパシタ 242… Ferroelectric capacitor
244---SiON膜 244 --- SiON film
246…バリア膜 248··•シリコン酸化膜 246… Barrier film 248 ··· Silicon oxide film
250·· 'バリア膜  250 ·· 'Barrier membrane
252·· •シリコン酸化膜  252 • Silicon oxide film
253-· -層間絶縁膜  253- ·-Interlayer insulation film
254a. , 254b…コンタク卜ホーノレ  254a., 254b… Contact 卜 Honore
256a. , 256b…導体プラグ  256a., 256b ... Conductor plug
258a. , 258b…酉己線  258a., 258b… Toshimi Line
260-· -シリコン酸化膜  260- · -Silicon oxide film
262-· -バリア膜  262- · -Barrier film
264-· -シリコン酸化膜  264- · -Silicon oxide film
265-· -層間絶縁膜  265 --- Interlayer insulation film
268-· -コンタクトホール  268- · -Contact hole
270·· •導体プラグ  270 · • Conductor plug
272·· •配線  272 · Wiring
274·· •シリコン酸化膜  274 ·· Silicon oxide film
276·· 'バリア膜  276 ... 'Barrier membrane
278·· •シリコン酸化膜  278 ·· Silicon oxide film
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0015] [第 1実施形態]  [0015] [First embodiment]
本発明の第 1実施形態による半導体装置及びその製造方法を図 1乃至図 17を用 いて説明する。図 1は本実施形態による半導体装置の構造を示す断面図、図 2及び 図 3は本実施形態による半導体装置の効果を説明する図、図 4乃至図 17は本実施 形態による半導体装置の製造方法を示す工程断面図である。  The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIGS. 2 and 3 are views for explaining the effects of the semiconductor device according to the present embodiment, and FIGS. 4 to 17 are methods for manufacturing the semiconductor device according to the present embodiment. It is process sectional drawing which shows these.
[0016] (半導体装置） [0016] (Semiconductor device)
まず、本実施形態による半導体装置の構造について図 1乃至図 3を用いて説明す る。  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0017] 図 1に示すように、例えばシリコンよりなる半導体基板 10上には、素子領域を画定 する素子分離領域 12が形成されている。素子分離領域 12が形成された半導体基板 10内には、ウエノレ 14a、 14bが形成されている。 As shown in FIG. 1, an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon. Semiconductor substrate on which element isolation region 12 is formed In FIG. 10, there are formed Uenoles 14a and 14b.
[0018] ゥエル 14a、 14bが形成された半導体基板 10上には、ゲート絶縁膜 16を介してゲ ート電極（ゲート配線） 18が形成されている。ゲート電極 18は、例えば、ポリシリコン 膜上に、タングステンシリサイド膜等の金属シリサイド膜が積層されたポリサイド構造 を有している。ゲート電極 18上には、シリコン酸化膜よりなる絶縁膜 19が形成されて いる。ゲート電極 18及び絶縁膜 19の側壁部分には、サイドウォール絶縁膜 20が形 成されている。 A gate electrode (gate wiring) 18 is formed via a gate insulating film 16 on the semiconductor substrate 10 on which the wells 14a and 14b are formed. The gate electrode 18 has, for example, a polycide structure in which a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film. On the gate electrode 18, an insulating film 19 made of a silicon oxide film is formed. Sidewall insulating films 20 are formed on the side walls of the gate electrode 18 and the insulating film 19.
[0019] サイドウォール絶縁膜 20が形成されたゲート電極 18の両側には、ソース Zドレイン 拡散層 22が形成されている。こうして、ゲート電極 18とソース Zドレイン拡散層 22と を有するトランジスタ 24が構成されている。トランジスタ 24のゲート長は、例えば 0. 3 5 z m、或いは例えば 0. 11—0. 18 x mに設定されている。  A source Z drain diffusion layer 22 is formed on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed. Thus, the transistor 24 having the gate electrode 18 and the source Z drain diffusion layer 22 is formed. The gate length of the transistor 24 is set to 0.35 zm, for example, or 0.11 to 0.18 xm, for example.
[0020] トランジスタ 24が形成された半導体基板 10上には、例えば膜厚 200nmの SiON膜 25と、例えば膜厚 600nmのシリコン酸化膜 26とが順次積層されている。こうして、 Si ON膜 25とシリコン酸化膜 26とを順次積層してなる層間絶縁膜 27が形成されている 。層間絶縁膜 27の表面は平坦ィ匕されている。  [0020] On the semiconductor substrate 10 on which the transistor 24 is formed, a SiON film 25 having a thickness of, for example, 200 nm and a silicon oxide film 26 having a thickness of, for example, 600 nm are sequentially stacked. Thus, an interlayer insulating film 27 formed by sequentially laminating the Si ON film 25 and the silicon oxide film 26 is formed. The surface of the interlayer insulating film 27 is flat.
[0021] 層間絶縁膜 27上には、例えば膜厚 lOOnmのシリコン酸化膜 34が形成されている 。平坦ィ匕された層間絶縁膜 27上にシリコン酸化膜 34が形成されているため、シリコン 酸化膜 34は平坦となっている。  On the interlayer insulating film 27, for example, a silicon oxide film 34 having a film thickness of lOOnm is formed. Since the silicon oxide film 34 is formed on the flattened interlayer insulating film 27, the silicon oxide film 34 is flat.
[0022] シリコン酸化膜 34上には、強誘電体キャパシタ 42の下部電極 36が形成されている 。下部電極 36は、例えば、膜厚 20— 50nmの酸ィ匕アルミニウム膜 36aと膜厚 100— 200nmの Pt膜 36bとを順次積層してなる積層膜により構成されている。ここでは、 Pt 膜 36bの膜厚は、 165nmに設定されている。  A lower electrode 36 of the ferroelectric capacitor 42 is formed on the silicon oxide film 34. The lower electrode 36 is composed of, for example, a laminated film in which an oxide aluminum film 36a having a thickness of 20 to 50 nm and a Pt film 36b having a thickness of 100 to 200 nm are sequentially laminated. Here, the film thickness of the Pt film 36b is set to 165 nm.
[0023] 下部電極 36上には、強誘電体キャパシタ 42の強誘電体膜 38が形成されている。  On the lower electrode 36, a ferroelectric film 38 of the ferroelectric capacitor 42 is formed.
強誘電体膜 38としては、例えば膜厚 100 250nmの PbZr Ti O膜（PZT膜）が  As the ferroelectric film 38, for example, a PbZr TiO film (PZT film) having a film thickness of 100 250 nm is used.
1-Χ X 3  1-Χ X 3
用いられている。ここでは、強誘電体膜 38には、膜厚 150nmの ΡΖΤ膜が用いられて いる。  It is used. Here, a 150 nm thick film is used for the ferroelectric film 38.
[0024] 強誘電体膜 38上には、強誘電体キャパシタ 42の上部電極 40が形成されている。  An upper electrode 40 of the ferroelectric capacitor 42 is formed on the ferroelectric film 38.
上部電極 40は、例えば膜厚 25 75nmの IrO膜 40aと、膜厚 150— 250nmの IrO 膜 40bとを順次積層してなる積層膜により構成されている。ここでは、 Ir〇膜 40aのFor example, the upper electrode 40 includes an IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm. It is composed of a laminated film obtained by sequentially laminating the film 40b. Here, Ir ○ film 40a
Y X Y X
膜厚は 50nmに設定され、 IrO膜 40bの膜厚は 200nmに設定されている。なお、 Ir  The film thickness is set to 50 nm, and the film thickness of the IrO film 40b is set to 200 nm. Ir
Y  Y
O膜 40bの酸素の組成比 Yは、 IrO膜 40aの酸素の組成比 Xより高く設定されてい The oxygen composition ratio Y of the O film 40b is set higher than the oxygen composition ratio X of the IrO film 40a.
Y X Y X
る。  The
[0025] こうして、下部電極 36と強誘電体膜 38と上部電極 40とからなる強誘電体キャパシタ 42が構成されている。  Thus, the ferroelectric capacitor 42 including the lower electrode 36, the ferroelectric film 38, and the upper electrode 40 is configured.
[0026] 強誘電体膜 38上及び上部電極 40上には、強誘電体膜 38及び上部電極 40の上 面及び側面を覆うようにバリア膜 44が形成されている。ノ リア膜 44としては、例えば 2 0— lOOnmの酸化アルミニウム（Al O )膜が用いられている。  A barrier film 44 is formed on the ferroelectric film 38 and the upper electrode 40 so as to cover the upper and side surfaces of the ferroelectric film 38 and the upper electrode 40. For example, a 20-lOOnm aluminum oxide (Al 2 O 3) film is used as the noria film 44.
2 3  twenty three
[0027] バリア膜 44は、水素及び水分の拡散を防止する機能を有する膜である。強誘電体 キャパシタ 42の強誘電体膜 38に水素や水分が達すると、強誘電体膜 38を構成する 金属酸化物が水素や水分により還元されてしまレ、、強誘電体キャパシタ 42の電気特 性が劣化してしまう。強誘電体膜 38及び上部電極 40の上面及び側面を覆うようにバ リア膜 44を形成することにより、強誘電体膜 38に水素及び水分が達するのが抑制さ れるため、強誘電体キャパシタ 42の電気的特性の劣化を抑制することが可能となる。  [0027] The barrier film 44 is a film having a function of preventing diffusion of hydrogen and moisture. When hydrogen or moisture reaches the ferroelectric film 38 of the ferroelectric capacitor 42, the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor 42 are reduced. Will deteriorate. By forming the barrier film 44 so as to cover the upper surface and the side surfaces of the ferroelectric film 38 and the upper electrode 40, it is possible to suppress hydrogen and moisture from reaching the ferroelectric film 38. It is possible to suppress the deterioration of the electrical characteristics of the.
[0028] バリア膜 44により覆われた強誘電体キャパシタ 42上及びシリコン酸化膜 34上には 、バリア膜 46が形成されている。バリア膜 46としては、例えば膜厚 20— lOOnmの酸 化アルミニウム膜が用レ、られてレ、る。  A barrier film 46 is formed on the ferroelectric capacitor 42 and the silicon oxide film 34 covered with the barrier film 44. As the barrier film 46, for example, an aluminum oxide film having a thickness of 20-lOOnm is used.
[0029] バリア膜 46は、バリア膜 44と同様に、水素及び水分の拡散を防止する機能を有す る膜である。  The barrier film 46 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier film 44.
[0030] バリア膜 46上には、例えば膜厚 1500nmのシリコン酸化膜よりなる層間絶縁膜 48 が形成されている。層間絶縁膜 48の表面は、平坦化されている。  On the barrier film 46, an interlayer insulating film 48 made of, for example, a silicon oxide film having a thickness of 1500 nm is formed. The surface of the interlayer insulating film 48 is planarized.
[0031] 層間絶縁膜 48、バリア膜 46、シリコン酸化膜 34、及び層間絶縁膜 27には、ソース /ドレイン拡散層 22に達するコンタクトホール 50a、 50bがそれぞれ形成されている。 また、層間絶縁膜 48、バリア膜 46、及びバリア膜 44には、上部電極 40に達するコン タクトホール 52aが形成されている。また、層間絶縁膜 48、バリア膜 46、及びバリア膜 44には、下部電極 36に達するコンタクトホール 52bが形成されている。  In the interlayer insulating film 48, the barrier film 46, the silicon oxide film 34, and the interlayer insulating film 27, contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed, respectively. Further, in the interlayer insulating film 48, the barrier film 46, and the barrier film 44, a contact hole 52a reaching the upper electrode 40 is formed. A contact hole 52b reaching the lower electrode 36 is formed in the interlayer insulating film 48, the barrier film 46, and the barrier film 44.
[0032] コンタクトホール 50a、 50b内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nm の TiN膜とを順次積層してなるバリアメタル膜（図示せず）が形成されている。ノ リアメ タル膜のうち Ti膜はコンタクト抵抗を低減するために形成され、 TiN膜は導体プラグ 材料のタングステンの拡散を防止するために形成されている。後述するコンタクトホ ールのそれぞれに形成されるバリアメタル膜についても、同様の目的で形成されてい る。 [0032] In the contact holes 50a and 50b, for example, a 20 nm thick Ti film and a 50 nm thick film, for example, A barrier metal film (not shown) is formed by sequentially laminating TiN films. Of the rare metal films, the Ti film is formed to reduce contact resistance, and the TiN film is formed to prevent diffusion of tungsten, which is a conductor plug material. The barrier metal film formed on each contact hole to be described later is also formed for the same purpose.
[0033] バリアメタル膜が形成されたコンタクトホール 50a、 50b内には、タングステンよりなる 導体プラグ 54a、 54bがそれぞれ坦め込まれている。  [0033] Conductor plugs 54a and 54b made of tungsten are respectively carried in the contact holes 50a and 50b in which the barrier metal film is formed.
[0034] 層間絶縁膜 48上及びコンタクトホール 52a内には、導体プラグ 54aと上部電極 40と に電気的に接続された配線 56aが形成されている。また、層間絶縁膜 48上及びコン タクトホール 52b内には、下部電極 36に電気的に接続された配線 56bが形成されて いる。また、層間絶縁膜 48上には、導体プラグ 54bに電気的に接続された配線 56c が形成されている。配線 56a、 56b, 56c (第 1金属配線層 56)は、例えば、膜厚 150 nmの TiN膜、膜厚 550nmの AlCu合金膜、膜厚 5nmの Ti膜、及び膜厚 150nmの TiN膜を順次積層してなる積層膜により構成されている。  A wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the interlayer insulating film 48 and in the contact hole 52a. A wiring 56b electrically connected to the lower electrode 36 is formed on the interlayer insulating film 48 and in the contact hole 52b. On the interlayer insulating film 48, a wiring 56c electrically connected to the conductor plug 54b is formed. For the wiring 56a, 56b, 56c (first metal wiring layer 56), for example, a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially formed. It is comprised by the laminated film formed by laminating | stacking.
[0035] こうして、トランジスタ 24のソース/ドレイン拡散層 22と強誘電体キャパシタ 42の上 部電極 40とが、導体プラグ 54a及び配線 56aを介して電気的に接続され、 1つのトラ ンジスタ 24及び 1つの強誘電体キャパシタ 42とを有する FeRAMの 1T1C型メモリセ ルが構成されている。実際には、複数のメモリセルが FeRAMチップのメモリセル領 域に配列されている。  In this way, the source / drain diffusion layer 22 of the transistor 24 and the upper electrode 40 of the ferroelectric capacitor 42 are electrically connected via the conductor plug 54a and the wiring 56a, so that one transistor 24 and 1 A FeRAM 1T1C type memory cell having two ferroelectric capacitors 42 is formed. Actually, multiple memory cells are arranged in the memory cell area of the FeRAM chip.
[0036] 配線 56a、 56b、 56cが形成された層間絶縁膜 48上には、配線 56a、 56b、 56cの 上面及び側面を覆うように、バリア膜 58が形成されている。バリア膜 58としては、例え ば 20nmの酸化アルミニウム膜が用いられてレ、る。  A barrier film 58 is formed on the interlayer insulating film 48 on which the wirings 56a, 56b, 56c are formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, 56c. For example, a 20 nm aluminum oxide film is used as the barrier film 58.
[0037] バリア膜 58は、バリア膜 44、 46と同様に、水素及び水分の拡散を防止する機能を 有する膜である。また、バリア膜 58は、プラズマによるダメージを抑えるためにも用い られている。 The barrier film 58 is a film having a function of preventing the diffusion of hydrogen and moisture similarly to the barrier films 44 and 46. The barrier film 58 is also used to suppress damage caused by plasma.
[0038] バリア膜 58上には、例えば膜厚 2600nmのシリコン酸化膜 60が形成されてレ、る。  On the barrier film 58, for example, a silicon oxide film 60 having a thickness of 2600 nm is formed.
シリコン酸化膜 60の表面は、平坦化されている。平坦化されたシリコン酸化膜 60は、 酉己泉 56a、 56b, 56c上に、例えば lOOOnmの膜厚で残存してレヽる。 [0039] シリコン酸化膜 60上には、例えば膜厚 lOOnmのシリコン酸化膜 61が形成されてい る。平坦ィ匕されたシリコン酸化膜 60上にシリコン酸化膜 61が形成されているため、シ リコン酸化膜 61は平坦となっている。 The surface of the silicon oxide film 60 is planarized. The planarized silicon oxide film 60 is left and deposited on the self-spring 56a, 56b, 56c with a film thickness of, for example, lOOOnm. [0039] On the silicon oxide film 60, for example, a silicon oxide film 61 having a film thickness of lOOnm is formed. Since the silicon oxide film 61 is formed on the flattened silicon oxide film 60, the silicon oxide film 61 is flat.
[0040] シリコン酸化膜 61上には、ノ リア膜 62が形成されている。バリア膜 62としては、例 えば膜厚 20— 70nmの酸化アルミニウム膜が用いられている。ここでは、ノ リア膜 62 として、膜厚 50nmの酸化アルミニウム膜が用いられている。平坦なシリコン酸化膜 6 1上にノ リア膜 62が形成されているため、バリア膜 62は平坦となっている。  A noor film 62 is formed on the silicon oxide film 61. As the barrier film 62, for example, an aluminum oxide film having a thickness of 20 to 70 nm is used. Here, an aluminum oxide film having a thickness of 50 nm is used as the noria film 62. Since the NORA film 62 is formed on the flat silicon oxide film 61, the barrier film 62 is flat.
[0041] バリア膜 62は、バリア膜 44、 46、 58と同様に、水素及び水分の拡散を防止する機 能を有する膜である。さらに、バリア膜 62は、平坦なシリコン酸化膜 61上に形成され ているため平坦となっており、バリア膜 44、 46、 58と比較して、極めて良好な被覆性 で形成されている。したがって、このような平坦なバリア膜 62により、更に確実に水素 及び水分の拡散を防止することができる。なお、実際には、バリア膜 62は、強誘電体 キャパシタ 42を有する複数のメモリセルが配列された FeRAMチップのメモリセル領 域のみならず、周辺回路領域等を含む FeRAMチップの全面にわたって形成されて いる。  [0041] The barrier film 62 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44, 46, and 58. Further, the barrier film 62 is flat because it is formed on the flat silicon oxide film 61, and is formed with extremely good coverage as compared with the barrier films 44, 46, and 58. Therefore, such a flat barrier film 62 can more reliably prevent hydrogen and moisture from diffusing. In practice, the barrier film 62 is formed not only on the memory cell region of the FeRAM chip on which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also on the entire surface of the FeRAM chip including the peripheral circuit region. ing.
[0042] バリア膜 62上には、例えば膜厚 50— lOOnmのシリコン酸化膜 64が形成されてい る。ここでは、シリコン酸化膜 64の膜厚は、 lOOnmに設定されている。  [0042] On the barrier film 62, for example, a silicon oxide film 64 having a film thickness of 50-lOOnm is formed. Here, the thickness of the silicon oxide film 64 is set to lOOnm.
[0043] こうして、バリア膜 58、シリコン酸化膜 60、シリコン酸化膜 61、バリア膜 62、及びシリ コン酸化膜 64により層間絶縁膜 66が構成されている。 Thus, the interlayer insulating film 66 is constituted by the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64.
[0044] 層間絶縁膜 66には、配線 56cに達するコンタクトホール 68が形成されている。 In the interlayer insulating film 66, a contact hole 68 reaching the wiring 56c is formed.
[0045] コンタクトホール 68内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nmの TiN 膜とを順次積層してなるバリアメタル膜（図示せず）が形成されている。なお、 Ti膜を 形成せずに、 TiN膜よりなるバリアメタル膜を形成してもよい。 In the contact hole 68, a barrier metal film (not shown) is formed by sequentially stacking, for example, a Ti film having a thickness of 20 nm and a TiN film having a thickness of 50 nm, for example. A barrier metal film made of a TiN film may be formed without forming a Ti film.
[0046] バリアメタル膜が形成されたコンタクトホール 68内には、タングステンよりなる導体プ ラグ 70が坦め込まれている。 [0046] A conductor plug 70 made of tungsten is carried in the contact hole 68 in which the barrier metal film is formed.
[0047] 層間絶縁膜 66上には、配線 72aが形成されている。また、層間絶縁膜 66上には、 導体プラグ 70に電気的に接続された配線 72bが形成されている。配線 72a、 72b (第A wiring 72 a is formed on the interlayer insulating film 66. On the interlayer insulating film 66, a wiring 72b electrically connected to the conductor plug 70 is formed. Wiring 72a, 72b (first
2金属配線層 72)は、例えば、膜厚 50nmの TiN膜、膜厚 500nmの AlCu合金膜、 膜厚 5nmの Ti膜、及び膜厚 150nmの TiN膜を順次積層してなる積層膜により構成 されている。 (2) The metal wiring layer 72) includes, for example, a TiN film with a thickness of 50 nm, an AlCu alloy film with a thickness of 500 nm, It consists of a laminated film consisting of a 5nm thick Ti film and a 150nm thick TiN film.
[0048] 層間絶縁膜 66上及び配線 72a、 72b上には、例えば膜厚 2200nmのシリコン酸化 膜 74が形成されている。シリコン酸化膜 74の表面は、平坦化されている。  [0048] A silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the interlayer insulating film 66 and on the wirings 72a and 72b. The surface of the silicon oxide film 74 is planarized.
[0049] シリコン酸化膜 74上には、例えば膜厚 lOOnmのシリコン酸化膜 76が形成されてい る。平坦化されたシリコン酸化膜 74上にシリコン酸化膜 76が形成されているため、シ リコン酸化膜 76は平坦となっている。  [0049] On the silicon oxide film 74, for example, a silicon oxide film 76 having a film thickness of lOOnm is formed. Since the silicon oxide film 76 is formed on the flattened silicon oxide film 74, the silicon oxide film 76 is flat.
[0050] シリコン酸化膜 76上には、ノ リア膜 78が形成されてレ、る。バリア膜 78としては、例 えば膜厚 20— lOOnmの酸化アルミニウム膜が用いられている。ここでは、バリア膜 7 8として、膜厚 50nmの酸化アルミニウム膜が用いられている。平坦なシリコン酸化膜 76上にノ リア膜 78が形成されているため、バリア膜 78は平坦となっている。  A noria film 78 is formed on the silicon oxide film 76. As the barrier film 78, for example, an aluminum oxide film having a film thickness of 20-lOOnm is used. Here, as the barrier film 78, an aluminum oxide film having a thickness of 50 nm is used. Since the NORA film 78 is formed on the flat silicon oxide film 76, the barrier film 78 is flat.
[0051] バリア膜 78は、バリア膜 44、 46、 58、 62と同様に、水素及び水分の拡散を防止す る機能を有する膜である。さらに、バリア膜 78は、平坦なシリコン酸化膜 61上に形成 されているため平坦となっており、バリア膜 62と同様に、バリア膜 44、 46、 58と比較し て、極めて良好な被覆性で形成されている。したがって、このような平坦なノ リア膜 6 2により、更に確実に水素及び水分の拡散を防止することができる。なお、実際には、 バリア膜 78は、バリア膜 62と同様に、強誘電体キャパシタ 42を有する複数のメモリセ ルが配列された FeRAMチップのメモリセル領域のみならず、周辺回路領域等を含 む FeRAMチップの全面にわたって形成されている。  [0051] Similar to the barrier films 44, 46, 58, 62, the barrier film 78 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 78 is formed on the flat silicon oxide film 61, it is flat. Like the barrier film 62, the barrier film 78 has an extremely good coverage as compared with the barrier films 44, 46, and 58. It is formed with. Therefore, diffusion of hydrogen and moisture can be prevented more reliably by using such a flat NOR film 62. Actually, the barrier film 78 includes not only the memory cell region of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit region and the like, like the barrier film 62. It is formed over the entire surface of the FeRAM chip.
[0052] バリア膜 78上には、例えば膜厚 lOOnmのシリコン酸化膜 80が形成されている。  On the barrier film 78, for example, a silicon oxide film 80 having a film thickness of lOOnm is formed.
[0053] こうして、シリコン酸化膜 74、シリコン酸化膜 76、バリア膜 78、及びシリコン酸化膜 8 0により層間絶縁膜 82が構成されている。  Thus, the interlayer insulating film 82 is configured by the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80.
[0054] 層間絶縁膜 82には、配線 72a、 72bに達するコンタクトホール 84a、 84bがそれぞ れ形成されている。  In the interlayer insulating film 82, contact holes 84a and 84b reaching the wirings 72a and 72b are formed, respectively.
[0055] コンタクトホール 84a、 84b内には、例えば膜厚 20nmの Ti膜と、例えば膜厚 50nm の TiN膜とを順次積層してなるバリアメタル膜（図示せず）が形成されている。なお、 T i膜を形成せずに、 TiN膜よりなるバリアメタル膜を形成してもよレ、。  In the contact holes 84a and 84b, a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm thick Ti film and a 50 nm thick TiN film, for example. Alternatively, a barrier metal film made of a TiN film may be formed without forming a Ti film.
[0056] バリアメタル膜が形成されたコンタクトホール 84a、 84b内には、タングステンよりなる 導体プラグ 86a、 86bがそれぞれ坦め込まれている。 [0056] The contact holes 84a and 84b in which the barrier metal film is formed are made of tungsten. Conductor plugs 86a and 86b are respectively carried.
[0057] 導体プラグ 86a、 86bが坦め込まれた層間絶縁膜 82上には、導体プラグ 86aに電 気的に接続された配線 88a、及び導体プラグ 86bに電気的に接続された配線 (ボン デイングパッド） 88bが形成されている。配線 88a、 88b (第 3金属配線層 88)は、例え ば、膜厚 50nmの TiN膜、膜厚 500nmの AlCu合金膜、及び膜厚 150nmの TiN膜 を順次積層してなる積層膜により構成されている。 [0057] On the interlayer insulating film 82 in which the conductor plugs 86a and 86b are carried, the wiring 88a electrically connected to the conductor plug 86a and the wiring electrically connected to the conductor plug 86b (bon Ding pad) 88b is formed. The wirings 88a and 88b (third metal wiring layer 88) are composed of, for example, a laminated film in which a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, and a 150 nm thick TiN film are sequentially laminated. ing.
[0058] 層間絶縁膜 82上及び配線 88a、 88b上には、例えば膜厚 100— 300nmのシリコ ン酸化膜 90が形成されている。ここでは、シリコン酸化膜 90の膜厚は、 lOOnmに設 定されている。  For example, a silicon oxide film 90 having a thickness of 100 to 300 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b. Here, the thickness of the silicon oxide film 90 is set to lOOnm.
[0059] シリコン酸化膜 90上には、例えば膜厚 350nmのシリコン窒化膜 92が形成されてい る。  [0059] On the silicon oxide film 90, a silicon nitride film 92 of, eg, a 350 nm-thickness is formed.
[0060] シリコン窒化膜 92上には、例えば膜厚 2 6 μ mのポリイミド樹脂膜 94が形成され ている。  [0060] On the silicon nitride film 92, for example, a polyimide resin film 94 with a film thickness of 26 μm is formed.
[0061] ポリイミド樹脂膜 94、シリコン窒化膜 92、及びシリコン酸化膜 90には、配線 (ボンデ イングパッド） 88bに達する開口部 96が形成されている。すなわち、シリコン窒化膜 92 及びシリコン酸化膜 90には、配線 (ボンディングパッド） 88bに達する開口部 96aが形 成されている。ポリイミド樹脂膜 94には、シリコン窒化膜 92及びシリコン酸化膜 90に 形成された開口部 96aを含む領域に、開口部 96bが形成されている。  In the polyimide resin film 94, the silicon nitride film 92, and the silicon oxide film 90, an opening 96 reaching the wiring (bonding pad) 88b is formed. That is, in the silicon nitride film 92 and the silicon oxide film 90, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92 and the silicon oxide film 90.
[0062] 配線 (ボンディングパッド） 88bには、開口部 96を介して、外部回路（図示せず）が 電気的に接続される。  [0062] An external circuit (not shown) is electrically connected to the wiring (bonding pad) 88b through the opening 96.
[0063] こうして本実施形態による半導体装置が構成されてレ、る。  Thus, the semiconductor device according to the present embodiment is configured.
[0064] 本実施形態による半導体装置は、水素及び水分の拡散を防止するバリア膜として、 バリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56 (配線 56a、 56b、 56c)と第 2金属配線層 72 (配線 72a、 72b)との間に形 成された平坦なバリア膜 62と、第 2金属配線層 72 (配線 72a、 72b)と第 3金属配線 層 88 (配線 88a、 88b)との間に形成された平坦なバリア膜 78とを有することに主たる 特徴がある。  In the semiconductor device according to the present embodiment, the first metal wiring layer formed above the ferroelectric capacitor 42 in addition to the barrier films 44, 46, 58 as a barrier film for preventing diffusion of hydrogen and moisture. A flat barrier film 62 formed between 56 (wirings 56a, 56b, 56c) and the second metal wiring layer 72 (wirings 72a, 72b), and a second metal wiring layer 72 (wirings 72a, 72b) The main feature is that it has a flat barrier film 78 formed between the third metal wiring layer 88 (wirings 88a and 88b).
[0065] 強誘電体キャパシタを有する半導体装置において、水素や水分による強誘電体キ ャパシタの電気的特性の劣化を防止する有効な手段として、強誘電体キャパシタの 上方に、水素や水分の拡散を防止する酸化アルミニウム等よりなるバリア膜を形成す ること力と考えられる。 In a semiconductor device having a ferroelectric capacitor, a ferroelectric key caused by hydrogen or moisture is used. As an effective means for preventing the deterioration of the electrical characteristics of the capacitor, it is considered that a barrier film made of aluminum oxide or the like for preventing diffusion of hydrogen or moisture is formed above the ferroelectric capacitor.
[0066] ここで、表面に段差が生じている層間絶縁膜等の上にバリア膜を形成した場合には 、バリア膜の被覆性があまり良好ではないため、ノ リア膜において水素や水分の拡散 を十分に防止し得ない。水素や水分が強誘電体キャパシタの強誘電体膜に達すると 、水素や水分により強誘電体膜の強誘電性が低下或いは消失し、強誘電体キャパシ タの電気的特性が劣化してしまうこととなる。  [0066] Here, when a barrier film is formed on an interlayer insulating film or the like having a step on the surface, the barrier film is not so well covered, so that diffusion of hydrogen and moisture in the barrier film is difficult. Cannot be sufficiently prevented. When hydrogen or moisture reaches the ferroelectric film of the ferroelectric capacitor, the ferroelectric properties of the ferroelectric film are reduced or lost by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor are deteriorated. It becomes.
[0067] これに対して、平坦化された絶縁膜上に形成された平坦なバリア膜は被覆性が極 めて良好であるため、このような平坦なバリア膜により水素及び水分を確実にバリアし 、水素及び水分が強誘電体キャパシタの強誘電体膜に達するのを防止することがで きる。  [0067] On the other hand, since a flat barrier film formed on a flattened insulating film has extremely good coverage, such a flat barrier film ensures a barrier against hydrogen and moisture. However, it is possible to prevent hydrogen and moisture from reaching the ferroelectric film of the ferroelectric capacitor.
[0068] し力 ながら、強誘電体キャパシタの上方に、単に 1層の平坦なバリア膜を形成した 場合には、 PTHS試験において不良が発生する等、過酷な環境下において水素に 対する耐性や耐湿性を充分に確保することができないことがあった。これは、平坦な バリア膜の下地層となる層間絶縁膜を CMP法等により平坦ィヒする際に層間絶縁膜 の表面に生じたマイクロ 'スクラッチによる段差が影響していると考えられる。すなわち 、層間絶縁膜の表面に生じたマイクロ 'スクラッチによる段差のために平坦なバリア膜 においても被覆性があまり良好でない欠陥部分が生じており、このような欠陥部分が 、平坦なバリア膜によっても水素に対する耐性や耐湿性を充分に確保することができ ない場合がある原因の一つとなっていると考えられる。実際には、マイクロ 'スクラッチ による段差を考慮して、 CMP法等による下地層の平坦ィ匕後に、例えば膜厚 lOOnm のシリコン酸化膜を形成している力 このような手法を用いても、マイクロ 'スクラッチに よる影響を完全に回避することはできていなかった。  [0068] However, when a single flat barrier film is formed above the ferroelectric capacitor, the resistance to hydrogen and moisture resistance in a harsh environment, such as failure in the PTHS test, occurs. In some cases, sufficient properties could not be ensured. This is thought to be due to the micro-scratch step that occurs on the surface of the interlayer insulating film when the interlayer insulating film that is the underlying layer of the flat barrier film is flattened by CMP or the like. That is, due to a step caused by micro scratches generated on the surface of the interlayer insulating film, a defective portion with poor coverage is generated even in the flat barrier film. Such a defective portion is also formed by the flat barrier film. This is considered to be one of the reasons why sufficient resistance to hydrogen and moisture resistance may not be ensured. In fact, considering the step due to micro scratches, the force of forming a silicon oxide film with a film thickness of lOOnm, for example, after planarization of the underlying layer by CMP or the like 'The effects of scratches could not be completely avoided.
[0069] 図 2は、強誘電体キャパシタを有する半導体装置において形成された平坦なバリア 膜に生じる欠陥部分を示す断面図である。なお、図 2に示す半導体装置では、本実 施形態による半導体装置とは異なり、平坦なバリア膜として 1層のノ リア膜 78のみが 形成されており、バリア膜 62は形成されていない。 [0070] 図 2に示すように、平坦なノくリア膜 78においても、その下層の絶縁膜の表面に生じ ているマイクロ 'スクラッチによる段差等により、被覆性のあまり良好でない欠陥部分 1 10が生じてレ、ると考えられる。 FIG. 2 is a cross-sectional view showing a defect portion generated in a flat barrier film formed in a semiconductor device having a ferroelectric capacitor. In the semiconductor device shown in FIG. 2, unlike the semiconductor device according to the present embodiment, only the single-layer film 78 is formed as a flat barrier film, and the barrier film 62 is not formed. [0070] As shown in FIG. 2, even in the flat knitted rear film 78, a defective portion 110 having a poor coverage is formed due to a step caused by micro scratches generated on the surface of the insulating film underneath. It is thought that it occurs.
[0071] したがって、半導体装置がおかれる環境下によつては、平坦なノ リア膜 78の欠陥 部分 110を介して半導体装置の内部に水素や水分が侵入してしまうと考えられる。  Therefore, under an environment where the semiconductor device is placed, it is considered that hydrogen and moisture enter the inside of the semiconductor device through the defective portion 110 of the flat nore film 78.
[0072] さらに、図 2に示す半導体装置のように、単に 1層の平坦なバリア膜が形成されてい るのみでは、欠陥部分 110を介して半導体装置の内部に侵入した水素や水分が強 誘電体キャパシタ 42に達するのを充分に防止することが困難となる。この結果、平坦 なバリア膜が強誘電体キャパシタの上方に形成されている場合であっても、単に 1層 の平坦なバリア膜が形成されてレ、るのみでは、強誘電体キャパシタの電気的特性が 劣化してしまうことがあると考えられる。  [0072] Further, as in the semiconductor device shown in FIG. 2, when only one flat barrier film is formed, hydrogen and moisture that have penetrated into the semiconductor device through the defective portion 110 are ferroelectric. It is difficult to sufficiently prevent the body capacitor 42 from being reached. As a result, even if a flat barrier film is formed above the ferroelectric capacitor, it is only necessary to form a flat barrier film of one layer. It is thought that the characteristics may deteriorate.
[0073] これに対し、本実施形態による半導体装置では、 2層の平坦なバリア膜、すなわち、 強誘電体キャパシタ 42の上方に形成された第 1金属配線層 56と第 2金属配線層 72 との間に形成された平坦なバリア膜 62と、第 2金属配線層 72と第 3金属配線層 88と の間に形成された平坦なバリア膜 78とが形成されている。  In contrast, in the semiconductor device according to the present embodiment, two flat barrier films, that is, the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42, A flat barrier film 62 formed between the second metal wiring layer 72 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed.
[0074] 本実施形態による半導体装置においても、図 3に示すように、 2層の平坦なバリア膜 62、 78に、被覆性があまり良好でない欠陥部分 110が生じている場合が想定される 。なお、図 3 (a)は本実施形態による半導体装置の構造を示す平面図であり、図 3 (b )は図3 ( に対応する本実施形態による半導体装置の断面図であり、両図において 、 2層の平坦なバリア膜 62、 78に生じている欠陥部分 110を概略的に示している。  In the semiconductor device according to the present embodiment as well, as shown in FIG. 3, it is assumed that a defective portion 110 with poor coverage is generated in the two flat barrier films 62 and 78. 3A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 3B is a cross-sectional view of the semiconductor device according to the present embodiment corresponding to FIG. FIG. 2 schematically shows a defect portion 110 generated in two flat barrier films 62 and 78. FIG.
[0075] し力し、図 3 (a)に示すように、平坦なバリア膜 62、 78において、互いにほぼ同じ平 面位置に欠陥部分 110が生じる確率は極めて小さいといえる。したがって、本実施形 態による半導体装置では、上層に位置する平坦なバリア膜 78に生じている欠陥部分 110を介して水素や水分が半導体装置の内部に侵入したとしても、下層に位置する 平坦なバリア膜 62により、侵入した水素や水分が強誘電体キャパシタ 42に達するの を確実に遮断することができる。  As shown in FIG. 3A, it can be said that in the flat barrier films 62 and 78, the probability that the defective portion 110 is generated at substantially the same plane position is very small. Therefore, in the semiconductor device according to the present embodiment, even if hydrogen or moisture enters the inside of the semiconductor device through the defect portion 110 generated in the flat barrier film 78 located in the upper layer, the flat device located in the lower layer is used. The barrier film 62 can reliably block the intruding hydrogen and moisture from reaching the ferroelectric capacitor 42.
[0076] このように、本実施形態による半導体装置では、強誘電体キャパシタ 42の上方に形 成された第 1金属配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属配線層 72と第 3金属配線層 88との間に形成された平坦なバリア膜 78 とが形成されているので、水素及び水分を確実にバリアし、水素及び水分が強誘電 体キャパシタ 42の強誘電体膜 38に達するのを確実に防止することができる。これに より、水素及び水分による強誘電体キャパシタ 42の電気的特性の劣化を確実に防止 することができ、強誘電体キャパシタを有する半導体装置の PTHS特性を大幅に向 上すること力 Sできる。 Thus, in the semiconductor device according to the present embodiment, the flat barrier formed between the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42. film 62 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 are formed, so that hydrogen and moisture are securely barriered, and hydrogen and moisture are strong. Reaching the ferroelectric film 38 of the dielectric capacitor 42 can be reliably prevented. As a result, it is possible to reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture, and to greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor S.
[0077] (半導体装置の製造方法） (Semiconductor Device Manufacturing Method)
次に、本実施形態による半導体装置の製造方法について図 4乃至図 17を用いて 説明する。  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0078] まず、例えばシリコンよりなる半導体基板 10に、例えば LOCOS (LOCal Oxidation of Silicon)法により、素子領域を画定する素子分離領域 12を形成する。  First, an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon by, for example, a LOCOS (LOCal Oxidation of Silicon) method.
[0079] 次いで、イオン注入法により、ドーパント不純物を導入することにより、ゥヱノレ 14a、 1 4bを形成する。  [0079] Next, the dopants 14a and 14b are formed by introducing dopant impurities by ion implantation.
[0080] 次いで、通常のトランジスタの形成方法を用いて、素子領域に、ゲート電極 (ゲート 配線） 18とソース/ドレイン拡散層 22とを有するトランジスタ 24を形成する（図 4 (a)を 参照）。  Next, a transistor 24 having a gate electrode (gate wiring) 18 and a source / drain diffusion layer 22 is formed in the element region by using a normal transistor formation method (see FIG. 4A). .
[0081] 次いで、全面に、例えばプラズマ CVD (Chemical Vapor Deposition)法により、例え ば膜厚 200nmの SiON膜 25を形成する。  Next, an SiON film 25 of, eg, a 200 nm-thickness is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition).
[0082] 次いで、全面に、プラズマ TEOSCVD法により、例えば例えば膜厚 600nmのシリ コン酸化膜 26を形成する（図 4 (b)を参照）。 Next, for example, a silicon oxide film 26 of, eg, a 600 nm-thickness is formed on the entire surface by a plasma TEOSCVD method (see FIG. 4B).
[0083] こうして、 SiON膜 25とシリコン酸化膜 26とにより層間絶縁膜 27が構成される。 Thus, the interlayer insulating film 27 is constituted by the SiON film 25 and the silicon oxide film 26.
[0084] 次いで、例えば CMP法により、層間絶縁膜 27の表面を平坦ィ匕する（図 4 (c)を参照Next, the surface of the interlayer insulating film 27 is flattened by, eg, CMP (see FIG. 4C).
) o ) o
[0085] 次いで、一酸化二窒素（N O)又は窒素（N )雰囲気にて、例えば 650°C、 30分間  [0085] Next, in an atmosphere of dinitrogen monoxide (N 2 O) or nitrogen (N 2), for example, 650 ° C, 30 minutes
2 2  twenty two
の熱処理を行う。  The heat treatment is performed.
[0086] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 34を形成する（図 5 (a)を参照）。  Next, a silicon oxide film 34 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 5A).
[0087] 次いで、 N Oガスを用いて発生させたプラズマ雰囲気にて、例えば 350°C、 2分間 の熱処理を行う。 [0087] Next, in a plasma atmosphere generated using NO gas, for example, 350 ° C, 2 minutes The heat treatment is performed.
[0088] 次いで、全面に、例えばスパッタ法又は CVD法により、例えば膜厚 20— 50nmの 酸化アルミニウム膜 36aを形成する。  Next, an aluminum oxide film 36a having a thickness of 20 to 50 nm, for example, is formed on the entire surface by, eg, sputtering or CVD.
[0089] 次いで、例えば RTA (Rapid Thermal Annealing)法により、酸素雰囲気中にて熱処 理を行う。熱処理温度は例えば 650°Cとし、熱処理時間は例えば 1一 2分とする。 Next, heat treatment is performed in an oxygen atmosphere by, eg, RTA (Rapid Thermal Annealing). The heat treatment temperature is, for example, 650 ° C, and the heat treatment time is, for example, 1-12 minutes.
[0090] 次いで、全面に、例えばスパッタ法により、例えば膜厚 100— 200nmの Pt膜 36bを 形成する。 Next, a Pt film 36b having a thickness of 100 to 200 nm, for example, is formed on the entire surface by, eg, sputtering.
[0091] こうして、酸化アルミニウム膜 36aと Pt膜 36bとからなる積層膜 36が形成される。積 層膜 36は、強誘電体キャパシタ 42の下部電極となるものである。  Thus, a laminated film 36 composed of the aluminum oxide film 36a and the Pt film 36b is formed. The multilayer film 36 becomes a lower electrode of the ferroelectric capacitor 42.
[0092] 次いで、全面に、例えばスパッタ法により、強誘電体膜 38を形成する。強誘電体膜  Next, a ferroelectric film 38 is formed on the entire surface by, eg, sputtering. Ferroelectric film
38としては、例えば膜厚 100 250nmの PZT膜を形成する。  As 38, for example, a PZT film having a thickness of 100 to 250 nm is formed.
[0093] なお、ここでは、強誘電体膜 38をスパッタ法により形成する場合を例に説明したが 、強誘電体膜の形成方法はスパッタ法に限定されるものではない。例えば、ゾル 'ゲ ル法、 MOD (Metal Organic Deposition)法、 MOCVD法等により強誘電体膜を形成 してもよい。  Here, the case where the ferroelectric film 38 is formed by the sputtering method has been described as an example, but the method of forming the ferroelectric film is not limited to the sputtering method. For example, the ferroelectric film may be formed by a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD method, or the like.
[0094] 次いで、例えば RTA法により、酸素雰囲気中にて熱処理を行う。熱処理温度は例 えば 550— 600°Cとし、熱処理時間は例えば 60— 120秒とする。  Next, heat treatment is performed in an oxygen atmosphere by, for example, the RTA method. The heat treatment temperature is, for example, 550-600 ° C, and the heat treatment time is, for example, 60-120 seconds.
[0095] 次いで、例えばスパッタ法又は MOCVD法により、例えば膜厚 25— 75nmの IrO [0095] Next, IrO having a film thickness of, for example, 25 to 75 nm is formed by, for example, sputtering or MOCVD.
X  X
膜 40aを形成する。  A film 40a is formed.
[0096] 次いで、アルゴン及び酸素雰囲気にて、例えば 600— 800°C、 10— 100秒間の熱 処理を行う。  [0096] Next, heat treatment is performed, for example, at 600 to 800 ° C for 10 to 100 seconds in an argon and oxygen atmosphere.
[0097] 次いで、例えばスパッタ法又は MOCVD法により、例えば膜厚 150 250nmの Ir O膜 40bを形成する。この際、 Ir〇膜 40bの酸素の組成比 Y力 IrO膜 40aの酸素 Next, an Ir 2 O film 40b having a thickness of 150 to 250 nm, for example, is formed by, eg, sputtering or MOCVD. At this time, the oxygen composition ratio of the IrO film 40b Y force The oxygen of the IrO film 40a
Y Y X Y Y X
の組成比 Xより高くなるように、 IrO膜 40bを形成する。  The IrO film 40b is formed so as to be higher than the composition ratio X.
Y  Y
[0098] こうして、 IrO膜 40aと Ir〇膜 40bとからなる積層膜 40が形成される（図 5 (b)を参  In this way, a laminated film 40 composed of the IrO film 40a and the IrO film 40b is formed (see FIG. 5B).
X Y  X Y
照）。積層膜 40は、強誘電体キャパシタ 42の上部電極となるものである。  See). The laminated film 40 becomes an upper electrode of the ferroelectric capacitor 42.
[0099] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 98を形成する。 Next, a photoresist film 98 is formed on the entire surface by, eg, spin coating.
[0100] 次いで、フォトリソグラフィ一により、フォトレジスト膜 98を強誘電体キャパシタ 42の 上部電極 40の平面形状にパターユングする。 Next, a photoresist film 98 is formed on the ferroelectric capacitor 42 by photolithography. Pattern in the planar shape of the upper electrode 40.
[0101] 次いで、フォトレジスト膜 98をマスクとして、積層膜 40をエッチングする。エッチング ガスとしては、例えば Arガスと C1ガスとを用いる。こうして、積層膜よりなる上部電極 4 Next, the laminated film 40 is etched using the photoresist film 98 as a mask. For example, Ar gas and C1 gas are used as the etching gas. Thus, the upper electrode made of a laminated film 4
2  2
0が形成される（図 5 (c)を参照）。この後、フォトレジスト膜 98を剥離する。  0 is formed (see FIG. 5 (c)). Thereafter, the photoresist film 98 is peeled off.
[0102] 次いで、例えば酸素雰囲気にて、例えば 400 700°C、 30— 120分間の熱処理を 行う。この熱処理は、上部電極 40の表面に異常が生ずるのを防止するためのもので ある。 [0102] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 700 ° C for 30 to 120 minutes. This heat treatment is intended to prevent the surface of the upper electrode 40 from becoming abnormal.
[0103] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 100を形成する。  [0103] Next, a photoresist film 100 is formed on the entire surface by, eg, spin coating.
[0104] 次いで、フォトリソグラフィ一により、フォトレジスト膜 100を強誘電体キャパシタ 42の 強誘電体膜 38の平面形状にパターニングする。 Next, the photoresist film 100 is patterned into a planar shape of the ferroelectric film 38 of the ferroelectric capacitor 42 by photolithography.
[0105] 次いで、フォトレジスト膜 100をマスクとして、強誘電体膜 38をエッチングする（図 6 ( a)を参照）。この後、フォトレジスト膜 100を剥離する。 Next, the ferroelectric film 38 is etched using the photoresist film 100 as a mask (see FIG. 6A). Thereafter, the photoresist film 100 is peeled off.
[0106] 次いで、酸素雰囲気にて、例えば 300— 400°C、 30— 120分間の熱処理を行う。 [0106] Next, heat treatment is performed in an oxygen atmosphere, for example, at 300 to 400 ° C for 30 to 120 minutes.
[0107] 次いで、例えばスパッタ法又は CVD法により、バリア膜 44を形成する（図 6 (b)を参 照）。バリア膜 44としては、例えば膜厚 20— 50nmの酸化アルミニウム膜を形成する Next, a barrier film 44 is formed by, eg, sputtering or CVD (see FIG. 6B). As the barrier film 44, for example, an aluminum oxide film having a thickness of 20 to 50 nm is formed.
[0108] 次いで、酸素雰囲気にて、例えば 400— 600°C、 30— 120分間の熱処理を行う。 [0108] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
[0109] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 102を形成する。 [0109] Next, a photoresist film 102 is formed on the entire surface by, eg, spin coating.
[0110] 次いで、フォトリソグラフィ一により、フォトレジスト膜 102を強誘電体キャパシタ 42の 下部電極 36の平面形状にパターユングする。 Next, the photoresist film 102 is patterned into the planar shape of the lower electrode 36 of the ferroelectric capacitor 42 by photolithography.
[0111] 次いで、フォトレジスト膜 102をマスクとして、バリア膜 44及び積層膜 36をエツチン グする（図 6 (c)を参照）。こうして、積層膜よりなる下部電極 36が形成される。また、バ リア膜 44が、上部電極 40及び強誘電体膜 38を覆うように残存する。この後、フオトレ ジスト膜 102を剥離する。 Next, using the photoresist film 102 as a mask, the barrier film 44 and the laminated film 36 are etched (see FIG. 6C). Thus, the lower electrode 36 made of a laminated film is formed. Further, the barrier film 44 remains so as to cover the upper electrode 40 and the ferroelectric film 38. Thereafter, the photoresist film 102 is peeled off.
[0112] 次いで、酸素雰囲気にて、例えば 400 600°C、 30— 120分間の熱処理を行う。 [0112] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 600 ° C for 30 to 120 minutes.
[0113] 次いで、全面に、例えばスパッタ法又は CVD法により、ノ リア膜 46を形成する。バ リア膜 46としては、例えば膜厚 20 lOOnmの酸化アルミニウム膜を形成する（図 7 ( a)を参照）。こうして、バリア膜 44により覆われた強誘電体キャパシタ 42を更に覆うよ うにバリア膜 46が形成される。 [0113] Next, the noor film 46 is formed on the entire surface by, eg, sputtering or CVD. As the barrier film 46, for example, an aluminum oxide film having a thickness of 20 lOOnm is formed (see FIG. 7A). Thus, the ferroelectric capacitor 42 covered with the barrier film 44 is further covered. Thus, the barrier film 46 is formed.
[0114] 次いで、酸素雰囲気にて、例えば 500— 700°C、 30— 120分間の熱処理を行う。 [0114] Next, heat treatment is performed in an oxygen atmosphere, for example, at 500 to 700 ° C for 30 to 120 minutes.
[0115] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 1500nmのシリ コン酸化膜よりなる層間絶縁膜 48を形成する（図 7 (b)を参照）。 Next, an interlayer insulating film 48 made of a silicon oxide film having a thickness of, eg, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 7B).
[0116] 次いで、例えば CMP法により、層間絶縁膜 48の表面を平坦ィ匕する（図 7 (c)を参照[0116] Next, the surface of the interlayer insulating film 48 is planarized by, eg, CMP (see FIG. 7C).
) o ) o
[0117] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、層間絶縁膜 48中の水分を除去するとと もに、層間絶縁膜 48の膜質を変化させ、層間絶縁膜 48中に水分が入りに《するた めのものである。この熱処理により、層間絶縁膜 48の表面は窒化され、層間絶縁膜 4 8の表面には SiON膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the interlayer insulating film 48 and changing the film quality of the interlayer insulating film 48 so that moisture enters the interlayer insulating film 48. By this heat treatment, the surface of the interlayer insulating film 48 is nitrided, and a SiON film (not shown) is formed on the surface of the interlayer insulating film 48.
[0118] 次いで、フォトリソグラフィー及びエッチングにより、層間絶縁膜 48、ノ リア膜 46、シ リコン酸化膜 34、及び層間絶縁膜 27に、ソース/ドレイン拡散層 22に達するコンタク トホール 50a、 50bを形成する（図 8 (a)を参照）。  [0118] Next, contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed in the interlayer insulating film 48, the NORA film 46, the silicon oxide film 34, and the interlayer insulating film 27 by photolithography and etching. (See Figure 8 (a)).
[0119] 次いで、全面に、例えばスパッタ法により、例えば膜厚 20nmの Ti膜を形成する。  [0119] Next, a Ti film of, eg, a 20 nm-thickness is formed on the entire surface by, eg, sputtering.
続いて、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。こ うして、 Ti膜と TiN膜とによりバリアメタル膜（図示せず）が構成される。  Subsequently, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering. Thus, the Ti film and the TiN film constitute a barrier metal film (not shown).
[0120] 次いで、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  [0120] Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0121] 次いで、例えば CMP法により、層間絶縁膜 48の表面が露出するまで、タンダステ ン膜及びバリアメタル膜を研磨する。こうして、コンタクトホール 50a、 50b内に、タンダ ステンよりなる導体プラグ 54a、 54bがそれぞれ坦め込まれる（図 8 (b)を参照）。  Next, the tandastain film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 48 is exposed. In this manner, the conductor plugs 54a and 54b made of tungsten are loaded in the contact holes 50a and 50b, respectively (see FIG. 8 (b)).
[0122] 次いで、例えばアルゴンガスを用いたプラズマ洗浄を行う。これにより、導体プラグ 5 4a、 54b表面に存在する自然酸化膜等が除去される。  Next, plasma cleaning using, for example, argon gas is performed. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 54a and 54b are removed.
[0123] 次いで、全面に、例えば CVD法により、例えば膜厚 lOOnmの Si〇N膜 104を形成 する。  Next, a SiON film 104 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD.
[0124] 次いで、フォトリソグラフィー及びドライエッチングにより、 Si〇N膜 104、層間絶縁膜 48、バリア膜 46、及びバリア膜 44に、強誘電体キャパシタ 42の上部電極 40に達す るコンタクトホール 52aと、強誘電体キャパシタ 42の下部電極 36に達するコンタクトホ ール 52aとを形成する（図 8 (c)を参照）。 [0124] Next, the upper electrode 40 of the ferroelectric capacitor 42 is reached in the SiON film 104, the interlayer insulating film 48, the barrier film 46, and the barrier film 44 by photolithography and dry etching. The contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 is formed (see FIG. 8 (c)).
[0125] 次いで、酸素雰囲気にて、例えば 400— 600°C、 30— 120分間の熱処理を行う。 [0125] Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
この熱処理は、強誘電体キャパシタ 42の強誘電体膜 38に酸素を供給し、強誘電体 キャパシタ 42の電気的特性を回復するためのものである。なお、ここでは酸素雰囲気 中にて熱処理を行う場合を例に説明したが、オゾン雰囲気中にて熱処理を行っても よい。オゾン雰囲気中にて熱処理を行った場合にも、キャパシタの強誘電体膜 38に 酸素を供給することができ、強誘電体キャパシタ 42の電気的特性を回復することが 可能である。  This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42. Note that here, the case where the heat treatment is performed in an oxygen atmosphere has been described as an example, but the heat treatment may be performed in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen can be supplied to the ferroelectric film 38 of the capacitor, and the electrical characteristics of the ferroelectric capacitor 42 can be recovered.
[0126] 次いで、エッチングにより SiON膜 104を除去する。  [0126] Next, the SiON film 104 is removed by etching.
[0127] 次いで、全面に、例えば膜厚 150nmの TiN膜と、例えば膜厚 550nmの AlCu合金 膜と、例えば膜厚 5nmの Ti膜と、膜厚 150nmの TiN膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と Ti膜と TiN膜とを順次積層してなる導体膜が形成される。  Next, for example, a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially stacked on the entire surface. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
[0128] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターニングする 。これにより、第 1金属配線層 56、すなわち強誘電体キャパシタ 42の上部電極 40と 導体プラグ 54aとに電気的に接続された配線 56a、強誘電体キャパシタ 42の下部電 極 36に電気的に接続された配線 56b、及び導体プラグ 54bに電気的に接続された 配線 56cが形成される（図 9 (a)を参照）。  Next, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 56, that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected. The wiring 56b thus formed and the wiring 56c electrically connected to the conductor plug 54b are formed (see FIG. 9 (a)).
[0129] 次いで、酸素雰囲気にて、例えば 350°C、 30分間の熱処理を行う。  [0129] Next, heat treatment is performed in an oxygen atmosphere, for example, at 350 ° C for 30 minutes.
[0130] 次いで、全面に、例えばスパッタ法又は CVD法により、ノくリア膜 58を形成する。バ リア膜 58としては、例えば膜厚 20— 70nmの酸化アルミニウム膜を形成する（図 9 (b )を参照）。ここでは、バリア膜 58として、膜厚 20nmの酸化アルミニウム膜を形成する 。こうして、配線 56a、 56b, 56cの上面及び側面を覆うようにバリア膜 58が形成され る。  Next, a silicon film 58 is formed on the entire surface by, eg, sputtering or CVD. As the barrier film 58, for example, an aluminum oxide film having a film thickness of 20 to 70 nm is formed (see FIG. 9B). Here, as the barrier film 58, an aluminum oxide film having a thickness of 20 nm is formed. Thus, the barrier film 58 is formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, and 56c.
[0131] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 2600nmのシリ コン酸化膜 60を形成する（図 10 (a)を参照）。  Next, a silicon oxide film 60 of, eg, a 2600 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 10A).
[0132] 次いで、例えば CMP法により、シリコン酸化膜 60の表面を平坦化する（図 10 (b)を 参照）。 [0133] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0132] Next, the surface of the silicon oxide film 60 is planarized by, eg, CMP (see FIG. 10B). [0133] Next, in a plasma atmosphere generated using NO gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 60中の水分を除去する とともに、シリコン酸化膜 60の膜質を変化させ、シリコン酸化膜 60中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 60の表面は窒化され、シ リコン酸化膜 60の表面には Si〇N膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 60 and changing the film quality of the silicon oxide film 60 so that moisture does not easily enter the silicon oxide film 60. By this heat treatment, the surface of the silicon oxide film 60 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 60.
[0134] 次いで、平坦化されたシリコン酸化膜 60上に、例えばプラズマ TEOSCVD法によ り、例えば膜厚 lOOnmのシリコン酸化膜 61を形成する。平坦化されたシリコン酸化 膜 60上にシリコン酸化膜 61を形成するため、シリコン酸化膜 61は平坦となる。  Next, a silicon oxide film 61 having a thickness of, for example, lOOnm is formed on the planarized silicon oxide film 60 by, eg, plasma TEOSCVD. Since the silicon oxide film 61 is formed on the planarized silicon oxide film 60, the silicon oxide film 61 becomes flat.
[0135] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0135] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 61中の水分を除去する とともに、シリコン酸化膜 61の膜質を変化させ、シリコン酸化膜 61中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 61の表面は窒化され、シ リコン酸化膜 61の表面には SiON膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 61 and changing the film quality of the silicon oxide film 61 so that moisture does not easily enter the silicon oxide film 61. By this heat treatment, the surface of the silicon oxide film 61 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 61.
[0136] 次いで、平坦なシリコン酸化膜 61上に、例えばスパッタ法又は CVD法により、バリ ァ膜 62を形成する。バリア膜 62としては、例えば膜厚 20— 70nmの酸化アルミニゥ ム膜を形成する。ここでは、ノくリア膜 62として、膜厚 50nmの酸化アルミニウム膜を形 成する。平坦なシリコン酸化膜 61上にバリア膜 62を形成するため、バリア膜 62は平 坦となる。 Next, the barrier film 62 is formed on the flat silicon oxide film 61 by, eg, sputtering or CVD. As the barrier film 62, for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Here, an aluminum oxide film having a thickness of 50 nm is formed as the noble film 62. Since the barrier film 62 is formed on the flat silicon oxide film 61, the barrier film 62 becomes flat.
[0137] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 64を形成する（図 11 (a)を参照）。  [0137] Next, a silicon oxide film 64 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 11A).
[0138] こうして、バリア膜 58、シリコン酸化膜 60、シリコン酸化膜 61、バリア膜 62、及びシリ コン酸化膜 64により層間絶縁膜 66が構成される。 Thus, the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64 constitute the interlayer insulating film 66.
[0139] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0139] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 64中の水分を除去する とともに、シリコン酸化膜 64の膜質を変化させ、シリコン酸化膜 64中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 64の表面は窒化され、シ リコン酸化膜 64の表面には Si〇N膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 64 and changing the film quality of the silicon oxide film 64 so that moisture does not easily enter the silicon oxide film 64. By this heat treatment, the surface of the silicon oxide film 64 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 64.
[0140] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸化膜 64、バリア 膜 62、シリコン酸化膜 61、シリコン酸化膜 60、及びノくリア膜 58に、配線 56cに達する コンタクトホール 68を形成する（図 11 (b)を参照）。 [0140] Next, the silicon oxide film 64 and the barrier are formed by photolithography and dry etching. A contact hole 68 reaching the wiring 56c is formed in the film 62, the silicon oxide film 61, the silicon oxide film 60, and the silicon film 58 (see FIG. 11B).
[0141] 次いで、 N雰囲気にて、例えば 350°C、 120分間の熱処理を行う。 [0141] Next, heat treatment is performed in an N atmosphere at, for example, 350 ° C for 120 minutes.
2  2
[0142] 次いで、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。  [0142] Next, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
こうして、 TiN膜によりバリアメタル膜（図示せず）が構成される。  Thus, a barrier metal film (not shown) is constituted by the TiN film.
[0143] 次いで、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  [0143] Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0144] 次いで、例えば EB (エッチバック）法により、 TiN膜の表面が露出するまで、タンダ ステン膜をエッチバックする。こうして、コンタクトホール 68内に、タングステンよりなる 導体プラグ 70が坦め込まれる（図 12 (a)を参照）。  [0144] Next, the tungsten film is etched back by, for example, the EB (etch back) method until the surface of the TiN film is exposed. Thus, the conductor plug 70 made of tungsten is loaded in the contact hole 68 (see FIG. 12A).
[0145] 次いで、全面に、例えば膜厚 500nmの AlCu合金膜と、例えば膜厚 5nmの Ti膜と[0145] Next, on the entire surface, for example, an AlCu alloy film having a thickness of 500 nm, and a Ti film having a thickness of 5 nm, for example,
、例えば膜厚 150nmの TiN膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と T i膜と TiN膜とを順次積層してなる導体膜が形成される。 For example, a TiN film having a thickness of 150 nm is sequentially stacked. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
[0146] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターニングする[0146] Next, the conductor film is patterned by photolithography and dry etching.
。これにより、第 2金属配線層 72、すなわち配線 72a、及び導体プラグ 70に電気的に 接続された配線 72bが形成される（図 12 (b)を参照）。 . As a result, the second metal wiring layer 72, that is, the wiring 72a and the wiring 72b electrically connected to the conductor plug 70 are formed (see FIG. 12B).
[0147] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 2200nmのシリ コン酸化膜 74を形成する（図 13 (a)を参照）。 Next, a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 13A).
[0148] 次いで、例えば CMP法により、シリコン酸化膜 74の表面を平坦ィ匕する（図 13 (b)を 参照）。 Next, the surface of the silicon oxide film 74 is flattened by, eg, CMP (see FIG. 13B).
[0149] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0149] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 74中の水分を除去する とともに、シリコン酸化膜 74の膜質を変化させ、シリコン酸化膜 74中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 74の表面は窒化され、シ リコン酸化膜 74の表面には Si〇N膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing water in the silicon oxide film 74 and changing the film quality of the silicon oxide film 74 so that the water does not easily enter the silicon oxide film 74. By this heat treatment, the surface of the silicon oxide film 74 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 74.
[0150] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 76を形成する。平坦化されたシリコン酸化膜 74上にシリコン酸化膜 76を 形成するため、シリコン酸化膜 76は平坦となる。 [0151] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 Next, a silicon oxide film 76 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD. Since the silicon oxide film 76 is formed on the planarized silicon oxide film 74, the silicon oxide film 76 becomes flat. [0151] Next, in a plasma atmosphere generated using NO gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 76中の水分を除去する とともに、シリコン酸化膜 76の膜質を変化させ、シリコン酸化膜 76中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 76の表面は窒化され、シ リコン酸化膜 76の表面には Si〇N膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 76 and changing the film quality of the silicon oxide film 76 to make it difficult for moisture to enter the silicon oxide film 76. By this heat treatment, the surface of the silicon oxide film 76 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 76.
[0152] 次いで、平坦なシリコン酸化膜 76上に、例えばスパッタ法又は CVD法により、バリ ァ膜 78を形成する。バリア膜 78としては、例えば膜厚 20 70nmの酸化アルミユウ ム膜を形成する。ここでは、ノ リア膜 78として、膜厚 50nmの酸化アルミニウム膜を形 成する。平坦なシリコン酸化膜 76上にバリア膜 78を形成するため、バリア膜 78は平 坦となる。 Next, a barrier film 78 is formed on the flat silicon oxide film 76 by, eg, sputtering or CVD. As the barrier film 78, for example, an aluminum oxide film having a thickness of 2070 nm is formed. Here, an aluminum oxide film having a thickness of 50 nm is formed as the noor film 78. Since the barrier film 78 is formed on the flat silicon oxide film 76, the barrier film 78 becomes flat.
[0153] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 80を形成する（図 14 (a)を参照）。  Next, a silicon oxide film 80 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 14 (a)).
[0154] こうして、シリコン酸化膜 74、シリコン酸化膜 76、バリア膜 78、及びシリコン酸化膜 8Thus, the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 8
0により層間絶縁膜 82が構成される。 The interlayer insulating film 82 is constituted by zero.
[0155] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0155] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 80中の水分を除去する とともに、シリコン酸化膜 76の膜質を変化させ、シリコン酸化膜 80中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 80の表面は窒化され、シ リコン酸化膜 80の表面には SiON膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 80 and changing the film quality of the silicon oxide film 76 so that moisture does not easily enter the silicon oxide film 80. By this heat treatment, the surface of the silicon oxide film 80 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 80.
[0156] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸化膜 80、バリア 膜 78、シリコン酸化膜 76、及びシリコン酸化膜 74に、配線 72a、 72bに達するコンタ タトホーノレ 84a、 84bを形成する（図 14 (b)を参照）。  Next, contact horns 84a and 84b reaching the wirings 72a and 72b are formed in the silicon oxide film 80, the barrier film 78, the silicon oxide film 76, and the silicon oxide film 74 by photolithography and dry etching (FIG. 14). (See (b)).
[0157] 次いで、 N雰囲気にて、例えば 350°C、 120分間の熱処理を行う。  [0157] Next, heat treatment is performed in an N atmosphere at, for example, 350 ° C for 120 minutes.
2  2
[0158] 次いで、全面に、例えばスパッタ法により、例えば膜厚 50nmの TiN膜を形成する。  [0158] Next, a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
こうして、 TiN膜によりバリアメタル膜（図示せず）が構成される。  Thus, a barrier metal film (not shown) is constituted by the TiN film.
[0159] 次いで、全面に、例えば CVD法により、例えば膜厚 500nmのタングステン膜を形 成する。  [0159] Next, a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
[0160] 次いで、例えば EB法により、 TiN膜の表面が露出するまで、タングステン膜をエツ チバックする。こうして、コンタクトホーノレ 84a、 84b内に、タングステンよりなる導体プ ラグ 86a、 86bがそれぞれ坦め込まれる（図 15 (a)を参照）。 [0160] Next, the tungsten film is etched until the surface of the TiN film is exposed, for example, by the EB method. Chibak back. In this way, the conductor plugs 86a and 86b made of tungsten are loaded in the contact holes 84a and 84b, respectively (see FIG. 15 (a)).
[0161] 次いで、全面に、例えば膜厚 500nmの AlCu合金膜と、例えば膜厚 150nmの TiN 膜とを順次積層する。こうして、 TiN膜と AlCu合金膜と TiN膜とを順次積層してなる 導体膜が形成される。 [0161] Next, an AlCu alloy film having a thickness of, for example, 500 nm and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, and a TiN film.
[0162] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターユングする 。これにより、第 3金属配線層 88、すなわち導体プラグ 86aに電気的に接続された配 線 88a、及び導体プラグ 88bに電気的に接続された配線 88bが形成される（図 15 (b )を参照）。  [0162] Next, the conductor film is patterned by photolithography and dry etching. As a result, the third metal wiring layer 88, that is, the wiring 88a electrically connected to the conductor plug 86a and the wiring 88b electrically connected to the conductor plug 88b are formed (see FIG. 15 (b)). ).
[0163] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 90を形成する。  Next, a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
[0164] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35 [0164] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 90中の水分を除去する とともに、シリコン酸化膜 90の膜質を変化させ、シリコン酸化膜 90中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 90の表面は窒化され、シ リコン酸化膜 90の表面には SiON膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 2 minutes. This heat treatment is for removing moisture in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that moisture does not easily enter the silicon oxide film 90. By this heat treatment, the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
[0165] 次いで、例えば CVD法により、例えば膜厚 350nmのシリコン窒化膜 92を形成する  Next, a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
(図 16 (a)を参照）。シリコン窒化膜 92は、水分を遮断し、水分により金属配線層 88、 72、 56等が腐食するのを防止するためのものである。  (See Figure 16 (a)). The silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
[0166] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 106を形成する。  [0166] Next, a photoresist film 106 is formed on the entire surface by, eg, spin coating.
[0167] 次いで、フォトリソグラフィ一により、フォトレジスト膜 106に、配線（ボンディングパッ ド） 88bに達する開口部をシリコン窒化膜 92及びシリコン酸化膜 90に形成する領域 を露出する開口部 108を形成する。  [0167] Next, by photolithography, an opening 108 is formed in the photoresist film 106 to expose a region where the opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90. .
[0168] 次いで、フォトレジスト膜 106をマスクとして、シリコン窒化膜 92及びシリコン酸化膜  Next, using the photoresist film 106 as a mask, the silicon nitride film 92 and the silicon oxide film
90をエッチングする。こうして、シリコン窒化膜 92及びシリコン酸化膜 90に、配線 (ボ ンデイングパッド） 88bに達する開口部 96aが形成される（図 16 (b)を参照）。この後、 フォトレジスト膜 106を剥離する。  Etch 90. Thus, an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90 (see FIG. 16B). Thereafter, the photoresist film 106 is peeled off.
[0169] 次いで、例えばスピンコート法により、例えば膜厚 2— 6 μ mのポリイミド樹脂膜 94を 形成する（図 17 (a)を参照)。 [0169] Next, for example, a polyimide resin film 94 having a film thickness of 2 to 6 μm is formed by spin coating, for example. (See Fig. 17 (a)).
[0170] 次いで、フォトリソグラフィ一により、ポリイミド榭脂膜 94に、配線 (ボンディングパッド ) 88bに達する開口部 96bを形成する（図 17 (b)を参照）。  Next, an opening 96b reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94 by photolithography (see FIG. 17B).
[0171] こうして、本実施形態による半導体装置が製造される。  Thus, the semiconductor device according to the present embodiment is manufactured.
[0172] (評価結果）  [0172] (Evaluation result)
本実施形態による半導体装置について PTHS試験を行レ、、本実施形態による半導 体装置の PTHS特性を評価した結果について説明する。  A PTHS test is performed on the semiconductor device according to the present embodiment, and the results of evaluating the PTHS characteristics of the semiconductor device according to the present embodiment are described.
[0173] PTHS試験では、 2気圧、温度 121°C、湿度 100%の条件下で、本実施形態による 半導体装置の FeRAMチップを保管し、 168時間、 336時間、 504時間、 504時間、 及び 672時間経過した時点のそれぞれにおいて、同一ゥヱーハを用いて形成された 5つのチップ試料毎に不良セルの発生の有無を確認した。 PTHS試験を行った本実 施形態による半導体装置では、バリア膜 58の膜厚を 20nm、平坦なバリア膜 62の膜 厚を 50nm、平坦なノくリア膜 78の月莫厚を 70nmとした。  [0173] In the PTHS test, the FeRAM chip of the semiconductor device according to the present embodiment was stored under conditions of 2 atm, temperature of 121 ° C, and humidity of 100%, and 168 hours, 336 hours, 504 hours, 504 hours, and 672 At each time point, the presence or absence of defective cells was confirmed for each of the five chip samples formed using the same woofer. In the semiconductor device according to the present embodiment in which the PTHS test was performed, the thickness of the barrier film 58 was set to 20 nm, the thickness of the flat barrier film 62 was set to 50 nm, and the monthly thickness of the flat rear film 78 was set to 70 nm.
[0174] なお、比較例として、平坦なバリア膜 58が形成されていない場合、すなわち平坦な バリア膜が 1層のみ形成されている場合についても上記と同様の PTHS試験を行つ た。比較例 1による半導体装置では、バリア膜 58の膜厚を 70nm、平坦なバリア膜 78 の膜厚を 70nmとした。また、比較例 2による半導体装置では、バリア膜 58の膜厚を 2 Onm、平坦なバリア膜 78の膜厚を 50nmとした。なお、比較例 1、 2による半導体装 置の構造は、平坦なバリア膜 58が形成されていない点を除いては、本実施形態によ る半導体装置と同様にした。  [0174] As a comparative example, the PTHS test similar to the above was performed when the flat barrier film 58 was not formed, that is, when only one flat barrier film was formed. In the semiconductor device according to Comparative Example 1, the thickness of the barrier film 58 was set to 70 nm, and the thickness of the flat barrier film 78 was set to 70 nm. In the semiconductor device according to Comparative Example 2, the thickness of the barrier film 58 was 2 Onm, and the thickness of the flat barrier film 78 was 50 nm. The structure of the semiconductor device according to Comparative Examples 1 and 2 was the same as that of the semiconductor device according to the present embodiment except that the flat barrier film 58 was not formed.
[0175] PTHS試験の結果は以下の通りとなった。  [0175] The results of the PTHS test were as follows.
[0176] まず、本実施形態の場合、 5つのチップ試料のすべてについて、 168時間、 336時 間、 504時間、 504時間、及び 672時間経過した時点のいずれにおいても、不良セ ルが発生することはなかった。  [0176] First, in the case of the present embodiment, defective cells occur at all of 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours for all five chip samples. There was no.
[0177] 一方、比較例 1の場合、 5つのチップ試料のうち、あるチップ試料では、 168時間経 過した時点で 1個の不良セルが発生し、 336時間経過した時点で不良セルは 3個と なり、 504時間経過した時点で不良セルは 10個となり、 672時間経過した時点で不 良セルは 18個となった。また、他のチップ試料では、 168時間及び 336時間経過し た時点までは不良セルは発生しなかったが、 504時間経過した時点で 1個の不良セ ルが発生し、 672時間経過した時点で不良セルは 26個となった。更に他のチップ試 料では、 168時間及び 336時間経過した時点までは不良セルは発生しな力 たが、 504時間経過した時点で 22個の不良セルが発生し、 672時間経過した時点で不良 セノレは 62個となった。 5つのチップ試料のうち、 168日寺間、 3363寺間、 504日寺間、 504 時間、及び 672時間経過した時点のいずれにおいても不良セルが発生しなかったの は、 2つのチップ試料のみであった。 [0177] On the other hand, in Comparative Example 1, one of the five chip samples had one defective cell after 168 hours, and three defective cells after 336 hours. When 504 hours passed, there were 10 defective cells, and when 672 hours passed, there were 18 bad cells. For other chip samples, 168 hours and 336 hours have passed. No defective cells were generated up to the time point, but one defective cell was generated after 504 hours, and 26 defective cells were reached after 672 hours. Furthermore, in other chip samples, no defective cells were generated until 168 hours and 336 hours passed, but 22 defective cells were generated after 504 hours and failed after 672 hours passed. There were 62 Senores. Of the five chip samples, only two chip samples had no defective cells at any time after 168 days temple, 3363 temples, 504 days temple, 504 hours, and 672 hours. there were.
[0178] また、比較例 2の場合、 5つのチップ試料のうち、あるチップ試料では、 168時間経 過した時点で 19個の不良セルが発生し、 336時間経過した時点で不良セルは 34個 となり、 504時間経過した時点で不良セルは 51個となり、 672時間経過した時点で不 良セルは 72個となった。また、他のチップ試料では、 168時間経過した時点では不 良セルは発生しなかったが、 336時間経過した時点で 3個の不良セルが発生し、 50 4時間経過した時点で不良セルは 5個となり、 672時間経過した時点で不良セルは 7 個となった。更に他のチップ試料では、 168時間経過した時点では不良セルは発生 しな力 た力 336時間経過した時点で 3個の不良セルが発生し、 504時間経過した 時点で不良セルは 113個となり、 672時間経過した時点で不良セルは 811個となつ た。更に他のチップ試料では、 168時間経過した時点で 106個の不良セルが発生し 、 336時間経過した時点で不良セルは 1690個となり、 504時間経過した時点で不良 セルは 3253個となり、 672時間経過した時点で不良セルは 5184個となった。 5つの チップ試料のうち、 168時間、 336時間、 504時間、 504時間、及び 672時間経過し た時点のいずれにおいても不良セルが発生しなかったのは、 1つのチップ試料のみ であった。 [0178] In the case of Comparative Example 2, in one chip sample among the five chip samples, 19 defective cells were generated after 168 hours and 34 defective cells were reached after 336 hours. When 504 hours passed, there were 51 defective cells, and when 672 hours passed, there were 72 bad cells. In other chip samples, no defective cells were generated after 168 hours, but 3 defective cells were generated after 336 hours, and 5 defective cells were detected after 504 hours. When 672 hours passed, there were 7 defective cells. Furthermore, in another chip sample, when 168 hours passed, the force that did not generate a defective cell. When 336 hours passed, three defective cells were generated, and when 504 hours passed, there were 113 defective cells. When 672 hours passed, there were 811 defective cells. In another chip sample, 106 defective cells were generated when 168 hours passed, 1690 defective cells were reached after 336 hours, and 3253 defective cells were reached after 504 hours, 672 hours. At that time, there were 5184 defective cells. Of the five chip samples, only one chip sample had no defective cells at any time after 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours.
[0179] 上記 PTHS試験の結果から、本実施形態によれば、強誘電体キャパシタを有する 半導体装置の PTHS特性を大幅に向上することができ、 FeRAMに関して PTHS試 験の量産認定レベルを充分に上回ることができることが確認された。  [0179] From the results of the PTHS test, according to the present embodiment, the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved, and the mass production certification level of the PTHS test for FeRAM is sufficiently exceeded. It was confirmed that it was possible.
[0180] また、単に平坦なノ リア膜を 1層形成しただけでは、充分な耐湿性を確保することが できず、強誘電体キャパシタを有する半導体装置の PTHS特性の向上を実現するこ とが困難であることが確認された。 [0181] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 バリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属配 線層 72と第 3金属配線層 88との間に形成された平坦なバリア膜 78とを有するので、 水素及び水分を確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強誘電 体膜 38に達するのを確実に防止することができる。これにより、水素及び水分による 強誘電体キャパシタ 42の電気的特性の劣化を確実に防止することができ、強誘電体 キャパシタを有する半導体装置の PTHS特性を大幅に向上することができる。 [0180] Further, it is not possible to ensure sufficient moisture resistance simply by forming a single flat noria film, and it is possible to improve the PTHS characteristics of a semiconductor device having a ferroelectric capacitor. It was confirmed that it was difficult. As described above, according to the present embodiment, as the barrier film for preventing the diffusion of hydrogen and moisture, in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided. A flat barrier film 62 formed between the metal wiring layer 56 and the second metal wiring layer 72, and a flat barrier film formed between the second metal wiring layer 72 and the third metal wiring layer 88. 78, it is possible to reliably block hydrogen and moisture and reliably prevent hydrogen and moisture from reaching the ferroelectric film 38 of the ferroelectric capacitor 42. As a result, the electrical characteristics of the ferroelectric capacitor 42 can be reliably prevented from being deteriorated by hydrogen and moisture, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
[0182] [第 2実施形態]  [0182] [Second Embodiment]
本発明の第 2実施形態による半導体装置及びその製造方法について図 18乃至図 21を用いて説明する。図 18は本実施形態による半導体装置の構造を示す断面図、 図 19乃至図 21は本実施形態による半導体装置の製造方法を示す工程断面図であ る。なお、第 1実施形態による半導体装置及びその製造方法と同様の構成要素には 、同一の符号を付し説明を省略或いは簡略にする。  A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 18 is a sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 19 to 21 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0183] (半導体装置）  [0183] (Semiconductor device)
本実施形態による半導体装置の基本的構成は、第 1実施形態による半導体装置と ほぼ同様である。本実施形態による半導体装置は、第 3金属配線層 88 (配線 88a、 8 8b)の上方に形成されたノ リア膜 114を更に有する点で、第 1実施形態による半導体 装置と異なっている。  The basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the present embodiment further includes a NOR film 114 formed above the third metal wiring layer 88 (wirings 88a and 88b).
[0184] すなわち、図 18に示すように、層間絶縁膜 82上及び配線 88a、 88b上には、例え ば膜厚 1500nmのシリコン酸化膜 112が形成されている。シリコン酸化膜 112の表面 は、その形成後に例えば CMP法により平坦ィ匕されており、配線 88b上のシリコン酸 化膜 112は例えば 350nmの膜厚で残存してレ、る。  That is, as shown in FIG. 18, a silicon oxide film 112 having a thickness of, eg, 1500 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b. The surface of the silicon oxide film 112 is flattened by, for example, CMP after the formation thereof, and the silicon oxide film 112 on the wiring 88b remains, for example, with a film thickness of 350 nm.
[0185] 平坦ィ匕されたシリコン酸化膜 112上には、ノ^ァ膜 114が形成されている。バリア膜 114としては、例えば膜厚 20 70nmの酸化アルミニウム膜が用いられている。平坦 化されたシリコン酸化膜 112上にバリア膜 114が形成されてレ、るため、バリア膜 114 は平坦となっている。  On the flattened silicon oxide film 112, a silicon film 114 is formed. As the barrier film 114, for example, an aluminum oxide film having a thickness of 2070 nm is used. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the barrier film 114 is flat.
[0186] バリア膜 114は、バリア膜 44、 46、 58、 62、 78と同様に、水素及び水分の拡散を 防止する機能を有する膜である。さらに、バリア膜 114は、平坦化されたシリコン酸化 膜 112上に形成されているため平坦となっており、バリア膜 62、 78と同様に、バリア 膜 44、 46、 58と比較して、極めて良好な被覆性で形成されている。したがって、この ような平坦なバリア膜 114により、更に確実に水素及び水分の拡散を防止することが できる。なお、実際には、バリア膜 114は、バリア膜 62、 78と同様に、強誘電体キャパ シタ 42を有する複数のメモリセルが配列された FeRAMチップのメモリセル領域のみ ならず、周辺回路領域等を含む FeRAMチップの全面にわたって形成されている。 [0186] The barrier film 114, like the barrier films 44, 46, 58, 62, 78, diffuses hydrogen and moisture. It is a film having a function to prevent. Further, since the barrier film 114 is formed on the flattened silicon oxide film 112, it is flat, and in the same way as the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, the barrier film 114 is extremely flat. It is formed with good coverage. Accordingly, such a flat barrier film 114 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 114 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit area, etc. It is formed over the entire surface of the FeRAM chip including
[0187] バリア膜 114上には、例えば膜厚 50— 150nmのシリコン酸化膜 90が形成されて いる。 [0187] On the barrier film 114, for example, a silicon oxide film 90 having a thickness of 50 to 150 nm is formed.
[0188] シリコン酸化膜 90上には、例えば膜厚 350nmのシリコン窒化膜 92が形成されてい る。  [0188] On the silicon oxide film 90, for example, a silicon nitride film 92 having a thickness of 350 nm is formed.
[0189] シリコン窒化膜 92上には、例えば膜厚 3 6 μ mのポリイミド樹脂膜 94が形成され ている。  [0189] On the silicon nitride film 92, for example, a polyimide resin film 94 with a film thickness of 36 μm is formed.
[0190] ポリイミド榭脂膜 94、シリコン窒化膜 92、シリコン酸化膜 90、バリア膜 114、及びシリ コン酸化膜 112には、配線 (ボンディングパッド） 88bに達する開口部 96が形成され ている。すなわち、シリコン窒化膜 92、シリコン酸化膜 90、バリア膜 114、及びシリコ ン酸化膜 112には、配線 (ボンディングパッド） 88bに達する開口部 96aが形成されて いる。ポリイミド樹脂膜 94には、シリコン窒化膜 92、シリコン酸化膜 90、バリア膜 114 、及びシリコン酸化膜 112に形成された開口部 96aを含む領域に、開口部 96bが形 成されている。  [0190] The polyimide resin film 94, the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 have an opening 96 reaching the wiring (bonding pad) 88b. That is, in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112.
[0191] このように、本実施形態による半導体装置は、水素及び水分の拡散を防止するバリ ァ膜として、バリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42の上方に形成さ れた第 1金属配線層 56 (配線 56a、 56b, 56c)と第 2金属配線層 72 (配線 72a、 72b )との間に形成された平坦なバリア膜 62と、第 2金属配線層 72 (配線 72a、 72b)と第 3金属配線層 88 (配線 88a、 88b)との間に形成された平坦なバリア膜 78と、第 3金 属配線層 88 (配線 88a、 88b)の上方に形成された平坦なバリア膜 114とを有するこ とに主たる特徴がある。  As described above, the semiconductor device according to the present embodiment is formed above the ferroelectric capacitor 42 in addition to the barrier films 44, 46, and 58 as a barrier film for preventing diffusion of hydrogen and moisture. A flat barrier film 62 formed between the first metal wiring layer 56 (wiring 56a, 56b, 56c) and the second metal wiring layer 72 (wiring 72a, 72b), and the second metal wiring layer 72 (wiring 72a, 72b) and the third metal wiring layer 88 (wiring 88a, 88b) and a flat barrier film 78 formed above the third metal wiring layer 88 (wiring 88a, 88b). The main feature is that it has a flat barrier film 114.
[0192] 本実施形態による半導体装置では、第 1実施形態による半導体装置における平坦 なバリア膜 62、 78に加えて、第 3金属配線層 88の上方に平坦なバリア膜 114が形成 されているので、水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キ ャパシタ 42の強誘電体膜 38に達するのを更に確実に防止することができる。これに より、水素及び水分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に 防止することができ、強誘電体キャパシタを有する半導体装置の PTHS特性を更に 大幅に向上することができる。 [0192] The semiconductor device according to the present embodiment is flat in the semiconductor device according to the first embodiment. In addition to the barrier films 62 and 78, the flat barrier film 114 is formed above the third metal wiring layer 88, so that the hydrogen and moisture are more securely barriered, and the hydrogen and moisture are ferroelectric capacitors. Reaching the ferroelectric film 38 of 42 can be prevented more reliably. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved.
[0193] (半導体装置の製造方法） [0193] (Method for Manufacturing Semiconductor Device)
次に、本実施形態による半導体装置の製造方法について図 19乃至図 21を用いて 説明する。  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0194] まず、図 4乃至図 15に示す第 1実施形態による半導体装置の製造方法と同様にし て、第 3金属配線層（配線 88a、配線 88b)までを形成する。  First, the third metal wiring layer (wiring 88a, wiring 88b) is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS.
[0195] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 1500nmのシリ コン酸化膜 112を形成する（図 19 (a)を参照）。 Next, a silicon oxide film 112 of, eg, a 1500 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 19A).
[0196] 次いで、例えば CMP法により、シリコン酸化膜 112の表面を平坦ィ匕する（図 19 (b) を参照）。 [0196] Next, the surface of the silicon oxide film 112 is planarized by, eg, CMP (see FIG. 19B).
[0197] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0197] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 4分間の熱処理を行う。この熱処理は、シリコン酸化膜 112中の水分を除去する とともに、シリコン酸化膜 112の膜質を変化させ、シリコン酸化膜 112中に水分が入り にくくするためのものである。この熱処理により、シリコン酸化膜 112の表面は窒化さ れ、シリコン酸化膜 112の表面には、 SiON膜（図示せず）が形成される。  Perform heat treatment at 0 ° C for 4 minutes. This heat treatment is for removing moisture in the silicon oxide film 112 and changing the film quality of the silicon oxide film 112 so that the moisture does not easily enter the silicon oxide film 112. By this heat treatment, the surface of the silicon oxide film 112 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 112.
[0198] 次いで、平坦ィ匕されたシリコン酸化膜 112上に、例えばスパッタ法又は CVD法によ り、 バリア膜 114を形成する。ノ リア膜 114としては、例えば膜厚 20— 70nmの酸化 アルミニウム膜を形成する。平坦化されたシリコン酸化膜 112上にバリア膜 114を形 成するため、ノ リア膜 114は平坦となる。  Next, a barrier film 114 is formed on the flattened silicon oxide film 112 by, eg, sputtering or CVD. As the nore film 114, for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the NOR film 114 becomes flat.
[0199] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 90を形成する。  Next, a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
[0200] 次いで、 N Oガス又は Nガスを用いて発生させたプラズマ雰囲気にて、例えば 35  [0200] Next, in a plasma atmosphere generated using N 2 O gas or N gas, for example, 35
2 2  twenty two
0°C、 2分間の熱処理を行う。この熱処理は、シリコン酸化膜 90中の水分を除去する とともに、シリコン酸化膜 90の膜質を変化させ、シリコン酸化膜 90中に水分が入りにく くするためのものである。この熱処理により、シリコン酸化膜 90の表面は窒化され、シ リコン酸化膜 90の表面には SiON膜（図示せず）が形成される。 Perform heat treatment at 0 ° C for 2 minutes. This heat treatment removes moisture in the silicon oxide film 90. At the same time, the film quality of the silicon oxide film 90 is changed to make it difficult for moisture to enter the silicon oxide film 90. By this heat treatment, the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
[0201] 次いで、例えば CVD法により、例えば膜厚 350nmのシリコン窒化膜 92を形成する  Next, a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
(図 20 (a)を参照）。シリコン窒化膜 92は、水分を遮断し、水分により金属配線層 88、 72、 56等が腐食するのを防止するためのものである。  (See Figure 20 (a)). The silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
[0202] 次いで、全面に、例えばスピンコート法により、フォトレジスト膜 106を形成する。  [0202] Next, a photoresist film 106 is formed on the entire surface by, eg, spin coating.
[0203] 次いで、フォトリソグラフィ一により、フォトレジスト膜 106に、配線（ボンディングパッ ド） 88bに達する開口部をシリコン窒化膜 92、シリコン酸化膜 90、バリア膜 114、及び シリコン酸化膜 112に形成する領域を露出する開口部 108を形成する。  Next, an opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 in the photoresist film 106 by photolithography. An opening 108 exposing the region is formed.
[0204] 次いで、フォトレジスト膜 106をマスクとして、シリコン窒化膜 92、シリコン酸化膜 90 、バリア膜 114、及びシリコン酸化膜 112をエッチングする。こうして、シリコン窒化膜 9 2、シリコン酸化膜 90、バリア膜 114、及びシリコン酸化膜 112に、配線（ボンディング パッド） 88bに達する開口部 96aが形成される（図 20 (b)を参照）。この後、フォトレジ スト膜 106を剥離する。  Next, using the photoresist film 106 as a mask, the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 are etched. Thus, an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 (see FIG. 20B). Thereafter, the photoresist film 106 is peeled off.
[0205] 次いで、例えばスピンコート法により、例えば膜厚 3— 6 μ mのポリイミド樹脂膜 94を 形成する（図 21 (a)を参照)。  Next, a polyimide resin film 94 having a film thickness of 3 to 6 μm, for example, is formed by, eg, spin coating (see FIG. 21 (a)).
[0206] 次いで、フォトリソグラフィ一により、ポリイミド榭脂膜 94に、開口部 96aを介して配線 [0206] Next, wiring is made through the opening 96a to the polyimide resin film 94 by photolithography.
(ボンディングパッド） 88bに達する開口部 96bを形成する（図 21 (b)を参照）。  (Bonding pad) Opening 96b reaching 88b is formed (see Fig. 21 (b)).
[0207] こうして、本実施形態による半導体装置が製造される。 Thus, the semiconductor device according to the present embodiment is manufactured.
[0208] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 バリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42の上方に形成された第 1金属 配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属配 線層 72と第 3金属配線層 88との間に形成された平坦なバリア膜 78と、第 3金属配線 層 88の上方に形成された平坦なバリア膜 114とを有するので、水素及び水分を更に 確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強誘電体膜 38に達する のを更に確実に防止することができる。これにより、水素及び水分による強誘電体キ ャパシタ 42の電気的特性の劣化を更に確実に防止することができ、強誘電体キャパ シタを有する半導体装置の PTHS特性を更に大幅に向上することができる。 As described above, according to the present embodiment, as the barrier film for preventing the diffusion of hydrogen and moisture, in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided. A flat barrier film 62 formed between the metal wiring layer 56 and the second metal wiring layer 72, and a flat barrier film formed between the second metal wiring layer 72 and the third metal wiring layer 88. 78 and the flat barrier film 114 formed above the third metal wiring layer 88, the hydrogen and moisture are more reliably barriered, and the hydrogen and moisture are the ferroelectric film 38 of the ferroelectric capacitor 42. This can be prevented more reliably. As a result, the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the ferroelectric capacitor 42 can be prevented. The PTHS characteristics of a semiconductor device having a shita can be further greatly improved.
[0209] [第 3実施形態]  [0209] [Third Embodiment]
本発明の第 3実施形態による半導体装置及びその製造方法について図 22乃至図 24を用いて説明する。図 22は本実施形態による半導体装置の構造を示す断面図、 図 23及び図 24は本実施形態による半導体装置の製造方法を示す工程断面図であ る。なお、第 1実施形態による半導体装置及びその製造方法と同様の構成要素につ いては同一の符号を付し説明を省略し或いは簡略にする。  A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 23 and 24 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0210] (半導体装置）  [0210] (Semiconductor device)
本実施形態による半導体装置の基本的構成は、第 1実施形態による半導体装置と ほぼ同様である。本実施形態による半導体装置は、強誘電体キャパシタ 42と、第 1金 属配線層 56 (配線 56a、 56b、 56c)との間に、平坦なバリア膜 116を更に有する点 で、第 1実施形態による半導体装置と異なっている。  The basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. The semiconductor device according to the present embodiment is different from the first embodiment in that it further includes a flat barrier film 116 between the ferroelectric capacitor 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). This is different from the semiconductor device.
[0211] すなわち、図 22に示すように、導体プラグ 50a、 50bが坦め込まれた層間絶縁膜 4 8上に、ノくリア膜 116が形成されている。バリア膜 116としては、例えば膜厚 20— 70η mの酸化アルミニウム膜が用いられている。ここで、層間絶縁膜 48は平坦化されてお り、平坦ィ匕された層間絶縁膜 48上にバリア膜 116が形成されているため、バリア膜 1 16は平坦となっている。  That is, as shown in FIG. 22, the rear film 116 is formed on the interlayer insulating film 48 on which the conductor plugs 50a and 50b are carried. As the barrier film 116, for example, an aluminum oxide film having a thickness of 20 to 70 ηm is used. Here, since the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 is flat.
[0212] バリア膜 116は、バリア膜 44、 46、 58、 62、 78と同様に、水素及び水分の拡散を 防止する機能を有する膜である。さらに、バリア膜 116は、平坦化されたシリコン酸化 膜 48上に形成されているため平坦となっており、バリア膜 62、 78と同様に、バリア膜 44、 46、 58と比較して、極めて良好な被覆性で形成されている。したがって、このよ うな平坦なバリア膜 116により、更に確実に水素及び水分の拡散を防止することがで きる。なお、実際には、バリア膜 116は、バリア膜 62、 78と同様に、強誘電体キャパシ タ 42を有する複数のメモリセルが配列された FeRAMチップのメモリセル領域のみな らず、周辺回路領域等を含む FeRAMチップの全面にわたって形成されている。  [0212] Similar to the barrier films 44, 46, 58, 62, and 78, the barrier film 116 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 116 is formed on the flattened silicon oxide film 48, it is flat, and, like the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, It is formed with good coverage. Therefore, such a flat barrier film 116 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 116 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, as in the barrier films 62 and 78, but also the peripheral circuit area. Etc. are formed over the entire surface of the FeRAM chip.
[0213] バリア膜 116上には、例えば膜厚 lOOnmのシリコン酸化膜 118が形成されている。  [0213] On the barrier film 116, for example, a silicon oxide film 118 having a thickness of lOOnm is formed.
[0214] シリコン酸化膜 118、バリア膜 116、層間絶縁膜 48、バリア膜 46、及びバリア膜 44 には、上部電極 40に達するコンタクトホール 52aが形成されている。また、シリコン酸 化膜 118、バリア膜 116、層間絶縁膜 48、バリア膜 46、及びノくリア膜 44には、下部 電極 36に達するコンタクトホール 52bが形成されている。 [0214] A contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the barrier film 44. Also silicon acid A contact hole 52b reaching the lower electrode 36 is formed in the oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44.
[0215] さらに、シリコン酸化膜 118及びバリア膜 116には、導体プラグ 54aに達するコンタ タトホール 120aが形成されている。また、シリコン酸化膜 1 18及びバリア膜 116には、 導体プラグ 54bに達するコンタクトホール 120bが形成されている。  [0215] Furthermore, a contact hole 120a reaching the conductor plug 54a is formed in the silicon oxide film 118 and the barrier film 116. Further, a contact hole 120b reaching the conductor plug 54b is formed in the silicon oxide film 118 and the barrier film 116.
[0216] シリコン酸化膜 118上、コンタクトホール 52a内、及びコンタクトホール 120a内には 、導体プラグ 54aと上部電極 40とに電気的に接続された配線 56aが形成されている 。また、シリコン酸化膜 118上及びコンタクトホール 52b内には、下部電極 36に電気 的に接続された配線 56bが形成されている。また、シリコン酸化膜 118上及びコンタ タトホール 120b内には、導体プラグ 54bに電気的に接続された配線 56cが形成され ている。  [0216] On the silicon oxide film 118, in the contact hole 52a, and in the contact hole 120a, a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed. A wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 118 and in the contact hole 52b. In addition, a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 118 and in the contact hole 120b.
[0217] このように、本実施形態による半導体装置は、水素及び水分の拡散を防止するバリ ァ膜として、バリア膜 44、 46、 58に加えて、強誘電体キャパシタ 42と強誘電体キャパ シタ 42の上方に形成された第 1金属配線層 56 (配線 56a、 56b、 56c)との間に形成 された平坦なバリア膜 116と、第 1金属配線層 56 (配線 56a、 56b、 56c)と第 2金属 配線層 72 (配線 72a、 72b)との間に形成された平坦なバリア膜 62と、第 2金属配線 層 72 (配線 72a、 72b)と第 3金属配線層 88 (配線 88a、 88b)の間に形成された平坦 なバリア膜 78とを有することに主たる特徴がある。  As described above, in the semiconductor device according to the present embodiment, the ferroelectric film 42 and the ferroelectric capacitor are used as the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, and 58. The flat barrier film 116 formed between the first metal wiring layer 56 (wirings 56a, 56b, 56c) formed above the 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c) The flat barrier film 62 formed between the second metal wiring layer 72 (wiring 72a, 72b), the second metal wiring layer 72 (wiring 72a, 72b) and the third metal wiring layer 88 (wiring 88a, 88b) And a flat barrier film 78 formed between them.
[0218] 本実施形態による半導体装置では、第 1実施形態による半導体装置における平坦 なバリア膜 62、 78に加えて、強誘電体キャパシタ 42と強誘電体キャパシタ 42の上方 に形成された第 1金属配線層 56との間に平坦なバリア膜 116が形成されているので 、水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強 誘電体膜 38に達するのを更に確実に防止することができる。これにより、水素及び水 分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に防止することがで き、強誘電体キャパシタを有する半導体装置の PTHS特性を更に大幅に向上するこ とができる。  In the semiconductor device according to the present embodiment, the ferroelectric capacitor 42 and the first metal formed above the ferroelectric capacitor 42 in addition to the flat barrier films 62 and 78 in the semiconductor device according to the first embodiment. Since the flat barrier film 116 is formed between the wiring layer 56 and the barrier layer 116, hydrogen and moisture are more securely blocked, and the hydrogen and moisture reach the ferroelectric film 38 of the ferroelectric capacitor 42 more reliably. Can be prevented. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
[0219] (半導体装置の製造方法）  [0219] (Method for Manufacturing Semiconductor Device)
次に、本実施形態による半導体装置の製造方法について図 23及び図 24を用いて 説明する。 Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. explain.
まず、図 4乃至図 7、図 8 (a)、及び図 8 (b)に示す第 1実施形態による半導体装置の 製造方法と同様にして、導体プラグ 54a、 54bまでを形成する（図 23 (a)を参照）。  First, the conductor plugs 54a and 54b are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 4 to 7, FIG. 8A, and FIG. see a)).
[0220] 次いで、例えばアルゴンガスを用いたプラズマ洗浄を行う。これにより、導体プラグ 5 4a、 54b表面に存在する自然酸化膜等が除去される。  [0220] Next, plasma cleaning using, for example, argon gas is performed. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 54a and 54b are removed.
[0221] 次いで、導体プラグ 54a、 54bが埋め込まれた層間絶縁膜 48上に、例えばスパッタ 法又は CVD法により、ノ リア膜 116を形成する。ノ リア膜 114としては、例えば膜厚 2 0— 70nmの酸化アルミニウム膜を形成する。層間絶縁膜 48は平坦ィ匕されており、平 坦化された層間絶縁膜 48上にバリア膜 116を形成するため、バリア膜 116は平坦と なる。  [0221] Next, on the interlayer insulating film 48 in which the conductor plugs 54a and 54b are embedded, a NOR film 116 is formed by, for example, sputtering or CVD. As the noria film 114, for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 becomes flat.
[0222] 次いで、全面に、例えばプラズマ TEOSCVD法により、例えば膜厚 lOOnmのシリ コン酸化膜 118を形成する（図 23 (b)を参照）。  [0222] Next, a silicon oxide film 118 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 23B).
[0223] 次いで、フォトリソグラフィー及びドライエッチングにより、シリコン酸化膜 118及びバ リア膜 116に、導体プラグ 54a、 54bに達するコンタクトホール 120a、 120bを形成す る（図 23 (c)を参照)。 Next, contact holes 120a and 120b reaching the conductor plugs 54a and 54b are formed in the silicon oxide film 118 and the barrier film 116 by photolithography and dry etching (see FIG. 23C).
[0224] 次いで、全面に、例えば CVD法により、例えば膜厚 lOOnmの SiON膜 122を形成 する（図 24 (a)を参照)。  Next, an SiON film 122 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD (see FIG. 24A).
[0225] 次いで、フォトリソグラフィー及びドライエッチングにより、 SiONfl莫 122、シリコン酸 化膜 118、バリア膜 116、層間絶縁膜 48、バリア膜 46、及びノくリア膜 44に、強誘電 体キャパシタ 42の上部電極 40に達するコンタクトホール 52aと、強誘電体キャパシタ 42の下部電極 36に達するコンタクトホール 52aとを形成する（図 24 (b)を参照）。  [0225] Next, the upper portion of the ferroelectric capacitor 42 is formed on the SiONfl layer 122, the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44 by photolithography and dry etching. A contact hole 52a reaching the electrode 40 and a contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 are formed (see FIG. 24B).
[0226] 次いで、酸素雰囲気にて、例えば 500°C、 60分間の熱処理を行う。この熱処理は、 強誘電体キャパシタ 42の強誘電体膜 38に酸素を供給し、強誘電体キャパシタ 42の 電気的特性を回復するためのものである。  [0226] Next, heat treatment is performed in an oxygen atmosphere, for example, at 500 ° C for 60 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
[0227] 次いで、エッチングにより SiON膜 122を除去する。  Next, the SiON film 122 is removed by etching.
[0228] 次いで、全面に、例えば膜厚 150nmの TiN膜と、例えば膜厚 550nmの AlCu合金 膜と、例えば膜厚 5nmの Ti膜と、例えば膜厚 150nmの TiN膜とを順次積層する。こ うして、 TiN膜と AlCu合金膜と Ti膜と TiN膜とを順次積層してなる導体膜が形成され る。 [0228] Next, a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm, for example, are sequentially laminated on the entire surface. Thus, a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film. The
[0229] 次いで、フォトリソグラフィー及びドライエッチングにより、導体膜をパターニングする 。これにより、第 1金属配線層 56、すなわち強誘電体キャパシタ 42の上部電極 40と 導体プラグ 54aとに電気的に接続された配線 56a、強誘電体キャパシタ 42の下部電 極 36に電気的に接続された配線 56b、及び導体プラグ 54bに電気的に接続された 配線 56cが形成される（図 24 (c)を参照）。  [0229] Next, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 56, that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected. The wiring 56b thus formed and the wiring 56c electrically connected to the conductor plug 54b are formed (see FIG. 24C).
[0230] この後の工程は、図 9 (b)乃至図 17に示す第 1実施形態による半導体装置の製造 方法と同様であるので説明を省略する。  [0230] The subsequent steps are the same as those of the semiconductor device manufacturing method according to the first embodiment shown in FIGS.
[0231] このように、本実施形態によれば、水素及び水分の拡散を防止するバリア膜として、 バリア膜 44、 46、 58にカロえて、強誘電体キャパシタ 42と強誘電体キャパシタ 42の上 方に形成された第 1金属配線層 56との間に形成された平坦なバリア膜 116と、第 1金 属配線層 56と第 2金属配線層 72との間に形成された平坦なバリア膜 62と、第 2金属 配線層 72と第 3金属配線層 88の間に形成された平坦なノ リア膜 78とを有するので、 水素及び水分を更に確実にバリアし、水素及び水分が強誘電体キャパシタ 42の強 誘電体膜 38に達するのを更に確実に防止することができる。これにより、水素及び水 分による強誘電体キャパシタ 42の電気的特性の劣化を更に確実に防止することがで き、強誘電体キャパシタを有する半導体装置の PTHS特性を更に大幅に向上するこ とができる。  As described above, according to the present embodiment, the barrier films 44, 46, and 58 are used as barrier films for preventing the diffusion of hydrogen and moisture, and the ferroelectric capacitors 42 and the ferroelectric capacitors 42 are formed. A flat barrier film 116 formed between the first metal wiring layer 56 and the first metal wiring layer 56 formed on the opposite side, and a flat barrier film formed between the first metal wiring layer 56 and the second metal wiring layer 72. 62, and a flat noor film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88, so that hydrogen and moisture are further securely blocked, and the hydrogen and moisture are ferroelectric. The capacitor 42 can be further reliably prevented from reaching the ferroelectric film 38. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
[0232] [変形実施形態]  [0232] [Modified Embodiment]
本発明は上記実施形態に限らず種々の変形が可能である。  The present invention is not limited to the above embodiment, and various modifications can be made.
[0233] 例えば、上記実施形態では、強誘電体膜 38として PZT膜を用いる場合を例に説明 したが、強誘電体膜 38は PZT膜に限定されるものではなぐ他のあらゆる強誘電体 膜を適宜用いることができる。例えば、強誘電体膜 38として、 Pb La Zr Ti O  For example, in the above embodiment, the case where a PZT film is used as the ferroelectric film 38 has been described as an example. However, the ferroelectric film 38 is not limited to the PZT film, but is any other ferroelectric film. Can be used as appropriate. For example, as the ferroelectric film 38, Pb La Zr Ti O
1-X X 1-Y Y 3 膜 (PLZT膜)、 SrBi (Ta Nb ) O膜、 Bi Ti O 膜等を用レヽてもよい。  A 1-X X 1-Y Y 3 film (PLZT film), an SrBi (Ta Nb) O film, a BiTi O film, or the like may be used.
2 X 1-X 2 9 4 2 12  2 X 1-X 2 9 4 2 12
[0234] また、上記実施形態では、酸化アルミニウム膜 36aと Pt膜 36bとの積層膜により下 部電極 36を構成したが、下部電極 36を構成する導体膜等の材料は力、かる材料に限 定されるものではなレ、。例えば、 Ir膜、 Ir〇膜、 Ru膜、 Ru〇膜、 SrRuO (ストロンチ  [0234] In the above embodiment, the lower electrode 36 is composed of the laminated film of the aluminum oxide film 36a and the Pt film 36b. However, the material of the conductor film or the like that constitutes the lower electrode 36 is limited to the force and the material. It ’s not something that ’s fixed. For example, Ir film, IrO film, Ru film, RuO film, SrRuO (Stront
2 2  twenty two
ゥムルテニウムオキサイド)膜（SR〇膜）、 Pd膜により下部電極 38を構成してもよい。 [0235] また、上記実施形態では、 IrO膜 40aと Ir〇膜 40bとの積層膜により上部電極 40 The lower electrode 38 may be composed of a (muruthenium oxide) film (SR film) or a Pd film. [0235] In the above embodiment, the upper electrode 40 is formed of a laminated film of the IrO film 40a and the IrO film 40b.
X Y  X Y
を構成したが、上部電極 40を構成する導体膜の材料は力かる材料に限定されるもの ではない。例えば、 Ir膜、 Ru膜、 Ru〇膜、 SRO膜、 Pd膜により上部電極 40を構成  However, the material of the conductor film constituting the upper electrode 40 is not limited to a strong material. For example, upper electrode 40 is composed of Ir film, Ru film, RuO film, SRO film, Pd film
2  2
してもよい。  May be.
[0236] また、上記実施形態では、平坦なバリア膜について、第 1実施形態においては第 1 金属配線層 56と第 2金属配線層 72との間にバリア膜 62を形成し、第 2金属配線層 7 2と第 3金属配線層 88との間にバリア膜 78を形成する場合について説明し、第 2実 施形態においてはバリア膜 62、 78に加えて第 3金属配線層 88の上方にバリア膜 11 4を形成する場合について説明し、第 3実施形態においてはバリア膜 62、 78に加え て強誘電体キャパシタ 42と第 1金属配線層 56との間にバリア膜 116を形成する場合 について説明したが、形成するバリア膜 62、 78、 114、 116の組合せは、上記実施 形態において説明した場合に限定されるものではない。平坦なバリア膜は、バリア膜 62、 78、 114、 116のうちの少、なくとも 2層力 S形成されてレヽればよく、 / リア月莫 62、 78 、 114、 116のうちの 3層を形成してもよレヽし、或レ、 ίま/ リア月莫 62、 78、 114、 116の 4 層すベてを形成してもよい。また、半導体基板 10上に形成する金属配線層の層数等 に応じて、更に多くの平坦なバリア膜を形成してもよい。  [0236] In the above-described embodiment, for the flat barrier film, in the first embodiment, the barrier film 62 is formed between the first metal wiring layer 56 and the second metal wiring layer 72, and the second metal wiring is formed. The case where the barrier film 78 is formed between the layer 72 and the third metal wiring layer 88 will be described. In the second embodiment, the barrier film 62, 78 and the barrier above the third metal wiring layer 88 are described. The case where the film 114 is formed will be described. In the third embodiment, the case where the barrier film 116 is formed between the ferroelectric capacitor 42 and the first metal wiring layer 56 in addition to the barrier films 62 and 78 will be described. However, the combination of the barrier films 62, 78, 114, and 116 to be formed is not limited to the case described in the above embodiment. The flat barrier film may be formed by forming at least two layers of the barrier films 62, 78, 114, and 116, and / or three layers of the rear layers 62, 78, 114, and 116. Alternatively, all four layers of 62, 78, 114, and 116 may be formed. Further, more flat barrier films may be formed according to the number of metal wiring layers formed on the semiconductor substrate 10.
[0237] また、上記実施形態では、ノくリア膜として酸化アルミニウム膜を用いる場合を例に説 明したが、ノくリア膜は酸化アルミニウム膜に限定されるものではなレ、。水素又は水分 の拡散を防止する機能を有する膜を、バリア膜として適宜用いることができる。ノくリア 膜としては、例えば金属酸化物よりなる膜を適宜用いることができる。金属酸化物より なるバリア膜としては、例えば、タンタル酸化物やチタン酸化物等を用いることができ る。また、バリア膜は、金属酸化物よりなる膜に限定されるものではなレ、。例えば、シリ コン窒化膜 (Si N膜)やシリコン窒化酸化膜 (SiON膜)等をバリア膜として用いること  [0237] In the above embodiment, the case where an aluminum oxide film is used as the noble film has been described as an example. However, the noria film is not limited to the aluminum oxide film. A film having a function of preventing diffusion of hydrogen or moisture can be appropriately used as the barrier film. As the silicon film, for example, a film made of a metal oxide can be used as appropriate. As the barrier film made of a metal oxide, for example, tantalum oxide or titanium oxide can be used. Further, the barrier film is not limited to a film made of a metal oxide. For example, silicon nitride film (SiN film) or silicon nitride oxide film (SiON film) should be used as the barrier film.
3 4  3 4
もできる。また、塗布型酸化膜、或レ、はポリイミド、ポリアリーレン、ポリアリーレンエー テル、ベンゾシクロブテン等よりなる樹脂膜のような吸湿性を有する有機膜をバリア膜 として用いることができる。  You can also. Further, a coating type oxide film or an organic film having a hygroscopic property such as a resin film made of polyimide, polyarylene, polyarylene ether, benzocyclobutene, or the like can be used as the barrier film.
[0238] また、上記実施形態では、形成するバリア膜のすべてに同一材料よりなるバリア膜 を用いる場合について説明したが、以下に述べるように、異なる材料よりなるバリア膜 を適宜用いることもできる。 [0238] In the above embodiment, the case where the barrier film made of the same material is used for all the barrier films to be formed has been described. However, as described below, the barrier film made of different materials Can also be used as appropriate.
[0239] 例えば、第 1又は第 2実施形態による半導体装置において、平坦なバリア膜 62、 78 、 114のうちで最も強誘電体キャパシタ 42側に形成されているバリア膜 62として酸化 アルミニウム膜を用いるとともに、ノ リア膜 62の上方に形成されているバリア膜 78又 はバリア膜 114としてシリコン窒化膜を用いてもょレ、。  [0239] For example, in the semiconductor device according to the first or second embodiment, an aluminum oxide film is used as the barrier film 62 formed closest to the ferroelectric capacitor 42 among the flat barrier films 62, 78, 114. At the same time, a silicon nitride film may be used as the barrier film 78 or the barrier film 114 formed above the noria film 62.
[0240] また、第 2実施形態による半導体装置において、第 3金属配線層 88の下方に形成 されている平坦なバリア膜 62、 78として酸化アルミニウム膜等の金属酸化物よりなる 膜やシリコン窒化膜等の無機膜を用レ、るとともに、第 3金属配線層 88の上方に形成 され、配線（ボンディングパッド） 88bに達する開口部 96bが形成される平坦なバリア 膜 114として、吸湿性を有する有機膜を形成してもよレ、。  [0240] In the semiconductor device according to the second embodiment, as the flat barrier films 62 and 78 formed below the third metal wiring layer 88, a film made of a metal oxide such as an aluminum oxide film or a silicon nitride film As a flat barrier film 114 formed above the third metal wiring layer 88 and having an opening 96b reaching the wiring (bonding pad) 88b, an organic material having a hygroscopic property is used. You can also form a film.
[0241] また、上記実施形態では、層間絶縁膜を構成する絶縁膜として、シリコン酸化膜を 形成する場合を例に説明したが、シリコン酸化膜に代えて、種々の絶縁膜を形成す ること力 Sできる。  [0241] In the above embodiment, the case where a silicon oxide film is formed as an insulating film constituting the interlayer insulating film has been described as an example. However, various insulating films may be formed instead of the silicon oxide film. Power S can be.
[0242] また、上記実施形態では、層間絶縁膜を構成する絶縁膜の表面を平坦化する方法 として CMP法を用いる場合を例に説明したが、絶縁膜の表面を平坦化する方法は、 CMP法に限定されるものではない。例えば、エッチングにより、絶縁膜の表面を平坦 ィ匕してもよレ、。エッチングガスとしては、例えば Arガスを用いることができる。  [0242] In the above embodiment, the case where the CMP method is used as a method for planarizing the surface of the insulating film constituting the interlayer insulating film has been described as an example. It is not limited to the law. For example, the surface of the insulating film may be flattened by etching. As an etching gas, for example, Ar gas can be used.
[0243] また、上記実施形態では、第 1金属配線層 56、第 2金属配線層 72、及び第 3金属 配線層 88の 3層の金属配線層により半導体基板 10上に回路が構成される場合を例 に説明したが、半導体基板 10上の回路を構成する金属配線層の層数は 3層に限定 されるものではない。金属配線層の層数は、半導体基板 10上に構成する回路の設 計に応じて適宜設定することができる。  [0243] In the above embodiment, the circuit is formed on the semiconductor substrate 10 by the three metal wiring layers of the first metal wiring layer 56, the second metal wiring layer 72, and the third metal wiring layer 88. However, the number of metal wiring layers constituting the circuit on the semiconductor substrate 10 is not limited to three. The number of metal wiring layers can be appropriately set according to the design of the circuit configured on the semiconductor substrate 10.
[0244] また、上記実施形態では、 1つのトランジスタ 24及び 1つの強誘電体キャパシタ 42 を有する 1T1 C型のメモリセルが形成されてレ、る場合を例に説明したが、メモリセル の構成は 1T1C型に限定されるものではなレ、。メモリセルの構成としては、 1T1C型 のほか、例えば 2つのトランジスタ及び 2つの強誘電体キャパシタを有する 2T2C型 等の種々の構成を用いることができる。  [0244] In the above embodiment, a case where a 1T1 C type memory cell having one transistor 24 and one ferroelectric capacitor 42 is formed has been described as an example, but the configuration of the memory cell is It is not limited to 1T1C type. As the configuration of the memory cell, in addition to the 1T1C type, various configurations such as a 2T2C type having two transistors and two ferroelectric capacitors can be used.
[0245] また、上記実施形態では、プレーナー型セルを有する FeRAM構造の半導体装置 について説明したが、本発明の適用範囲はこれに限定されるものではなレ、。例えば、 本発明は、スタック型セルを有し、ゲート長が例えば 0. 18 μ mに設定された FeRA M構造の半導体装置についても適用することができる。 [0245] In the above-described embodiment, a FeRAM structure semiconductor device having a planar type cell. However, the scope of the present invention is not limited to this. For example, the present invention can also be applied to a FeRA M structure semiconductor device having a stack type cell and having a gate length set to, for example, 0.18 μm.
[0246] 図 25は、本発明を適用したスタック型セルを有する FeRAM構造の半導体装置の 構造を示す断面図である。  FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having a stack type cell to which the present invention is applied.
[0247] 図示するように、例えばシリコンよりなる半導体基板 210上には、素子領域を画定す る素子分離領域 212が形成されている。素子分離領域 212が形成された半導体基 板 210内には、ウエノレ 214a、 214bが形成されている。  As shown in the drawing, an element isolation region 212 that defines an element region is formed on a semiconductor substrate 210 made of, for example, silicon. Uenoles 214a and 214b are formed in the semiconductor substrate 210 in which the element isolation region 212 is formed.
[0248] ウエノレ 214a、 214bが形成された半導体基板 210上には、ゲート絶縁膜 216を介し てゲート電極（ゲート配線） 218が形成されている。ゲート電極 218は、例えば、ポリシ リコン膜上に、トランジスタのゲート長等に応じてコバルトシリサイド膜、ニッケルシリサ イド膜、タングステンシリサイド膜等の金属シリサイド膜が積層されたポリサイド構造を 有している。ゲート電極 218上には、シリコン酸化膜 219が形成されている。ゲート電 極 218及びシリコン酸化膜 219の側壁部分には、サイドウォール絶縁膜 220が形成 されている。  A gate electrode (gate wiring) 218 is formed on the semiconductor substrate 210 on which the wells 214a and 214b are formed via a gate insulating film 216. The gate electrode 218 has, for example, a polycide structure in which a metal silicide film such as a cobalt silicide film, a nickel silicide film, or a tungsten silicide film is stacked on a polysilicon film in accordance with the gate length of the transistor. A silicon oxide film 219 is formed on the gate electrode 218. Sidewall insulating films 220 are formed on the side walls of the gate electrode 218 and the silicon oxide film 219.
[0249] サイドウォール絶縁膜 220が形成されたゲート電極 218の両側には、ソース/ドレイ ン拡散層 222が形成されている。こうして、ゲート電極 218とソース/ドレイン拡散層 2 22とを有するトランジスタ 224が構成されている。トランジスタ 224のゲート長は、例え ば 0. 18 /i mに設定されている。  [0249] A source / drain diffusion layer 222 is formed on both sides of the gate electrode 218 on which the sidewall insulating film 220 is formed. Thus, the transistor 224 having the gate electrode 218 and the source / drain diffusion layer 222 is formed. The gate length of the transistor 224 is set to, for example, 0.18 / im.
[0250] トランジスタ 224が形成された半導体基板 210上には、 SiON膜 225と、シリコン酸 化膜 226とを順次積層してなる層間絶縁膜 227が形成されている。層間絶縁膜 227 の表面は平坦化されてレ、る。  On the semiconductor substrate 210 on which the transistor 224 is formed, an interlayer insulating film 227 formed by sequentially laminating a SiON film 225 and a silicon oxide film 226 is formed. The surface of the interlayer insulating film 227 is planarized.
[0251] 層間絶縁膜 227上には、例えば酸化アルミニウム膜よりなるバリア膜 228が形成さ れている。  [0251] On the interlayer insulating film 227, a barrier film 228 made of, for example, an aluminum oxide film is formed.
[0252] バリア膜 228及び層間絶縁膜 227には、ソース/ドレイン拡散層 222に達するコン タクトホーノレ 230a、 230b力 S形成されてレヽる。  Contact barriers 230a and 230b force S reaching the source / drain diffusion layer 222 are formed in the barrier film 228 and the interlayer insulating film 227, and are reduced.
[0253] コンタクトホール 230a、 230bには、 Ti膜と TiN膜とを順次積層してなるバリアメタノレ 膜 (図示せず)が形成されてレ、る。 [0254] バリアメタル膜が形成されたコンタクトホール 230a、 230b内には、タングステンより なる導体プラグ 232a、 232bが埋め込まれてレ、る。 [0253] Barrier methanol films (not shown) formed by sequentially laminating Ti films and TiN films are formed in the contact holes 230a and 230b. [0254] Conductor plugs 232a and 232b made of tungsten are buried in the contact holes 230a and 230b in which the barrier metal film is formed.
[0255] バリア膜 228上には、導体プラグ 232aに電気的に接続された Ir膜 234が形成され ている。 [0255] On the barrier film 228, an Ir film 234 electrically connected to the conductor plug 232a is formed.
[0256] Ir膜 234上には、強誘電体キャパシタ 242の下部電極 236が形成されている。  [0256] On the Ir film 234, the lower electrode 236 of the ferroelectric capacitor 242 is formed.
[0257] 下部電極 236上には、強誘電体キャパシタ 242の強誘電体膜 238が形成されてい る。強誘電体膜 238としては、例えば PZT膜が用いられている。 A ferroelectric film 238 of the ferroelectric capacitor 242 is formed on the lower electrode 236. As the ferroelectric film 238, for example, a PZT film is used.
[0258] 強誘電体膜 238上には、強誘電体キャパシタ 242の上部電極 240が形成されてい る。 On the ferroelectric film 238, the upper electrode 240 of the ferroelectric capacitor 242 is formed.
[0259] 積層されている上部電極 240、強誘電体膜 238、下部電極 236、及び Ir膜 234は、 エッチングにより一括してパターユングされ、互いにほぼ同じ平面形状を有している。  The upper electrode 240, the ferroelectric film 238, the lower electrode 236, and the Ir film 234 that are laminated are patterned together by etching and have substantially the same planar shape.
[0260] こうして、下部電極 236と強誘電体膜 238と上部電極 240とからなる強誘電体キヤ パシタ 242が構成されている。強誘電体キャパシタ 242の下部電極 236は、 Ir膜 234 を介して導体プラグ 232aに電気的に接続されている。 Thus, a ferroelectric capacitor 242 composed of the lower electrode 236, the ferroelectric film 238, and the upper electrode 240 is formed. The lower electrode 236 of the ferroelectric capacitor 242 is electrically connected to the conductor plug 232a via the Ir film 234.
[0261] 層間絶縁膜 227の Ir膜 234が形成されていない領域上には、 Ir膜 234と同程度の 膜厚或いは Ir膜 234よりも薄い膜厚の SiON膜 244が形成されている。なお、 SiON 膜 244に代えて、シリコン酸化膜を形成してもよい。 [0261] On the region of the interlayer insulating film 227 where the Ir film 234 is not formed, a SiON film 244 having a film thickness comparable to or thinner than the Ir film 234 is formed. Instead of the SiON film 244, a silicon oxide film may be formed.
[0262] 強誘電体キャパシタ 242上及び SiON膜 244上には、水素及び水分の拡散を防止 する機能を有するバリア膜 246が形成されている。ノくリア膜 246としては、例えば酸 化アルミニウム膜が用レ、られてレ、る。 [0262] On the ferroelectric capacitor 242 and the SiON film 244, a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed. As the rear film 246, for example, an aluminum oxide film is used.
[0263] バリア膜 246上にはシリコン酸化膜 248が形成され、シリコン酸化膜 248により強誘 電体キャパシタ 242が埋め込まれてレ、る。シリコン酸化膜 248の表面は平坦化されて いる。  [0263] A silicon oxide film 248 is formed on the barrier film 246, and the strong dielectric capacitor 242 is embedded by the silicon oxide film 248. The surface of the silicon oxide film 248 is planarized.
[0264] 平坦化されたシリコン酸化膜 248上には、水素及び水分の拡散を防止する機能を 有する平坦なバリア膜 250が形成されている。ノ リア膜 250としては、例えば酸化ァ ノレミニゥム膜が用いられてレヽる。  [0264] On the planarized silicon oxide film 248, a flat barrier film 250 having a function of preventing the diffusion of hydrogen and moisture is formed. As the nore film 250, for example, an anolymium oxide film is used.
[0265] バリア膜 250上には、シリコン酸化膜 252が形成されている。  A silicon oxide film 252 is formed on the barrier film 250.
[0266] こうして、 Si〇N膜 244、 ノ リア膜 246、シリコン酸ィ匕膜 248、バリア膜 250、及びシリ コン酸化膜 252により層間絶縁膜 253が構成されている。 [0266] Thus, the SiON film 244, the noria film 246, the silicon oxide film 248, the barrier film 250, and the silicon film An interlayer insulating film 253 is constituted by the con oxide film 252.
[0267] シリコン酸化膜 252、バリア膜 250、シリコン酸化膜 248及びバリア膜 246には、強 誘電体キャパシタ 242の上部電極 240に達するコンタクトホール 254aが形成されて いる。また、シリコン酸化膜 252、バリア膜 250、シリコン酸化膜 248、 ノ リア膜 246、 及び SiON膜 244には、導体プラグ 232bに達するコンタクトホール 254bが形成され ている。 A contact hole 254a reaching the upper electrode 240 of the ferroelectric capacitor 242 is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, and the barrier film 246. In addition, a contact hole 254b reaching the conductor plug 232b is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, the noria film 246, and the SiON film 244.
[0268] コンタクトホール 254a、 254b内には、 Ti膜と TiN膜とを順次積層してなるバリアメタ ル膜（図示せず）が形成されている。なお、バリアメタル膜として、 Ti膜を形成せずに [0268] In the contact holes 254a and 254b, a barrier metal film (not shown) formed by sequentially stacking a Ti film and a TiN film is formed. As a barrier metal film, without forming a Ti film
、 TiN膜よりなるバリアメタル膜を形成してもよい。 A barrier metal film made of a TiN film may be formed.
[0269] バリアメタル膜が形成されたコンタクトホール 254a、 254b内には、タングステンより なる導体プラグ 256a、 256bがそれぞれ坦め込まれている。 [0269] Conductive plugs 256a and 256b made of tungsten are respectively carried in the contact holes 254a and 254b in which the barrier metal film is formed.
[0270] シリコン酸化膜 252上には、導体プラグ 256aに電気的に接続された配線 258aと、 導体プラグ 256bに電気的に接続された配線 258bとが形成されている。 [0270] On the silicon oxide film 252, a wiring 258a electrically connected to the conductor plug 256a and a wiring 258b electrically connected to the conductor plug 256b are formed.
[0271] 配線 258a、 258bが形成されたシリコン酸化膜 252上にはシリコン酸化膜 260が形 成され、シリコン酸ィ匕膜 260により酉己線 258a、 258b力 ¾1め込まれている。シリコン酸 化膜 260の表面は平坦ィ匕されている。 [0271] A silicon oxide film 260 is formed on the silicon oxide film 252 on which the wirings 258a and 258b are formed, and the self-insulating lines 258a and 258b are applied by the silicon oxide film 260. The surface of the silicon oxide film 260 is flattened.
[0272] 平坦化されたシリコン酸化膜 260上には、水素及び水分の拡散を防止する機能を 有する平坦なバリア膜 262が形成されている。ノ リア膜 262としては、例えば酸化ァ ノレミニゥム膜が用いられてレ、る。 A flat barrier film 262 having a function of preventing the diffusion of hydrogen and moisture is formed on the flattened silicon oxide film 260. As the noria film 262, for example, an anolymium oxide film is used.
[0273] バリア膜 262上には、シリコン酸化膜 264が形成されている。  A silicon oxide film 264 is formed on the barrier film 262.
[0274] こうして、シリコン酸化膜 260、 ノくリア膜 262、及びシリコン酸化膜 264により層間絶 縁膜 265が構成されている。  In this way, the interlayer insulating film 265 is constituted by the silicon oxide film 260, the silicon rear film 262, and the silicon oxide film 264.
[0275] シリコン酸化膜 264、バリア膜 262、及びシリコン酸化膜 260には、配線 258bに達 するコンタクトホール 268が形成されてレ、る。 [0275] A contact hole 268 reaching the wiring 258b is formed in the silicon oxide film 264, the barrier film 262, and the silicon oxide film 260.
[0276] コンタクトホール 260内には、 Ti膜と TiN膜とを順次積層してなるバリアメタル膜（図 示せず）が形成されている。 In the contact hole 260, a barrier metal film (not shown) is formed by sequentially stacking a Ti film and a TiN film.
[0277] バリアメタル膜が形成されたコンタクトホール 268内には、タングステンよりなる導体 プラグ 270が坦め込まれている。 [0278] シリコン酸化膜 264上には、導体プラグ 268に電気的に接続された配線 272が形 成されている。 [0277] A conductor plug 270 made of tungsten is loaded in the contact hole 268 in which the barrier metal film is formed. On the silicon oxide film 264, a wiring 272 electrically connected to the conductor plug 268 is formed.
[0279] 配線 272が形成されたシリコン酸化膜 264上にはシリコン酸化膜 274が形成され、 シリコン酸化膜 274により配線 272が埋め込まれている。シリコン酸化膜 274の表面 は平坦ィ匕されている。  A silicon oxide film 274 is formed on the silicon oxide film 264 on which the wiring 272 is formed, and the wiring 272 is embedded by the silicon oxide film 274. The surface of the silicon oxide film 274 is flattened.
[0280] 平坦化されたシリコン酸化膜 274上には、水素及び水分の拡散を防止する機能を 有する平坦なバリア膜 276が形成されている。ノ リア膜 276としては、例えば酸化ァ ノレミニゥム膜が用いられてレヽる。  [0280] On the planarized silicon oxide film 274, a flat barrier film 276 having a function of preventing the diffusion of hydrogen and moisture is formed. As the noria film 276, for example, an anode oxide film is used.
[0281] バリア膜 276上には、シリコン酸化膜 278が形成されている。  A silicon oxide film 278 is formed on the barrier film 276.
[0282] なお、シリコン酸化膜 278から上部は図示しないが、回路設計に応じて、シリコン酸 化膜等により構成される層間絶縁膜に埋め込まれた配線が適宜形成されている。  [0282] Although the upper portion from the silicon oxide film 278 is not shown, wirings embedded in an interlayer insulating film composed of a silicon oxide film or the like are appropriately formed according to the circuit design.
[0283] 上述のように、スタック型セルを有する FeRAM構造の半導体装置においても、上 記実施形態と同様に、水素及び水分の拡散を防止する平坦なバリア膜 250、 262、 276を形成することにより、水素及び水分による強誘電体キャパシタ 242の電気的特 性の劣化を確実に防止することができ、 PTHS特性を大幅に向上することができる。 なお、この場合においても、水素及び水分の拡散を防止する平坦なバリア膜は、少 なくとも 2層形成されていればよぐノくリア膜 250、 262、 276の 3層すべてが形成され ていなくてもよい。また、必要に応じて、更に多くの平坦なノくリア膜を形成してもよい。 産業上の利用可能性  [0283] As described above, in the FeRAM structure semiconductor device having a stack type cell as well, the flat barrier films 250, 262, and 276 that prevent the diffusion of hydrogen and moisture are formed as in the above-described embodiment. As a result, it is possible to reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 242 due to hydrogen and moisture, and to greatly improve the PTHS characteristics. Even in this case, the flat barrier film for preventing the diffusion of hydrogen and moisture is sufficient if at least two layers are formed, and all three layers of the rear films 250, 262, and 276 are formed. It does not have to be. Further, if necessary, a larger number of flat rear films may be formed. Industrial applicability
[0284] 本発明による半導体装置及びその製造方法は、強誘電体キャパシタを有する半導 体装置の信頼性を向上するのに有用である。 The semiconductor device and the manufacturing method thereof according to the present invention are useful for improving the reliability of a semiconductor device having a ferroelectric capacitor.

Claims

請求の範囲 The scope of the claims
[1] 半導体基板上に形成され、下部電極と、前記下部電極上に形成された強誘電体 膜と、前記強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタと、 前記半導体基板上及び前記強誘電体キャパシタ上に形成され、表面が平坦化さ れた第 1の絶縁膜と、  [1] A ferroelectric capacitor formed on a semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film; A first insulating film formed on a semiconductor substrate and on the ferroelectric capacitor and having a planarized surface;
前記第 1の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 1のバ リア膜と、  A flat first barrier film formed on the first insulating film and preventing diffusion of hydrogen or moisture;
前記第 1のバリア膜上に形成され、表面が平坦化された第 2の絶縁膜と、 前記第 2の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 2のバ リア膜と  A second insulating film formed on the first barrier film and having a planarized surface; and a flat second barrier film formed on the second insulating film and preventing diffusion of hydrogen or moisture. With membrane
を有することを特徴とする半導体装置。  A semiconductor device comprising:
[2] 請求の範囲第 1項記載の半導体装置において、 [2] In the semiconductor device according to claim 1,
前記強誘電体キャパシタの前記下部電極又は前記上部電極に電気的に接続され た第 1の配線と、  A first wiring electrically connected to the lower electrode or the upper electrode of the ferroelectric capacitor;
前記第 1の配線上に形成された第 2の配線と、  A second wiring formed on the first wiring;
前記第 2の配線上に形成され、外部回路が電気的に接続される第 3の配線とを更 に有する  And a third wiring formed on the second wiring and electrically connected to an external circuit.
ことを特徴とする半導体装置。  A semiconductor device.
[3] 請求の範囲第 2項記載の半導体装置において、 [3] In the semiconductor device according to claim 2,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記第 1の配線と前記第 2の配線と の間に形成されている  The first insulating film and the first barrier film are formed between the first wiring and the second wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[4] 請求の範囲第 3項記載の半導体装置において、 [4] In the semiconductor device according to claim 3,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the second wiring and the third wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[5] 請求の範囲第 4項記載の半導体装置において、 [5] In the semiconductor device according to claim 4,
前記第 3の配線上に形成され、表面が平坦化された第 3の絶縁膜と、 前記第 3の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 3のバ リア膜とを更に有し、 A third insulating film formed on the third wiring and having a planarized surface; A flat third barrier film formed on the third insulating film and preventing diffusion of hydrogen or moisture;
前記第 3の絶縁膜及び前記第 3のバリア膜には、前記第 3の配線に達する開口部 が形成されている  An opening reaching the third wiring is formed in the third insulating film and the third barrier film.
ことを特徴とする半導体装置。  A semiconductor device.
請求の範囲第 3項記載の半導体装置において、  In the semiconductor device according to claim 3,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている  The second insulating film and the second barrier film are formed on the third wiring, and the second insulating film and the second barrier film have an opening reaching the third wiring. Part is formed
ことを特徴とする半導体装置。  A semiconductor device.
請求の範囲第 2項記載の半導体装置において、  In the semiconductor device according to claim 2,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されており、  The first insulating film and the first barrier film are formed between the second wiring and the third wiring;
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている  The second insulating film and the second barrier film are formed on the third wiring, and the second insulating film and the second barrier film have an opening reaching the third wiring. Part is formed
ことを特徴とする半導体装置。  A semiconductor device.
請求の範囲第 2項記載の半導体装置において、  In the semiconductor device according to claim 2,
前記第 1の絶縁膜及び前記第 1のバリア膜は、前記強誘電体キャパシタと前記第 1 の配線との間に形成されている  The first insulating film and the first barrier film are formed between the ferroelectric capacitor and the first wiring.
ことを特徴とする半導体装置。  A semiconductor device.
請求の範囲第 8項記載の半導体装置において、  In the semiconductor device according to claim 8,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 1の配線と前記第 2の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the first wiring and the second wiring.
ことを特徴とする半導体装置。  A semiconductor device.
請求の範囲第 9項記載の半導体装置において、 前記第 2の配線と前記第 3の配線との間に形成され、表面が平坦化された第 3の絶 縁膜と、 In the semiconductor device according to claim 9, A third insulating film formed between the second wiring and the third wiring and having a planarized surface;
前記第 3の配線下、前記第 3の絶縁膜上に形成され、水素又は水分の拡散を防止 する平坦な第 3のバリア膜とを更に有する  A flat third barrier film that is formed on the third insulating film under the third wiring and prevents diffusion of hydrogen or moisture.
ことを特徴とする半導体装置。  A semiconductor device.
[11] 請求の範囲第 10項記載の半導体装置において、 [11] In the semiconductor device according to claim 10,
前記第 3の配線上に形成され、表面が平坦化された第 4の絶縁膜と、  A fourth insulating film formed on the third wiring and having a planarized surface;
前記第 4の絶縁膜上に形成され、水素又は水分の拡散を防止する平坦な第 4のバ リア膜とを更に有し、  A flat fourth barrier film formed on the fourth insulating film and preventing diffusion of hydrogen or moisture;
前記第 4の絶縁膜及び前記第 4のバリア膜には、前記第 3の配線に達する開口部 が形成されている  An opening reaching the third wiring is formed in the fourth insulating film and the fourth barrier film.
ことを特徴とする半導体装置。  A semiconductor device.
[12] 請求の範囲第 8項記載の半導体装置において、 [12] In the semiconductor device according to claim 8,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 2の配線と前記第 3の配線と の間に形成されている  The second insulating film and the second barrier film are formed between the second wiring and the third wiring.
ことを特徴とする半導体装置。  A semiconductor device.
[13] 請求の範囲第 8項記載の半導体装置において、 [13] In the semiconductor device according to claim 8,
前記第 2の絶縁膜及び前記第 2のバリア膜は、前記第 3の配線上に形成されており 前記第 2の絶縁膜及び前記第 2のバリア膜には、前記第 3の配線に達する開口部 が形成されている  The second insulating film and the second barrier film are formed on the third wiring, and the second insulating film and the second barrier film have an opening reaching the third wiring. Part is formed
ことを特徴とする半導体装置。  A semiconductor device.
[14] 請求の範囲第 1項乃至第 13項のいずれか 1項に記載の半導体装置において、 前記第 1のバリア膜及び前記第 2のバリア膜の少なくともいずれかは、前記半導体 基板の全面にわたって形成されている [14] The semiconductor device according to any one of [1] to [13], wherein at least one of the first barrier film and the second barrier film extends over the entire surface of the semiconductor substrate. Formed
ことを特徴とする半導体装置。  A semiconductor device.
[15] 請求の範囲第 2項乃至第 14項のいずれか 1項に記載の半導体装置において、 前記第 1の配線を覆うように形成され、水素又は水分の拡散を防止する第 5のバリ ァ膜を更に有する [15] The semiconductor device according to any one of [2] to [14], which is formed so as to cover the first wiring and prevents diffusion of hydrogen or moisture. Further comprising a film
ことを特徴とする半導体装置。  A semiconductor device.
[16] 請求の範囲第 1項乃至第 15項のいずれか 1項に記載の半導体装置において、 前記強誘電体キャパシタを覆うように形成され、水素又は水分の拡散を防止する第 6のノ リア膜を更に有する  [16] The semiconductor device according to any one of [1] to [15], wherein the sixth device is formed to cover the ferroelectric capacitor and prevents diffusion of hydrogen or moisture. Further having a membrane
ことを特徴とする半導体装置。  A semiconductor device.
[17] 請求の範囲第 1項乃至第 16項のいずれか 1項に記載の半導体装置において、 前記第 1のバリア膜又は前記第 2のバリア膜は、金属酸化物よりなる [17] The semiconductor device according to any one of [1] to [16], wherein the first barrier film or the second barrier film is made of a metal oxide.
ことを特徴とする半導体装置。  A semiconductor device.
[18] 請求の範囲第 17項記載の半導体装置において、 [18] In the semiconductor device according to claim 17,
前記金属酸化物は、酸化アルミニウム、酸化チタン、又は酸化タンタルである ことを特徴とする半導体装置。  The semiconductor device is characterized in that the metal oxide is aluminum oxide, titanium oxide, or tantalum oxide.
[19] 請求の範囲第 1項乃至第 16項のいずれか 1項に記載の半導体装置において、 前記第 1のノくリア膜又は前記第 2のバリア膜は、シリコン窒化膜又はシリコン窒化酸 化膜である [19] The semiconductor device according to any one of [1] to [16], wherein the first barrier film or the second barrier film is a silicon nitride film or a silicon nitride oxide film. Is a membrane
ことを特徴とする半導体装置。  A semiconductor device.
[20] 請求の範囲第 1項乃至第 16項のいずれか 1項に記載の半導体装置において、 前記第 1のノくリア膜は、酸化アルミニウム膜であり、 [20] The semiconductor device according to any one of claims 1 to 16, wherein the first noria film is an aluminum oxide film,
前記第 2のノくリア膜は、シリコン窒化膜である  The second noble film is a silicon nitride film.
ことを特徴とする半導体装置。  A semiconductor device.
[21] 請求の範囲第 1項乃至第 16項のいずれか 1項に記載の半導体装置において、 前記第 1のバリア膜は、酸化アルミニウム膜であり、 [21] The semiconductor device according to any one of claims 1 to 16, wherein the first barrier film is an aluminum oxide film,
前記第 2のバリア膜は、吸湿性を有する有機膜である  The second barrier film is a hygroscopic organic film
ことを特徴とする半導体装置。  A semiconductor device.
[22] 請求の範囲第 1項乃至第 21項のいずれか 1項に記載の半導体装置において、 前記強誘電体膜は、 PbZr Ti O膜、 Pb La Zr Ti O膜、 SrBi (Ta Nb l-X X 3 1-X X l—Y Y 3 2 X 1-[22] The semiconductor device according to any one of [1] to [21], wherein the ferroelectric film includes a PbZrTiO film, a PbLaZrTiO film, an SrBi (TaNb lX X 3 1-XX l—YY 3 2 X 1-
) 〇膜、又は Bi Ti O 膜である ) 〇 Film or Bi Ti O film
X 2 9 4 2 12  X 2 9 4 2 12
ことを特徴とする半導体装置。 [23] 半導体基板上に、下部電極と、前記下部電極上に形成された強誘電体膜と、前記 強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタを形成する工程 と、 A semiconductor device. [23] forming a ferroelectric capacitor having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film on a semiconductor substrate; ,
前記半導体基板上及び前記強誘電体キャパシタ上に、第 1の絶縁膜を形成するェ 程と、  Forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor;
前記第 1の絶縁膜の表面を平坦化する工程と、  Planarizing the surface of the first insulating film;
前記第 1の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 1のバリア膜を 形成する工程と、  Forming a flat first barrier film for preventing diffusion of hydrogen or moisture on the first insulating film;
前記第 1のバリア膜上に、第 2の絶縁膜を形成する工程と、  Forming a second insulating film on the first barrier film;
前記第 2の絶縁膜の表面を平坦化する工程と、  Planarizing the surface of the second insulating film;
前記第 2の絶縁膜上に、水素又は水分の拡散を防止する平坦な第 2のバリア膜を 形成する工程と  Forming a flat second barrier film for preventing diffusion of hydrogen or moisture on the second insulating film;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
[24] 請求の範囲第 23項記載の半導体装置の製造方法において、 [24] In the method of manufacturing a semiconductor device according to claim 23,
前記第 1の絶縁膜の表面を平坦化する工程の後、前記第 1のバリア膜を形成する 工程の前に、第 1の熱処理を行う工程を更に有する  A step of performing a first heat treatment after the step of planarizing the surface of the first insulating film and before the step of forming the first barrier film;
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[25] 請求の範囲第 24項記載の半導体装置の製造方法において、 [25] In the method for manufacturing a semiconductor device according to claim 24,
前記第 1の熱処理を行う工程では、少なくとも窒素ガスを用いて発生させたプラズマ 雰囲気にて第 1の熱処理を行うことにより、前記第 1の絶縁膜の表面を窒化する ことを特徴とする半導体装置の製造方法。  In the step of performing the first heat treatment, the surface of the first insulating film is nitrided by performing the first heat treatment in a plasma atmosphere generated using at least nitrogen gas. Manufacturing method.
[26] 請求の範囲第 23項乃至第 25項のいずれか 1項に記載の半導体装置の製造方法 において、  [26] The method for manufacturing a semiconductor device according to any one of claims 23 to 25,
前記第 2の絶縁膜の表面を平坦化する工程の後、前記第 2のバリア膜を形成する 工程の前に、第 2の熱処理を行う工程を更に有する  After the step of planarizing the surface of the second insulating film, the method further includes a step of performing a second heat treatment before the step of forming the second barrier film.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[27] 請求の範囲第 26項記載の半導体装置の製造方法において、 [27] In the method for manufacturing a semiconductor device according to claim 26,
前記第 2の熱処理を行う工程では、少なくとも窒素ガスを用いて発生させたプラズマ 雰囲気にて第 2の熱処理を行うことにより、前記第 2の絶縁膜の表面を窒化する ことを特徴とする半導体装置の製造方法。 In the step of performing the second heat treatment, plasma generated using at least nitrogen gas A method for manufacturing a semiconductor device, characterized in that a second heat treatment is performed in an atmosphere to nitride the surface of the second insulating film.
請求の範囲第 23項乃至第 27項のいずれか 1項に記載の半導体装置の製造方法 において、  In the method for manufacturing a semiconductor device according to any one of claims 23 to 27,
前記第 1の絶縁膜の表面を平坦化する工程又は前記第 2の絶縁膜の表面を平坦 化する工程では、 CMP法により前記第 1の絶縁膜の表面又は前記第 2の絶縁膜の 表面を研磨することにより、前記第 1の絶縁膜の表面又は前記第 2の絶縁膜の表面 を平坦化する  In the step of planarizing the surface of the first insulating film or the surface of the second insulating film, the surface of the first insulating film or the surface of the second insulating film is formed by CMP. By polishing, the surface of the first insulating film or the surface of the second insulating film is flattened.
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
PCT/JP2004/009429 2004-07-02 2004-07-02 Semiconductor device and process for fabricating the same WO2006003707A1 (en)

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