WO2007116443A1

WO2007116443A1 - Semiconductor device and process for producing the same

Info

Publication number: WO2007116443A1
Application number: PCT/JP2006/306665
Authority: WO
Inventors: Hideaki Kikuchi; Kouichi Nagai
Original assignee: Fujitsu Microelectronics Limited
Priority date: 2006-03-30
Filing date: 2006-03-30
Publication date: 2007-10-18
Also published as: JPWO2007116443A1

Abstract

A hydrogen-occluding conductive material having the property of absorbing hydrogen is used in combination with hydrogen diffusion preventive films (23, 27, 28) in order to prevent, without fail, hydrogen generated from coming into a ferroelectric film (25). The hydrogen-occluding conductive material or a conductive material containing it, palladium (Pd) in this case, is deposited on an interlayer dielectric (33) so as to fill via-holes (34a, 35a) through glue films (34b, 35b). CMP is then conducted to form plugs (34, 35). This relatively simple constitution prevents the penetration of water/hydrogen into inner parts without fail and enables a ferroelectric capacitor structure (30) to retain high performance. This can be realized without the need of increasing the number of constituent members and the number of steps.

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device using a conductive plug for connection to a conductive structure and a method for manufacturing the same, and in particular, a ferroelectric material in which a ferroelectric film is sandwiched between a lower electrode and an upper electrode. The main target is a semiconductor device having a capacitor structure.

Background art

In recent years, development of a ferroelectric memory (FeRAM) in which information is held in a ferroelectric capacitor structure by using polarization inversion of the ferroelectric has been advanced. Ferroelectric memory is a non-volatile memory in which retained information is not lost even when the power is turned off, and is particularly attracting attention because it can be expected to achieve high integration, high speed drive, high durability, and low power consumption.

[0003] As a material of the ferroelectric film constituting the ferroelectric capacitor structure, PZT (Pb (Zr, Ti) 0) having a large remanent polarization, for example, about 10 CZcm ² ) to 30 CZcm ² ) Membrane, S

Three

Ferroelectric oxides with a bottom bskite crystal structure such as BT (SrBi Ta O) film are mainly used.

2 2 9

It is used as.

Patent Document 1: Japanese Patent Laid-Open No. 5-183106

Patent Document 2: JP-A-9 97883

Disclosure of the invention

In a capacitor structure, particularly a ferroelectric capacitor structure, the characteristics of a capacitor film having a ferroelectric force due to moisture entering from the outside through an interlayer insulating film having a high affinity with water, such as a silicon oxide film. It is known to deteriorate. That is, first, moisture that has entered from the outside decomposes into hydrogen and oxygen during a high-temperature process during the formation of an interlayer insulating film or metal wiring. When this hydrogen enters the capacitor film, it reacts with oxygen in the capacitor film to form oxygen defects in the capacitor film and lower the crystallinity. The same phenomenon occurs when a ferroelectric memory is used for a long time. As a result, performance degradation of the ferroelectric capacitor structure occurs, such as a decrease in the amount of remanent polarization and dielectric constant of the capacitor film. In addition, such hydrogen intrusion degrades the performance of transistors and the like as well as ferroelectric capacitor structures. There are things to do.

[0006] In this regard, there is an attempt to prevent hydrogen from entering by forming a hydrogen diffusion prevention film such as alumina on the upper layer of the ferroelectric capacitor structure. Although this hydrogen diffusion preventing film can be expected to have a certain level of hydrogen blocking function, it cannot be said to be sufficient to maintain the high performance of the ferroelectric capacitor structure.

[0007] The present invention has been made in view of the above-described problems, and reliably prevents water and hydrogen from penetrating into the interior with a relatively simple configuration, and has a high performance in a capacitor structure, particularly a ferroelectric capacitor structure. It is an object of the present invention to provide a highly reliable semiconductor device and a method for manufacturing the same, which can realize this without increasing the number of constituent members and the number of processes.

The semiconductor device of the present invention is formed above a semiconductor substrate, and has a capacitor structure in which a capacitor film is sandwiched between a lower electrode and an upper electrode, and wiring formed above the capacitor structure. And a conductive plug that is formed on the capacitor structure and electrically connects at least the upper electrode and the wiring thereabove, and the conductive plug is a first conductive material that occludes hydrogen. It is formed including.

Another aspect of the semiconductor device of the present invention is formed above a semiconductor substrate, and is formed above a capacitor structure having a capacitor film sandwiched between a lower electrode and an upper electrode, and the capacitor structure. And a conductive plug that is formed on the capacitor structure and electrically connects the upper electrode and the wiring above the wiring. The wiring has a conductive material that absorbs hydrogen. Formed.

[0010] A method for manufacturing a semiconductor device of the present invention includes a step of forming a capacitor structure having a capacitor film sandwiched between a lower electrode and an upper electrode above a semiconductor substrate, and at least the capacitor structure on the capacitor structure. Forming a conductive plug electrically connected to the upper electrode; and forming a wiring on the conductive plug to form a wiring electrically connected to the upper electrode via the conductive plug; The conductive plug is formed of a material including a first conductive material that absorbs hydrogen.

[0011] According to the present invention, hydrogen can be reliably prevented from entering the capacitor film with a relatively simple configuration, and the high reliability of the capacitor structure, particularly the ferroelectric capacitor structure, can be maintained. It is possible to realize a semiconductor device without increasing the number of constituent members and the number of processes.

Brief Description of Drawings

[FIG. 1A] FIG. 1A is a schematic cross-sectional view showing the structure of a planar-type FeRAM according to a first embodiment along with its manufacturing method in the order of steps.

[FIG. 1B] FIG. 1B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

[FIG. 1C] FIG. 1C is a schematic cross-sectional view showing the structure of the planar-type FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

FIG. 1D is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

[FIG. 2A] FIG. 2A is a schematic cross-sectional view showing the structure of the planar-type FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

FIG. 2B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

[FIG. 2C] FIG. 2C is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

[FIG. 2D] FIG. 2D is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

FIG. 3A is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

FIG. 3B is a schematic cross-sectional view showing the structure of the planar type FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

FIG. 3C is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

[FIG. 4A] FIG. 4A is a schematic cross-sectional view showing the structure of the planar type FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

[FIG. 4B] FIG. 4B shows the structure of the planar type FeRAM according to the first embodiment. It is a schematic sectional drawing shown in order of a process with a method.

[FIG. 4C] FIG. 4C is a schematic cross-sectional view showing the structure of the planar type FeRAM according to the first embodiment in the order of processes together with its manufacturing method.

FIG. 5A is a schematic cross-sectional view showing the structure of the planar type FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

FIG. 5B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the first embodiment in the order of steps together with its manufacturing method.

[FIG. 6A] FIG. 6A is a schematic cross-sectional view showing the structure of FeRAM in the order of steps together with its manufacturing method (main steps) when damascene wiring is formed according to the first embodiment.

FIG. 6B is a schematic cross-sectional view showing the structure of the FeRAM when forming damascene wiring in the first embodiment, together with its manufacturing method (main steps), in the order of steps.

FIG. 6C is a schematic cross-sectional view showing the structure of the FeRAM when forming damascene wiring in the first embodiment, together with its manufacturing method (main steps), in the order of steps.

FIG. 6D is a schematic cross-sectional view showing the structure of FeRAM when forming damascene wiring in the first embodiment, together with its manufacturing method (main process), in order of process.

FIG. 6E is a schematic cross-sectional view showing the structure of the FeRAM when forming damascene wiring in the first embodiment, together with its manufacturing method (main steps), in the order of steps.

[FIG. 7A] FIG. 7A is a schematic cross-sectional view showing the structure of FeRAM in the order of steps together with its manufacturing method (main steps) when forming damascene wiring according to the first embodiment.

[FIG. 7B] FIG. 7B is a schematic cross-sectional view showing the structure of FeRAM in the first embodiment together with its manufacturing method (main steps) in the order of steps when forming damascene wiring.

[FIG. 7C] FIG. 7C is a schematic cross-sectional view showing the structure of the FeRAM when forming the damascene wiring in the first embodiment, together with its manufacturing method (main process).

FIG. 7D is a schematic cross-sectional view showing the structure of the FeRAM when forming damascene wiring in the first embodiment, together with its manufacturing method (main steps), in the order of steps.

[FIG. 8A] FIG. 8A is a schematic cross-sectional view showing the structure of FeRAM in the order of steps together with its manufacturing method (main steps) when damascene wiring is formed according to the first embodiment.

[FIG. 8B] FIG. 8B shows FeRAM when damascene wiring is formed in the first embodiment. It is a schematic sectional drawing which shows this structure with the manufacturing method (main process) in order of a process.

FIG. 9A is a schematic cross-sectional view showing the structure of a planar FeRAM according to Modification 1 of the first embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 9B is a schematic cross-sectional view showing the structure of the planar FeRAM according to Modification 1 of the first embodiment in the order of steps together with its manufacturing method (main steps).

[FIG. 10A] FIG. 10A is a schematic cross-sectional view showing the structure of a planar type FeRAM according to Modification 2 of the first embodiment along with its manufacturing method (main steps) in the order of steps.

FIG. 10B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in the order of steps.

FIG. 10C is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in the order of steps.

FIG. 10D is a schematic cross-sectional view showing the structure of the planar FeRAM according to Modification 2 of the first embodiment together with the manufacturing method (main steps) in the order of steps.

[FIG. 11A] FIG. 11A is a schematic cross-sectional view showing the structure of a planar type FeRAM according to Modification 2 of the first embodiment along with its manufacturing method (main steps) in the order of steps.

FIG. 11B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in the order of steps.

[FIG. 11C] FIG. 11C is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in the order of steps.

[FIG. 11D] FIG. 11D is a schematic cross-sectional view showing the structure of the planar type FeRAM according to the second modification of the first embodiment along with its manufacturing method (main process).

[FIG. 12A] FIG. 12A is a schematic cross-sectional view showing the structure of a planar type FeRAM according to Modification 2 of the first embodiment in the order of steps together with its manufacturing method (main steps).

[FIG. 12B] FIG. 12B is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in the order of steps.

[FIG. 12C] FIG. 12C is a schematic cross-sectional view showing the structure of the planar FeRAM according to the second modification of the first embodiment in the order of steps together with its manufacturing method (main steps).

[FIG. 13A] FIG. 13A shows the structure of a planar type FeRAM according to the second modification of the first embodiment. It is a schematic sectional drawing shown in order of a process with the manufacturing method (main process).

FIG. 13B is a schematic cross-sectional view showing the structure of the planar FeRAM according to Modification 2 of the first embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 14A is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment together with its manufacturing method in the order of steps.

FIG. 14B is a schematic cross-sectional view showing the configuration of the stacked FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 14C is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second embodiment along with its manufacturing method in the order of steps.

FIG. 14D is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 15A is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 15B is a schematic cross-sectional view showing the configuration of the stacked FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 15C is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 15D is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 16A is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 16B is a schematic cross-sectional view showing the configuration of the stacked FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof.

FIG. 16C is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 17A is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment along with its manufacturing method in the order of steps.

[FIG. 17B] FIG. 17B shows a stack type FeRAM configuration according to the second embodiment. It is a schematic sectional drawing shown in order of a process with a method.

[FIG. 18A] FIG. 18A is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second embodiment in the order of steps together with its manufacturing method.

FIG. 18B is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the second embodiment along with its manufacturing method in the order of steps.

FIG. 19A is a schematic cross-sectional view showing the structure of a stacked FeRAM according to Modification 1 of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 19B is a schematic cross-sectional view showing the configuration of the stack type FeRAM according to the first modification of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 20A is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 20B is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 20C is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 20D is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 21A is a schematic cross-sectional view showing the structure of a stacked FeRAM according to Modification 2 of the second embodiment, together with its manufacturing method (main steps), in the order of steps.

FIG. 21B is a schematic cross-sectional view showing the structure of the stacked FeRAM according to the second modification of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 21C is a schematic cross-sectional view showing the structure of the stack type FeRAM according to Modification 2 of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 21D is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment together with its manufacturing method (main steps) in the order of steps.

FIG. 22A is a schematic cross-sectional view showing the structure of a stack type FeRAM according to Modification 2 of the second embodiment in the order of steps together with its manufacturing method (main steps).

[FIG. 22B] FIG. 22B shows the configuration of the stack type FeRAM according to the second modification of the second embodiment. It is a schematic sectional drawing shown in order of a process with the manufacturing method (main process).

FIG. 23A is a schematic cross-sectional view showing the structure of a stacked FeRAM according to Modification 2 of the second embodiment in the order of steps together with its manufacturing method (main steps).

FIG. 23B is a schematic cross-sectional view showing the structure of the stack type FeRAM according to the second modification of the second embodiment together with its manufacturing method (main steps) in the order of steps.

BEST MODE FOR CARRYING OUT THE INVENTION

[0013] Basic structure of the present invention

The inventor of the present invention desirably provides a component having a material force having a property of blocking hydrogen to prevent the generated hydrogen from entering the capacitor film as much as possible above the capacitor film, that is, the capacitor structure. Considered. As the constituent member, a configuration in which an insulating film such as a metal oxide is formed in an insulating portion above the capacitor structure, and a configuration in which a conductive film is similarly formed in a conductive portion can be considered. As a selection criterion for the material of the component and its arrangement site, in addition to providing it in a site where a sufficient hydrogen blocking function can be exerted on the capacitor film, the number of components and processes are not increased as much as possible. It becomes important. In other words, it is desirable to form the existing and essential components as much as possible with a material having a hydrogen blocking function in a portion close to the capacitor structure.

[0014] Most of the existing and indispensable constituent members provided in the vicinity of the capacitor structure are conductive members except for an interlayer insulating film or the like. Based on this point, the inventor of the present invention has come up with the present invention as a result of comprehensively examining each of the above points. As a material of the constituent member, the inventor of the present invention is a highly conductive and highly moisture-resistant conductive material that exhibits a water / hydrogen barrier function more than an insulating material, such as palladium (Pd), lithium (Li), sodium (Na ), Magnesium (Mg), calcium (Ca), titanium (Ti), zirconium (Zr), vanadium (V), niobium (Nb), lanthanum (La), neodymium (Nd), samarium (Sm), etc. It was judged that a conductive material (hydrogen storage conductive material) having a property of absorbing hydrogen or a conductive material containing these materials is optimal.

[0015] Then, the present inventor forms a conductive film of a hydrogen-occlusion conductive material on the upper electrode as an arrangement site of the constituent member (application place of the constituent member) close to the capacitor structure. Larger surface area and volume compared to other cases (thus increasing hydrogen absorption) Existing and indispensable for a semiconductor device having a capacitor structure, that is, a conductive plug electrically connected to the upper electrode of the capacitor structure, and an electrical connection with the upper electrode through z or a conductive plug. The idea was to apply it to the wiring that is connected to each other.

[0016] For example, Pd is a metal having a hydrogen storage function that absorbs hydrogen of 935 times its own volume. Using this hydrogen-absorbing conductive material typified by Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, Sm, etc. A large amount of hydrogen absorption capacity (a large surface area and a large surface area) can be achieved without increasing the number of components and processes by forming a conductive plug connected to the wiring and / or a wiring electrically connected to the upper electrode via the conductive plug. Therefore, it is possible to efficiently prevent hydrogen from entering the capacitor film and to reliably maintain high capacitor characteristics.

[0017] When a metal having a hydrogen absorption function is used for the conductive plug and wiring, it is not always necessary to use a material that can withstand high-temperature annealing such as Pd. Therefore, the above hydrogen-absorbing conductive material can be used alone, or any metal can be used as an alloy. That is, (l) Hydrogen-absorbing conductive materials such as Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm may be used alone, or (2) ( Even if an alloy of any combination of the hydrogen-absorbing conductive materials shown in 1) is used, at least one of the hydrogen-absorbing conductive materials shown in (3) (1) and other metals (aluminum (A1), At least one of common conductive metal materials such as copper (Cu), iron (Fe), nickel (Ni), or iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium An alloy with (Ru), rhodium (Rh), osmium (Os) or other noble metals) may be used.

Furthermore, in the present invention, in addition to the configuration in which the conductive plug and Z or wiring are formed of a hydrogen storage conductive material, the hydrogen is similarly applied on the upper electrode of the capacitor structure, that is, between the upper electrode and the conductive plug. A structure is also proposed in which a conductive film made of an occlusive conductive material or a conductive material containing the same is provided.

In this case, it is necessary to use a material having excellent heat resistance because high-temperature annealing is performed after the contact hole is formed. Therefore, the material of the conductive film is Pd, or other noble metals (Ir, Pt, Au, Ag, Ru, Rh, Os, etc.) must be limited to alloys with at least one of them. These materials also have resistance to halogen-based gases as will be described later.

In the ferroelectric capacitor structure, the capacitor characteristics are easily deteriorated even by an etching cache or the like. For this reason, it is essential to recover the characteristics of the capacitor film using high-temperature annealing. For this reason, noble metals that can withstand high-temperature annealing and conductive oxides of noble metals are frequently used as materials for the upper and lower electrodes. These electrode materials are difficult to react with an etching gas such as a halogen-based gas, and are therefore usually difficult to be etched.

By the way, in the planar type semiconductor memory in which another conductive plug is provided on the lower electrode of the capacitor structure, when forming the via hole for connecting the upper electrode and the wiring, Each via hole to the lower electrode is formed by etching at the same time. Therefore, the upper electrode is excessively overetched and the upper electrode is scraped, and the thickness of the upper electrode is reduced. Further, as shown below, the etching rate of the hydrogen diffusion preventing film is low, and the etching product from the hydrogen diffusion preventing film lowers the selectivity, thereby further increasing the amount of scraping of the upper electrode material. As a result, retention defects increase.

On the other hand, in the stacked type semiconductor memory in which another conductive plug is provided under the lower electrode, the simultaneous via hole as described above is often not formed. However, regardless of stack type or planar type, the above-mentioned hydrogen diffusion prevention film is often formed to cover the ferroelectric capacitor structure in the ferroelectric capacitor structure. If this hydrogen diffusion prevention film is present on the upper electrode, the etching time of the hydrogen diffusion prevention film is low, so that the etching time is increased, and the amount of overetching exerted on the upper electrode during the formation of the via hole is greatly increased. In addition, it has been confirmed that the etching product from the hydrogen diffusion prevention film lowers the selectivity and greatly increases the amount of scraping of the upper electrode material that is the base film.

[0023] In this respect, hydrogen storage materials such as Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm have not only the above hydrogen absorption function. , Other hydrogen-absorbing conductive materials, and metal materials that are difficult to react with halogen-based gases (for example, noble materials such as Ir, p _t , Au, Ag, Ru, Rh, Os) By alloying with (metal) or the like, it is difficult to react with a halogen-based etching gas used when etching a via hole, and a material can be obtained. As a result, when the via hole is formed, the etching rate is low and it is difficult to perform the etching.

Accordingly, in addition to the configuration in which the conductive plug and Z or wiring are formed of a hydrogen storage conductive material in addition to the slight increase in the number of components and the number of steps (both one point and one step), the upper electrode By providing a conductive film made of a conductive material including a hydrogen storage conductive material between the conductive plug and the conductive plug, the hydrogen absorption capability is improved and hydrogen can be further prevented from entering the capacitor film, and the upper electrode can be prevented. It is possible to suppress retention failure without overetching.

[0025] Note that Patent Documents 1 and 2 disclose a configuration in which a hydrogen absorption layer having Pd isotropic force is provided on the upper force side of the upper electrode in a semiconductor memory having a ferroelectric capacitor structure. However, in this semiconductor memory, the conductive plug is not an essential component, and not only the basic configuration that is the premise of the present invention is different, but also the object of application of Pd is completely different. Therefore, the present invention is completely different from the inventions of Patent Documents 1 and 2.

[0026] Specific embodiments to which the present invention is applied

Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the following embodiments, a case where the present invention is applied to a FeRAM having a ferroelectric capacitor structure in which a ferroelectric film is applied to a capacitor film will be exemplified. In each embodiment, for convenience of explanation, the configuration of FeRAM will be described together with its manufacturing method. The present invention can also be applied to a semiconductor memory in which a normal dielectric film is applied to the capacitor film.

[0027] (First embodiment)

This embodiment exemplifies V, a so-called planar type FeRA M, in which a conductive plug is formed on the lower electrode and the upper electrode of the ferroelectric capacitor structure, respectively, so as to be conductive.

FIG. 1A to FIG. 5B are schematic cross-sectional views showing the structure of the planar type FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

[0028] First, as shown in FIG. 1A, the silicon semiconductor substrate 10 functions as a selection transistor. A MOS transistor 20 is formed.

Specifically, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, STI (Shallow Trench Isolation) method to determine the element active region.

Next, an impurity, here B, for example, is ion-implanted into the element active region under the conditions of a dose of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV to form the wall 12.

[0029] Next, a thin gate insulating film 13 with a thickness of about 3. Onm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film with a thickness of about 180 nm is formed on the gate insulating film 13 by a CVD method. For example, a silicon nitride film having a thickness of about 29 nm is deposited, and the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 are processed into an electrode shape by lithography and subsequent dry etching, whereby the gate insulating film 13 is formed. The gate electrode 14 is patterned. At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.

[0030] Next, using the cap film 15 as a mask, an impurity, for example, arsenic (As) in this case, is ion-implanted under the conditions of a dose of 5. OX 10 ¹⁴ Zcm ² and an acceleration energy of lOkeV. LDD region 16 is formed.

Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, so that the silicon oxide film is formed only on the side surfaces of the gate electrode 14 and the cap film 15. A sidewall insulating film 17 is formed leaving the film.

[0032] Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity in the element active region, here phosphorus (P), has a higher impurity concentration than the LDD region 16, for example, a dose of 5 Ion implantation under conditions of OX 10 ¹⁴ Zcm ² and acceleration energy of 13 keV to form the source Z drain region 18 that overlaps the LDD region 16, thereby completing the MOS transistor 20.

Subsequently, as shown in FIG. 1B, a protective film 21 and an interlayer insulating film 22a of the MOS transistor 20 are sequentially formed.

Specifically, a protective film 21 and an interlayer insulating film 22a are sequentially deposited so as to cover the MOS transistor 20. Here, as the protective film 21, a silicon oxide film is used as a material, and is deposited to a film thickness of about 20 nm by a CVD method. As the interlayer insulating film 22a, for example, a plasma SiO film (film thickness 20 nm), a plasma SiN film (film thickness of about 80 nm), and a plasma TEOS film (film thickness of about 1 OOOnm) are sequentially formed, and after stacking, until CMP reaches a film thickness of about 700 nm Grind.

Subsequently, as shown in FIG. 1C, an interlayer insulating film 22b and a hydrogen diffusion preventing film 23 are sequentially formed. 1C and subsequent drawings, for convenience of illustration, only the structure above the interlayer insulating film 22a is shown, and illustration of the silicon semiconductor substrate 10, the MOS transistor 20, and the like is omitted.

[0035] Specifically, first, a silicon oxide film is deposited to a thickness of about lOOnm on the interlayer insulating film 22a by, for example, a plasma CVD method using TEOS to form the interlayer insulating film 22b. Thereafter, the interlayer insulating film 22b is annealed. The condition for this annealing treatment is N gas

For example, run 2 at a flow rate of 20 liters Z for 20 minutes to 45 minutes at 650 ° C.

Next, on the interlayer insulating film 22b, the deterioration of the capacitor characteristics of the ferroelectric capacitor structure to be described later is prevented (the ferroelectric substance of hydrogen generated due to moisture generated from the external or upper insulating film) A hydrogen diffusion prevention film 23 is formed to prevent intrusion into the film). The hydrogen diffusion prevention film 23 is made of a metal oxide such as alumina (Al 2 O 3) as a material, and a

twenty three

Film thickness of 20ηπ by using the Deposits at ~ 50nm. Thereafter, the hydrogen diffusion preventing film 23 is annealed. The conditions for this annealing process are: O gas flow rate of 2 liters Z

2

For example, at 650 ° C. for 30 seconds to 120 seconds.

Subsequently, as shown in FIG. 1D, a lower electrode layer 24, a ferroelectric film 25, and an upper electrode layer 26 are sequentially formed.

Specifically, first, for example, the film thickness is 150 ηπ! A Pt film is deposited to about 200 nm to form the lower electrode layer 24.

Next, a ferroelectric film 25 having a PbZr Ti O (PZT: 0 <x <1) force, which is a ferroelectric material, is formed on the lower electrode layer 24 to a film thickness of about 100 nm to 300 nm by RF sputtering. Deposit

Three

The Then, the ferroelectric film 25 is annealed to crystallize the ferroelectric film 25. The annealing conditions include ArZO gas with 1.98 liters Z for Ar and 0.02 for O.

twenty two

While supplying at a flow rate of 5 liters Z, for example, run at 550 ° C to 650 ° C for 60 seconds to 120 seconds. The material of the ferroelectric film 25 is Pb La Zr Ti O (0 l -xl -yy 3 <χ <1, 0 <y <l), SrBi (Ta Nb) O (0 <x <1), Bi Ti O, etc. may be used.

2 x 1-x 2 9 4 2 12

Yes.

Next, the upper electrode layer 26 is deposited on the ferroelectric film 25.

As the upper electrode layer 26, first, for example, an IrO film 26a, which is a conductive oxide, is formed to a thickness of about 30 nm to 70 nm by reactive sputtering. Then, anneal the IrO film 26a

twenty two

Process. The annealing conditions include ArZO gas with 2.0 liters of Z,

2

While O is supplied at a flow rate of 0.02 liters Z, for example, 650 ° C to 850 ° C for 10 seconds to 6

2

Run for 0 seconds. Next, the IrO film 26b is formed on the IrO film 26a by reactive sputtering.

twenty two

It is formed in a thickness of about 150 nm to 300 nm. Then, a key of the IrO film 26b is formed on the IrO film 26b.

twenty two

A noble metal film functioning as a yap film, here a Pt film 26c, is formed to a thickness of about lOOnm by sputtering. The upper electrode layer 26 is composed of the IrO films 26a and 26b and the Pt film 26c.

2

In the upper electrode layer 26, Ir, Ru, RuO, SrRuO are used instead of the IrO films 26a, 26b.

twenty two

Other conductive oxides or a laminated structure thereof may be used. Also, formation of Pt film 26c

Three

Can be omitted.

Subsequently, as shown in FIG. 2A, the upper electrode 31 is patterned.

Specifically, the upper electrode layer 26 is processed into a plurality of electrode shapes by lithography and subsequent dry etching, and the upper electrode 31 is patterned.

Subsequently, as shown in FIG. 2B, the ferroelectric film 25 is processed.

Specifically, the ferroelectric film 25 is aligned with the upper electrode 31 and processed by lithography and subsequent dry etching. After the patterning of the ferroelectric film 25, the ferroelectric film 25 is annealed to restore the function of the ferroelectric film 25.

Subsequently, as shown in FIG. 2C, a hydrogen diffusion preventing film 27 for preventing the invasion of hydrogen 'water into the ferroelectric film 25 is formed.

Specifically, on the lower electrode layer 24 so as to cover the ferroelectric film 25 and the upper electrode 31, aluminum (Al 2 O 3) is used as a material and deposited to a film thickness of about 50 nm by a sputtering method to prevent hydrogen diffusion.

twenty three

A film 27 is formed. Thereafter, the hydrogen diffusion preventing film 27 is annealed.

Subsequently, as shown in FIG. 2D, the lower electrode layer 24 is covered together with the hydrogen diffusion preventing film 27 to complete the ferroelectric capacitor structure 30. In detail, the hydrogen diffusion prevention film 27 and the lower electrode layer 24 are aligned with the processed ferroelectric film 25 so that the lower electrode layer 24 remains larger in size than the ferroelectric film 25. Subsequent dry etching is performed to form a pattern of the lower electrode 32. Thus, the ferroelectric film 25 and the upper electrode 31 are sequentially laminated on the lower electrode 32, and the ferroelectric capacitor structure 30 in which the lower electrode 32 and the upper electrode 31 are capacitively coupled through the ferroelectric film 25 is obtained. Finalize. At the same time, the hydrogen diffusion preventing film 27 remains so as to cover from the upper surface of the upper electrode 31 to the side surfaces of the upper electrode 31 and the ferroelectric film 25 and the upper surface of the lower electrode layer 24. Thereafter, the hydrogen diffusion preventing film 27 is annealed.

Subsequently, as shown in FIG. 3A, a hydrogen diffusion preventing film 28 is formed.

Specifically, the capacitor characteristics of the ferroelectric capacitor structure 30 are prevented from deteriorating so as to cover the entire surface of the ferroelectric capacitor structure 30 (hydrogen generated due to moisture generated from an external or upper insulating film). Hydrogen diffusion prevention film 28 is formed to prevent the intrusion into the ferroelectric film 25). As the hydrogen diffusion preventing film 28, a metal oxide, for example, alumina (Al 2 O 3) is used as a material and deposited to a thickness of about 20 nm to 50 nm by a sputtering method. That

twenty three

Thereafter, the hydrogen diffusion prevention 28 is annealed.

Subsequently, as shown in FIG. 3B, an interlayer insulating film 33 is formed.

Specifically, the interlayer insulating film 33 is formed so as to cover the ferroelectric capacitor structure 30 via the hydrogen diffusion preventing films 27 and 28. Here, the interlayer insulating film 33 is formed by depositing a silicon oxide film with a film thickness of about 1500 nm to 2500 nm by, for example, a plasma CVD method using TEOS, and then polishing the film by CMP to a film thickness of about lOOOnm. To do. After CMP, for example, N 2 O plasma is used for the purpose of dehydration (and surface nitriding) of the interlayer insulating film 33.

2 Apply Manil processing.

Subsequently, as shown in FIG. 3C, a plug 36 connected to the source Z drain region 18 of the transistor structure 20 is formed.

Specifically, first, using the source Z drain region 18 as an etching stopper, the interlayer insulating film 33, the hydrogen diffusion preventing films 28, 27, the interlayer insulating film 22b, until a part of the surface of the source Z drain region 18 is exposed. 22a and protective film 21 are processed by lithography and subsequent dry etching to form, for example, a via hole 36a having a diameter of about 0.3 ^ πι (about 0.35 m) To do.

Next, a base film (glue film) 36b is formed by sequentially depositing, for example, a Ti film and a TiN film with a film thickness of about 20 nm and a film thickness of about 50 nm by a sputtering method so as to cover the wall surface of the via hole 36a. To do. Then, for example, a W film is formed by the CVD method so as to fill the via hole 36a through the glue film 36b. Thereafter, the W film and the glue film 36b are polished by CMP using the interlayer insulating film 33 as a stopper to form a plug 36 that fills the via hole 36a with W through the glue film 36b. After CMP, for example, N 2 plasma annealing is performed.

2

Subsequently, as shown in FIG. 4A, after a protective film 37 and a resist mask 38 for preventing oxidation of the plug 36 are sequentially formed as will be described later, a via to the ferroelectric capacitor structure 30 is formed. Holes 3 4a and 35a are formed.

Specifically, first, a protective film 37 is formed by depositing, for example, a SiON film on the interlayer insulating film 33 and the plug 36 to a thickness of about lOOnm by the CVD method. Next, a resist is applied on the protective film 37, and the resist is processed by lithography to form a resist mask 38 having openings 38a and 38b.

Next, the protective film 37 is dry-etched using the resist mask 38, and openings 37a and 37b are formed at portions matching the openings 38a and 38b of the protective film 37. Then, using the upper electrode 31 and the lower electrode 32 as an etching stopper, the interlayer insulating film 33 and the hydrogen diffusion preventing films 28 and 27 are dry-etched. In this dry etching, the interlayer insulating film 33 and the hydrogen diffusion preventing films 28 and 27 are processed until a part of the surface of the upper electrode 31 is exposed, and the interlayer insulating film is exposed until a part of the surface of the lower electrode 32 is exposed. 33 and the hydrogen diffusion preventing films 28 and 27 are simultaneously performed, and via holes 34a and 35a having a diameter of about 0.5 m, for example, are simultaneously formed at the respective portions.

[0050] Subsequently, as shown in FIG. 4B, the resist mask 38 is removed. At this time, the plug 36 is covered with the protective film 37. Thereafter, a failure treatment for recovering the damage received by the ferroelectric capacitor structure 30 is performed by various steps after the formation of the ferroelectric capacitor structure 30. Here, since the plug 36 is covered with the protective film 37, the oxidation of W is prevented.

Subsequently, as shown in FIG. 4C, plugs 34, 3 connected to the ferroelectric capacitor structure 30 are connected. Form 5.

Specifically, first, the protective film 37 is removed by whole surface anisotropic etching, so-called etch back.

Next, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm by a sputtering method so as to cover the wall surfaces of the via holes 34a, 35a, and a base film (glue film) 34 b, 35b is formed.

Next, plugs 34 and 35 are formed.

In the present embodiment, in combination with the hydrogen diffusion prevention films 23, 27, 28, the hydrogen occlusion property has the property of absorbing hydrogen to reliably prevent the generated hydrogen from entering the strong dielectric film 25. Using the conductive material, the hydrogen storage conductive material or a conductive material containing the same is deposited on the interlayer insulating film 33 so as to fill the via holes 34a and 35a via the glue films 34b and 35b. Examples of hydrogen storage conductive materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen-absorbing conductive materials such as Nd and Sm may be used alone, or (2) Even if an alloy of any combination of hydrogen-absorbing conductive materials shown in (1) is used, (3) ( At least one of the hydrogen-absorbing conductive materials shown in 1) and at least one of the other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni), etc.) Or an alloy with iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os) or other noble metals. May be used. Here, Pd is used as the conductive material to be deposited, and the plugs 34 and 35 are formed by, for example, the C VD method or the P VD method.

Then, the deposited Pd and glue films 34b and 35b are polished by CMP using the interlayer insulating film 33 as a stopper, and the via holes 34a and 35a are filled with W via the glue films 34b and 35b, respectively. , 35. After CMP, eg N 2 O plasma anneal

2

Processing may be performed.

In the present embodiment, the present invention is applied to a conductive plug that is indispensable for electrical connection with the upper electrode 31 and the lower electrode 32, and the plugs 34 and 35 are provided with a large amount of hydrogen absorption capacity (a large surface area). And Pd, which is a hydrogen storage conductive material having a volume). Therefore, hydrogen permeates into the ferroelectric film 25 without increasing the number of components and processes. Can be efficiently prevented, and high capacitor characteristics can be reliably maintained.

Subsequently, as shown in FIG. 5A, first wirings 45 connected to the plugs 34, 35, 36 are formed.

Specifically, first, the barrier metal film 42, the wiring film 43, and the barrier metal film 44 are deposited on the entire surface of the interlayer insulating film 33 by sputtering or the like. As the noria metal film 42, for example, a Ti film is sequentially formed to a thickness of about ⁵ nm and a TiN film is formed to a thickness of about 150 nm by sputtering. As the wiring film 43, for example, an A1 alloy film (here, Al—Cu film) is formed to a film thickness of about 350 nm. As the noria metal film 44, for example, a Ti film is sequentially formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering. The laminated structure of Ti film and TiN film has the function as a barrier metal and the effect of suppressing stress migration. The Ti film, which is a constituent element of the barrier metal film, has the effect of reducing the contact resistance. Here, the structure of the wiring film 43 is the same as that of the logic part other than FeRAM of the same rule, so there is no problem in wiring processing or reliability!

Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the noria metal film 44, the wiring film 43, and the barrier metal film 42 are formed by lithography and subsequent dry etching. The first wiring 45 connected to the plugs 34, 35, and 36 is patterned. Instead of forming an A1 alloy film as the wiring film 43, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 45. .

Subsequently, as shown in FIG. 5B, a second wiring 54 connected to the first wiring 45 is formed.

Specifically, first, an interlayer insulating film 46 is formed so as to cover the first wiring 45. As the interlayer insulating film 46, a silicon oxide film is formed to a thickness of about ⁷ OOnm, a plasma TEOS film is formed to a total thickness of about lOOm, and then the surface is polished by CMP. The film thickness is about 750 nm.

Next, a plug 47 connected to the first wiring 45 is formed.

The interlayer insulating film 46 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 45 is exposed, for example, to form a via hole 47a having a diameter of about 0.25 m. To do. Next, after forming a base film (glue film) 48 so as to cover the wall surface of the via hole 47a,

Then, a W film is formed so as to fill the via hole 47a through the glue film 48 by the CVD method. Then, for example, the W film and the glue film 48 are polished by CMP using the interlayer insulating film 46 as a stopper to form a plug 47 filling the via hole 47a with W via the glue film 48.

Note that instead of CMP, the plug 47 may be formed by performing anisotropic etching of the entire surface of the W film and the glue film 48 or so-called etch back. At this time, only W is etched, and the glue film 48 remains as it is.

Next, second wirings 54 connected to the plugs 47 are formed.

First, the barrier metal film 51, the wiring film 52, and the barrier metal film 5 are formed on the entire surface by sputtering or the like.

3 is deposited. As the rare metal film 51, for example, a Ti film is formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering.

Here, when the plug 47 is formed by the etch-back method, the glue film 48 remaining when the plug 47 is formed functions as a barrier metal film, and thus the barrier metal film 51 is unnecessary.

As the wiring film 52, for example, an A1 alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the rare metal film 53, for example, a Ti film is formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 52 is assumed to be the same structure as that of the logic part other than the Fe RAM of the same rule, there is no problem in wiring processing and reliability.

[0063] Next, after forming, for example, a SiON film or an antireflection film (not shown) as the antireflection film, the antireflection film, the NORA metal film 53, the wiring film 52, and the barrier metal film are formed by lithography and subsequent dry etching. 51 is covered with the wiring shape, and the second wiring 54 is formed into a pattern.

[0064] After that, the planar type FeRAM according to the present embodiment is completed through various processes such as the formation of an upper layer wiring and the interlayer insulating film.

As described above, according to the present embodiment, hydrogen can be reliably prevented from entering the ferroelectric film 25 with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 can be maintained. Highly reliable planar type FeRAM without increasing the number of components and processes Can be realized.

[0066] Here, various wirings of FeRAM, a part of the wiring located in the upper layer of the ferroelectric capacitor structure 30, for example, the first wiring and the second wiring (and subsequent wirings) in FIG. It may be formed by a so-called damascene method. In the following, an example is given of the case where Cu wiring is formed by applying the damascene method to the second wiring.

FIGS. 6A to 8B are schematic cross-sectional views showing the structure of the FeRAM in FIG. 5A and subsequent steps together with its manufacturing method (main steps) when forming damascene wiring in the first embodiment.

First, after the process of FIG. 5A, an interlayer insulating film 46 is formed so as to cover the first wiring 45 as shown in FIG. 6A.

Specifically, a silicon oxide film is formed to a thickness of about 700 nm so as to cover the first wiring 45, a plasma TEOS film is formed to a total thickness of about lOO nm, and then a CMP film is formed. The surface is then polished to a thickness of about 750 nm, and an interlayer insulating film 46 is formed. After CMP, for example, plasma annealing of N 2 O is performed.

2

Subsequently, as shown in FIG. 6B, a via hole 49 a that exposes the surface of the first wiring 45 is formed. 6B and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 46 is shown, and illustration of the ferroelectric capacitor structure 30, the first wiring 45, and the like is omitted. Here, the plug 49 connected to one of the first wires 45 connected to the plugs 34, 35, 36 (for example, the first wire 45 connected to the plug 35) is shown as a representative. To do.

[0070] Specifically, the interlayer insulating film 46 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 45 is exposed, for example, a via hole having a diameter of about 0.25 / zm. 49a is formed.

Subsequently, as shown in FIG. 6C, a base film 64 made of a silicide film is formed and Cu plating is performed.

Specifically, the base film is formed of a silicide film as an oxygen-impermeable conductor. Specifically, for example, a Ta film is formed on the interlayer insulating film 46 by sputtering or the like so as to cover the inner wall surface of the via hole 49a. Form a base film (glue film) 61 with a thickness of about 20 nm Then, after forming a Cu seed film (not shown), a Cu (or alloy) film 62 is formed on the glue film 61 so as to embed the via hole 49a via the glue film 61 by a plating method. accumulate

Subsequently, as shown in FIG. 6D, a plug 49 is formed.

Specifically, the Cu film 62 and the glue film 61 are polished by CMP using the interlayer insulating film 46 as a stopper, and a plug 49 is formed in which the via hole 49a is filled with Cu via the glue film 61.

Subsequently, as shown in FIG. 6E, the silicon nitride film 63, the interlayer insulating film 64, the SOG film 65, the interlayer insulating film 66, and the silicon nitride film 67 are formed on the interlayer insulating film 46 so as to cover the plug 49. Are sequentially stacked.

Specifically, as the silicon nitride film 63, for example, a film thickness of 50ηπ! ~ LOOnm is formed. As the interlayer insulating film 64, for example, a film thickness of 200 ηπ! Forms about ~ 400 nm. The SOG film 65 is formed to have a film thickness of about 100 ηm to 200 nm by spin coating SOG. The interlayer insulating film 66 is formed with a film thickness of about 10 Onm by, for example, the CVD method. The silicon nitride film 67 is formed to a thickness of about lOOnm by, for example, the CVD method.

Subsequently, as shown in FIG. 7A, the silicon nitride film 67 is processed.

Specifically, the silicon nitride film 67 is patterned by lithography and dry etching, and a wiring-shaped opening 67 a is formed in the silicon nitride film 67.

Subsequently, as shown in FIG. 7B, the interlayer insulating film 66 and the SOG film 65 are cleaned.

Specifically, the interlayer insulating film 66 and the SOG film 65 are patterned by lithography and dry etching, and a hole-shaped opening 66a is formed at a position located above the plug 49 aligned with the opening 67a of the interlayer insulating film 66 and the SOG film 65. , 65a.

Subsequently, as shown in FIG. 7C, the interlayer insulating film 66 and the interlayer insulating film 64 are processed.

Specifically, using the silicon nitride film 67 as a node mask, the interlayer insulating film 66 is patterned into a wiring shape following the opening 67a by lithography and dry etching to form an opening 66b in which the opening 66a is expanded. At the same time, the interlayer insulating film 66 and the SOG film 65 function as a mask, the interlayer insulating film 64 is patterned into a hole shape following the opening 65a, and the opening 64a is formed. Subsequently, as shown in FIG. 7D, the wiring trench 68 is completed.

Specifically, using the silicon nitride film 67 as a node mask, the silicon nitride film 63 is patterned by lithography and dry etching until the surface of the plug 47 is exposed. At this time, the SOG film 65 is formed with a wiring-shaped opening 65b in which the opening 65a is expanded following the openings 67a and 66b, and the silicon nitride film 63 is formed with a hole-shaped opening following the opening 64a. Hole 63a is formed. Here, the silicon nitride film 67 is also thinned by the thickness of the silicon nitride film 63 by etching. At this time, the openings 63a and 64a formed in the silicon nitride film 63 and the interlayer insulating film 64 and the openings 65b, 66b and 67a formed in the SOG film 65, the interlayer insulating film 66 and the silicon nitride film 67 are integrated. Thus, the wiring groove 68 is completed.

Subsequently, as shown in FIG. 8A, a base film 69 made of a silicide film is formed and Cu plating is performed.

Specifically, for example, a Ta film is formed by sputtering, etc. 膜厚 ηπ! A base film (glue film) 69 is formed to a thickness of about 20 nm.

Then, after forming a Cu seed film (not shown: film thickness of about 130 nm), a Cu film 70 is formed on the glue film 69 so as to embed the wiring groove 68 through the glue film 69 by a plating method. accumulate.

Subsequently, as shown in FIG. 8B, a wiring structure 71 is formed.

Specifically, the Cu film 70, the glue film 69, and the silicon nitride film 67 are polished by CMP using the interlayer insulating film 66 as a stopper, and the wiring groove 68 is filled with Cu (or an alloy thereof) through the glue film 69, and plugged. A wiring structure 71 that is electrically connected to the first wiring 45 through 49 is formed. Here, in the wiring structure 71, the portions where the openings 63a and 64a are embedded with Cu via the glue film 69 are embedded in the conductive plug portion, and the openings 65b and 66b are embedded with Cu via the glue film 69. Corresponds to a wiring portion, and is formed by forming a conductive plug portion and a wiring portion.

[0082] A variation

Hereinafter, a modification of the first embodiment will be described.

[0083] (Modification 1)

In this example, in addition to the configuration of the first embodiment, in the multilayer wiring structure, at least the first As a material for the wiring film of 1 wiring, a hydrogen storage conductive material or a conductive material containing this is used.

FIG. 9A and FIG. 9B are schematic cross-sectional views showing the structure of the planar type FeRAM according to Modification 1 of the first embodiment in the order of steps together with the manufacturing method (main steps).

First, similarly to the first embodiment, the respective steps of FIGS. 1A to 4C are performed.

Subsequently, as shown in FIG. 9A, first wirings 84 connected to the plugs 34, 35, 36 are formed.

Specifically, first, a barrier metal film 81, a wiring film 82, and a barrier metal film 83 are deposited on the entire surface of the interlayer insulating film 33 by sputtering or the like. As the noria metal film 81, for example, a Ti film and a TiN film are sequentially laminated to a film thickness of about 5 nm and 150 nm, respectively, by sputtering or the like.

[0085] In this example, in combination with the hydrogen diffusion prevention films 23, 27, 28 and the plugs 34, 35, hydrogen is absorbed so as to surely prevent the generated hydrogen from entering the ferroelectric film 25. The wiring film 82 is formed using a hydrogen storage conductive material having such a property or a conductive material containing the same. Examples of hydrogen storage conductive materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, Sm and other hydrogen-absorbing conductive materials can be used alone, or (2) (3) (3) ( At least one of the hydrogen-absorbing conductive materials shown in 1) and at least one of the other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni), etc.) Or at least one precious metal such as iridium (Ir), platinum (Pt), gold (Au), silver (A g), ruthenium (R _U ), rhodium (Rh), osmium (Os) An alloy may be used. Here, Pd is used as the conductive material to be deposited, and the wiring film 82 is formed to a thickness of about 350 nm by, for example, the CV D method or the PVD method.

[0086] In this example, the present invention is applied to wiring that is indispensable for making electrical connection to the plugs 34 and 35 and establishing electrical connection with the upper electrode 31 and the lower electrode 32 via the plugs 34 and 35. 82 is formed from Pd, which is a hydrogen storage conductive material having a large amount of hydrogen absorption capacity (large surface area and volume). Therefore, it is possible to efficiently prevent hydrogen from entering the strong dielectric film 25 without increasing the number of constituent members and the number of processes, thereby ensuring high capacitor characteristics. It is possible to hold it.

[0087] As the rare metal film 83, for example, a Ti film and a TiN film are sequentially stacked to a thickness of about 5 nm and 150 nm, respectively, by sputtering or the like. Since the structure of the wiring film 82 is assumed to be the same structure as that of the logic part other than the FeRAM having the same rule, there is no problem in processing and reliability of the wiring.

Next, for example, after forming a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the noria metal film 83, the wiring film 82 and the barrier metal film 81 are formed by lithography and subsequent dry etching. Then, the first wiring 84 connected to the plugs 34, 35, and 36 is patterned.

In this example, the case where the plugs 34 and 35 and the first wiring 84 are formed as separate bodies is illustrated, but these may be formed integrally.

In this case, for example, after forming via holes 34a and 35a simultaneously in FIG. 4B, glue film 81 (only a TiN film having a thickness of about 150 nm) is formed so as to cover the inner wall surface of via holes 34a and 35a and interlayer insulating film 33. Pd is deposited so as to fill the via holes 34a and 35a and cover the glue film 81 on the interlayer insulating film 33 using a hydrogen storage conductive material or a conductive material containing this, for example, Pd. A glue film 83 (a laminated structure of a Ti film (film thickness of about 5 nm) and a TiN film (film thickness of about 150 nm)) is deposited thereon. Then, on the interlayer insulating film 33, the glue films 83, Pd, and the glue film 81 are patterned in a wiring shape. As a result, the via holes 34a and 35a are filled with Pd through the glue film 81, and the upper surface is covered with the glue film 83 and extends on the interlayer insulating film 33 (the plugs 34 and 35 and the first wiring 84). Are integrally formed). At the same time, the first wiring 84 connected to the plug 36 is formed.

Further, the plug 36 may be integrally formed with the first wiring 84 in the same manner as described above. In this case, Pd is used as the conductive material, and the plugs 34, 35, 36 and the first wiring 84 are integrally formed.

Subsequently, as shown in FIG. 9B, a second wiring 54 connected to the first wiring 84 is formed.

Specifically, first, the interlayer insulating film 46 is formed so as to cover the first wiring 84. As the interlayer insulating film 46, a silicon oxide film is formed to a thickness of about ⁷ OOnm, a plasma TEOS film is formed to a total thickness of about lOOm, and then the surface is polished by CMP. , Film thickness 7 Form about 50 nm.

Next, a plug 47 connected to the first wiring 84 is formed.

The interlayer insulating film 46 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 84 is exposed, thereby forming a via hole 47a having a diameter of about 0.25 m, for example. Next, after forming a base film (glue film) 48 so as to cover the wall surface of the via hole 47a, a W film is formed by the CVD method so as to fill the via hole 47a through the glue film 48. Then, for example, the W film and the glue film 48 are polished by CMP using the interlayer insulating film 46 as a stopper to form a plug 47 filling the via hole 47a with W via the glue film 48.

Note that instead of CMP, the plug 47 may be formed by performing anisotropic etching on the entire surface of the W film and the glue film 48 or so-called etch back. At this time, only W is etched, and the glue film 48 remains as it is.

Next, second wirings 54 connected to the plugs 47 are formed.

First, a barrier metal film 51, a wiring film 52, and a barrier metal film 53 are deposited on the entire surface by sputtering or the like. As the rare metal film 51, for example, a Ti film is formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering.

As the wiring film 52, for example, an A1 alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the rare metal film 53, for example, a Ti film is formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 52 is assumed to be the same structure as that of the logic part other than the Fe RAM of the same rule, there is no problem in wiring processing and reliability.

Next, for example, a SiON film or an antireflection film (not shown) is formed as an antireflection film, and then the antireflection film, the NORA metal film 53, the wiring film 52, and the barrier metal film are formed by lithography and subsequent dry etching. 51 is covered with the wiring shape, and the second wiring 54 is formed into a pattern.

[0098] Note that an A1 alloy film is used as the wiring film 52 (and the wiring film in the Z or upper wiring). Instead of forming, it is also preferable to use a hydrogen storage conductive material such as Pd or a conductive material containing the same as the wiring film 82.

[0099] Instead of forming the A1 alloy film as the wiring film 52 (and the wiring film in Z or an upper layer wiring thereof), a so-called damascene method or the like may be used as in FIGS. 6A to 8B according to the first embodiment. A Cu film (or Cu alloy film) may be formed by using it, and a Cu wiring may be formed as the second wiring 54.

[0100] After the pressing force, the planar type FeRAM according to this example is completed through various processes such as the formation of an interlayer wiring and further upper layer wiring.

[0101] As described above, according to this example, hydrogen can be more reliably prevented from entering the ferroelectric film 25 with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 can be maintained. A highly reliable planar FeRAM can be realized without increasing the number of components and processes.

[0102] (Variation 2)

In this example, in addition to the configuration of Modification 1, a conductive film made of a hydrogen storage conductive material or a conductive material including the same is formed on the ferroelectric capacitor structure 30 (between the upper electrode 31 and the plug 34). To do.

FIG. 10A to FIG. 13B are schematic cross-sectional views showing the structure of the planar type FeRAM according to the second modification of the first embodiment along with its manufacturing method (main steps) in order of steps.

First, similarly to the first embodiment, the respective steps of FIGS. 1A to 1C are performed.

Subsequently, as shown in FIG. 10A, a lower electrode layer 24, a ferroelectric film 25, an upper electrode layer 26, and a conductive film 91 are sequentially formed.

Specifically, first, a Pt film is deposited to a thickness of, for example, about 150 nm to 200 nm by sputtering, and the lower electrode layer 24 is formed.

Next, a ferroelectric film 25 made of a ferroelectric material such as PZT is formed on the lower electrode layer 24 by RF sputtering, with a film thickness of 膜厚 ηπ! Deposits to about 300nm. Then, the ferroelectric film 25 is annealed to crystallize the ferroelectric film 25. As the conditions for this annealing treatment, ArZO gas is used for Ar 1.98 liters Z 025

2 minutes, O

While 2 is supplied at a flow rate of 0.1 liters Z, for example, it is performed at 550 ° C to 650 ° C for 60 seconds to 120 seconds. Next, the upper electrode layer 26 is deposited on the ferroelectric film 25.

twenty two

Process. The annealing conditions include ArZO gas with 2.0 liters of Z,

2

twenty two

It is formed in a thickness of about 150 nm to 300 nm.

Next, a noble metal film functioning as a cap film for the IrO film 26b, on the IrO film 26b,

twenty two

Here, the Pt film 26c is formed to a thickness of about lOOnm by sputtering. IrO film 26a, 26b

2

The upper electrode layer 26 is composed of the Pt film 26c. In the upper electrode layer 26, instead of the IrO films 26a and 26b, Ir, Ru, RuO, SrRuO, other conductive oxides and these

2 2 3

It is good also as a laminated structure. Further, the formation of the Pt film 26c can be omitted.

Next, a conductive film 91 is formed.

In this example, a hydrogen storage conductive material or a conductive material including the same is deposited on the upper electrode layer 26. The hydrogen-occlusion conductive material should be a material that has not only the hydrogen-occlusion property but also excellent heat resistance enough to withstand high-temperature annealing and resistance to halogen-based gas. Specifically, Pd has a high hydrogen absorption capacity that absorbs 935 times its own volume of hydrogen, and other noble metals (Ir, Pt, An alloy with at least one of Au, Ag, Ru, Rh, Os and the like is preferable. Here, Pd is used as a conductive material to be deposited, and the film thickness is such that it does not penetrate through the conductive film 91 by, for example, CVD or PVD, due to overetching when the via hole 34a described later is formed, in this case, about lOOnm. To form.

Subsequently, as shown in FIG. 10B, the upper electrode 31 whose upper surface is covered with the conductive film 91 is patterned.

Specifically, the conductive film 91 and the upper electrode layer 26 are processed into a plurality of electrode shapes by lithography and subsequent dry etching, and the upper electrode 31 is patterned in a state where the upper surface is covered with the conductive film 91.

Subsequently, as shown in FIG. 10C, the ferroelectric film 25 is processed. Specifically, the ferroelectric film 25 is aligned with the upper electrode 31 and processed by lithography and subsequent dry etching. After the patterning of the ferroelectric film 25, the ferroelectric film 25 is annealed to restore the function of the ferroelectric film 25.

Subsequently, as shown in FIG. 10D, a hydrogen diffusion preventing film 27 for preventing the entry of hydrogen into the ferroelectric film 25 is formed.

twenty three

Subsequently, as shown in FIG. 11A, the lower electrode layer 24 is covered together with the hydrogen diffusion preventing film 27 to complete the ferroelectric capacitor structure 30.

Lithography and subsequent dry etching are performed so that the hydrogen diffusion preventing film 27 and the lower electrode layer 24 are aligned with the processed ferroelectric film 25 so that the lower electrode layer 24 remains larger than the ferroelectric film 25. Then, the lower electrode 32 is patterned. As a result, the ferroelectric film 25 and the upper electrode 31 whose upper surface is covered with the conductive film 91 are sequentially laminated on the lower electrode 32, and the lower electrode 32 and the upper electrode 31 are capacitively connected via the ferroelectric film 25. The ferroelectric capacitor structure 30 to be coupled is completed. At the same time, the hydrogen diffusion preventing film 27 remains so as to cover the upper surface force of the conductive film 91 over the conductive film 91, the side surfaces of the upper electrode 31 and the ferroelectric film 25, and the upper surface of the lower electrode layer 24. Thereafter, the hydrogen diffusion prevention film 27 is annealed.

Subsequently, as shown in FIG. 11B, a hydrogen diffusion preventing film 28 is formed.

More specifically, a film thickness of 20ηπ is formed by sputtering using alumina (Al 2 O 3) as a material so as to cover the entire surface of the ferroelectric capacitor structure 30 and the conductive film 91! ~ 50nm deposition and hydrogen expansion

twenty three

A scattering prevention film 28 is formed. Thereafter, the hydrogen diffusion preventing film 28 is annealed.

Subsequently, as shown in FIG. 11C, an interlayer insulating film 33 is formed.

Specifically, the interlayer insulating film 33 is formed so as to cover the ferroelectric capacitor structure 30 and the conductive film 91 with the hydrogen diffusion preventing films 27 and 28 interposed therebetween. Here, as the interlayer insulating film 33, for example, a silicon oxide film is deposited to a film thickness of about 1500 nm to 2500 nm by a plasma CVD method using TEOS, and then, for example, until the film thickness becomes about lOOOnm by CMP. Polished and shaped To do. After CMP, for example, for the purpose of dehydrating the interlayer insulating film 33, for example, a plasma plasma of NO.

2

Neal treatment is applied.

Subsequently, as shown in FIG. 11D, a plug 36 connected to the source Z drain region 18 of the transistor structure 20 is formed.

Specifically, first, using the source Z drain region 18 as an etching stopper, the interlayer insulating film 33, the hydrogen diffusion preventing films 28, 27, the interlayer insulating film 22b, until a part of the surface of the source Z drain region 18 is exposed. 22a and the protective film 21 are processed by lithography and subsequent dry etching to form a via hole 36a having a diameter of about 0.3 m, for example.

Next, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm by a sputtering method so as to cover the wall surface of the via hole 36a, and a base film (glue film) 36b is formed. Form. Then, for example, a W film is formed by the CVD method so as to fill the via hole 34a through the glue film 36b. Thereafter, the W film and the glue film 36b are polished by CMP using the interlayer insulating film 33 as a stopper to form a plug 36 filling the via hole 36a with W via the glue film 36a. After CMP, for example, N 2 plasma annealing is performed.

2

Subsequently, as shown in FIG. 12A, after forming a protective film 37 and a resist mask 38 for preventing oxidation of the plug 36 in sequence, via holes 34a and 35a to the ferroelectric capacitor structure 30 are formed. To do.

Next, the protective film 37 is dry-etched using the resist mask 38, and openings 37a and 37b are formed at portions matching the openings 38a and 38b of the protective film 37. Then, the interlayer insulating film 33 and the hydrogen diffusion preventing films 28 and 27 are dry-etched using the conductive film 91 and the lower electrode 32 as etching stoppers, respectively. In this dry etching, the interlayer insulating film 33 and the hydrogen diffusion preventing films 28 and 27 are processed until a part of the surface of the conductive film 91 is exposed, and the interlayer insulating film is exposed until a part of the surface of the lower electrode 32 is exposed. 33 and the hydrogen diffusion prevention films 28 and 27 are simultaneously performed, and a via hole 34a having a diameter of, for example, about 0.5 m is formed in each portion. , 35a are formed simultaneously.

Here, each material of the upper electrode is difficult to react with an etching gas such as a halogen-based gas, and thus is normally difficult to be etched. Since the via holes to the upper electrode and the lower electrode are simultaneously formed by etching as described above, the upper electrode is excessively overetched and the upper electrode is scraped, and the thickness of the upper electrode is reduced. As a result, the so-called retention failure increases. Further, it has been confirmed that when the hydrogen diffusion preventing film is present on the upper electrode, the overetching of the upper electrode during the formation of the via hole is greatly increased.

[0119] In this respect, the hydrogen storage conductive material such as Pd has not only a function of absorbing hydrogen as described above, but also because it is difficult to react with a halogen-based etching gas used for etching a via hole. At the time of forming the hole, it has a function that the etching rate is low and etching is difficult.

[0120] In this example, by providing the conductive film 91 made of Pd on the upper electrode 31, the hydrogen absorption capability is improved, and the penetration of hydrogen into the ferroelectric film 25 is more reliably prevented, and the via When the holes 34a and 35a are formed at the same time, it is possible to suppress the retention failure without over-etching the upper electrode 31.

Subsequently, as shown in FIG. 12B, the resist mask 38 is removed. At this time, the plug 36 is covered with the protective film 37. Thereafter, a failure treatment for recovering the damage received by the ferroelectric capacitor structure 30 is performed by various steps after the formation of the ferroelectric capacitor structure 30. Here, since the plug 36 is covered with the protective film 37, the oxidation of W is prevented.

Subsequently, as shown in FIG. 12C, plugs 34 and 35 connected to the ferroelectric capacitor structure 30 are formed.

Next, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm by a sputtering method so as to cover the wall surfaces of the via holes 34a, 35a, and a base film (glue film) 34 b, 35b is formed. Next, plugs 34 and 35 are formed.

In this example, the hydrogen storage conductive material or a conductive material containing the hydrogen storage conductive material is deposited on the interlayer insulating film 33 so as to fill the via holes 34a and 35a via the glue films 34b and 35b. Examples of hydrogen storage conductive materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen-absorbing conductive materials such as Nd and Sm may be used alone, or (2) Even if an alloy based on any combination of hydrogen-absorbing conductive materials shown in (1) is used, (3) At least one of the hydrogen-absorbing conductive materials shown in (1) and other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni), etc.) Or at least one precious metal such as iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os) An alloy may be used. Here, Pd is used as the conductive material to be deposited, and the plugs 34 and 35 are formed by, for example, the CVD method or the PVD method.

2

Processing may be performed.

Subsequently, as shown in FIG. 13A, each first wiring 84 connected to each of the plugs 34, 35, and 36 is formed.

In this example, in combination with the hydrogen diffusion preventing films 23, 27, 28, the conductive film 91, and the plugs 34, 35, it is necessary to reliably prevent the generated hydrogen from entering the ferroelectric film 25. The wiring film 82 is formed using a hydrogen storage conductive material having the property of absorbing hydrogen or a conductive material containing the same. Examples of hydrogen storage conductive materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen-absorbing conductive materials such as Nd and Sm may be used alone, or (2) Hydrogen-absorbing properties shown in (1) Even if an alloy of any combination of conductive materials is used, at least one of the hydrogen-absorbing conductive materials shown in (3) (1) and other metals (aluminum (A1), copper (Cu), iron (Fe)) , -Kel (Ni) and other common conductive metal materials, or iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium ( Rh), an alloy with at least one of noble metals such as osmium (Os) may be used. Here, Pd is used as the conductive material to be deposited, and the wiring film 82 is formed to a thickness of about 350 nm by, for example, the CVD method or the PVD method.

In this example, the conductive film 91 is formed on the upper electrode 31, and the plug 34 that is electrically connected to the upper electrode 31 via the conductive film 91, the plug 35 that is connected to the lower electrode 32, First wiring 84 electrically connected to upper electrode 31 via conductive film 91 and plug 34 Wiring 82 of first wiring 84 and first wiring 84 electrically connected to lower electrode 32 and plug 35 The wiring film 82 is formed using Pd, which is a hydrogen storage material having a large amount of hydrogen absorption capacity (large surface area and volume), as a material. Accordingly, it is possible to prevent hydrogen from entering the ferroelectric film 25 as efficiently as possible without increasing the number of constituent members and the number of processes, and it is possible to reliably maintain high capacitor characteristics. Become.

[0128] As the rare metal film 83, for example, a Ti film and a TiN film are sequentially stacked to a thickness of about 5 nm and 150 nm, respectively, by sputtering or the like. Since the structure of the wiring film 82 is assumed to be the same structure as that of the logic part other than the FeRAM having the same rule, there is no problem in processing and reliability of the wiring.

Next, for example, a SiON film or an antireflection film (not shown) is formed as an antireflection film, and then the antireflection film, the noria metal film 83, the wiring film 82, and the barrier metal film 81 are formed by lithography and subsequent dry etching. Then, the first wiring 84 connected to the plugs 34, 35, and 36 is patterned.

Subsequently, as shown in FIG. 13B, a second wiring 54 connected to the first wiring 84 is formed. Specifically, first, an interlayer insulating film 46 is formed so as to cover the first wiring 84. Form. As the interlayer insulating film 46, a silicon oxide film is formed to a thickness of about ⁷ OOnm, a plasma TEOS film is formed to a total thickness of about lOOm, and then the surface is polished by CMP. , Film thickness 7 Form about 50 nm.

Next, a plug 47 connected to the first wiring 84 is formed.

Next, second wirings 54 connected to the plugs 47 are formed.

[0136] Next, for example, a SiON film or an antireflection film (not shown) is formed as an antireflection film, and then the antireflection film, the NORA metal film 53, the wiring film 52, and the barrier metal film are formed by lithography and subsequent dry etching. 51 is covered with the wiring shape, and the second wiring 54 is formed into a pattern.

[0137] Note that an A1 alloy film is used as the wiring film 52 (and the wiring film in the Z or upper wiring). Instead of forming, it is also preferable to use a hydrogen storage conductive material such as Pd or a conductive material containing the same as the wiring film 82.

In addition, instead of forming the A1 alloy film as the wiring film 52 (and the wiring film in the Z or the upper layer wiring), a so-called damascene method or the like is performed in the same manner as in FIGS. 6A to 8B according to the first embodiment. A Cu film (or Cu alloy film) may be formed by using it, and a Cu wiring may be formed as the second wiring 54.

[0139] After applying the force, the planar type FeRAM according to the present example is completed through various processes such as formation of an interlayer wiring and further upper layer wiring.

[0140] As described above, according to the present example, hydrogen is prevented from entering the ferroelectric film 25 as much as possible with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 is maintained. At the same time, it is possible to suppress the retention failure without over-etching the upper electrode 31. With this configuration, an extremely reliable planar FeRAM can be realized without increasing the number of components and processes.

In the first embodiment, the plugs 34 and 35 are replaced with the plugs 34 and 35 in the first modification, and the first wiring 84 is replaced with the plugs 34 and 35 and the first wiring 84 in the first modification. In addition to the above, the configuration in which the conductive film 91 is formed using Pd, which is a hydrogen storage conductive material, is disclosed, but the following configurations are also included in the scope of the present invention.

[0142] (1) The plugs 34 and 35 are formed using a hydrogen storage conductive material such as Pd or a conductive material containing the same, and the conductive film 91 is a hydrogen storage conductive material such as Pd or the like. The first wiring shall be a normal A1 alloy wiring or the like.

(2) The first wiring 84 is formed using a conductive material containing hydrogen, such as Pd, which is a hydrogen storage conductive material, and the conductive film 91 is formed of Pd, which is a hydrogen storage conductive material. Each plug formed by using a conductive material containing the same or the like and electrically connected to the ferroelectric capacitor structure 30 is a normal W plug or the like.

[0144] Even in the methods (1) and (2), the plugs 34 and 35, the first wiring 84, and the conductive film 91 are all hydrogen-absorbing conductive material such as Pd. Although it is inferior to the case where it is used (in the case of Modification 2), it can reliably maintain high capacitor characteristics and achieve high reliability and FeRAM. [0145] (Second Embodiment)

This embodiment exemplifies V, a so-called stack type FeRAM having a configuration in which conductive plugs are formed under the lower electrode and the upper electrode of the ferroelectric capacitor structure, respectively, so as to be conductive.

FIG. 14A to FIG. 18B are schematic cross-sectional views showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof.

First, as shown in FIG. 14A, a MOS transistor 120 that functions as a selection transistor is formed on a silicon semiconductor substrate 110.

Specifically, the element isolation structure 111 is formed on the surface layer of the silicon semiconductor substrate 110 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.

Next, an impurity, here boron (B), is ion-implanted into the element active region, for example, under the conditions of a dose of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV to form the well 112.

Next, a thin gate insulating film 113 having a thickness of about 3. Onm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film and a film having a thickness of about 180 nm are formed on the gate insulating film 113 by a CVD method. For example, a silicon nitride film having a thickness of about 29 nm is deposited, and the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 113 are processed into an electrode shape by lithography and subsequent dry etching, thereby forming a gate on the gate insulating film 113. The electrode 114 is patterned. At the same time, a cap film 115 made of a silicon nitride film is patterned on the gate electrode 114.

[0148] Next, using the cap film 115 as a mask, an impurity, for example, arsenic (As) is ion-implanted into the element active region under the conditions of a dose of 5. OX 10 ¹⁴ Zcm ² and an acceleration energy of lOkeV, and V LDD region 116 is formed.

Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, so that the silicon oxide film is formed only on the side surfaces of the gate electrode 114 and the cap film 115. A sidewall insulating film 117 is formed leaving the film.

[0150] Next, using the cap film 115 and the sidewall insulating film 117 as a mask, an impurity in the element active region, here phosphorus (P), has a higher impurity concentration than the LDD region 116, for example, a dose amount 5. OX Ion implantation under conditions of 10 ¹⁴ Zcm ² and acceleration energy of 13 keV, LD A source Z drain region 118 that overlaps the D region 116 is formed to complete the MOS transistor 120.

Subsequently, as shown in FIG. 14B, the protective film 121, the interlayer insulating film 122, and the upper insulating film 123 of the MOS transistor 120 are sequentially formed.

Specifically, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123 are sequentially formed so as to cover the MOS transistor 120. Here, as the protective film 121, a silicon oxide film is used as a material, and is deposited to a film thickness of about 20 nm by a CVD method. As the interlayer insulating film 122, for example, a stacked structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm), and a plasma TEOS film (film thickness of about lOOOnm) are sequentially formed is formed. After that, polishing is performed by CMP until the film thickness reaches about 700 nm. As the upper insulating film 123, a silicon nitride film is used as a material, and is deposited to a thickness of about lOOnm by a CVD method.

Subsequently, as shown in FIG. 14C, a plug 119 connected to the source Z drain region 118 of the transistor structure 120 is formed. 14C and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 122 is shown, and the illustration of the silicon semiconductor substrate 110, the MOS transistor 120, and the like is omitted.

Specifically, first, using the source Z drain region 118 as an etching stopper, the upper insulating film 223, the interlayer insulating film 122, and the protective film 121 until a part of the surface of the source Z drain region 118 is exposed. Is processed by lithography and subsequent dry etching to form a via hole 119a having a diameter of about 0.3 μm, for example.

Next, for example, a Ti film and a TiN film are sequentially deposited to a film thickness of about 20 nm and a film thickness of about 50 nm by a sputtering method so as to cover the wall surface of the via hole 119a, and a base film (glue film) 119b is formed. Form. Then, for example, a W film is formed by the CVD method so as to fill the via hole 119a through the glue film 119b. Thereafter, the W film and the glue film 119b are polished by CMP using the upper insulating film 123 as a stopper to form a plug 219 that fills the via hole 219a with W via the glue film 219a. For example, plasma annealing with N 2 O is performed after CMP.

2

The

Subsequently, as shown in FIG. 14D, a lower electrode layer 124, a ferroelectric film 125, and an upper electrode layer 126 are sequentially formed. Specifically, first, for example, the film thickness is 150 ηπ! A Pt film is deposited to about 200 nm to form the lower electrode layer 124.

Next, a ferroelectric film 225 made of a ferroelectric material such as PZT is formed on the lower electrode layer 124 by RF sputtering, with a film thickness of 膜厚 ηπ! Deposits to about 300nm. Then, the ferroelectric film 125 is annealed to crystallize the ferroelectric film 125. The conditions for this annealing are ArZO gas with 1.98 liters Z for Ar and 0.025 liters for O.

2. While supplying at a flow rate of 2 Z, for example, run from 550 ° C to 650 ° C for 60 seconds to 120 seconds. The material of the ferroelectric film 125 is Pb La Zr Ti O (0 <x <1, 0 <v <1 l -x l -y y 3 instead of PZT.

), SrBi (Ta Nb) O (0 <x <1), Bi Ti O or the like may be used.

2 x l -x 2 9 4 2 12

Next, the upper electrode layer 126 is deposited on the ferroelectric film 125.

As the upper electrode layer 126, first, for example, an IrO film 126a, which is a conductive oxide, is formed to a thickness of about 200 nm by reactive sputtering. After that, the IrO film 126a is annealed.

twenty two

Make sense. The annealing conditions include ArZO gas with 2.0 liters Z of Ar, O

While 2 2 is supplied at a flow rate of 0.02 liters Z, for example, run at 650 ° C to 850 ° C for 10 seconds to 60 seconds. Then, on the IrO film 126a, it functions as a cap film for the IrO film 126a.

twenty two

A noble metal film, here a Pt film 126b, is formed to a thickness of about lOOnm by sputtering. The upper electrode layer 126 is composed of the IrO film 126a and the Pt film 126b. Upper electrode layer 1

2

26, Ir, Ru, RuO, SrRuO, other conductive acids instead of IrO film 126a

2 2 3

It is good also as a compound and these laminated structures. In addition, the formation of the Pt film 126b can be omitted.

Subsequently, as shown in FIG. 15A, a TiN film 128 and a silicon oxide film 129 are formed.

Specifically, the TiN film 128 is deposited on the upper electrode layer 126 to a thickness of about 200 nm by sputtering or the like. The silicon oxide film 129 is deposited on the TiN film 128 to a thickness of about lOOOnm by, for example, a CVD method using TEOS. Here, an HDP film may be formed instead of the TEOS film. It is also preferable to further form a silicon nitride film on the silicon oxide film 129.

Subsequently, as shown in FIG. 15B, a resist mask 101 is formed.

Specifically, a resist is applied on the silicon oxide film 129, and this resist is integrated with lithography. The resist mask 101 is formed by further processing into an electrode shape.

Subsequently, as shown in FIG. 15C, the silicon oxide film 129 is processed.

Specifically, the silicon oxide film 129 is dry etched using the resist mask 101 as a mask. At this time, the silicon oxide film 129 is patterned following the electrode shape of the resist mask 101, and a hard mask 129a is formed. Further, the thickness of the resist mask 101 is reduced by etching.

Subsequently, as shown in FIG. 15D, the TiN film 128 is cleaned.

Specifically, the TiN film 128 is dry etched using the resist mask 101 and the hard mask 129a as a mask. At this time, the TiN film 128 is patterned following the electrode shape of the hard mask 129a. Further, the resist mask 101 is etched and thinned during the etching. Thereafter, the resist mask 101 is removed by ashing or the like.

Subsequently, as shown in FIG. 16A, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are processed.

Specifically, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are dry-etched using the hard mask 129a and the TiN film 128 as a mask and the upper insulating film 123 as an etch duster. At this time, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are patterned following the electrode shape of the TiN film 128. Further, the hard mask 129a is thinned by being etched during the etching. Thereafter, the hard mask 129a is removed by dry etching (etchback) on the entire surface.

Subsequently, as shown in FIG. 16B, the ferroelectric capacitor structure 130 is completed.

Specifically, the TiN film 128 used as a mask is removed by wet etching. At this time, a ferroelectric film 125 and an upper electrode 132 are sequentially laminated on the lower electrode 131, and the ferroelectric capacitor structure 130 in which the lower electrode 131 and the upper electrode 132 are capacitively coupled through the ferroelectric film 125. To complete. In the ferroelectric capacitor structure 130, the lower electrode 131 is connected to the plug 119, and the source Z drain 118 and the lower electrode 131 are electrically connected via the plug 119.

Subsequently, as shown in FIG. 16C, a hydrogen diffusion preventing film 133 and an interlayer insulating film 134 for preventing the entry of hydrogen into the ferroelectric film 125 are formed. Specifically, first, a metal oxide such as alumina (Al 2 O 3) is used as a material so as to cover the entire surface of the ferroelectric capacitor structure 130, and a film thickness of about 20 nm to 50 nm is formed by sputtering.

twenty three

A hydrogen diffusion prevention film 133 is formed by deposition. Thereafter, the hydrogen diffusion preventing film 133 is annealed.

Next, an interlayer insulating film 134 is formed so as to cover the ferroelectric capacitor structure 130 with the hydrogen diffusion preventing film 133 interposed therebetween. Here, as the interlayer insulating film 134, for example, a silicon oxide film is deposited to a film thickness of about 1500 nm to 2500 nm by a plasma CVD method using TEOS, and then polished by CMP until the film thickness becomes, for example, about lOOOnm. Form. After CMP, for example, N 2 O plasma annealing is performed for the purpose of dehydrating the interlayer insulating film 134.

2

Apply.

Subsequently, as shown in FIG. 17A, a via hole 135a to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.

Specifically, the interlayer insulating film 134 and the hydrogen diffusion preventing film 133 are patterned by lithography and subsequent dry etching, and a via hole 135a exposing a part of the surface of the upper electrode 132 is formed.

Subsequently, as shown in FIG. 17B, a plug 135 connected to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.

Specifically, first, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm so as to cover the wall surface of the via hole 135a, and a base film (glue film) 135b is formed. Form.

[0168] Next, the plug 135 is formed.

In the present embodiment, in combination with the hydrogen diffusion prevention film 133, a hydrogen storage conductive material having a property of absorbing hydrogen is used to reliably prevent the generated hydrogen from entering the ferroelectric film 125. Then, the hydrogen storage conductive material or a conductive material containing the same is deposited on the interlayer insulating film 134 so as to fill the via hole 135a through the glue film 135b. Examples of hydrogen storage materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen absorbing conductive materials such as Nd and Sm may be used alone, or (2) any combination of hydrogen absorbing conductive materials shown in (1). (3) At least one of the hydrogen-absorbing conductive materials shown in (1) and other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni)) At least one of the common conductive metal materials such as iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os) An alloy with at least one kind of precious metal such as the above may be used. Here, Pd is used as the conductive material to be deposited, and the plug 135 is formed by, for example, the CVD method or the PVD method.

Then, using the interlayer insulating film 134 as a stopper by CMP, the deposited Pd and glue film 135b are polished to form a plug 135 that fills the via hole 135a with W via the glue film 135b. For example, even if plasma annealing of N 2 O is performed after CMP

2

good.

[0170] In this embodiment, the present invention is applied to a conductive bragg that is essential for electrical connection with the upper electrode 132, and the plug 135 has a large amount of hydrogen absorption capacity (large surface area and volume). Pd, a hydrogen storage conductive material, is used as a material. Accordingly, it is possible to efficiently prevent hydrogen from entering the ferroelectric film 125 without increasing the number of constituent members and the number of processes, and it is possible to reliably retain the capacitor characteristics.

Subsequently, as shown in FIG. 18A, a first wiring 145 connected to the plug 135 is formed.

Specifically, first, the barrier metal film 142, the wiring film 143, and the barrier metal film 144 are deposited on the entire surface of the interlayer insulating film 134 by sputtering or the like. As the noria metal film 142, for example, a TiN film is formed with a film thickness of about 150 nm by a sputtering method. As the wiring film 143, for example, an A1 alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the noria metal film 144, for example, a TiN film is formed to a thickness of about 150 nm by sputtering. Here, the structure of the wiring film 143 is the same structure as the logic part other than FeRAM of the same rule V, so there is no problem in wiring processing or reliability! /.

Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the noria metal film 144, the wiring film 143, and the barrier metal film are formed by lithography and subsequent dry etching. 142 is processed into a wiring shape, and the first wiring 145 connected to the plug 135 is patterned. Instead of forming the A1 alloy film as the wiring film 143, a Cu film (or Cu alloy film) is formed using a so-called damascene method or the like, and the first wiring is formed. A Cu wiring may be formed as the line 145.

Subsequently, as shown in FIG. 18B, a second wiring 154 connected to the first wiring 145 is formed.

Specifically, first, an interlayer insulating film 146 is formed so as to cover the first wiring 145. As the interlayer insulating film 146, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about lOO nm, and then the surface is polished by CMP. The film thickness is formed to about 750 nm.

[0174] Next, a plug 147 connected to the first wiring 145 is formed.

The interlayer insulating film 146 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 145 is exposed to form a via hole 147a having a diameter of about 0.25 m, for example. Next, after forming a base film (glue film) 148 so as to cover the wall surface of the via hole 147a, a W film is formed by the CVD method so as to fill the via hole 147a via the glue film 148. Then, for example, the W film and the glue film 248 are polished by CMP using the interlayer insulating film 146 as a stopper to form a plug 147 that fills the via hole 247a with W via the glue film 148.

Note that the plug 147 may be formed by performing anisotropic etching on the entire surface of the W film and the glue film 148 or so-called etch back instead of CMP. At this time, only W is etched, and the glue film 148 remains as it is.

Next, second wirings 154 connected to the plugs 147 are formed.

First, a barrier metal film 151, a wiring film 152, and a barrier metal film 153 are deposited on the entire surface by sputtering or the like. As the noria metal film 151, for example, a TiN film is formed with a film thickness of about 150 nm by sputtering.

Here, when the plug 147 is formed by the etch-back method, the glue film 148 remaining when the plug 147 is formed functions as a barrier metal film, and thus the barrier metal film 151 is unnecessary.

[0178] As the wiring film 152, for example, an A1 alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the noria metal film 153, for example, a TiN film is formed to a thickness of about 150 nm by sputtering. Here, the structure of the wiring film 152 is a logic other than FeRAM of the same rule. Since it has the same structure as the hook portion, there is no problem in wiring processing or reliability.

Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the noria metal film 153, the wiring film 152, and the barrier metal film are formed by lithography and subsequent dry etching. 151 is processed into a wiring shape, and the second wiring 154 is formed into a pattern. Instead of forming an A1 alloy film as the wiring film 152, a Cu film (or Cu alloy film) is formed using a so-called damascene method or the like, as in FIGS. 6A to 8B according to the first embodiment. However, a Cu wiring may be formed as the second wiring 154.

[0180] After that, the stack type FeRAM according to the present embodiment is completed through various processes such as the formation of an upper layer wiring after the interlayer insulating film.

[0181] As described above, according to the present embodiment, hydrogen can be reliably prevented from entering the ferroelectric film 125 with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 130 can be maintained. A highly reliable stack-type FeRAM can be realized without increasing the number of components and the number of processes.

[0182] A variation

Hereinafter, a modification of the second embodiment will be described.

[0183] (Variation 1)

In this example, in addition to the configuration of the second embodiment, in the multilayer wiring structure, as the material for at least the wiring film of the first wiring, a hydrogen storage conductive material or a conductive material including the same is used.

FIG. 19A and FIG. 19B are schematic cross-sectional views showing the configuration of the stack type FeRAM according to the first modification of the second embodiment in the order of steps together with the manufacturing method (main steps).

First, similarly to the second embodiment, the respective steps of FIGS. 14A to 17B are performed.

Subsequently, as shown in FIG. 19A, a first wiring 164 is formed.

Specifically, first, a barrier metal film 161, a wiring film 162, and a barrier metal film 163 are deposited on the entire surface of the interlayer insulating film 134 by sputtering or the like. As the noria metal film 161, for example, a Ti film and a TiN film are sequentially stacked to a thickness of about 5 nm and 150 nm, respectively, by a sputtering method or the like.

In this example, in combination with the hydrogen diffusion preventing film 133 and the plug 135, the generated hydrogen is strongly induced. The wiring film 162 is formed using a hydrogen storage conductive material or a conductive material including the hydrogen storage property having a property of absorbing hydrogen to surely prevent entry into the electric conductor film 125. Examples of hydrogen storage materials include (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen-absorbing conductive materials such as Nd and Sm may be used alone, or (2) Even if an alloy of any combination of hydrogen-absorbing conductive materials shown in (1) is used, (3) ( At least one of the hydrogen-absorbing conductive materials shown in 1) and at least 1 of other conductive metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni), etc.) Seed or alloy with iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os) and other alloys You may do it. Here, Pd is used as the conductive material to be deposited, and the wiring film 162 is formed to a thickness of about 350 nm by, for example, the CVD method or the PVD method.

In this example, in addition to the plug 135, the present invention is applied to wiring that is indispensable for electrical connection via the upper electrode 132 and the plug 135, and the wiring film 162 has a large amount of hydrogen absorption capability. Pd, which is a hydrogen storage conductive material having a large surface area and volume, is used as a material. Therefore, it is possible to efficiently prevent hydrogen from entering the ferroelectric film 125 without increasing the number of constituent members and the number of processes, and it is possible to reliably maintain high capacitor characteristics.

[0187] The noria metal film 163 is formed by sequentially laminating, for example, a Ti film and a TiN film in a thickness of about 5 nm and about 150 nm, respectively, by sputtering or the like. Here, the structure of the wiring film 162 is the same as that of the logic part other than the FeRAM of the same rule, so there is no problem in reliability if the wiring is added.

Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the noria metal film 163, the wiring film 162, and the barrier metal film are formed by lithography and subsequent dry etching. 161 is processed into a wiring shape, and the first wiring 164 connected to the plug 135 is patterned.

[0189] In this example, the case where the plug 135 and the first wiring 164 are formed separately is illustrated, but they may be integrally formed. In this case, for example, the via hole 135a is formed simultaneously in FIG. 17A, and then the inner wall surface of the via hole 135a and the interlayer insulating film 134 are covered. A film 161 (only a TiN film having a thickness of about 150 nm) is formed, and a hydrogen storage conductive material or a conductive material containing the same, for example, Pd, is used to fill the via hole 135a and on the interlayer insulating film 134 on the glue film 161. Pd is deposited so as to cover, and a glue film 163 (a laminated structure of a Ti film (film thickness of about 5 nm) and a TiN film (film thickness of about 150 nm)) is deposited on Pd. Then, on the interlayer insulating film 134, the glue films 163, Pd, and the glue film 161 are patterned in a wiring shape. As a result, the via hole 135a is filled with Pd through the glue film 161 and the upper surface is covered with the glue film 163 and extends on the interlayer insulating film 134 (the plug 135 and the first wiring 164 A body formed) is formed.

Subsequently, as shown in FIG. 19B, a second wiring 154 connected to the first wiring 164 is formed.

Specifically, first, an interlayer insulating film 146 is formed so as to cover the first wiring 164. As the interlayer insulating film 146, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about lOO nm, and then the surface is polished by CMP. The film thickness is formed to about 750 nm.

[0191] Next, a plug 147 connected to the first wiring 164 is formed.

The interlayer insulating film 146 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 164 is exposed to form a via hole 147a having a diameter of about 0.25 m, for example. Next, after forming a base film (glue film) 148 so as to cover the wall surface of the via hole 147a, a W film is formed by the CVD method so as to fill the via hole 147a via the glue film 148. Then, for example, the W film and the glue film 248 are polished by CMP using the interlayer insulating film 146 as a stopper to form a plug 147 that fills the via hole 247a with W via the glue film 148.

Note that instead of CMP, the plug 147 may be formed by performing anisotropic etching of the entire surface of the W film and the glue film 148, or a so-called etch back. At this time, only W is etched, and the glue film 148 remains as it is.

Next, second wirings 154 connected to the plugs 147 are formed.

First, a barrier metal film 151, a wiring film 152, and a barrier metal film 153 are deposited on the entire surface by sputtering or the like. As the noria metal film 151, for example, a TiN film is formed by sputtering. The film is formed to a thickness of about 150 nm.

[0195] As the wiring film 152, for example, an A1 alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the noria metal film 153, for example, a TiN film is formed to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 152 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in wiring processing and reliability.

[0196] Next, after forming, for example, a SiON film or an antireflection film (not shown) as the antireflection film, the antireflection film, the noria metal film 153, the wiring film 152, and the barrier metal film are formed by lithography and subsequent dry etching. 151 is processed into a wiring shape, and the second wiring 154 is formed into a pattern.

[0197] Instead of forming the A1 alloy film as the wiring film 152 (and the wiring film in Z or an upper layer wiring thereof), similarly to the wiring film 162, a hydrogen storage conductive material such as Pd or the like is included. It is also preferable to use a conductive material.

[0198] Further, instead of forming an A1 alloy film as the wiring film 152, FIG. 6A according to the first embodiment

~ Similar to Fig. 8B, Cu film (or Cu alloy film) is formed using the so-called damascene method.

Alternatively, a Cu wiring may be formed as the second wiring 154.

[0199] After this, the stack-type FeRAM according to this example is completed through various processes such as formation of an interlayer wiring and further upper layer wiring.

[0200] As described above, according to this example, hydrogen can be more reliably prevented from entering the ferroelectric film 125 with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 130 can be maintained. A highly reliable stack-type FeRAM can be realized without increasing the number of components and processes.

[0201] (Variation 2)

In this example, in addition to the configuration of the first modification, the ferroelectric capacitor structure 130 (upper electrode 1) is used.

A conductive film made of a hydrogen storage conductive material or a conductive material containing this is formed between 32 and the plug 135). FIG. 20A to FIG. 23B are schematic cross-sectional views showing the configuration of the stack type FeRAM according to the second modification of the second embodiment, together with its manufacturing method (main steps), in the order of steps.

First, similarly to the second embodiment, the respective steps of FIGS. 14A to 14D are performed.

Subsequently, as shown in FIG. 20A, a conductive film 171 is formed on the upper electrode layer 126.

[0203] In this example, a hydrogen storage conductive material or a conductive material including the same is deposited on the upper electrode layer 126. The hydrogen-occlusion conductive material is required to be a material that has not only the hydrogen-occlusion property but also excellent heat resistance enough to withstand high-temperature annealing and resistance to halogen-based gas. Specifically, Pd has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, and other noble metals (Ir, Pt) that have heat resistance with Pd (or have conductivity even when oxidized) , Au, Ag, Ru, Rh, Os, etc.) and the like are preferable. Here, Pd is used as the conductive material to be deposited. For example, a film thickness that does not penetrate through the conductive film 171 by over-etching when the via hole 135a described later is formed by CVD or PVD, for example, about lOOnm. To form.

Subsequently, as shown in FIG. 20B, a TiN film 128 and a silicon oxide film 129 are formed.

Specifically, the TiN film 128 is deposited on the conductive film 171 to a thickness of about 200 ηm by sputtering or the like. The silicon oxide film 129 is deposited on the TiN film 128 to a thickness of about lOOOnm by, for example, a CVD method using TEOS. Here, an HDP film may be formed instead of the TEOS film. It is also preferable to further form a silicon nitride film on the silicon oxide film 129.

Subsequently, as shown in FIG. 20C, a resist mask 101 is formed.

Specifically, a resist is applied on the silicon oxide film 129, and this resist is processed into an electrode shape by lithography to form a resist mask 101.

Subsequently, as shown in FIG. 20D, the silicon oxide film 129 is cached.

Subsequently, as shown in FIG. 21A, the TiN film 128 is cached. Specifically, the TiN film 128 is dry etched using the resist mask 101 and the hard mask 129a as a mask. At this time, the TiN film 128 is patterned following the electrode shape of the hard mask 129a. Further, the resist mask 101 is etched and thinned during the etching. Thereafter, the resist mask 101 is removed by ashing or the like.

Subsequently, as shown in FIG. 21B, the upper electrode layer 126, the ferroelectric film 125, the lower electrode layer 124, and the conductive film 171 are processed.

Specifically, the hard mask 129a and the TiN film 128 are used as a mask, the upper insulating film 123 is used as an etch duster, and the conductive film 171, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are dried. Etch. At this time, the conductive film 171, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are patterned following the electrode shape of the TiN film 128. Further, the hard mask 129a is etched and thinned during the etching. Thereafter, the hard mask 129a is removed by dry etching (etchback) on the entire surface.

Subsequently, as shown in FIG. 21C, a ferroelectric capacitor structure 130 whose upper surface is covered with a conductive film 171 is completed.

Specifically, the TiN film 128 used as a mask is removed by wet etching. At this time, a ferroelectric film 125 and an upper electrode 132 are sequentially laminated on the lower electrode 131, and the ferroelectric capacitor structure 130 in which the lower electrode 131 and the upper electrode 132 are capacitively coupled through the ferroelectric film 125. To complete. The upper surface of the ferroelectric capacitor structure 130 is covered with a conductive film 171. In this ferroelectric capacitor structure 130, the lower electrode 131 is connected to the plug 119, and the source Z drain 118 and the lower electrode 131 are electrically connected via the plug 119.

Subsequently, as shown in FIG. 21D, a hydrogen diffusion preventing film 133 and an interlayer insulating film 134 for preventing intrusion of hydrogen 'water into the ferroelectric film 125 are formed.

Specifically, first, a metal oxide such as alumina (Al 2 O 3) is used as a material to cover the entire surface of the ferroelectric capacitor structure 130 having the conductive film 171 formed on the upper surface.

twenty three

More film thickness 20ηπ! A hydrogen diffusion preventing film 133 is formed by depositing to about 50 nm. Thereafter, the hydrogen diffusion preventing film 133 is annealed. [0212] Next, an interlayer insulating film 134 is formed so as to cover the ferroelectric capacitor structure 130 and the conductive film 171 with the hydrogen diffusion preventing film 133 interposed therebetween. Here, as the interlayer insulating film 134, a silicon oxide film is deposited to a thickness of about 1500 nm to 2500 nm by, for example, a plasma CVD method using TEOS, and then polished by CMP to a thickness of about 1 OOOnm. Form. After CMP, for the purpose of dehydrating the interlayer insulating film 134, for example, a plasma plasma of NO is used.

2

Neal treatment is applied.

[0213] Subsequently, as shown in FIG. 22A, a via hole 135a to the conductive film 171 is formed.

[0214] Here, it has been confirmed that the presence of a hydrogen diffusion preventing film on the upper electrode significantly increases the overetching of the upper electrode during the formation of the via hole. In this respect, the hydrogen storage conductive material such as Pd is not only due to the hydrogen absorption function as described above, but also because it is difficult to react with the halogen-based etching gas used when etching the via hole. When formed, it has a function that the etching rate is low and etching is difficult.

[0215] In this example, by providing the conductive film 171 made of Pd on the upper electrode 132, the hydrogen absorption capability is improved and the penetration of hydrogen into the ferroelectric film 125 can be prevented more reliably, and the via can be prevented. When forming the hole 135a, even if a hydrogen diffusion preventing film 133 is formed to cover the upper electrode 132 to further protect the ferroelectric film 125 from hydrogen, the retention failure is not caused without over-etching the upper electrode 132. Can be suppressed.

Subsequently, as shown in FIG. 22B, a plug 135 electrically connected to the upper electrode 132 of the ferroelectric capacitor structure 130 via the conductive film 171 is formed.

[0217] Next, the plug 135 is formed.

In this embodiment, the hydrogen storage conductive material or a conductive material containing the hydrogen storage conductive material is deposited on the interlayer insulating film 134 so as to fill the via hole 135a via the glue film 135b. hydrogen Occupant conductive materials include: (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd , Sm and other hydrogen-absorbing conductive materials may be used alone, or (2) (3) (3) ( At least one of the hydrogen-absorbing conductive materials shown in 1) and other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni), etc.) At least one kind or alloy with iridium (Ir), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os) or other noble metals May be used. Here, Pd is used as the conductive material to be deposited. For example, the plug 135 is formed by the CVD method or the PVD method.

[0218] Then, the deposited Pd and glue film 135b are polished by CMP using the interlayer insulating film 134 as a stopper, thereby forming a plug 135 filling the via hole 135a with W via the glue film 135b. For example, even if plasma annealing of N 2 O is performed after CMP

2

good.

Subsequently, as shown in FIG. 23A, a first wiring 164 connected to the plug 135 is formed.

[0220] In this example, in combination with the hydrogen diffusion prevention film 133, the conductive film 91, and the plug 135, the property of absorbing hydrogen to prevent the generated hydrogen from entering the ferroelectric film 125 reliably. The wiring film 162 is formed using a hydrogen storage conductive material having or a conductive material including the same. Examples of hydrogen storage conductive materials include: (1) Pd, which has a high hydrogen absorption capacity to absorb 935 times its own volume of hydrogen, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Hydrogen absorbing conductive materials such as Nd and Sm may be used alone, or (2) Even if an alloy of any combination of hydrogen absorbing conductive materials shown in (1) is used, (3) (1 ) And other metals (aluminum (A1), copper (Cu), iron (Fe), nickel (Ni) and other common conductive metal materials), Or there are few precious metals such as iridium (Ir), platinum (Pt), gold (A u), silver (Ag), ruthenium (Ru), rhodium (Rh), osmium (Os). An alloy with both of them may be used. Here, Pd is used as the conductive material to be deposited, and the wiring film 162 is formed to a thickness of about 350 nm by, for example, the CVD method or the PVD method.

In this example, the conductive film 171 is formed on the upper electrode 132 and the plug 135 electrically connected to the upper electrode 132 via the conductive film 171, the upper electrode 132, the conductive film 171, and the plug 135 are formed. The wiring films 162 of the first wirings 164 that are electrically connected via each other are formed using Pd, which is a hydrogen storage conductive material having a large amount of hydrogen absorption capacity (large surface area and volume), as a material. Therefore, it is possible to prevent hydrogen from entering the strong dielectric film 125 without increasing the number of components and the number of processes as efficiently as possible, and high capacitor characteristics can be reliably maintained. It becomes.

[0222] As the noria metal film 163, for example, a Ti film and a TiN film are sequentially stacked to a thickness of about 5 nm and 150 nm, respectively, by sputtering or the like. Here, the structure of the wiring film 162 is the same as that of the logic part other than the FeRAM of the same rule, so there is no problem in reliability if the wiring is added.

[0223] Next, after forming, for example, a SiON film or an antireflection film (not shown) as the antireflection film, the antireflection film, the noria metal film 163, the wiring film 162, and the barrier metal film are formed by lithography and subsequent dry etching. 161 is processed into a wiring shape, and the first wiring 164 connected to the plug 135 is patterned.

Subsequently, as shown in FIG. 23B, a second wiring 154 connected to the first wiring 164 is formed.

[0225] Next, a plug 147 connected to the first wiring 164 is formed.

The interlayer insulating film 146 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 164 is exposed to form a via hole 147a having a diameter of about 0.25 m, for example. Next, a base film (glue film) 148 is formed so as to cover the wall surface of the via hole 147a, and then a W film is formed so as to fill the via hole 147a through the glue film 148 by the CVD method. Form. Then, for example, the W film and the glue film 248 are polished by CMP using the interlayer insulating film 146 as a stopper to form a plug 147 that fills the via hole 247a with W via the glue film 148.

Note that instead of CMP, the plug 147 may be formed by performing anisotropic etching on the entire surface of the W film and the glue film 148, or a so-called etch back. At this time, only W is etched, and the glue film 148 remains as it is.

Next, second wirings 154 connected to the plugs 147 are formed.

[0229] As the wiring film 152, for example, an A1 alloy film (here, an Al-Cu film) is formed to a thickness of about 350 nm. As the noria metal film 153, for example, a TiN film is formed to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 152 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in wiring processing and reliability.

Next, after forming, for example, a SiON film or an antireflection film (not shown) as the antireflection film, the antireflection film, the noria metal film 153, the wiring film 152, and the barrier metal film are formed by lithography and subsequent dry etching. 151 is processed into a wiring shape, and the second wiring 154 is formed into a pattern.

[0231] Instead of forming the A1 alloy film as the wiring film 152 (and the wiring film in Z or an upper layer wiring thereof), similarly to the wiring film 162, it contains a hydrogen storage conductive material such as Pd or the like. It is also preferable to use a conductive material.

Further, instead of forming an A1 alloy film as the wiring film 152, FIG. 6A according to the first embodiment is used.

Alternatively, a Cu wiring may be formed as the second wiring 154.

[0233] After applying the force, the interlayer insulating film is subjected to various processes such as the formation of a further upper layer wiring. Complete the tack-type FeRAM.

[0234] As described above, according to this example, hydrogen is prevented from entering the ferroelectric film 125 as much as possible with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 is maintained. At the same time, it is possible to suppress retention failure without over-etching the upper electrode 132. With this configuration, an extremely reliable stack-type FeRAM can be realized without increasing the number of components and processes.

[0235] In the second embodiment, the plug 135, the first wiring 164 in addition to the plug 135 in the first modification, and the plug 135 and the first wiring 164 in the first modification are connected to the conductive film 171. Each of the above-described structures formed from Pd, which is a hydrogen storage conductive material, is disclosed, but the following structures are also included in the scope of the present invention.

[0236] (1) The plug 135 is formed using a conductive material containing hydrogen, such as Pd, which is a hydrogen storage conductive material, and the conductive film 171 is formed using a conductive material including this, such as Pd, which is a hydrogen storage conductive material. The first wiring shall be a normal A1 alloy wiring or the like.

[0237] (2) The first wiring 164 is formed using Pd or the like which is a hydrogen storage conductive material or a conductive material including the same, and the conductive film 171 is Pd or the like which is a hydrogen storage conductive material. Is formed using a conductive material containing this, and each plug electrically connected to the ferroelectric capacitor structure 130 is a normal W plug or the like.

[0238] In the methods (1) and (2), the plug 135, the first wiring 164, and the conductive film 171 are all made of a hydrogen-absorbing conductive material such as Pd. Although it is inferior to the case where it is formed (in the case of Modification 2), it can reliably maintain high capacitor characteristics, achieve high reliability, and realize an FeRAM.

Industrial applicability

[0239] According to the present invention, a highly reliable semiconductor device that reliably prevents hydrogen from entering the capacitor film with a relatively simple configuration and maintains the high performance of the capacitor structure, particularly the ferroelectric capacitor structure. Can be realized without increasing the number of components and the number of processes.

Claims

The scope of the claims

[1] a capacitor structure formed above a semiconductor substrate and having a capacitor film sandwiched between a lower electrode and an upper electrode;

Wiring formed above the capacitor structure;

A conductive plug formed on the capacitor structure and electrically connecting at least the upper electrode and the wiring above the upper electrode;

Including

The semiconductor device is characterized in that the conductive plug includes a first conductive material that absorbs hydrogen.

[2] Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm in the first group, Al, Cu, Fe

, And Ni as the second group, Ir, Pt, Au, Ag, Ru, Rh, and Os as the third group,

The first conductive material is selected from the first group force selected one type, the first group force selected from a combination of a plurality of types, the first group force selected at least one type and the first group force. Group power of 2 Alloy of at least one selected combination, or alloy of at least one selected from the first group and at least one combination selected from the third group power The semiconductor device according to claim 1, characterized in that:

[3] A conductive film is provided between the upper electrode and the conductive plug,

2. The semiconductor device according to claim 1, wherein the conductive film includes a second conductive material that occludes hydrogen.

[4] The second conductive material may be Pd or an alloy of Pd and a combination of at least one selected from Ir, Pt, Au, Ag, Ru, Rh, and Os. The semiconductor device according to 3.

5. The semiconductor device according to claim 1, wherein the wiring is formed to include a third conductive material that absorbs hydrogen.

[6] Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm in the first group, Al, Cu, Fe

The third conductive material is selected from the first group force selected one type, the first group force selected from a combination of a plurality of types, the first group force selected at least one type and the first group force. 2 Group force of an alloy of at least one selected combination, or an alloy of at least one selected from the first group and a combination of at least one selected from the third group force The semiconductor device according to claim 5.

7. The semiconductor device according to claim 1, wherein the conductive plug and the wiring are integrally formed including the first conductive material.

[8] The semiconductor device according to [1], wherein the capacitor film is made of a ferroelectric material having ferroelectric characteristics.

[9] The capacitor structure is a planar type in which another conductive plug is provided on the lower electrode,

2. The semiconductor device according to claim 1, wherein the other conductive plug is formed including the first conductive material together with the conductive plug.

10. The semiconductor device according to claim 1, wherein the capacitor structure is of a stack type in which another conductive plug is provided under the lower electrode.

[11] A capacitor structure formed above a semiconductor substrate and sandwiching a capacitor film between a lower electrode and an upper electrode;

Wiring formed above the capacitor structure;

A conductive plug formed on the capacitor structure and electrically connecting the upper electrode and the wiring thereabove;

Including

The semiconductor device is characterized in that the wiring is formed of a conductive material that occludes hydrogen.

[12] Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm in the first group, Al, Cu, Fe, and Ni in the second group, Ir, Pt , Au, Ag, Ru, Rh, and Os as a third group,

The conductive material is one selected from the first group, an alloy of a plurality of combinations selected from the first group, at least one selected from the first group force and the second group. Or an alloy of at least one combination selected from the above, or an alloy of at least one combination selected from the first group force and the third group force. Item 12. The semiconductor device according to Item 11.

[13] The conductive film is provided between the upper electrode and the conductive plug, and the conductive film is formed to include another conductive material that absorbs hydrogen. 11. The semiconductor device according to 11.

[14] The other conductive material is Pd or an alloy of Pd and a combination of at least one selected from Ir, Pt, Au, Ag, Ru, Rh, and Os. A semiconductor device according to 1.

[15] forming a capacitor structure having a capacitor film sandwiched between a lower electrode and an upper electrode above the semiconductor substrate;

Forming a conductive plug electrically connected to at least the upper electrode on the capacitor structure;

Forming a wiring on the conductive plug to form a wiring electrically connected to the upper electrode through the conductive plug;

Including

The method of manufacturing a semiconductor device, wherein the conductive plug is formed of a material including a first conductive material that occludes hydrogen.

[16] Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm in the first group, Al, Cu, Fe, and Ni in the second group, Ir, Pt , Au, Ag, Ru, Rh, and Os as a third group,

The first conductive material is selected from the first group force selected one type, the first group force selected from a combination of a plurality of types, the first group force selected at least one type and the first group force. Group power of 2 Alloy of at least one selected combination, or alloy of at least one selected from the first group and at least one combination selected from the third group power 16. The method for manufacturing a semiconductor device according to claim 15, wherein:

[17] forming the conductive plug on the upper electrode through a conductive film,

16. The method for manufacturing a semiconductor device according to claim 15, wherein the conductive film is formed of a material including a second conductive material that occludes hydrogen.

[18] The second conductive material may be Pd or an alloy of Pd and a combination of at least one selected from Ir, Pt, Au, Ag, Ru, Rh, and Os. 18. A method for manufacturing a semiconductor device according to 17.

19. The method of manufacturing a semiconductor device according to claim 15, wherein the wiring is formed from a material including a third conductive material that occludes hydrogen.

[20] Pd, Li, Na, Mg, Ca, Ti, Zr, V, Nb, La, Nd, and Sm in the first group, Al, Cu, Fe

The third conductive material is selected from the first group force selected one type, the first group force selected from a combination of a plurality of types, the first group force selected at least one type and the first group force. Group power of 2 Alloy of at least one selected combination, or alloy of at least one selected from the first group and at least one combination selected from the third group power 20. The method for manufacturing a semiconductor device according to claim 19, wherein:

21. The method of manufacturing a semiconductor device according to claim 15, wherein the conductive plug and the wiring are integrally formed using a material including the first conductive material.

[22] The method for manufacturing a semiconductor device according to claim 15, wherein the capacitor film is made of a ferroelectric material having ferroelectric characteristics.

[23] The capacitor structure is a planar type in which another conductive plug is provided on the lower electrode,

16. The method of manufacturing a semiconductor device according to claim 15, wherein the other conductive plug is formed of a material containing the first conductive material simultaneously with the conductive plug.

24. The method of manufacturing a semiconductor device according to claim 15, wherein the capacitor structure is of a stack type in which another conductive plug is provided under the lower electrode.