JPH1187633A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize interconnection metal layer deposition by using CVD method at high efficiency and reliability, while the capacitor degradation is prevented, in a semiconductor device having a capacitor with a perovskite type oxide ferroelectrics layer and an electrode contact hole of a high aspect ratio, in the manufacture of the semiconductor device. SOLUTION: Accordingly to this method, wiring of a semiconductor device comprising such capacitor as having a capacitor dielectric layer 15 of perovskite type oxide ferroelectric is formed. Here, after an electrode contact hole has been formed at an inter-layer insulating layer 17, a hydrogen-block metal layer of hydrogen-storage metal or hydrogen-impermeable metal is formed over the entire surface, a wiring 20 is formed on the hydrogen-block metal layer by applying CVD method, and a vacuum heating process is performed for excluding hydrogen under a condition such that at least the entire surface is covered with the hydrogen-block metal layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to PZT (PbZr).
To manufacture a semiconductor device having a capacitor using a perovskite-type oxide ferroelectric such as TiO ₃ ) or SBT (SrBi ₂ Ta ₂ O ₉ ) and having an electrode contact hole with a high aspect ratio. It relates to a preferred method.

At present, semiconductor devices are still being miniaturized and highly integrated. For example, a capacitor in a memory must be miniaturized, and moreover, in order to exchange highly reliable information, It is necessary to increase the capacity of the capacitor as much as possible.

Attempts have been made to obtain a small and large-capacity capacitor using a ferroelectric material, for example, a perovskite-type oxide ferroelectric material for the capacitor dielectric layer. Since the aspect ratio of the electrode contact hole becomes high and the formation of wiring becomes difficult, the present invention intends to disclose one means for solving the problem.

[0004]

2. Description of the Related Art FIG. 13 is a cutaway side view showing a main part of a semiconductor device having a capacitor using a perovskite oxide ferroelectric layer.

In the figure, 1 is a wiring, 2 is an upper electrode, 3
Is a ferroelectric layer, 4 is a lower electrode, 5 is a Si substrate, 6 to 8
Denotes an SiO ₂ film, and 10 denotes a conductive plug.

The semiconductor device shown in FIG. 13 has a structure having a wiring 1 or a conductive plug 10 directly connected to an upper electrode 2 or a lower electrode 4 in a capacitor. In FIG. 4B, the conductive plug 10 connected to the lower electrode 4 is connected to the Si substrate 5.

Generally, in a capacitor using a perovskite oxide ferroelectric layer such as PZT or SBT, it is known that when a reducing atmosphere such as hydrogen is encountered, oxygen is desorbed from the ferroelectric layer and deteriorated. In addition, CVD (chem
It is also known that hydrogen is generated when a wiring metal layer is deposited by an ionic vapor deposition method.

As described above, in the case of manufacturing a semiconductor device having a capacitor using a perovskite oxide ferroelectric layer, the CVD method cannot be applied to the deposition of the wiring metal layer.

To cope with this problem, there is known a semiconductor device having a structure in which only the upper part of a capacitor is covered with a hydrogen storage metal layer, or a structure using a hydrogen impermeable layer as an interlayer insulating film. No. 5-183106 "," Japanese Unexamined Patent Publication No.
No. 102367, Japanese Patent Application Laid-Open No. 7-27329, and the like. )

However, even if a hydrogen impermeable layer is used as the interlayer insulating film, hydrogen penetrates through the electrode / wiring through the opening while the electrode contact / hole is being formed to form the electrode / wiring. And Japanese Patent Application Laid-Open No. 5-183106.
As shown in the publication, when only the upper part of the capacitor is covered with the hydrogen storage metal layer, the hydrogen penetrates from the side of the capacitor through the interlayer insulating film.
It is difficult to prevent the deterioration of the capacitor due to the deposition of the wiring metal layer using the CVD method.

Therefore, in the formation of wiring in a semiconductor device having a capacitor using a perovskite-type oxide ferroelectric layer, means for generating no reducing atmosphere such as hydrogen, for example, a non-reducing atmosphere such as argon or nitrogen is used. The wiring metal layer is deposited by sputtering in the middle.

However, in recent years, despite the miniaturization of semiconductor devices, the size of perovskite-type oxide ferroelectrics in capacitors has been reduced in spite of the fact that the size of electrode contact holes has become submicron. It is difficult to shrink.

Therefore, the upper electrode and the S
Since the aspect ratio of the electrode contact hole for forming the wiring connecting to the i-substrate is high,
It is difficult to form a wiring filling such an electrode contact hole by a sputtering method.

FIG. 14 is a cutaway side view showing a main part of a semiconductor device having an electrode contact hole having a high aspect ratio. The same symbols as used in FIG. 13 represent the same parts or have the same meanings. Shall be.

In FIG. 1, reference numeral 9 denotes a high aspect ratio electrode contact hole formed on the SiO ₂ layer 7 and exposing the underlying Si substrate 5.

As is apparent from FIG.
Since it takes a long time to fill the hole 9 with the wiring 1, the productivity is reduced, and it is not always possible to completely fill the hole 9, and the reliability may be reduced due to a void.

In a general semiconductor device, even if an electrode contact hole having a high aspect ratio is provided, it is possible to avoid the problem by applying a CVD method and depositing titanium nitride, tungsten, aluminum, or the like. As described above, it is impossible with a semiconductor device having a capacitor using a perovskite oxide ferroelectric layer.

[0018]

An object of the present invention is to provide a semiconductor device having a capacitor using a perovskite oxide ferroelectric layer and a high aspect ratio electrode by making a simple modification to the manufacturing process. A wiring metal layer is deposited with high efficiency and high reliability by using a CVD method in a semiconductor device having a contact hole, and the perovskite oxide ferroelectric layer can be prevented from being deteriorated.

[0019]

According to the present invention, after an electrode contact hole is opened, a hydrogen storage metal layer or a hydrogen impermeable metal layer is first formed, and then a wiring metal layer is formed by applying a CVD method. It is basically to form a film
Hydrogen generated during the formation of the wiring metal layer is cut off by the underlying hydrogen storage metal layer or the hydrogen impermeable metal layer. At this stage, a capacitor using a perovskite oxide ferroelectric layer is used. There is no degradation due to hydrogen.

Usually, since a certain amount of hydrogen is contained in the wiring metal layer formed by the CVD method, it is preferable to discharge hydrogen by heating in a vacuum in a subsequent step. By doing so, hydrogen is not generated in the heat treatment step after the wiring is formed, and deterioration of the capacitor using the perovskite oxide ferroelectric layer can be suppressed.

[0021] Some of the hydrogen storage metals have a property of easily permeating hydrogen at high temperatures. In such a case, hydrogen desorbed from the wiring metal in the vacuum heating step passes through the hydrogen storage metal layer. In this case, the perovskite oxide ferroelectric layer may reach the ferroelectric layer, and the capacitor may be slightly deteriorated. Annealing can be performed in an atmosphere to recover the characteristics of the capacitor.

As described above, in the method of manufacturing a semiconductor device according to the present invention, there are provided: (1) a dielectric layer for a capacitor made of a perovskite oxide ferroelectric (for example, a perovskite oxide ferroelectric In a wiring forming process of a semiconductor device having a capacitor having a capacitor dielectric layer 15) made of a capacitor, an electrode contact hole is formed in an insulating layer (for example, an interlayer insulating layer 17 made of SiO ₂ ), and then hydrogen is formed on the entire surface. Forming a hydrogen blocking metal layer (for example, a hydrogen storing metal layer or a hydrogen impermeable metal layer) made of a storage metal or a hydrogen impermeable metal, and applying a CVD method to the wiring metal layer on the hydrogen blocking metal layer (For example, the wiring 20) and a step of performing a vacuum heat treatment for eliminating hydrogen in a state where the entire surface is covered with at least the metal layer for preventing hydrogen. It is either characterized by comprising, or,

(2) The method according to (1), further comprising a step of processing the hydrogen blocking metal layer into a wiring pattern after performing a vacuum heat treatment for removing hydrogen. Or

(3) In the above (1), after performing a vacuum heat treatment for eliminating hydrogen, a metal layer for preventing hydrogen and a wiring metal layer other than those present in the electrode contact holes are removed. And then forming a wiring metal layer again (for example, wiring metal layer 37: see FIG. 7) and processing it into a wiring pattern.

(4) Perovskite oxide ferroelectric
Dielectric layer for capacitors (eg perovskite type)
Capacitor dielectric layer 15) made of oxide ferroelectric
Forming Process in Semiconductor Device with Capacitor
In the process, an insulating layer (for example, SiO _TwoInterlayer insulation consisting of
Electrode contact hole and electrode contact in layer 17)
.Grooves for wiring embedding connected to holes (for example, wiring embedding
Groove 32B: see FIG. 8) and collect hydrogen over the entire surface.
Storage metal (such as palladium) or hydrogen impermeable metal
Metal layer for preventing hydrogen (for example, aluminum)
Forming hydrogen, and applying the CVD method to prevent hydrogen
Forming a wiring metal layer (for example, wiring 20) on the metal layer
And at least the entire surface is covered with a hydrogen blocking metal layer.
Of performing vacuum heat treatment to eliminate hydrogen in a hot state
And the electrode contact hole and the electrode contact hole.
Other than hydrogen in the trench for wiring
Remove the metal layer and metal layer for prevention
Characterized by comprising the step of forming
Is

(5) In any one of the above (1) to (4), after the wiring metal layer is processed into a wiring pattern and the entire surface is covered with the insulating film, the perovskite oxidation is performed from the surface of the insulating film. Supply hole (for example, oxygen supply hole 21A: FIG. 1) reaching the dielectric layer for a capacitor made of a ferroelectric material.
1 and FIG. 12) and performing a heat treatment in an oxygen atmosphere.

By adopting the above-mentioned means, when the wiring metal layer is formed by the CVD method, the entire surface of the wafer is covered with the hydrogen storage metal layer or the hydrogen impermeable metal layer. Intrusion of hydrogen from the side surface of the capacitor or from the contact hole during the formation of the wiring metal layer is almost completely prevented, and the capacitor is not deteriorated.

Further, since the hydrogen storage metal layer or the hydrogen impermeable metal layer is processed into the same pattern simultaneously with the wiring in the wiring forming step, a unique photolithography step is unnecessary, and This is also advantageous for reducing the device size in the apparatus.

Further, in either the hydrogen storage layer or the hydrogen impermeable layer, conductivity is ensured because it is a metal,
Even if the structure remains as a wiring base, the influence on the wiring contact resistance is small.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional side view showing a main part of a semiconductor device manufactured according to an embodiment of the present invention.

In the figure, 11 is a Si substrate, and 12 is a Si substrate.
An element isolation insulating layer made of O ₂ , an interlayer insulating layer made of SiO ₂ , a lower electrode for a capacitor made of Pt, Ir, IrO, etc., and a dielectric for a capacitor made of a perovskite oxide ferroelectric material Layer 16 is Pt, I
a capacitor upper electrode made of r, IrO or the like; 17 an interlayer insulating layer made of SiO ₂ ; 18 a local wiring layer;
Denotes an interlayer insulating layer made of SiO ₂ , 20 denotes a wiring made of Al, W, Ti, TiN, Cu or the like laminated on a hydrogen blocking metal layer, and 21 denotes an insulating layer made of SiO ₂ .

In the semiconductor device shown in FIG.
8 is slightly pulled out from the region in contact with the lower electrode 14 or the upper electrode 16, and the wiring 2
However, when such a means is employed, the wiring 20 and the capacitor dielectric layer 15 are separated from each other, so that there is an advantage that deterioration of the capacitor dielectric layer 15 is reduced. When the CVD method is used to form the local wiring 18, hydrogen is generated. Therefore, the sputtering method is used. Therefore, it is difficult to fill the deep contact opening. Therefore, the interlayer insulating film 19 must be thin. Must.

For the hydrogen blocking metal layer, either a hydrogen storage metal or a hydrogen impermeable metal is used.
Hydrogen storage metals are palladium, vanadium, niobium, nickel, chromium, magnesium, TiFeLaNi ₅ ,
Ti ₂ Mn ₃ , VNb, TiCo, ZrMn ₂ , Mg ₂
Cu, Mg ₂ Ni, LaCo ₅ , Ti ₂ V ₈ , Ti ₂ C
oFe, Ti ₂ CoMn, etc.
Further, as the hydrogen impermeable metal, for example, Al can be used.

As the wiring metal, aluminum, tungsten, titanium nitride, copper, gold, silver and platinum can be used as usual.

FIG. 2 is a cutaway side view showing a main part of a semiconductor device manufactured according to another embodiment of the present invention. The same reference numerals and symbols as used in FIG. 1 denote the same parts. Or have the same meaning.

The semiconductor device of FIG. 2 differs from the semiconductor device of FIG. 1 in that the lower electrode 14 for a capacitor is connected to the substrate 11 via a conductive plug 22.

FIGS. 3 to 5 are cutaway side views showing a main part of a semiconductor device in a process step for explaining the first embodiment of the present invention. Referring to FIGS. I will explain it. Here, the description will be given mainly of the hydrogen blocking metal layer and its vicinity, and in the target semiconductor device,
The hydrogen blocking metal layer in contact with the upper electrode of the underlying capacitor and the wiring metal layer in contact with the hydrogen blocking metal film are all in the same location, that is, the electrode contact
Contact is made at the hole.

3 (A) 3- (1) By applying the CVD method, the thickness covering the underlayer (for example, including the capacitor upper electrode) 31 is, for example, 100 [nm] to 500 [nm]. The interlayer insulating layer 32 made of SiO ₂ is formed.

3- (2) Etching of the interlayer insulating layer 32 by applying a resist process in the lithography technique and a dry etching method in which an etching gas is a CF ₄ -based or CHF ₃ -based gas. To form electrode contact holes 32A.

Referring to FIG. 3B, a 3- (3) adhesion metal layer 33 made of Ti having a thickness of, for example, 10 nm to 20 nm is formed by applying the sputtering method.

3- (4) Hydrogen comprising palladium is applied so that the thickness at the side wall and bottom of the electrode contact hole 32A is 30 nm to 50 nm or more by applying the sputtering method. A blocking metal layer 34 is formed.

4 (A) 4- (1) An underlying metal layer 35 made of aluminum having a thickness of, for example, about 50 [nm] is formed by applying the sputtering method. The reason for selecting aluminum as the material of the underlying metal layer 35 is that a wiring metal layer made of aluminum is formed by a CVD method in the next step. If the wiring metal layer is, for example, tungsten, , Titanium nitride or the like.

4- (2) A wiring metal layer 36 made of aluminum having a thickness of, for example, 300 nm to 1000 nm is formed by applying the CVD method. The wiring metal layer 36 can be made of a material other than aluminum, for example, titanium nitride, tungsten, or the like.

Referring to FIG. 4B, 4- (3) a resist process in lithography and an etching gas of Cl ₂ , BCl ₃ , HB
The wiring metal layer 36 and the underlying metal layer 35 are processed into a wiring pattern by applying a dry etching method using a gas selected from r or the like.

Referring to FIG. 5, 5- (1) a resist process in the lithography technique and an etching gas of Cl ₂ , BCl ₃ , HB
By applying a dry etching method using a gas selected from r or the like, the hydrogen blocking metal layer 34 and the adhesion metal layer 33 are processed into a wiring pattern.

Here, the patterning of the wiring metal layer 36 and the underlying metal layer 35 and the patterning of the hydrogen blocking metal layer 34 and the adhesion layer 33 are performed in two separate steps. A heat treatment step is interposed therebetween, and the heat treatment step will be described later in detail.

FIGS. 6 and 7 are cutaway side views of a main part of a semiconductor device in a process step for explaining a second embodiment of the present invention. Referring to FIGS. I will explain it. Note that the same symbols as those used in FIGS. 3 to 5 represent the same parts or have the same meanings. Further, in the second embodiment, steps until the wiring metal layer 36 is formed Is the same as in the first embodiment, and will be described from the next stage.

6 (A) 6- (1) Chemical mechanical polishing
By applying an electrical polishing (CMP) method, the wiring metal layer 36 and the underlying metal layer 3 are formed.
Of the 5, those other than those existing in the electrode contact holes are removed. In this case, an etch-back method can be applied in addition to the CMP method.

6 (B) 6- (2) By applying the CMP method, of the hydrogen blocking metal layer 34 and the adhesion layer 33,
Remove anything not in the hall.

Here, the wiring metal layer 36 and the underlying metal layer 3
5. The reason for removing the hydrogen blocking metal layer 34 and the adhesion layer 33 in two steps is the same as in the first embodiment.

7 (A) 7- (1) The thickness A is, for example, 300 [nm] to 1000 [nm] by applying the sputtering method.
Wiring metal layer 3 made of 1, Ti, TiN, Cu, W, etc.
7 is formed.

Refer to FIG. 7B. 7- (2) Resist process in lithography technology and etching gas of Cl ₂ , BCl ₃ , HB
The wiring metal layer 37 is processed into a wiring pattern by applying a dry etching method using a gas selected from r or the like.

FIGS. 8 to 10 are cutaway side views of a main part of a semiconductor device in a process step for explaining a third embodiment of the present invention. Referring to FIGS. I will explain it. It is to be noted that the same symbols as those used in FIGS. 3 to 7 represent the same parts or have the same meaning, and the third embodiment described here is directed to the formation of wiring by the damascene method. ing.

8 (A) 8- (1) By applying the CVD method, the thickness covering the base (for example, including the upper electrode for the capacitor) 31 is, for example, 400 [nm] to 1500 [nm]. About SiO
_An interlayer insulating layer 32 of 2 is formed.

8- (2) Etching of the interlayer insulating layer 32 by applying a resist process in the lithography technique and a dry etching method in which an etching gas is a CF ₄ or CHF ₃ gas. To form electrode contact holes 32A.

8- (3) The resist process in the lithography technique and the dry etching method in which the etching gas is a CF ₄ -based or CHF ₃ -based gas is applied, so that the interlayer insulating layer 32 is formed again. Etching is performed to form a wiring embedding groove 32B continuous with the electrode contact hole 32A.

Referring to FIG. 8B, an adhesion layer 33 made of titanium having a thickness of, for example, 10 [nm] to 20 [nm] is formed by applying the sputtering method 8- (3).

8- (4) Hydrogen comprising palladium is applied so that the thickness at the side wall and bottom of the electrode contact hole 32A is 30 [nm] to 50 [nm] or more by applying the sputtering method. A blocking metal layer 34 is formed.

9 (A) 9- (1) An underlying metal layer 35 made of aluminum having a thickness of, for example, about 50 [nm] is formed by applying the sputtering method.

9- (2) A wiring metal layer 36 made of aluminum having a thickness of, for example, 300 [nm] to 1000 [nm] is formed by applying the CVD method. The wiring metal layer 36 can be made of a material other than aluminum, for example, titanium nitride, tungsten, or the like.

9 (B) 9- (3) By applying the CMP method, of the wiring metal layer 36 and the underlying metal layer 35,
Except for those existing in the holes and in the trenches for embedding the wiring, those are removed. In this case, as in the second embodiment, the CMP
In addition to the method, an etch-back method can be applied.

FIG. 10 10- (1) By applying the CMP method, the electrode contact / contact of the hydrogen blocking metal layer 34 and the adhesion layer 33 is formed.
Except for those existing in the holes and in the trenches for embedding the wiring, those are removed.

The reason why the CMP is performed twice is the same as in the first and second embodiments.

In any of the above embodiments, the CVD
At the stage of forming the wiring metal layer by applying the method, it is clear that the entire surface of the wafer is covered with a hydrogen blocking metal layer made of a hydrogen storage metal or a hydrogen impermeable metal. Is a significant improvement in suppressing deterioration of a capacitor having a capacitor dielectric layer made of a perovskite oxide ferroelectric.

Since hydrogen is taken into the wiring metal layer formed by the CVD method, removing the hydrogen is extremely useful for suppressing the deterioration of the capacitor. For this purpose, heating is effective. However, from the viewpoint of productivity, the timing of performing the heating is as shown in FIG. 4A or FIG. 9A. Efficiency is improved when the hydrogen blocking metal layer and the wiring metal layer formed by the CVD method cover the entire surface.

However, from the viewpoint of effectively suppressing the deterioration of the capacitor, FIGS. 4B, 6A and 9
As shown in (B), the entire surface is covered with a hydrogen blocking metal layer, but it is better to carry out the process in a state where the wiring metal layer formed by the CVD method is processed into a wiring pattern and has a small volume. Good results are obtained.

This is because if the volume of the hydrogen blocking metal is larger than the volume of the wiring metal, the amount of hydrogen permeating the hydrogen blocking metal layer and reaching the capacitor can be reduced.

The heating for eliminating hydrogen in the wiring metal layer is performed by 1
Since it is carried out in a high vacuum of × 10 ^-6 [Torr] or less,
For the exhaust system, it is necessary to use a vacuum pump such as a turbo molecular pump capable of eliminating hydrogen, and the heating temperature is 4
00 [° C]-500 [° C], heating time is 5 [min]-60
The selection is made in the range of [minutes], and this selection depends on the material of the wiring metal, and it goes without saying that the higher the temperature, the shorter the processing time. After the heat treatment, the cover film is formed after completing the wiring.

According to any of the above embodiments, the deterioration of a capacitor having a dielectric layer for a capacitor made of a perovskite oxide ferroelectric substance due to hydrogen can be effectively suppressed. When the volume of the hydrogen-blocking metal layer is smaller than the volume of the metal layer, or when the temperature in the heating step is high, hydrogen passes through the hydrogen-blocking metal layer and the perovskite-type oxide Oxygen in the dielectric is desorbed, which may cause deterioration of the capacitor.

In order to avoid such a problem, it is necessary to suppress the deterioration of the characteristics of the capacitor by supplying oxygen released from the perovskite oxide ferroelectric.

FIG. 11 and FIG. 12 are cutaway side views of a main part showing a semiconductor device in a process step for explaining a fourth embodiment of the present invention. Referring to these figures, FIG. I will explain it. 1 and 2 represent the same parts or have the same meaning.

Since the basic configuration of the semiconductor device to which the fourth embodiment is applied is exactly the same as that of the semiconductor device shown in FIG. 1, the description of the steps from the beginning to the step of forming insulating layer 21 is omitted. The following steps will be described.

Referring to FIG. 11, 11- (1) A wiring 20 including a hydrogen blocking metal layer is formed by a CVD method and a lithography technique.
After forming the insulating film 21 by the method D, a resist process in the lithography technique and a dry etching method using an CF ₄ gas or a CHF ₃ gas as an etching gas are applied. Thus, an oxygen supply hole 21A is formed from the surface of the insulating layer 21 to the capacitor dielectric layer 15 made of a perovskite oxide ferroelectric.

11- (2) In an oxygen atmosphere, heat treatment is performed at a temperature of 450 ° C. to 600 ° C. for a required time.

The heat treatment temperature and the heat treatment time need to be optimized depending on the wiring metal. For example, if the wiring metal is Al, the temperature should be 450 from the viewpoint of reliability. [° C] about 30 minutes
And if the wiring metal is W, the temperature is 65
0 ° C., a shorter heat treatment is required.

12- (1) A cover film 22 is formed on the entire surface including the inside of the oxygen supply hole 21A to cover the exposed capacitor dielectric layer 15.

Incidentally, the cover film 22 is formed of a SiO ₂ film using a tetraethyl oxysilicate (Si (OC ₂ H ₅ ) ₄ : TEOS) -based gas, which generates less hydrogen than a silane-based gas. After that, a hydrogen impermeable layer made of a metal oxide such as aluminum or titanium is formed,
After that, using a silane-based or TEOS-based gas,
It is completed by depositing an N film.

[0078]

According to the method of manufacturing a semiconductor device according to the present invention, in a wiring forming step in a semiconductor device having a capacitor having a dielectric layer for a capacitor made of a perovskite oxide ferroelectric. After forming an electrode contact hole in the insulating layer, a hydrogen blocking metal layer made of a hydrogen storage metal or a hydrogen impermeable metal is formed on the entire surface, and CV
A wiring metal layer is formed on the hydrogen blocking metal layer by applying the method D, and a vacuum heat treatment for removing hydrogen is performed while at least the entire surface is covered with the hydrogen blocking metal layer.

By adopting the above configuration, when the wiring metal layer is formed by the CVD method, the entire surface of the wafer is covered with the hydrogen storage metal layer or the hydrogen impermeable metal layer. Intrusion of hydrogen from the side surface of the capacitor or from the contact hole during the formation of the wiring metal layer is almost completely prevented, and the capacitor is not deteriorated.

Since the hydrogen storage metal layer or the hydrogen impermeable metal layer is processed into the same pattern simultaneously with the wiring in the wiring forming step, a unique photolithography step is unnecessary, and This is also advantageous for reducing the device size in the apparatus.

Further, in any of the hydrogen storage layer and the hydrogen impermeable layer, conductivity is ensured because it is a metal.
Even if the structure remains as a wiring base, the influence on the wiring contact resistance is small.

[Brief description of the drawings]

FIG. 1 is a fragmentary sectional side view showing a semiconductor device manufactured according to an embodiment of the present invention.

FIG. 2 is a fragmentary side view showing a semiconductor device manufactured according to another embodiment of the present invention.

FIG. 3 is a fragmentary sectional side view showing a semiconductor device in a process essential point for explaining the first embodiment of the present invention;

FIG. 4 is a fragmentary side view showing a semiconductor device at a key point in the process for describing Embodiment 1 of the present invention;

FIG. 5 is a fragmentary side view showing a semiconductor device at a key step in the process for describing Embodiment 1 of the present invention;

FIG. 6 is a main part cutaway side view showing a semiconductor device in a process essential point for describing Embodiment 2 of the present invention;

FIG. 7 is an essential part cutaway side view showing a semiconductor device at an important part of a process for describing Embodiment 2 of the present invention;

FIG. 8 is a fragmentary side view showing a semiconductor device at a key step in the process for describing Embodiment 3 of the present invention.

FIG. 9 is a fragmentary side view showing a semiconductor device in a process step for explaining a third embodiment of the present invention;

FIG. 10 is an essential part cutaway side view showing a semiconductor device in a process essential point for describing Embodiment 3 of the present invention;

FIG. 11 is a fragmentary side view showing a semiconductor device at a key step in the process for describing Embodiment 4 of the present invention.

FIG. 12 is a fragmentary side view showing a semiconductor device at a key step for explaining a fourth embodiment of the present invention;

FIG. 13 is a fragmentary side view showing a semiconductor device having a capacitor using a perovskite oxide ferroelectric layer.

FIG. 14 is a fragmentary side view showing a semiconductor device having a high aspect ratio electrode contact hole.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Substrate 12 Element isolation insulating layer 13 Interlayer insulating layer 14 Lower electrode for capacitor 15 Dielectric layer for capacitor 16 Upper electrode for capacitor 17 Interlayer insulating layer 18 Local wiring layer 19 Interlayer insulating layer 20 Wiring 21 Insulating layer 22 Conductive plug

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (5)

[Claims] In a wiring forming process of a semiconductor device having a capacitor having a dielectric layer for a capacitor made of a perovskite oxide ferroelectric, an electrode contact hole is formed in an insulating layer and hydrogen is formed on the entire surface. Forming a hydrogen blocking metal layer made of a storage metal or a hydrogen impermeable metal, forming a wiring metal layer on the hydrogen blocking metal layer by applying a CVD method, Performing a vacuum heat treatment for removing hydrogen in a state where the whole surface is covered. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of processing a hydrogen blocking metal layer into a wiring pattern after performing a vacuum heat treatment for eliminating hydrogen. . 3. After performing a vacuum heat treatment for removing hydrogen, a metal layer for preventing hydrogen and a wiring metal layer other than those existing in the electrode contact holes are removed, and then a wiring metal layer is formed again. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: 4. A semiconductor device having a capacitor having a dielectric layer for a capacitor made of a perovskite-type oxide ferroelectric, in a wiring forming step, an electrode contact hole and an electrode contact hole are formed in the insulating layer.
Forming a wiring-embedding groove connected to the hole and then forming a hydrogen-blocking metal layer made of a hydrogen-storage metal or a hydrogen-impermeable metal on the entire surface; and applying a CVD method to the wiring on the hydrogen-blocking metal layer. A step of forming a metal layer, a step of performing a vacuum heat treatment for eliminating hydrogen in a state where the entire surface is covered with at least the metal layer for preventing hydrogen, and a wiring connected to the electrode contact hole and the electrode contact hole A method for manufacturing a semiconductor device, comprising a step of forming a damascene wiring by removing a hydrogen blocking metal layer, a wiring metal layer, and the like other than those present in an embedding groove. 5. An oxygen supply hole reaching a capacitor dielectric layer made of a perovskite oxide ferroelectric from the surface of the insulating film after the wiring metal layer is processed into a wiring pattern and the entire surface is covered with the insulating film. 5. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming and performing a heat treatment in an oxygen atmosphere.