JP2002043540A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having the ferroelectric capacitor of satisfactory characteristics suppressing deterioration caused by hydrogen reduction. SOLUTION: A first hydrogen barrier film 101, a lower electrode film 30, a ferroelectric film 4, an upper electrode film 50 and a second hydrogen barrier film 102 are successively deposited on a silicon substrate 1 through an insulating film 2, and an upper electrode 5 is patterned by successively etching the hydrogen barrier film 102 and the upper electrode film 50 while using a mask 103. A third hydrogen barrier film 104 is deposited while covering the exposed ferroelectric film 4 and while using a mask formed thereon, and the ferroelectric film 4 and a lower electrode 3 self-matched thereto are patterned by successively etching the ferroelectric film 4 and the lower electrode film 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a ferroelectric capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory (hereinafter, FRAM (registered trademark)) which stores data in a nonvolatile manner by utilizing spontaneous polarization of a ferroelectric capacitor has been known. Since FRAM can be used without a battery and can operate at high speed, a contactless card (RF-I
D: Radio Frequency-Identification) is beginning to be developed, and there are great expectations for replacement with existing SRAMs, DRAMs, flash memories, and the like, and also for logic embedded memories.

[0003] A ferroelectric capacitor typically uses platinum (Pt) films for upper and lower electrodes and a PZT (Pt) film for the ferroelectric film.
(bZr1-xTiOx) film. When an FRAM is formed by an LSI process using a silicon substrate, the surface of the silicon substrate on which transistors and the like are formed is covered with an insulating film such as a silicon oxide film, and a lower Pt electrode, a PZT film, and an upper Pt Pattern the electrodes,
A ferroelectric capacitor is made. Usually, a TiOx film or the like is interposed under the lower Pt electrode to improve adhesion.

[0004]

In the above-mentioned conventional ferroelectric capacitor, the ferroelectric characteristics are deteriorated by a reducing gas such as hydrogen contained in the Si-LSI process, and more specifically, spontaneous polarization. It is known that a reduction in volume occurs. As a countermeasure against the deterioration of the characteristics of the ferroelectric capacitor due to the hydrogen reduction, some protection measures for preventing intrusion of hydrogen or the like into the capacitor portion have been conventionally proposed, but so far, simple and reliable ones have not been developed yet. Absent.

In addition to the characteristic deterioration due to hydrogen reduction, there are many problems to be solved in ferroelectric capacitors, such as characteristic deterioration due to processing damage.

For example, in order to prevent interdiffusion between a ferroelectric capacitor such as PZT and an SiO ₂ insulating film, a method of covering the ferroelectric capacitor with a diffusion preventing film so that they do not come into direct contact with each other is disclosed in Japanese Unexamined Patent Publication No. It is disclosed in JP-A-8-335573. TiO ₂ , Zr
O ₂ and Al ₂ O ₃ are said to be effective. But,
The problem here is the phenomenon of peeling of the capacitor ferroelectric film due to mutual diffusion, and the deterioration of the characteristics of the ferroelectric capacitor due to hydrogen diffusion occurring in the processing process is not considered to be a problem.

On the other hand, according to recent studies by the present inventors,
Strong using the TiOx film as an adhesion layer between the dielectric capacitor and the SiO ₂ insulating film, can result in several disadvantages have become apparent. For example, T is introduced into the PZT film.
It has been clarified that the ferroelectric characteristics deteriorate due to the diffusion of i.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having a ferroelectric capacitor having excellent characteristics and a method of manufacturing the same.

[0009]

The present invention comprises a semiconductor substrate, and a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode sequentially laminated on the semiconductor substrate via an insulating film. The first SrxRuyOz film between the ferroelectric film and the lower electrode,
A second SrxR between the ferroelectric film and the upper electrode;
uyOz films are respectively formed, and the respective thicknesses Tsro (BE) (nm) and Tsro of the first and second SrxRuyOz films are formed.
(TE) (nm) is the thickness Tpzt (nm) of the ferroelectric film.
Where 10 ≦ Tsro (BE) + Tsro (TE) ≦ (2/12)
It is characterized in that it is set in the range of Tpzt.

As described above, Sr is formed on the upper and lower interfaces of the ferroelectric film.
By interposing the xRuyOz film such that its total thickness falls within a certain range in relation to the ferroelectric film thickness, the fatigue characteristics of the ferroelectric capacitor are greatly improved. In particular, it has been experimentally confirmed that setting the total thickness in the range of Tsro ≦ (2/15) Tpzt is more preferable.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIGS. 1 to 5 show a process of manufacturing a ferroelectric capacitor of an FRAM according to a first embodiment. As shown in FIG. 1, after a transistor (not shown) is formed on a silicon substrate 1, its surface is covered with an interlayer insulating film 2 such as a silicon oxide film and flattened. Interlayer insulating film 2
An about 10 nm aluminum oxide film (hereinafter, Al2O3 film) 101 as a hydrogen barrier film also serving as an adhesion layer is deposited thereon by, for example, sputtering, and a lower Pt electrode film 30 of about 100 nm is further deposited thereon by, for example, sputtering. On the lower Pt electrode film 30, a PZT film 4 of about 150 nm
Is deposited by, for example, a sputtering method or a sol-gel method. Thereafter, the PZT film 4 is crystallized by, for example, RTA (Rapid Thermal Anneal) treatment in an oxygen atmosphere at 650 ° C.

In the crystallization process, the Al ₂ O ₃ film 10
1 suppresses diffusion of Pb in the PZT film 4 into the underlying interlayer insulating film 2. This facilitates control of the Pb concentration of the PZT film 4 and prevents deterioration of transistor characteristics due to diffusion of Pb into the interlayer insulating film 2.

On the crystallized PZT film 4, 5
An upper Pt electrode film 50 having a thickness of about 0 nm is deposited by sputtering.
l ₂ O ₃ film 102 is about 10nm is deposited. Al ₂ O ₃ film 10
2, an SiO ₂ film (or SiNx film) 103 as a hard mask material film is formed on the plasma C as shown in FIG.
VD, a resist pattern (not shown) is formed and patterned, and then the upper Pt electrode 5 is formed.
Is patterned. Here, the thickness of the SiO ₂ film 103 is about 1.2 to 4 times the upper Pt electrode 5.

The Al ₂ O ₃ film 102 functions not only as an adhesion layer of the hard mask material film but also to prevent damage to the capacitor material film in the hard mask material film deposition step.

According to an experiment conducted by the present inventors, the hydrogen barrier film underlying the lower Pt electrode film 30 and the hydrogen barrier film on the upper Pt electrode are made of a metal oxide film having a hydrogen diffusion constant of 1E-5 cm 2 / s or less. well, another of the Al ₂ O ₃ film, AlxOy film, a
1N film, WN film, SrRuO3 film, IrOx film, RuO
It is confirmed that the same effect can be obtained by using at least one kind of metal oxide film such as an x film, a ReOx film, an OsOx film, a ZrOx film, and an MgO film, and that the effect can be obtained when the thickness is at least 1 nm or more. ing.

Next, as shown in FIG. 3, the oxide film 103 is removed, and the upper Pt electrode 5 and the exposed PZT film 4 which have been patterned are covered, and Al _{2 serving as a} hydrogen barrier film is again formed.
An O ₃ film 104 is deposited to a thickness of about 10 nm. Thereafter, as shown in FIG. 4, a SiO ₂ film (or SiNx film) 105 is deposited by plasma CVD, and this is patterned as a hard mask covering the upper Pt electrode 5. Again, Al
The SiO ₂ film 10 as a hard mask is used as the SiO ₂ film 104.
In addition to acting as an adhesion layer with the film 5, it functions to prevent damage to the capacitor material film in the film deposition step. In addition to the Al ₂ O ₃ film 104, an AlxOy film, an AlN film, a WN
Film, SrRuO ₃ film, IrOx film, RuOx film, ReOx
At least one kind of metal oxide film such as a film, an OsOx film, a ZrOx film, and a MgOx film can be used. However, it is necessary to have a high resistance here, and preferably as a metal oxide having a specific resistance of 1 kΩcm or more, in addition to Al ₂ O ₃ ,
It is preferable to use at least one of AlxOy, ZrOx, and MgOx films.

Then, using the SiO ₂ film 105 as a mask, the Al ₂ O ₃ film 104, the PZT film 4, and the lower Pt electrode 3
Is patterned to obtain a ferroelectric capacitor C. At this time, the Al ₂ O ₃ film 101 underlying the lower Pt electrode 3 is also patterned. The ferroelectric capacitor C is patterned so as to have a PZT film 4 having a larger area than the upper Pt electrode 5 and a lower Pt electrode 3 as shown in the figure. After this,
While removing or leaving the SiO ₂ film 105, an interlayer insulating film 6 is deposited as shown in FIG. 5, a contact hole is opened, and a terminal wiring 7 is formed. Prior to the deposition of the interlayer insulating film 6, A is again applied so as to cover the entire ferroelectric capacitor C.
An l ₂ O ₃ film may be deposited.

According to this embodiment, a material film containing titanium such as TiOx and TiN is used by using a metal oxide film such as Al ₂ O ₃ containing no titanium as the adhesion layer and the hydrogen barrier film. FRAM with less deterioration in ferroelectric characteristics and transistor characteristics compared to the case
Can be obtained. That is, the diffusion of hydrogen into the capacitor region is effectively blocked by the hydrogen barrier film of the Al ₂ O ₃ film. In addition, the PZT film has almost no contact with the interlayer insulating film, suppresses outward diffusion of Pb, and furthermore, since Ti is not used, excellent characteristics can be obtained without titanium diffusion into the PZT film. Further, providing the Al ₂ O ₃ film 102 has an action of preventing damage when forming the mask material 103 thereon.

In this embodiment, however, three hydrogen barrier films are used so as to extend above and below the ferroelectric capacitor and further extend from the upper electrode to the side surface of the ferroelectric film. The effect is also obtained by using only one or two layers.

[Second Embodiment] FIGS. 6 to 11 show a process of manufacturing a ferroelectric capacitor of an FRAM according to a second embodiment. In this embodiment, the hydrogen barrier film is formed only on the upper surface of the upper electrode of the ferroelectric capacitor. First, as shown in FIG. 6, after a transistor (not shown) is formed on a silicon substrate 1, its surface is covered with an interlayer insulating film 2 such as a silicon oxide film and flattened. A lower Pt electrode film 30 of about 100 nm is deposited on the interlayer insulating film 2 via an adhesion layer containing no titanium, for example, by sputtering. On the lower Pt electrode film 30, a PZT film 4 of about 150 nm is further deposited by, for example, a sputtering method or a sol-gel method. Then PZ
The T film 4 is formed, for example, by RTA in an oxygen atmosphere at 650 ° C.
(Rapid Thermal Anneal) treatment.

An upper Pt electrode film 50 is deposited on the PZT film 4 to a thickness of about 50 nm, and a hydrogen barrier film 202 is further formed thereon.
Is deposited to a thickness of about 10 nm. As the hydrogen barrier film 202, a metal oxide film having a hydrogen diffusion constant of 1E-5 cm ² / s or less is preferable, and typically, an aluminum oxide (Al ₂
O ₃₎ is a film, other AlxOy film, AlN film, WN
Film, SrRuO ₃ film, IrOx film, RuOx film, ReOx
At least one of a film, an OsOx film, a MgOx film, a ZrOx film and the like can be used.

As shown in FIG. 7, a silicon nitride film (SixN) is formed on the hydrogen barrier film 202 as a hard mask material.
y film) 203 (or SixOyNz film) by plasma CV
It is deposited by the D method. In the process of depositing the insulating film, the hydrogen barrier film 202 functions to prevent plasma damage to the underlying layer by the plasma CVD method and to improve the adhesion of the insulating film.

Next, a resist pattern (not shown) is formed on the SixNy film 203, and the SixNy film 203 is etched using the resist pattern. Using the obtained SixNy film 203 as a mask, the Al ₂ O ₃ film 202 and the upper Pt electrode 5 are etched as shown in FIG. Further, as shown in FIG. 8, a hard mask 204 of SiO ₂ or the like is formed in a pattern so as to cover the upper Pt electrode 5, and the PZT film 4 and the lower Pt electrode film 30 are etched using the hard mask 204 to form the PZT film 4. And lower Pt electrode 3
Is larger than the upper Pt electrode 5 to obtain a self-aligned ferroelectric capacitor C. After that, an Al ₂ O ₃ film may be formed on the entire surface (not shown).

Thereafter, as shown in FIG. 9, an interlayer insulating film 6 made of a SiO ₂ film covering the ferroelectric capacitor is deposited. Then, the interlayer insulating film 6 is flattened by the CMP process. At this time, the SixNy film 203 serves as a stopper for the flattening process, and the flattened structure shown in FIG. 10 is obtained.

Thereafter, as shown in FIG. 11, a contact hole is opened, and a terminal wiring 7 connected to the upper Pt electrode 5 is formed.

According to this embodiment, the diffusion of hydrogen into the PZT film is suppressed by the hydrogen barrier film covering the upper Pt electrode, and excellent ferroelectric capacitor characteristics can be obtained.
In the case of this embodiment, the hydrogen barrier film is patterned together with the upper Pt electrode by the SiN film which is a hard mask formed thereon. Then, the hard mask is left as it is, and is used as a stopper for a later flattening process, so that the flattening after the formation of the capacitor is surely performed.
Furthermore, since Ti is not used, excellent characteristics can be obtained without titanium diffusion into the PZT film.

[Third Embodiment] FIGS. 12 to 16 show a process of manufacturing a ferroelectric capacitor of an FRAM according to a third embodiment. In this embodiment, the hydrogen barrier film is formed so as to extend from the upper surface of the ferroelectric capacitor to the side surface, and further to the upper surface of the lower electrode via the side surface of the ferroelectric film. As shown in FIG. 12, after a transistor (not shown) is formed on a silicon substrate 1, its surface is covered with an interlayer insulating film 2 such as a silicon oxide film and flattened. About 100 nm on the interlayer insulating film 2 via the adhesion layer 301 containing no titanium.
Is deposited by sputtering. On the lower Pt electrode film 30, a PZT film 4 of about 150 nm is further deposited by a sputtering method or a sol-gel method. Then PZ
The T film 4 is formed by RTA (Rapid) in an oxygen atmosphere at 650 ° C.
Thermal Anneal) treatment. PZT
An upper Pt electrode film 50 is deposited on the film 4 to a thickness of about 50 nm.

On the upper Pt electrode film 50, an SiO ₂ film 3
02 is deposited by a plasma CVD method, and a pattern is formed using this SiO ₂ film 302 as a hard mask. Then, as shown in FIG. 13, the upper Pt electrode film 5 and the PZT
The film 4 is sequentially etched. This etching process is performed until the surface of the lower Pt electrode film 30 is partially etched.

Then, the SiO ₂ film 30 used as a mask
2 is removed, as shown in FIG.
03 is deposited. This hydrogen barrier film 303 is preferably a film having a hydrogen diffusion constant of 1E-5 cm ² / s or less, typically an aluminum oxide (Al ₂ O ₃ ) film, but other AlxOy film, AlN Film, WN film, SrRu
O ₃ film, IrOx film, RuOx film, ReOx film, OsOx
At least one of a film, an MgOx film, a ZrOx film and the like can be used. However, the hydrogen barrier film of this embodiment needs to have a high resistance, and from this point, it is preferable to use AlxOy, a metal oxide film having a specific resistance of 1 kΩ-cm or more.
At least one of a ZrOx film and a MgOx film can be used.

Thereafter, as shown in FIG. 15, a hard mask of the SiO ₂ film 304 covering the capacitor region is patterned again, and the hydrogen barrier film 30 is formed using this mask.
3. The ferroelectric capacitor C is formed by etching the lower Pt electrode film 3 and the adhesion layer 301. Then, the mask is removed, and as shown in FIG. 16, an interlayer insulating film 6 is deposited, a contact hole is opened, and a terminal wiring 7 is formed.

According to this embodiment, the upper Pt electrode 5
And the PZT film 4 are formed in a self-aligned pattern, and the lower Pt electrode 3 is formed with a larger area. Then, from the upper surface of the upper Pt electrode 5, the upper Pt electrode 5
Hydrogen barrier film 30 extending to the side surface of the PZT film, which is patterned in a self-aligned manner, and to the surface of the lower Pt electrode.
3 is formed. Thereby, PTZ in the subsequent process
Hydrogen diffusion to the lower electrode interface of the film 4 is suppressed, and excellent ferroelectric characteristics are obtained. Further, the PZT film does not contact the interlayer insulating film, so that the diffusion of Pb is prevented. Furthermore, since no Ti adhesion layer is used, there is no Ti diffusion into the PZT film, and excellent characteristics can be obtained.

[Fourth Embodiment] FIGS. 17 to 20 show a process of manufacturing a ferroelectric capacitor of an FRAM according to a fourth embodiment. In this embodiment, a hydrogen barrier film is provided inside the interlayer insulating film covering the ferroelectric capacitor so as to surround the ferroelectric capacitor. As shown in FIG. 17, after forming a transistor (not shown) on the silicon substrate 1,
The surface is covered with an interlayer insulating film 2 such as a silicon oxide film and flattened. On this interlayer insulating film 2 via an adhesion layer 401,
A ferroelectric capacitor C including the lower Pt electrode 3, the PZT film 4, and the upper Pt electrode 5 is formed.

More specifically, a lower Pt electrode film 3 of about 100 nm is deposited by sputtering, and a PZT film 4 of about 150 nm is deposited thereon by sputtering or sol-gel method. RTA (Rapid Therm
al Anneal). On the PZT film 4, an upper Pt electrode film 5 is deposited to a thickness of about 50 nm. Then, these laminated films are sequentially etched to form a ferroelectric capacitor C. At this time, although not shown, the first
Etching the upper Pt electrode film 5 using the mask material of
Further, the PZT film 4 and the lower Pt electrode film 3 are etched by using a second mask material having an area larger than the first mask material.

As shown in FIG. 18, a thin interlayer insulating film 6a is deposited over the ferroelectric capacitor C thus patterned. A hydrogen barrier film 402 is deposited on the interlayer insulating film 6a as shown in FIG. 19, and an interlayer insulating film 6b is further deposited. That is, the hydrogen barrier film 402
To form interlayer insulating films 6a and 6b. In the case of this embodiment, the thickness of the interlayer insulating film 6a is
0.2 of thickness of the electrode 5, the PZT film 4, the lower Pt electrode 3, etc.
The hydrogen barrier film 402 can be deposited with good coverage by making the thickness more than twice to less than twice or making the thickness of the ferroelectric capacitor C more than 0.05 to three times. Finally, as shown in FIG. 20, a contact hole is opened, and a terminal wiring 7 connected to the upper Pt electrode 5 is formed.

Also in this embodiment, the hydrogen barrier film 402 has a hydrogen diffusion constant of 1E-5 cm ² / s.
The following films are preferable, and a metal oxide film having a specific resistance of 1 kΩ-cm or more is preferable, and is typically an aluminum oxide (Al ₂ O ₃ ) film. As described above, by inserting the hydrogen barrier film into the interlayer insulating film, performance degradation of the ferroelectric capacitor is prevented. The hydrogen barrier film in the interlayer insulating film suppresses damage to the ferroelectric capacitor in the step of finally depositing a passivation film (usually a SiN film) covering the upper surface of the device. Further, the portion of the interlayer insulating film 6a functions to prevent a reaction due to direct contact between the hydrogen barrier film and the ferroelectric capacitor C. Furthermore, PZT
Pb diffusion prevention effect of film, P by not using Ti
The effect of preventing Ti diffusion into the ZT film can be obtained. Also, Al
_{Since the 2} O ₃ film is an insulating film, it can be entirely covered in the interlayer insulating film without patterning, and short-circuiting of the contact with the diffusion layer does not occur. Further, by forming a hydrogen barrier film with an interlayer insulating film interposed therebetween,
Stress relaxation of the hydrogen barrier film is achieved.

In this embodiment, in addition to Al ₂ O ₃ , AlxOy, TiOx, ZrOx, Mg
At least one of Ox, MgTiOx and the like is effective.

[Fifth Embodiment] FIG. 21 shows a structure obtained according to the fourth embodiment, further including interlayer insulating films 6c and 6d.
When the passivation film 8 made of a SiN film is formed, the hydrogen barrier film 4 is interposed between the interlayer insulating films 6c and 6d.
03 is interposed. By interposing a multi-layered hydrogen barrier film in the interlayer insulating film in this way, a further effect of preventing hydrogen diffusion can be expected. In addition, it has been confirmed that this structure effectively reduces damage caused by deposition of a passivation film made of SiN.

FIG. 22 shows a structure in which the wiring 7 is formed by flattening the interlayer insulating film 6b based on the structure of FIG. FIG. 23 further shows the interlayer insulating film 6a in FIG.
Is flattened to form a hydrogen barrier film 402 on the flat surface.

[Embodiment 6] FIG. 24 shows Embodiment 4 of the present invention.
Is an embodiment in which the structure obtained by the above is modified. That is, in this embodiment, the bottom of the hydrogen barrier film 402 inserted between the interlayer insulating films 6a and 6b is lower than the bottom of the lower Pt electrode 3 of the ferroelectric capacitor C by Δt. . With such a structure, the diffusion path of the hydrogen gas supplied to the region of the ferroelectric capacitor C through the interlayer insulating film below the hydrogen barrier film 402 can be narrowed, and more effective hydrogen can be obtained. Diffusion is prevented. Needless to say, the same effect as in the fifth embodiment can be obtained.

FIG. 25 shows a structure in which the hydrogen barrier film 402 is patterned in a certain range covering the region of the ferroelectric capacitor C based on the structure of FIG. By arranging the hydrogen barrier film 402 around the capacitor below the bottom of the lower Pt electrode 3, the effect of preventing hydrogen diffusion is increased. Even if the hydrogen barrier film 402 is provided, a sufficient effect of preventing hydrogen diffusion can be expected. In FIG. 25, the interlayer insulating film 6b is flattened.

FIG. 26 shows a structure in which the hydrogen barrier film 402 is patterned in a certain range covering the region of the ferroelectric capacitor C based on the structure of FIG.

FIGS. 27 to 29 show an embodiment in which the structure obtained in the fourth embodiment is modified. That is, in this embodiment, the hydrogen barrier film 402 is replaced with the interlayer insulating film 6b.
As a stopper film at the time of flattening in the CMP process. As shown in FIG. 18, after depositing the interlayer insulating film 6a, a hydrogen barrier film 402 is deposited on the interlayer insulating film 6a as shown in FIG. 27, and further, an interlayer insulating film 6b is deposited. In this embodiment, the interlayer insulating film is deposited such that the thickness of the interlayer insulating film is about 0.15 times the thickness of the ferroelectric capacitor C. Then, as shown in FIG.
In the process, the interlayer insulating film 6b is planarized using the hydrogen barrier film 402 as a stopper film. Further, as shown in FIG. 29, an interlayer insulating film 6c is formed on the interlayer insulating film 6b. Finally, a contact hole is opened, and a terminal wiring 7 connected to the upper Pt electrode 5 is formed.

In this embodiment, the hydrogen barrier film 4
Reference numeral 02 denotes a film having a hydrogen diffusion constant of 1E-5 cm ² / S or less, and is typically an aluminum oxide film (Al ₂ O ₃ ) film. In addition, AlxOy film, TiOx film, MgOx
The effect is obtained by using a film, a ZrOx film, or a combination thereof, or a composite metal oxide containing one or more of the above elements.

According to this embodiment, an interlayer insulating film between capacitor C and terminal wiring 7 can be formed to a desired thickness. In addition, by inserting the hydrogen barrier film into the interlayer insulating film, performance degradation of the ferroelectric capacitor is prevented. Needless to say, the same effect as in the fourth embodiment can be obtained.

This embodiment is similar to the embodiment shown in FIGS.
It is also possible to use the embodiment shown in FIG. That is, the interlayer insulating film 6b is planarized by using the hydrogen barrier film 402 of FIGS. 22 and 25 as a stopper film, and the interlayer insulating film 6c is formed thereon, so that the capacitor C and the terminal wiring 7 are formed.
Is formed to a desired thickness. Further, it is needless to say that this embodiment can be used when the interlayer insulating film 6 of FIG. 16 is formed to a desired film thickness. The hydrogen barrier film 303 in FIG. 16 is used as a stopper. Further, it is also possible to use in combination with other embodiments.

Here, when the hydrogen barrier film 402 is insufficient as a stopper film, SixNy (or SixNyOz) is formed on the 402 hydrogen barrier film as shown in FIG.
A method of forming the stopper film 402b of about 100 ° is also conceivable. In this case, as shown in FIG.
The interlayer insulating film 6b is planarized using the stopper film 402b. Further, as shown in FIG. 32, an interlayer insulating film 6c is formed on the interlayer insulating film 6b. Finally, a contact hole is opened, and a terminal wiring 7 connected to the upper Pt electrode 5 is formed. The stopper SixNy (or SixNyOz) film on this hydrogen barrier film is shown in FIGS.
Can be used in the same manner.

[Seventh Embodiment] FIGS. 33 to 36 show a process of manufacturing a ferroelectric capacitor of an FRAM according to a seventh embodiment. As shown in FIG. 33, after a transistor (not shown) is formed on a silicon substrate 1, its surface is covered with an interlayer insulating film 2 such as a silicon oxide film and flattened. A groove 701 is formed in the ferroelectric capacitor forming region on interlayer insulating film 2.
To process. Then, as shown in FIG. 34, a hydrogen barrier film 702 is deposited to a thickness of about 20 nm, subsequently, a lower Pt electrode film 30 is deposited to about 100 nm, and a PZT film 4 is deposited to about 150 nm. Thereafter, the PZT film 4 is crystallized by RTA (Rapid Thermal Anneal) treatment in an oxygen atmosphere at 650 ° C.

Subsequently, as shown in FIG. 35, a CMP process is performed to remove the hydrogen barrier film 702 outside the trench 701 and to planarize the PZT film 4 so that the PZT film 4 is buried only in the trench 701. I do. Then, as shown in FIG. 36, a hydrogen barrier film 703 is deposited on the PZT film 4, an upper electrode opening is formed in the hydrogen barrier film 703, and an upper Pt electrode 5 is patterned. The hydrogen barrier film 703 is patterned together with the upper Pt electrode 5. Thus, the ferroelectric capacitor C is obtained.

Thereafter, although not shown, an interlayer insulating film is deposited, and a contact hole is opened to form a terminal wiring.

In this embodiment, the hydrogen barrier film 7
02,703, the diffusion constant of hydrogen is 1E-5 cm
² / s or less, preferably having a specific resistance of 1 kΩ-c
A metal oxide film having a thickness of m or more is preferable, and is typically an aluminum oxide (Al ₂ O ₃ ) film. In the case of this embodiment, as the hydrogen barrier films 702 and 703, in addition to Al ₂ O ₃ ,
SrRuO ₃ , ZrOx, RuOx, SrOx, MgOx, or the like is used. However, since the upper hydrogen barrier film 703 short-circuits the upper and lower electrodes, it is preferable to use as high a resistance film as possible.

According to this embodiment, in particular, hydrogen diffusion to the lower Pt electrode 3 is effectively suppressed, and excellent ferroelectric capacitor characteristics can be obtained. Furthermore, T on the PZT film
There is no i-diffusion and there is no outward diffusion of Pb in the PZT film, and excellent characteristics can be obtained. Further, the hydrogen barrier film 702, the lower electrode 4, and the PZT film 4 can be formed in the trench 701 in a self-aligned manner. Further, the hydrogen barrier film 702, the lower electrode film 30, and the PZT film 4 are formed by CMP
Processed by processing. Therefore, the hydrogen barrier film 70
No step is formed on the side surfaces of the second and lower electrodes 30 and the like, and a highly reliable ferroelectric capacitor can be obtained.

[Eighth Embodiment] FIG. 37 shows an embodiment obtained by modifying the structure of the seventh embodiment. In this embodiment, after the hydrogen barrier film 702 is formed on the bottom surface and the side surface of the groove 701 formed in the interlayer insulating film 2, the lower Pt electrode 3, the PZT film 4, and the upper Pt electrode 5 are sequentially buried in the groove 701. . Then, a region of the capacitor C is further covered with a hydrogen barrier film 707 and an interlayer insulating film 6 is deposited. Then, a contact hole is opened to form a terminal wiring 7.

According to this embodiment, diffusion of hydrogen into the PZT film is more effectively suppressed, and excellent ferroelectric capacitor characteristics can be obtained. Further, there is no diffusion of Ti into the PZT film, and there is no outward diffusion of Pb in the PZT film, so that excellent characteristics can be obtained. Further, the entire ferroelectric capacitor is
Formed in a self-aligned manner.

[Embodiment 9] FIG. 38 shows Embodiment 8 of the present invention.
And the groove 701 is extended to the upper hydrogen barrier layer 703.
This is an embodiment in which the information is embedded in a file. According to these embodiments, the entire ferroelectric capacitor is covered with the hydrogen barrier film, and the influence on hydrogen diffusion can be reduced more effectively. Furthermore, there is no diffusion of Ti into the PZT film, no outward diffusion of Pb in the PZT film, excellent characteristics are obtained, and the effect that the entire ferroelectric capacitor is formed in the groove 701 in a self-aligned manner is obtained. Can be

[Embodiment 10] FIGS. 39 to 41 and FIGS. 42 to 43 show an embodiment in which a hydrogen barrier film is formed under a lower Pt electrode. 1 also shows a capacitor manufacturing process of an FRAM in which a hydrogen barrier film is formed. As shown in FIG. 39, after an interlayer insulating film 2 is formed on a silicon substrate 1 on which a transistor is formed, a lower Pt electrode film 30, a PZT film 4, and an upper electrode film 50 are formed thereon via a hydrogen barrier film 801. Are sequentially deposited. Performing a crystallization heat treatment on the PZT film 4 is the same as in the previous embodiments. The hydrogen barrier film 801 has a hydrogen diffusion constant of 1E-5c.
A metal oxide film of m ² / s or less is preferable, and is typically an aluminum oxide (Al ₂ O ₃ ) film. In the case of this embodiment, the hydrogen barrier film 801 is made of S ₂ in addition to Al ₂ O _3.
At least one of rRuO ₃ , ZrOx, RuOx, SrOx, MgOx and the like is used.

Thereafter, as shown in FIG. 40, the upper Pt electrode 5 is patterned. Thereafter, as shown in FIG. 41, an SiO ₂ film 802 is deposited and a resist pattern 80 is formed.
3 is formed by patterning so as to cover the upper Pt electrode 5. The SiO ₂ film 80 thus patterned is formed.
2 is used as a mask, dry etching such as RIE is performed on the PZT film 4, the lower Pt electrode film 30 and the hydrogen barrier film 801 to form the PZT film 4 and the lower Pt electrode 3 on the upper Pt electrode 3.
The pattern processing is performed with an area larger than the electrode 5. Thus, a ferroelectric capacitor C is obtained as shown in FIG.

In the above-described dry etching process of the PZT film 4, the lower Pt electrode film 3, and the hydrogen barrier film 801, the PZT film 4
A condition is used in which the T film 4 and the lower Pt electrode film 30 are etched so as to have nearly vertical side walls, specifically, a steeply inclined surface of 75 ° or more. When such etching conditions are used, a redeposited film 804 is formed on the side surfaces of the processed PZT film 4 and the lower Pt electrode 3, as shown in FIG.
The redeposited film 804 includes, in addition to the material of the hydrogen barrier film 801, an etched material such as a PZT film 4, a Pt film, and a SiO ₂ film. Is shown.

Thereafter, as shown in FIG. 43, an interlayer insulating film 6 is deposited, and a contact hole is opened to form a terminal wiring 7.

According to this embodiment, a protective film having a hydrogen barrier effect can be automatically formed on the side surface of the ferroelectric capacitor C. Diffusion of Ti into PZT film, PZT
There is no outward diffusion of Pb in the film, and excellent characteristics can be obtained. Further, the PZT film 4 and the lower electrode 3 are processed with a large area in a state where the upper electrode 5 is covered with the insulating film, so that a short circuit between the upper and lower electrodes is reliably prevented.

[Eleventh Embodiment] FIG. 44 shows a ferroelectric capacitor structure of an FRAM according to an eleventh embodiment.
In a conventional ferroelectric capacitor having a Pt / PZT / Pt structure, deterioration of ferroelectric characteristics due to a hydrogen reduction effect or the like is recognized through a multilayer wiring process. In particular,
The spontaneous polarization switch from 1E5 to 1E8 times greatly reduces the amount of spontaneous polarization. In this embodiment, as shown in FIG. 44, an SrxRuyOz film between the upper and lower electrodes 5, 3 and the PZT film 4 (including the case where the composition ratio x, y is zero, hereinafter simply referred to as an SRO film). By interposing 901 and 902 and setting the thickness in a predetermined range in relation to the thickness of the PZT film 4, the fatigue characteristics are improved.

In a specific manufacturing process, the lower Pt electrode 3 and the SRO film 901 are deposited on the interlayer insulating film 2 by sputtering, and crystallization annealing is performed. Next, a PZT film 4 is deposited by thick sputtering under the conditions of a gas pressure of 2 to 4.5 Pa, followed by depositing an SRO film 902, and crystallization annealing is performed at this stage. Further, the upper Pt electrode 5 is deposited by sputtering, and crystallization annealing is performed again.

Thereafter, a silicon oxide film serving as a cap material is deposited, and the upper Pt electrode is patterned by lithography and RIE. Subsequently, the PZT film and the lower Pt electrode are patterned by another lithography process and RIE process. At this stage, recovery annealing at 650 ° C. is performed. Thereafter, although not shown, an interlayer insulating film is deposited, a contact hole for the upper Pt electrode is opened, and
A recovery annealing at 50 ° C. is performed to form a wiring.

In the actual process, the thickness Tpzt of the PZT film 4
(Nm), the thickness Tsro (BE) of each of the SRO films 901 and 902
(Nm), Tsro (TE) (nm), crystallization temperature of PZT film 4
Various test samples using degree (° C) etc. as parameters
It made and evaluated the characteristic. Table 1 below shows the test
Sample conditions and evaluation results are shown. In each sample
Is Tsro (BE) = Tsro (TE), which is simply
Shown as sro. However, sample No. 12 is the lower
Example in which an SRO film was provided only on the pole side, 13 is any
This is also an example in which no SRO film is provided. The evaluation result is spontaneous polarization.
QSW (μC / cm ^Two) And comprehensive evaluation (○ is good, △ is
And good, x is bad).In addition, regarding the leak characteristics, when a DC 5 V is applied,
Leakage current is 10-4 A / cm^TwoMore than bad
In addition to the leak characteristics, the spontaneous polarization characteristics
Judgment was made including the sex squareness ratio.

From the above results, FIG. 45 shows the quality of the characteristics based on the data of the main test samples in relation to the thickness Tpzt of the PZT film and the thickness Tsro of the SRO film. Sample No. As is clear from FIG. 7, when the thickness Tsro of the SRO film is 5 nm, and thus the total thickness of the upper and lower SRO films is less than 10 nm, good results cannot be obtained. In the range between the dashed line A in FIG. 45 and the diagonal line separated by the minimum value 5 nm of the SRO film thickness Tsro that can be formed by the current technology, almost satisfactory results can be obtained. The range of this oblique line is approximately 10 ≦ Tsro (BE) + Tsro (RE) ≦ (3/20) Tpzt
-2. Schematically, this range is 10 ≦ Tsro
(BE) + Tsro (TE) ≦ (2/12) Tpzt Particularly preferred is a range below the solid line B, which is roughly
10 ≦ Tsro (BE) + Tsro (TE) ≦ (2/15) Tpzt.

Regarding the crystallization temperature, the sample No. of 750 ° C. In No. 3, the leak is large, which indicates that the crystallization annealing is excessive.

FIG. 46 shows the test sample No. described above. 4
3 shows spontaneous polarization (solid line) after performing a fatigue test (3E10 times of a 5 V AC stress with a pulse width of 20 μS) together with an initial state (broken line).
FIG. 47 shows the relationship between the number of fatigue tests and the magnitude of the amount of spontaneous polarization. From FIG. 46, it can be seen that the initial state is about 20 μm.
C / cm ² , whereas after fatigue was 30 μC / cm ² , which indicates that the characteristics were improved as compared with the initial state.

That is, as shown in FIG.
When a ferroelectric capacitor having a PZT / SRO / Pt structure is formed, the PZT film and S
By selecting the thickness of the RO film, a ferroelectric capacitor with improved fatigue characteristics can be obtained. That is, it is possible to obtain a ferroelectric capacitor having improved characteristics as the number of times of rewriting increases.

[Embodiment 12] In a FRAM having a ferroelectric capacitor using a PZT film, there is a problem of deterioration of characteristics due to a damage of a capacitor processing process. Normally, against this processing damage, after forming the capacitor,
Before forming the metal wiring, damage recovery processing is performed by a high-temperature heat treatment in an oxygen atmosphere. After forming the metal wiring, high-temperature heat treatment cannot be performed. However, this damage recovery process has not been sufficiently studied so far, and the recovery is often incomplete. If the damage recovery is incomplete, the resistance to damage in subsequent processes is also reduced, resulting in a decrease in the electrical characteristics, reliability and yield of the final FRAM.

In this embodiment, the recovery of the damage is ensured by improving the contact structure of the ferroelectric capacitor.

FIG. 48 shows an FRAM according to this embodiment.
The structure of is shown. On the silicon substrate 1, a transistor Q forming a memory cell together with a ferroelectric capacitor C is formed. The transistor Q includes a gate electrode 12 formed on the silicon substrate 1 with a gate insulating film 11 interposed therebetween, and an n-type diffusion layer 13 formed so as to be self-aligned with the gate electrode 12. The substrate on which the transistor Q is formed is covered with the interlayer insulating film 2 and planarized. A contact plug 14 for n-type diffusion layer 13 is embedded in interlayer insulating film 2.

The lower Pt electrode 3, PZ
A ferroelectric capacitor C including the T film 4 and the upper electrode 5 is formed. An interlayer insulating film 6 is further formed on the substrate on which the ferroelectric capacitor C is formed, and a first layer connecting the upper electrode 5 of the capacitor C and the n-type diffusion layer 13 of the transistor Q is formed on the interlayer insulating film 6. The metal wiring 7 is formed.

In this embodiment, the contact 21 of the metal wiring 7 with respect to the ferroelectric capacitor C is such that the contact area Y with respect to the upper electrode area X is Y / X ≧
0.5 is set.
Normally, the size of the contact is fixed according to the design rule, and the contact 22 for the n-type diffusion layer 13 of the metal wiring 7 and the contact 21 for the ferroelectric capacitor C are generally the same size. On the other hand, in this embodiment, the contact 21 for the capacitor C is set larger than the contact 22 for the diffusion layer 13. Then, the size of the contact 21 with respect to the capacitor C becomes effective in the damage recovery processing before forming the metal wiring.

FIGS. 49 to 51 show a manufacturing process focusing on the capacitor C in this embodiment. A Ti film as an adhesion layer is deposited on the interlayer insulating film 2 to a thickness of about 20 nm by sputtering, and a lower Pt electrode film 30 of about 150 nm is deposited thereon by sputtering. On the lower Pt electrode film 30, a PZT film 4 of about 200 nm is further deposited by a sputtering method or a sol-gel method. Thereafter, the PZT film 4 becomes 650
RTA (Rapid Thermal Annea
l) Crystallize by treatment. On the PZT film 4, an upper electrode film 50 is deposited. The upper electrode film 50 is a Pt film of about 175 nm or SrRuOx (1 nm) / Pt (17
5 nm).

The upper electrode film 50 is etched using a mask material (not shown), and the PZT film 4 and the lower Pt electrode film 3 are further etched using a mask material covering the patterned upper electrode 5.
The 0 and Ti films are etched. In this state, 65
A heat treatment for recovering damage is performed in an oxygen atmosphere at 0 ° C.

Further, an interlayer insulating film 6 is deposited, and a contact hole 21 is opened. At this time, as described above, the contact 21 to the ferroelectric capacitor C has its upper electrode area X
Is set so that the contact area Y with respect to the condition of Y / X satisfies Y / X ≧ 0.5. In this state, a heat treatment for recovering damage is performed again in an oxygen atmosphere at 650 ° C. afterwards,
A wiring is formed by a Ti / Al film.

FIGS. 52 and 53 show the results of measuring the relationship between the size of the contact area of the upper electrode and the amount of polarization when a Pt film and an SRO / Pt film are used as the upper electrode, respectively. The solid line in each figure is the polarization amount when the upper electrode contact hole is opened, and the dashed line is the polarization amount after recovery annealing is performed and wiring is formed in that state. Conventional general upper contact area ratio is
At this time, in FIG. 52, the polarization amount after the wiring is formed is smaller than the polarization amount after the contact hole is formed in FIG.
When the upper electrode contact area ratio is 0.5 or more, the polarization amount after the recovery annealing is performed and the wiring is formed is significantly larger than the polarization amount after the contact hole is formed.
A similar tendency is observed in FIG.

As is apparent from these figures, when the upper electrode contact area ratio is 0.5 or more, remarkable recovery characteristics are exhibited.

[Embodiment 13] FIG. 54 shows an embodiment of an FRAM having a COP structure, in which a fine ferroelectric capacitor self-aligned is formed by one lithography process. 55 to 61
The manufacturing process will be specifically described with reference to FIG.

First, an STI (Shallo) is formed on the silicon substrate 1.
An element isolation insulating film 31 is formed by (w Trench Isolation). The element isolation insulating film 31 may be formed by a LOCOS method. Then, after ion implantation for threshold adjustment is performed on the silicon substrate, a gate oxide film 11 is formed, and a gate electrode 12 having a stacked structure of n-type polycrystalline silicon and a silicide film such as WSi is formed. The gate electrode 12 is patterned as a word line by lithography. A self-aligned silicide (salicide) process can be used for forming the gate electrode. A protective film 32 is formed around the gate electrode 12 by thermal oxidation. A deposited film may be used as the protective film 32. Thereafter, ion implantation is performed to form n-type diffusion layers 13 in the source and drain regions.
Is formed (FIG. 55).

Next, after depositing and planarizing the first interlayer insulating film 2, a contact hole for the n-type diffusion layer 13 is opened (FIG. 56), and a contact plug 16 is buried in the contact hole (FIG. 57). . This contact plug 14
Is buried by depositing a conductive material such as tungsten by sputtering or vapor phase epitaxy, and flattening this by CMP. The contact plug 14 may be embedded by a selective growth method of tungsten or the like.

Thereafter, a lower Pt electrode film 30, a PZT film 4, and an upper Pt electrode film 50 for forming a capacitor are sequentially deposited on the interlayer insulating film 2 in which the contact plugs 14 are embedded. After the PZT film 4 is deposited, crystallization annealing is performed at 650 ° C. to 700 ° C. It is preferable that an SRO film is interposed between the lower Pt electrode 30 and the upper Pt electrode 50 and the PZT film 4 as described in the eleventh embodiment.

After the formation of the above laminated film, a hard mask material 33 such as a silicon oxide film or a silicon nitride film is deposited, and a resist pattern 35 is formed thereon (FIG. 5).
8). Then, after patterning the hard mask material 33 by anisotropic etching and removing the resist pattern by ashing, the upper electrode material film 50 is etched to pattern the upper electrode 5 (FIG. 59).

Next, the hard mask material 34 is deposited again (FIG. 60). The hard mask material 34 is preferably made of the same material as the hard mask material 33 described above, but may be formed of a different material film. The thickness of the hard mask material 34 is PZ
The thickness is approximately equal to or less than twice the thickness of the T film 4. This is because the line of electric force passing from the end of the upper electrode 5 to the lower electrode extends outward by about the thickness of the PZT film 4, so that a corresponding side wall thickness is required. In addition, it is preferable to secure a sufficient thickness of the side wall in order to reduce the process damage. However, it is optimal to set the thickness to this level in consideration of miniaturization.

Then, the hard mask material 34 is etched back by anisotropic dry etching to leave a protective film only on the first hard mask 33 and the side wall of the upper electrode 5 (FIG. 61). Thereafter, the PZT film 4 and the lower Pt electrode film 30 are patterned by anisotropic etching using the hard masks 33 and 34 as masks (FIG. 54). As a result, the PZT film 4 and the lower Pt electrode 3 are
A ferroelectric capacitor C having a structure having a more constant area spread, that is, a fringe structure is obtained.

Also in this embodiment, it is preferable in terms of reliability to provide a hydrogen barrier film as described in the first embodiment and thereafter.

As described above, according to this embodiment, 1
A ferroelectric capacitor in which the ferroelectric film has a fringe with respect to the upper electrode in the lithography step is obtained. With such a fringe, the ferroelectric capacitor can be protected from damage in a later process. In addition, since the lower electrode extends outside the upper electrode, it is possible to prevent a situation in which the deposited film (fence) generated on the side surface of the PZT film contacts the upper electrode when the lower electrode is etched. Further, the lines of electric force between the end of the upper electrode and the lower electrode pass through the ferroelectric film, so that an action equivalent to the case where the upper electrode has a large area can be obtained.

In the above embodiment, except for the COP structure described with reference to FIG. 54, the upper electrode serves as an individual terminal of each ferroelectric capacitor. Therefore, it is necessary to connect the lower electrode to the plate in common by a plurality of memory cells. Although the description is omitted, for example, the plate may be formed by continuously patterning the lower electrode in a direction orthogonal to the element cross section in each drawing. In the case of the embodiment of FIG. 54, a plate for connecting the upper electrodes is provided.

In the embodiments described above, the PZT film is used as the ferroelectric film. However, another layered oxide ferroelectric having a perovskite crystal structure, for example, PLZT
((Pb, La) (Zr, Ti) O ₃ ) or SBT (S
The present invention can be similarly applied to the case where rBi ₂ Ta ₂ O ₉ ) is used.

The eleventh embodiment is also effective when another metal electrode such as Ir is used instead of the Pt electrode.
Other embodiments are also effective when using an Ir electrode, an electrode such as a metal oxide IrOx, RuOx, SrRuOX, or a composite electrode thereof in addition to the Pt electrode.

[0091]

As described above, according to the present invention, it is possible to obtain a semiconductor device having a ferroelectric capacitor having excellent characteristics by suppressing the characteristic deterioration of the ferroelectric capacitor due to the hydrogen reduction effect generated in the processing process. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a ferroelectric capacitor of an FRAM according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the first embodiment of the present invention.

FIG. 3 is a view showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 5 is a view showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 6 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the second embodiment of the present invention.

FIG. 9 is a view showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 10 is a view showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 11 is a view showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 12 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the third embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the third embodiment of the present invention.

FIG. 14 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the third embodiment of the present invention.

FIG. 15 is a view showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 16 is a diagram showing a manufacturing process of the ferroelectric capacitor according to the embodiment.

FIG. 17 is a diagram illustrating a manufacturing process of the ferroelectric capacitor of the FRAM according to the fourth embodiment of the present invention;

FIG. 18 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the fourth embodiment of the present invention.

FIG. 19 is a view showing a manufacturing step of the ferroelectric capacitor according to the embodiment.

FIG. 20 is a view showing a manufacturing step of the ferroelectric capacitor according to the embodiment.

FIG. 21 is a diagram showing a structure of a ferroelectric capacitor of an FRAM according to a fifth embodiment of the present invention.

FIG. 22 is a diagram showing a structure obtained by modifying the structure of the embodiment.

FIG. 23 is a view showing a structure obtained by modifying the structure of the embodiment shown in FIG. 22;

FIG. 24 is a diagram showing a structure of a ferroelectric capacitor of an FRAM according to a sixth embodiment of the present invention.

FIG. 25 is a diagram showing a structure obtained by modifying the structure of the embodiment.

FIG. 26 is a diagram showing a structure obtained by modifying the structure of the embodiment shown in FIG. 21;

FIG. 27 is a diagram illustrating a manufacturing process of the ferroelectric capacitor of the FRAM according to the fourth embodiment of the present invention;

FIG. 28 is a diagram showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the fourth embodiment of the present invention.

FIG. 29 is a diagram illustrating a manufacturing process of the ferroelectric capacitor of the FRAM according to the fourth embodiment of the present invention;

FIG. 30 is an FRA according to a modification of the fourth embodiment of the present invention.
It is a figure showing the manufacturing process of M ferroelectric capacitors.

FIG. 31 is a FRA according to a modification of the fourth embodiment of the present invention.
It is a figure showing the manufacturing process of M ferroelectric capacitors.

FIG. 32 is an FRA according to a modification of the fourth embodiment of the present invention.
It is a figure showing the manufacturing process of M ferroelectric capacitors.

FIG. 33 is a view showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the seventh embodiment of the present invention;

FIG. 34 is a view showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the seventh embodiment of the present invention;

FIG. 35 is a view illustrating a manufacturing process of the ferroelectric capacitor of the FRAM according to the seventh embodiment of the present invention;

FIG. 36 is a view illustrating a process of manufacturing the ferroelectric capacitor of the FRAM according to the seventh embodiment of the present invention;

FIG. 37 shows a structure of a ferroelectric capacitor of an FRAM according to an eighth embodiment of the present invention.

FIG. 38 is a diagram showing a structure of a ferroelectric capacitor of an FRAM according to a ninth embodiment of the present invention.

FIG. 39 shows a process of manufacturing a ferroelectric capacitor of an FRAM according to Embodiment 10 of the present invention;

FIG. 40 is a view showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the tenth embodiment of the present invention;

FIG. 41 is a view showing a manufacturing process of the ferroelectric capacitor of the FRAM according to the tenth embodiment of the present invention;

FIG. 42 is a view showing a manufacturing step of the ferroelectric capacitor according to the embodiment.

FIG. 43 is a view showing a manufacturing step of the ferroelectric capacitor according to the embodiment.

FIG. 44 shows a structure of a ferroelectric capacitor of an FRAM according to an eleventh embodiment of the present invention.

FIG. 45 is a diagram showing a relationship between a film thickness and a characteristic of a test sample in the embodiment.

FIG. 46 is a diagram showing initial characteristics and fatigue characteristics of a non-defective test sample.

FIG. 47 is a view showing the fatigue characteristics of non-defective samples.

FIG. 48 is a diagram showing a ferroelectric capacitor structure of an FRAM according to a twelfth embodiment of the present invention.

FIG. 49 is a view showing a manufacturing process of the capacitor in the embodiment.

FIG. 50 is a view showing a manufacturing process of the capacitor in the embodiment.

FIG. 51 is a view showing a manufacturing process of the capacitor in the embodiment.

FIG. 52 is a diagram showing an upper electrode contact area ratio and recovery characteristics of a sample ferroelectric capacitor in the same embodiment.

FIG. 53 is a diagram showing an upper electrode contact area ratio and a recovery characteristic of a sample ferroelectric capacitor in the same embodiment.

FIG. 54 is a diagram showing a structure of an FRAM according to a thirteenth embodiment of the present invention.

FIG. 55 is a view showing a manufacturing process of the FRAM of the embodiment.

FIG. 56 is a view showing the manufacturing process of the FRAM of the embodiment.

FIG. 57 is a view showing a manufacturing process of the FRAM of the embodiment.

FIG. 58 is a view showing a manufacturing process of the FRAM according to the embodiment.

FIG. 59 is a view illustrating a manufacturing process of the FRAM according to the embodiment.

FIG. 60 is a view showing a manufacturing process of the FRAM of the embodiment.

FIG. 61 is a view showing a manufacturing process of the FRAM according to the embodiment;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Interlayer insulating film, 30 ... Lower Pt electrode film, 3 ... Lower Pt electrode, 4 ... PZT film, 50 ... Upper P
t electrode film, 5: upper Pt electrode, 6: interlayer insulating film, 7: wiring, 101, 102, 104, 202, 303, 40
2,403,702,703,801 ... hydrogen barrier film,
901, 902: SRO film, 34: sidewall protective film, C: ferroelectric capacitor, Q: transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toyota Morimoto 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Osamu Hidaka Osamu 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Toshiba Yokohama Office (72) Inventor Iwao Kunishima 8 at Shinsugitacho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Go Iwamoto 33, Shinisogocho, Isogo-ku, Yokohama, Kanagawa Prefecture F-term in Toshiba Production Technology Laboratory (reference) 5F083 FR01 FR02 GA21 GA25 JA15 JA17 JA38 JA39 JA43 MA06 MA17 NA01 NA08 PR34 PR39 PR40

Claims (1)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; and a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode sequentially laminated on the semiconductor substrate via an insulating film, A first SrxR between the body film and the lower electrode;
a second SrxRuyOz film is formed between the ferroelectric film and the upper electrode, and a thickness Tsro (BE) (n) of the first and second SrxRuyOz films.
m) and Tsro (TE) (nm) are 10 ≦ Tsro (BE) + Tsro (TE) with respect to the thickness Tpzt (nm) of the ferroelectric film.
≦ (2/12) Tpzt The semiconductor device is set in a range.