JP2005050899A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce the aspect ratio of a plug and which can improve the characteristics and reliability. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 100 having a transistor; a first capacitor provided above the semiconductor substrate and having first lower electrodes 111, 112, 113, first upper electrodes 115, 116, and a first dielectric film 114 provided between the first upper electrode and the first lower electrode; wiring 124 connected to the first upper electrode; and a first plug 123 for electrically connecting the wiring to one of the source and drain 101 of the transistor. The upper surface of the first upper electrode and the lower surface of the wiring exist substantially in the same plane. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor.
[0002]
[Prior art]
In recent years, a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) using a ferroelectric film as a dielectric film of a capacitor has been developed.
[0003]
FIG. 10 is a cross-sectional view schematically showing an example of a ferroelectric memory according to the prior art. As shown in FIG. 10, conventionally, an upper electrode 201 of a capacitor and a source or drain 202 of a transistor are connected by a plug 203, a wiring 204, a plug 205, and a plug 206.
[0004]
However, since the plug 203 connected to the upper electrode 201 of the capacitor is provided, it is necessary to increase the height of the plug 205 in accordance with the height of the plug 203, and there is a problem that the aspect ratio of the plug 205 is increased. It was. When the aspect ratio becomes high, it becomes difficult to reliably embed the plug 205 in the hole formed in the insulating film such as the interlayer insulating film 207, leading to deterioration of characteristics and reliability such as contact failure.
[0005]
As a known technique, Patent Document 1 describes a configuration in which wiring is directly formed on an upper electrode of a ferroelectric capacitor. However, this wiring is a plate line and is not connected to the source or drain of the transistor. Therefore, the wiring described in Patent Document 1 is basically different from that connected to the source or drain of the transistor through the plug.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-178155
[Problems to be solved by the invention]
Thus, conventionally, there has been a problem that the aspect ratio of the plug connected to the source or drain of the transistor is increased, and the characteristics and reliability are deteriorated such as contact failure.
[0008]
The present invention has been made to solve the above-described conventional problems, and an object thereof is to provide a semiconductor device capable of reducing the aspect ratio of a plug and improving the characteristics and reliability.
[0009]
[Means for Solving the Problems]
A semiconductor device according to an aspect of the present invention includes a semiconductor substrate provided with a transistor, a first lower electrode, a first upper electrode, and the first upper electrode, which are provided above the semiconductor substrate. A first capacitor including a first dielectric film provided between the first lower electrode, a wiring connected to the first upper electrode,
A first plug that electrically connects the wiring and one of a source and a drain of the transistor, and the upper surface of the first upper electrode and the lower surface of the wiring exist in substantially the same plane. It is characterized by doing.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0011]
FIG. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device (ferroelectric memory) according to an embodiment of the present invention. In this semiconductor device, both ends of a capacitor (C) are connected between the source and drain of a cell transistor (T), which are used as unit cells, and a plurality of unit cells are connected in series. It is a dielectric memory. Hereinafter, the configuration of the semiconductor device will be described with reference to FIG.
[0012]
An STI (shallow trench isolation) type element isolation region (not shown) is formed on the surface region of the p-type silicon substrate (semiconductor substrate) 100, and an MIS transistor is formed on the silicon substrate 100. . This MIS transistor is formed of a gate insulating film 102, a gate electrode to be a word line (polycide structure comprising a polycrystalline silicon film 104 and a tungsten silicide film (WSi _x film) 105), a gate cap film 106, and a silicon nitride film. The gate sidewall film 103 and the source / drain diffusion layer 101 are formed.
[0013]
The MIS transistor is covered with an interlayer insulating film 107, and an n ⁺ polycrystalline silicon plug 108 connected to one of the source / drain diffusion layers 101 is formed in a contact hole formed in the interlayer insulating film 107. ing. Further, an interlayer insulating film 109 is formed on the interlayer insulating film 107, and the contact hole formed in the interlayer insulating film 107 and the interlayer insulating film 109 is connected to the other of the source / drain diffusion layers 101. An n ⁺ polycrystalline silicon plug 110 is formed. Note that a barrier metal film (not shown) having a laminated structure of TiN / Ti, for example, is formed on the n ⁺ polycrystalline silicon plug 110.
[0014]
On the interlayer insulating film 109, a ferroelectric capacitor including a lower electrode, an upper electrode, and a ferroelectric film (dielectric film) is formed. A laminated structure of an iridium film (Ir film) 111, a titanium film (Ti film) 112, and an SRO film (SrRuO ₃ film) 113 is used for the lower electrode. For the ferroelectric film 114 formed on the lower electrode, a PZT film (Pb (Zr _x Ti _1-x ) O ₃ film) is used. The upper electrode formed on the ferroelectric film 114 uses a laminated structure of an SRO film 115 and a platinum film (Pt film) 116.
[0015]
An insulating region is formed outside the capacitor by a diffusion barrier film 119, a CVD oxide film 120, a diffusion barrier film 121, and an interlayer insulating film 122. The diffusion barrier films 119 and 121 have a barrier property against hydrogen. For example, the barrier property against hydrogen is higher than that of a silicon oxide film used for an interlayer insulating film. Note that the diffusion barrier films 119 and 121 preferably have a barrier property against oxygen. In this embodiment, Al ₂ O ₃ film (alumina film) is used as the diffusion barrier films 119 and 121. The CVD oxide film 120 is used as a hard mask for processing the upper electrode.
[0016]
A via plug 123 extending in a direction perpendicular to the main surface of the silicon substrate 100 is formed between adjacent capacitors, and the via plug 123 is connected to the polycrystalline silicon plug 108. The via plug 123 is formed by embedding an Al film in a via hole that penetrates the interlayer insulating film 109, the diffusion barrier film 121, and the interlayer insulating film 122. Note that a barrier metal film (not shown) made of, for example, Ta, TaN, or a laminated structure thereof is formed on the bottom and side surfaces of the via silicon plug 123.
[0017]
A wiring (Al wiring) 124 is directly connected to the Pt film 116 constituting the upper electrode, and the wiring 124 and one of the source / drain diffusion layers 101 are connected by a via plug 123 and a polycrystalline silicon plug 108. . Further, the upper electrodes of the capacitors adjacent to each other with the via plug 123 interposed therebetween are connected by the wiring 124. Thus, the entire wiring 124 extends in a direction parallel to the main surface of the silicon substrate 100, and the upper surface of the Pt film 116 and the lower surface of the wiring 124 exist in substantially the same plane. Further, the boundary between the wiring 124 and the via plug 123 also exists substantially in the plane.
[0018]
The wiring 124 is covered with a diffusion barrier film 125. Similar to the diffusion barrier films 119 and 121, this diffusion barrier film 125 has a barrier property against hydrogen (preferably also has a barrier property against oxygen), and is an Al ₂ O ₃ film (alumina film). Is formed. Further, an interlayer insulating film 126 is formed on the diffusion barrier film 125.
[0019]
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.
[0020]
First, as shown in FIG. 2, a groove is formed on the surface of the silicon substrate 100, and a silicon oxide film is buried in the groove to form an STI type element isolation region (not shown). Subsequently, a MIS transistor for performing a switching operation is formed as follows. First, a silicon oxide film (gate insulating film 102) having a thickness of about 6 nm is formed on the entire surface by thermal oxidation. Subsequently, an n ⁺ polycrystalline silicon film 104 doped with arsenic, a WSi _x film 105, and a silicon nitride film 106 (gate cap film) are sequentially formed. Thereafter, the polycrystalline silicon film 104, the WSi _x film 105, and the silicon nitride film 106 are processed by a normal photolithography method and an RIE method to form a gate electrode. Further, a silicon nitride film is deposited, and this silicon nitride film is processed by RIE to form a gate sidewall film 103 on the sidewall of the gate electrode. Although detailed description is omitted, in this step, the source / drain diffusion layer 101 is also formed by ion implantation or the like.
[0021]
Next, a CVD oxide film is deposited as an interlayer insulating film 107 on the entire surface, and the CVD oxide film is planarized by a CMP (Chemical Mechanical Polishing) method. Subsequently, a contact hole reaching one of the source / drain diffusion layers 101 is formed in the interlayer insulating film 107. Thereafter, a thin titanium film (not shown) is deposited by sputtering or CVD, and a TiN film (not shown) is formed by performing heat treatment in a forming gas. Subsequently, the n ⁺ polycrystalline silicon film is deposited on the entire surface by the CVD method, to further remove n ⁺ polycrystalline silicon film outside the contact holes by CMP. As a result, a plug 108 in which an n ⁺ polycrystalline silicon film is selectively embedded in the contact hole is formed. Thereafter, a CVD nitride film is deposited as an interlayer insulating film 109 on the entire surface. Subsequently, a contact hole reaching the other of the source / drain diffusion layers 101 is formed in the interlayer insulating films 107 and 109. Further, a TiN film (not shown) and an n ⁺ polycrystalline silicon film are embedded in the contact hole to form a polycrystalline silicon plug 110.
[0022]
Next, a Ti film (not shown) having a thickness of 5 nm and a TiN film (not shown) having a thickness of 10 nm are deposited on the entire surface by sputtering. Subsequently, as a lower electrode of the capacitor, an Ir film 111 having a thickness of about 120 nm, a Ti film 112 having a thickness of about 2.5 nm, and an SRO film 113 having a thickness of about 10 nm are formed on the entire surface by sputtering. Subsequently, a PZT film 114 is formed on the entire surface by sputtering as a dielectric film (ferroelectric film) of the capacitor, and the PZT film 114 is crystallized by rapid heating treatment (RTA) in an oxygen atmosphere. Subsequently, as a lower electrode of the capacitor, an SRO film 115 and a Pt film 116 having a thickness of about 10 nm are formed on the entire surface by a sputtering method. Thereafter, an Al ₂ O ₃ film is deposited on the entire surface by a sputtering method as the diffusion barrier film 117. Further, a CVD oxide film 118 used as a hard mask for processing the upper electrode is deposited.
[0023]
Next, as shown in FIG. 3, the CVD oxide film 118 and the diffusion barrier film 117 are patterned by photolithography and RIE.
[0024]
Next, as shown in FIG. 4, the platinum film 116, the SRO film 115, and the PZT film 114 are etched by the RIE method using the patterned CVD oxide film 118 and the diffusion barrier film 117 as a mask. Subsequently, an Al ₂ O ₃ film is formed as a diffusion barrier film 119 on the entire surface by a sputtering method. Further, a CVD oxide film 120 used as a hard mask for processing the lower electrode is formed on the entire surface by the CVD method.
[0025]
Next, as shown in FIG. 5, the CVD oxide film 120 and the diffusion barrier film 119 are patterned by photolithography and RIE.
[0026]
Next, as shown in FIG. 6, the SRO film 113, the Ti film 112, and the Ir film 111 are patterned using the patterned CVD oxide film 120 and the diffusion barrier film 119 as a mask. This completes the formation of the capacitor structure. Thereafter, an Al ₂ O ₃ film is formed as a diffusion barrier film 121 on the entire surface by sputtering. The capacitor structure is covered with this diffusion barrier film 121. Subsequently, a CVD oxide film is deposited on the entire surface as an interlayer insulating film 122 by a CVD method. Further, in order to remove the damage generated in the PZT film 114 during the capacitor processing, a heat treatment is performed at about 600 ° C. in an oxygen atmosphere.
[0027]
Next, as shown in FIG. 7, an etch back process is performed until the Pt film 116 is exposed by CMP. By this etch back process, the entire surface is flattened. Subsequently, the CVD oxide film 122, the diffusion barrier layer film 121 and the CVD nitride film 109 are etched by photolithography and RIE to form a via hole reaching the polycrystalline silicon plug 108.
[0028]
Next, as shown in FIG. 8, a barrier metal film (not shown) having a TiN / Ti structure is deposited on the entire surface by sputtering, and an Al film is further deposited on the entire surface by sputtering. As a result, a conductive portion for the via plug 123 is formed in the via hole, and a conductive portion 124a for wiring is formed in a region other than the via hole.
[0029]
Next, as shown in FIG. 9, the conductive portion 124a is patterned by the photolithography method and the RIE method to form the wiring 124. Thereafter, an Al ₂ O ₃ film is formed as a diffusion barrier film 125 on the entire surface by sputtering.
[0030]
Furthermore, a structure as shown in FIG. 1 is obtained by depositing a CVD oxide film on the entire surface as the interlayer insulating film 126. Although the subsequent processes are not shown, the ferroelectric memory is completed through a drive line and bit line formation process, an upper metal wiring formation process, and the like.
[0031]
As described above, in the ferroelectric memory of the present embodiment, the Pt film 116 constituting the upper electrode and the lower surface of the wiring 124 exist in substantially the same plane, and are connected to the upper electrode as in the conventional case. There is no provided plug. Therefore, the aspect ratio of the via plug 123 can be reduced, and the via plug 123 can be reliably formed in the via hole. As a result, contact failure and the like can be prevented, and a ferroelectric memory excellent in characteristics and reliability can be obtained.
[0032]
Further, in this embodiment, since the plug connected to the upper electrode is not provided as in the prior art, the number of lithography processes can be reduced as compared with the prior art, and the manufacturing process can be reduced and the yield can be improved. It becomes.
[0033]
In the conventional ferroelectric memory, the plug and the wiring connected to the upper electrode are formed in the insulating film by the damascene method. Therefore, when processing in a hydrogen atmosphere such as a sintering process is performed after forming the capacitor structure, the insulating film can prevent hydrogen diffusion to the capacitor to some extent. In this embodiment, a conductive film for wiring is formed directly on the upper electrode, and this conductive film is patterned by etching to form the wiring 124. Therefore, although it is difficult to suppress hydrogen diffusion by the insulating film as described above, hydrogen diffusion can be suppressed by the diffusion barrier film 125 formed over the wiring 124, so that hydrogen damage to the capacitor can be prevented. it can.
[0034]
In the embodiment described above, the wiring is formed of an aluminum film (Al film), but a platinum film (Pt film), an iridium film (Ir film), a ruthenium film (Ru film), an iridium oxide film (IrO). ₂ film), ruthenium oxide film (RuO ₂ film), SRO film or TiN film may be used. A film in which these conductive films are stacked can also be used. In addition to the sputtering method, a CVD method can be used as a method for forming the wiring film.
[0035]
In the embodiment described above, the diffusion barrier film is formed of an Al ₂ O ₃ film (aluminum oxide film), but a tantalum oxide film may be used. In addition to the sputtering method, a CVD method can be used as a method for forming the diffusion barrier film.
[0036]
In the above-described embodiment, the PZT film is used as the ferroelectric film of the capacitor. However, a metal oxide film other than the PZT film such as an SBT film (SrBi ₂ Ta ₂ O ₉ film) may be used.
[0037]
Further, an iridium film (Ir film), a ruthenium film (Ru film), an iridium oxide film (IrO ₂ film), a ruthenium oxide film (RuO ₂ film), or the like can be used as the electrode material of the capacitor.
[0038]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as an invention as long as a predetermined effect can be obtained.
[0039]
【The invention's effect】
According to the present invention, since the aspect ratio of the plug can be reduced, contact failure and the like can be prevented, and a semiconductor device having excellent characteristics and reliability can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 3 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 4 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 5 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 6 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 7 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 8 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 9 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.
FIG. 10 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a conventional technique.
[Explanation of symbols]
100 ... silicon substrate, 101 ... source / drain diffusion layer,
102 ... Gate insulating film, 103 ... Gate sidewall film,
104 ... polycrystalline silicon film, 105 ... WSi ₂ film,
106: gate cap film,
107, 109, 122, 126 ... interlayer insulating film,
108, 110 ... polycrystalline silicon plug,
111 ... Iridium film, 112 ... Titanium film,
113 ... SRO film, 114 ... Ferroelectric film,
115 ... SRO film, 116 ... Platinum film,
117, 119, 121, 125 ... diffusion barrier film,
118, 120 ... CVD oxide film, 123 ... Via plug,
124 ... Wiring

Claims (12)

A semiconductor substrate provided with a transistor;
A first dielectric film provided above the semiconductor substrate, and provided between the first lower electrode, the first upper electrode, and the first upper electrode and the first lower electrode; A first capacitor comprising:
A wiring connected to the first upper electrode;
A first plug electrically connecting the wiring and one of a source and a drain of the transistor;
With
The semiconductor device according to claim 1, wherein an upper surface of the first upper electrode and a lower surface of the wiring are present in substantially the same plane. The semiconductor device according to claim 1, wherein the wiring extends in a direction parallel to a main surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein a boundary between the wiring and the first plug exists substantially in the plane. The semiconductor device according to claim 1, wherein the first plug extends in a direction perpendicular to a main surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, further comprising a second plug that electrically connects the lower electrode and the other of the source and the drain of the transistor. A second dielectric film provided above the semiconductor substrate, and provided between the second lower electrode, the second upper electrode, and the second upper electrode and the second lower electrode; A second capacitor comprising:
2. The semiconductor device according to claim 1, wherein the second upper electrode is connected to the wiring, and an upper surface of the second upper electrode is substantially in the plane. An insulating region provided at least between the first capacitor and the second capacitor;
The semiconductor device according to claim 6, wherein the first plug is formed in the insulating region. The semiconductor device according to claim 1, further comprising a diffusion barrier film that covers the wiring and prevents diffusion of hydrogen into the capacitor. The semiconductor device according to claim 8, wherein the diffusion barrier film includes at least one of an aluminum oxide film and a tantalum oxide film. 2. The wiring according to claim 1, wherein the wiring includes at least one of an aluminum film, a platinum film, an iridium film, a ruthenium film, an iridium oxide film, a ruthenium oxide film, a SrRuO ₃ film, and a TiN film. Semiconductor device. The semiconductor device according to claim 1, wherein the wiring is formed by etching. The semiconductor device according to claim 1, wherein the dielectric film includes a ferroelectric film.

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