JP4649899B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device using an insulating metal oxide as a capacitive insulating film.

  In recent years, with the advancement of digital technology, electronic devices have become more sophisticated as the tendency to process and store large volumes of data has been promoted, and semiconductor devices used have been rapidly miniaturized. . Accordingly, in order to realize high integration of the dynamic RAM, a technique of using a high dielectric as a capacitive insulating film instead of the conventional silicon oxide or nitride has been widely researched and developed. In addition, research and development on a ferroelectric film having spontaneous polarization characteristics are being actively carried out with the aim of putting a non-volatile RAM capable of unprecedented low operating voltage and high speed writing / reading into practical use. In a semiconductor memory device using such a high dielectric material or a ferroelectric material as a capacitor insulating film, a stack type memory cell is used instead of a conventional planar type memory cell for a megabit-class highly integrated memory.

  A conventional semiconductor device will be described below with reference to the drawings.

  FIG. 6 is a cross-sectional view of an essential part of a semiconductor memory device as a first conventional example (see, for example, Patent Document 1).

  As shown in FIG. 6, the conventional semiconductor memory device includes a source / drain region 102 formed on a semiconductor substrate 101 and a gate electrode 104 formed on a channel region of the semiconductor substrate 101 via a gate insulating film 103. The transistor 105 is formed. An interlayer insulating film 106 covering the entire surface including the transistor 105 is formed on the semiconductor substrate 101, and a contact plug 107 electrically connected to one of the source / drain regions 102 is formed on the interlayer insulating film 106. Is formed.

An insulating hydrogen barrier layer 108 made of silicon nitride (Si ₃ N ₄ ) is formed on the interlayer insulating film 106, and a conductive hydrogen barrier layer made of titanium nitride (TiN) is formed on the upper end portion of the contact plug 107. 109 is formed.

A lower electrode 110 containing iridium dioxide (IrO ₂ ) or ruthenium dioxide (RuO ₂ ) serving as an oxygen barrier film is formed on the insulating hydrogen barrier layer 108 so as to be connected to the conductive hydrogen barrier layer 109. Yes.

A buried insulating film 111 made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or the like is formed between the lower electrodes 110 on the insulating hydrogen barrier layer 108. Yes.

On the buried insulating film 111 including the lower electrode 110, capacitive insulation made of a ferroelectric material such as lead zirconate titanate (Pb (Zr, Ti) O ₃ ) or strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ). A film 112 is formed, and an upper electrode 113 containing iridium dioxide or ruthenium dioxide is formed on the capacitor insulating film 112.

However, the semiconductor memory device according to the first conventional example constitutes the lower electrode 110, and a conductive oxide film made of IrO ₂ or RuO _{2 serving as} a barrier against oxygen is reduced by hydrogen generated during manufacture. There was a problem that the barrier property against oxygen deteriorated.

This point will be described in detail with reference to FIGS. 7 (a) and 7 (b). As shown in FIG. 7A, after forming the lower electrode 110 including an oxygen barrier film such as IrO ₂ or RuO ₂ , the insulating film 111A is formed on the lower electrode 110 when the insulating film 111A to be the buried insulating film 111 is formed. Is formed so as to be in direct contact, hydrogen generated from SiH ₄ or NH _{3 serving as} a source gas of the insulating film 111A penetrates (diffuses) into an oxygen barrier film such as IrO ₂ or RuO ₂ constituting the lower electrode 110, This causes a defective shape of the oxygen barrier film. This is particularly noticeable when the insulating film 111A is formed by plasma CVD. For example, in the case where the oxygen barrier film is IrO ₂ , IrO ₂ is reduced to Ir, thereby causing a shape defect and impairing oxygen barrier properties. Further, it is considered that the oxygen barrier property is also impaired by the occurrence of a shape defect caused by direct exposure of IrO ₂ to plasma.

As a result, the barrier property against oxygen diffusion of the oxygen barrier film such as IrO ₂ or RuO ₂ is deteriorated, and as shown in FIG. 7B, it is made of a high dielectric material or a ferroelectric material formed on the lower electrode 110. During oxygen annealing at 650 ° C. to 800 ° C. necessary for crystallization of the capacitor insulating film 112, oxygen from the upper direction diffuses to the interface of the contact plug 107, resulting in a sudden increase in contact resistance, that is, contact resistance failure.

  As a configuration for solving this problem, there is a semiconductor memory device as a second conventional example described below.

  FIG. 8 is a cross-sectional view of a main part of a semiconductor memory device as a second conventional example (see, for example, Patent Document 2).

  As shown in FIG. 8, a semiconductor memory device as a second conventional example includes a plurality of cell transistors 220 made of MOSFETs formed on a semiconductor substrate 211 made of, for example, silicon (Si), and an interlayer covering each cell transistor 220. A capacitor 230 formed for each cell transistor 220 is provided on the insulating film 213.

  Each cell transistor 220 includes a source / drain region 221 formed on the semiconductor substrate 211 and a gate electrode 223 formed on the channel region of the semiconductor substrate 211 via a gate insulating film 222.

  Each capacitive element 230 includes a lower electrode 231, a capacitive insulating film 232, and an upper electrode 233 that are sequentially stacked from the substrate side.

The lower electrode 231 is made of titanium aluminum nitride (TiAlN) in order from the bottom, a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a second conductive barrier layer that consists of iridium (Ir) and prevents diffusion of oxygen. , A third conductive barrier layer made of iridium dioxide (IrO ₂ ) for preventing diffusion of oxygen, and a laminated film of a conductive layer made of platinum (Pt).

The capacitor insulating film 232 is made of strontium bismuth tantalum niobate (SrBi ₂ (Ta _1−x Nb _x ) ₂ O ₉ ) (where x is 0 ≦ x ≦ 1), and the upper electrode 233 is made of platinum.

On the semiconductor substrate 211, an interlayer insulating film 213 made of, for example, silicon oxide (SiO ₂ ) is formed so as to cover each cell transistor 220, and the lower end portion of the interlayer insulating film 213 has a source drain region 221. A plurality of contact plugs 214 made of tungsten (W) or polysilicon, which is electrically connected to one of them and whose upper end is electrically connected to the lower electrode 231 of each capacitor 230, is formed.

The side surface of the lower electrode 231 and the region on the side of the lower electrode 231 on the interlayer insulating film 213 are covered with a first insulating barrier layer 215 made of, for example, aluminum oxide (Al ₂ O ₃ ) and preventing diffusion of oxygen and hydrogen. It has been broken.

  Here, the diameter in the substrate surface direction of the lower electrode 231 is smaller than the dimension of the diameter in the substrate surface direction of the capacitor insulating film 232 and the upper electrode 233. Therefore, the peripheral portions of the capacitor insulating film 232 and the upper electrode 233 are the lower electrode. It protrudes from the peripheral edge of H.231.

A region on the side of the lower electrode 231 and below the protruding portion of the capacitor insulating film 232 is buried with a buried insulating film 216 made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  As a result, the side surface of the lower electrode 231 is covered with the first insulating barrier layer 215 that prevents diffusion of oxygen and hydrogen.

  A method for manufacturing the semiconductor memory device as the second conventional example configured as described above will be described below.

  FIG. 9 shows a cross-sectional configuration in the order of steps of a semiconductor memory device manufacturing method which is a second conventional example.

  First, as shown in FIG. 9A, a gate insulating film 222 and a gate electrode 223 are formed on a semiconductor substrate 211 made of silicon, and further, a source / drain region 221 is formed. Thereafter, an interlayer insulating film 213 made of silicon oxide is deposited over the entire surface including the plurality of cell transistors 220 on the semiconductor substrate 211 by CVD. Subsequently, the upper surface of the deposited interlayer insulating film 213 is planarized by using a chemical mechanical polishing (CMP) method or the like. Subsequently, a contact hole is formed in one of the source / drain regions 221 of each cell transistor 220 in the interlayer insulating film 213, and a conductor film made of tungsten or polysilicon is deposited by CVD to fill each contact hole. To do. Subsequently, the deposited conductor film is etched back or subjected to chemical mechanical polishing to remove the conductor film on the interlayer insulating film 213, thereby forming a plurality of contact plugs 214.

  Next, a first conductive barrier layer made of titanium aluminum nitride that prevents diffusion of oxygen and hydrogen is formed on the interlayer insulating film 213 including the plurality of contact plugs 214 by sputtering, for example, and iridium that prevents diffusion of oxygen. A second conductive barrier layer, a third conductive barrier layer made of iridium dioxide for preventing oxygen diffusion, and a conductive layer made of platinum are sequentially deposited to form a lower electrode formation film. Subsequently, the lower electrode formation film is patterned so as to include the contact plug 214 to form a plurality of lower electrodes 231 made of the lower electrode formation film. Thereafter, a first insulating barrier layer 215 made of aluminum oxide and preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 213 so as to cover the upper surface and side surfaces of the lower electrode 231 by sputtering or CVD. . Subsequently, a buried insulating film 216 made of silicon oxide or silicon nitride is deposited so as to cover the first insulating barrier layer 215.

  Next, as shown in FIG. 9B, by using the CMP method, the buried insulating film 216 and the first insulating barrier layer 215 are planarized until the respective lower electrodes 231 are exposed, so that The periphery of the lower electrode 231 is buried with a buried insulating film 216. Therefore, the upper surface of the lower electrode 231 has substantially the same height as the exposed surfaces of the buried insulating film 216 and the first insulating barrier layer 215.

Next, as shown in FIG. 9C, strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb) is formed on the entire surface of the first insulating barrier layer 215, the buried insulating film 216, and the lower electrode 231. _A capacitive insulating film forming film 232A made of _x ) ₂ O ₉ ) is formed. Subsequently, an upper electrode forming film 233A made of platinum is formed on the capacitor insulating film forming film 232A by sputtering. Thereafter, heat treatment is performed to crystallize the metal oxide constituting the capacitor insulating film formation film 232A.

  Next, the upper electrode forming film 233A, the capacitor insulating film forming film 232A, and the embedded insulating film 216 are sequentially dry-etched to form the upper electrode 233 from the upper electrode forming film 233A, and from the capacitor insulating film forming film 232A. A capacitor insulating film 232 is formed. As a result, a capacitor element 230 including the lower electrode 231, the capacitor insulating film 232, and the upper electrode 233 electrically connected to the contact plug 214 is formed.

  Thus, the structure shown in FIG. 8 is formed.

As described above, according to the semiconductor memory device of the second conventional example, the first insulating barrier layer 215 that prevents the diffusion of oxygen and hydrogen covers the side surface of the lower electrode 231 of the capacitor 230. It is possible to prevent a conductive oxide such as iridium oxide which is an oxygen barrier constituting H.sub.231 from being reduced by hydrogen and deteriorating its oxygen barrier property.
Japanese Patent Laid-Open No. 11-8355 JP 2003-86771 A

  However, in the semiconductor memory device according to the second conventional example, the semiconductor memory device according to the first conventional example is strengthened in order to strengthen the function of preventing hydrogen from entering the capacitor insulating film 232 from below the lower electrode 231. When a hydrogen barrier layer made of silicon nitride corresponding to the insulating hydrogen barrier layer 108 is formed between the interlayer insulating film 213, the lower electrode 231, and the first insulating barrier layer 215, the following problems occur. Was found to occur.

  FIG. 10 shows a hydrogen barrier layer 240 made of silicon nitride, an interlayer insulating film 213, a lower electrode 231 and aluminum oxide in FIG. 9A for explaining a method of manufacturing a semiconductor memory device as a second conventional example. It is a figure for demonstrating the case where it forms between the 1st insulating barrier layers 215 which consist of.

  In this case, the first insulating barrier layer 215 made of aluminum oxide is in contact with the hydrogen barrier layer 240 made of silicon nitride.

  During the oxygen annealing at 650 ° C. to 800 ° C. necessary for crystallization of the capacitive insulating film in the step after FIG. 9A, the hydrogen barrier layer 240 made of silicon nitride and the first insulating barrier made of aluminum oxide It was found that peeling occurred at the interface of layer 215. This is considered to be caused by the difference in thermal expansion coefficient between silicon nitride and aluminum oxide.

  When delamination occurs at the interface between the hydrogen barrier layer 240 and the first insulating barrier layer 215 made of aluminum oxide, oxygen from above diffuses to the contact plug interface during oxygen annealing, resulting in a rapid increase in contact resistance, that is, contact resistance. Defects will occur.

The present invention solves the above-described conventional problems, reliably prevents hydrogen from entering the capacitive insulating film, and conducts conductivity such as IrO ₂ or RuO ₂ that serves as an oxygen barrier constituting the lower electrode. Provided are a semiconductor memory device and a method for manufacturing the same, which can prevent the oxygen barrier film from being reduced by hydrogen, thereby preventing the oxygen barrier property from deteriorating and increasing the contact resistance of the contact plug. For the purpose.

  In order to achieve the above object, a semiconductor memory device of the present invention includes an interlayer insulating film formed on a substrate, an insulating hydrogen barrier film formed on the interlayer insulating film, an interlayer insulating film, and a hydrogen barrier. A contact plug formed through the film; a lower electrode including a conductive oxygen barrier film formed on the insulating hydrogen barrier film and electrically connected to the contact plug; and a periphery of the lower electrode. A semiconductor memory device comprising: a buried insulating film to be buried; a capacitive insulating film made of a ferroelectric film provided on the lower electrode and the buried insulating film; and an upper electrode formed on the capacitive insulating film. And an insulating reaction preventing film formed to be in contact with at least the side surface of the lower electrode.

  According to the semiconductor memory device of the present invention, the conductive oxygen barrier film can be prevented from being reduced by the insulating reaction preventing film formed so as to be in contact with the side surface of the lower electrode including the conductive oxygen barrier film. In addition, there is no shape defect in the conductive oxygen barrier film. As a result, the oxygen barrier property of the conductive oxygen barrier film does not deteriorate, oxygen can be prevented from entering the contact plug, and the contact resistance of the contact plug can be prevented from increasing. In addition, the hydrogen barrier film can prevent hydrogen from entering the capacitor insulating film from below the lower electrode. Further, when at least the surface portion of the hydrogen barrier film is made of silicon nitride, the adhesion between the insulating reaction preventing film and the hydrogen barrier film is improved.

  In the semiconductor memory device of the present invention, the insulating reaction preventing film is a film containing a multimer formed by polymerization of TEOS, and the embedded insulating film has a large amount formed by polymerization of TEOS. Or a multimer formed by polymerizing TEOS in an amount smaller than the amount of multimers formed by polymerizing TEOS contained in the insulating reaction prevention film. Preferably it is.

  By doing so, it is possible to easily prevent the conductive oxygen barrier film from being reduced by the insulating reaction preventing film which is a film containing a multimer formed by polymerization of TEOS. In addition, there is no shape defect in the conductive oxygen barrier film. Further, since the adhesion between the insulating reaction preventing film and the hydrogen barrier film is good, no peeling occurs between the insulating reaction preventing film and the hydrogen barrier film. In particular, the adhesion is further improved when at least the surface portion of the hydrogen barrier film is made of silicon nitride.

  In the semiconductor memory device of the present invention, it is preferable that the insulating reaction preventing film is a film made of silicon nitride.

  By doing so, it is possible to easily prevent the conductive oxygen barrier film from being reduced by the insulating reaction preventing film which is a film made of silicon nitride. In addition, there is no shape defect in the conductive oxygen barrier film. Further, since the adhesion between the insulating reaction preventing film and the hydrogen barrier film is good, no peeling occurs between the insulating reaction preventing film and the hydrogen barrier film. In particular, the adhesion is further improved when at least the surface portion of the hydrogen barrier film is made of silicon nitride.

In the semiconductor memory device of the present invention, the conductive oxygen barrier film includes iridium dioxide (IrO ₂ ), a laminated film formed of iridium (Ir) and iridium dioxide (IrO ₂ ) sequentially formed from the lower layer, ruthenium dioxide ( RuO ₂ ) and any one of laminated films sequentially formed from the lower layer of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ), or a laminated film including at least two of them. It is preferable that

  By doing so, it is possible to effectively prevent oxygen from entering the contact plug by the conductive oxygen barrier film.

  In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming an interlayer insulating film on a substrate, a step of forming an insulating hydrogen barrier film on the interlayer insulating film, A step of forming a contact plug so as to penetrate the interlayer insulating film and the insulating hydrogen barrier film, and a step of forming a lower electrode including a conductive oxygen barrier film on the insulating hydrogen barrier film and the contact plug A step of forming an insulating reaction preventing film so as to cover at least a side surface of the lower electrode, a step of forming a buried insulating film on the insulating reaction preventing film so as to cover the lower electrode, and a lower portion Removing the buried insulating film and the insulating reaction preventing film so as to expose the upper surface of the electrode; forming a capacitive insulating film made of a ferroelectric film on the lower electrode and the buried insulating film; Insulation film Above, characterized in that it comprises a step of forming an upper electrode.

  According to the method for manufacturing a semiconductor memory device of the present invention, in the step of forming the buried insulating film with the insulating reaction preventing film formed so as to be in contact with the side surface of the lower electrode including the conductive oxygen barrier film, the conductive oxygen film is formed. It is possible to prevent the barrier film from being reduced. In addition, there is no shape defect in the conductive oxygen barrier film. As a result, the oxygen barrier property of the conductive oxygen barrier film does not deteriorate, oxygen can be prevented from entering the contact plug, and the contact resistance of the contact plug can be prevented from increasing. In addition, the hydrogen barrier film can prevent hydrogen from entering the capacitor insulating film from below the lower electrode.

  In the method for manufacturing a semiconductor memory device of the present invention, the step of forming the insulating reaction preventing film includes a film containing a multimer formed by polymerization of TEOS by an atmospheric pressure CVD method using TEOS and ozone as raw materials. It is preferable to include the process of forming.

  In this way, in the step of forming the buried insulating film by covering the side surface of the lower electrode with the insulating reaction preventing film which is a film containing a polymer formed by polymerization of TEOS, the conductive oxygen barrier is formed in the step of forming the buried insulating film. It is possible to easily prevent the film from being reduced. In addition, there is no shape defect in the conductive oxygen barrier film. Further, since the adhesion between the insulating reaction preventing film and the hydrogen barrier film is good, no peeling occurs between the insulating reaction preventing film and the hydrogen barrier film.

  As described above, according to the semiconductor memory device of the present invention, the conductive oxygen barrier film is reduced by the insulating reaction preventing film formed so as to be in contact with the side surface of the lower electrode including the conductive oxygen barrier film. Can be prevented. In addition, there is no shape defect in the conductive oxygen barrier film. As a result, the oxygen barrier property of the conductive oxygen barrier film does not deteriorate, oxygen can be prevented from entering the contact plug, and the contact resistance of the contact plug can be prevented from increasing. In addition, the hydrogen barrier film can prevent hydrogen from entering the capacitor insulating film from below the lower electrode.

  Further, according to the method for manufacturing a semiconductor memory device according to the present invention, in the step of forming the buried insulating film with the insulating reaction preventing film formed so as to be in contact with the side surface of the lower electrode including the conductive oxygen barrier film, The conductive oxygen barrier film can be prevented from being reduced. In addition, there is no shape defect in the conductive oxygen barrier film. As a result, the oxygen barrier property of the conductive oxygen barrier film does not deteriorate, oxygen can be prevented from entering the contact plug, and the contact resistance of the contact plug can be prevented from increasing. In addition, the hydrogen barrier film can prevent hydrogen from entering the capacitor insulating film from below the lower electrode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIG.

  FIG. 1 is a cross-sectional view of an essential part of a semiconductor memory device according to a first embodiment of the present invention.

  As shown in FIG. 1, an element isolation region 2 and an active region 3 including a source region or a drain region are formed on a semiconductor substrate 1, and further from a gate insulating film 4a, a gate electrode 4b, and sidewalls 4c. A gate 4 is formed. The active region 3 and the gate 4 constitute a transistor. An interlayer insulating film 5 made of silicon oxide or silicon nitride having a thickness of 500 to 1000 nm is formed so as to cover the gate 4 over the entire surface of the semiconductor substrate 1 having the element isolation region 2 and the active region 3. Yes. An insulating hydrogen barrier film 7 made of silicon nitride having a thickness of 10 nm to 150 nm is formed on the interlayer insulating film 5. A contact plug 6 (diameter: 0.24 μm) having a lower end in contact with the active region 3 is formed through the interlayer insulating film 5 and the hydrogen barrier film 7 and made of low-resistance polysilicon doped with tungsten or n-type impurities. ing.

A conductive hydrogen barrier film 8a made of TiAlN, a conductive oxygen barrier film 8b made of Ir and IrO _{2 in} order from the lower layer, and a conductor made of Pt on the hydrogen barrier film 7 including the contact plug 6 in order from the lower layer. A lower electrode 8 made of a laminated film with the film 8c is formed. Here, it is desirable that the thickness of each film constituting the lower electrode 8 is in the range of 40 to 60 nm for TiAlN, and the range of 50 to 100 nm for Ir, IrO ₂ , and Pt, respectively.

  Among the lower electrodes 8, an insulating reaction preventing film 9 (having a thickness of 5 nm to 60 nm) which is a reaction preventing layer for preventing the conductive oxygen barrier film 8 b from reacting with hydrogen or plasma in particular is at least the lower part. A buried insulating film 10 made of silicon oxide, silicon nitride, silicon oxynitride or the like is formed so as to completely cover the side surface of the electrode 8 and to embed the periphery of the lower electrode 8 via the insulating reaction preventing film 9. ing. The surfaces of the buried insulating film 10 and the reaction preventing film 9 are flattened and are almost the same height as the surface of the lower electrode 8.

  Here, the insulating reaction preventing film 9 is a film containing a multimer formed by polymerization of TEOS. Note that the embedded insulating film 10 does not include a multimer formed by polymerization of TEOS, or if the embedded insulating film 10 is a TEOS film, the embedded insulating film 10 includes the insulating reaction prevention film 9. A multimer formed by polymerization of TEOS in an amount smaller than the amount of multimers formed by polymerization of TEOS contained is included. A film containing a polymer formed by polymerization of TEOS has an effect of blocking hydrogen and plasma, and thus has an effect of preventing reaction of hydrogen and plasma with the conductive oxygen barrier film 8b. . In addition, the adhesion between the film containing multimers formed by polymerization of TEOS and the silicon nitride is very good, so that no peeling occurs between the insulating reaction preventing film 9 and the hydrogen barrier film 7.

On the lower electrode 8 and the buried insulating film 10, a strong film such as SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (0 ≦ x ≦ 1) having a bismuth layered perovskite structure having a thickness of 50 nm to 150 nm is formed. A capacitor insulating film 11 made of a dielectric is formed, and an upper electrode 12 made of Pt having a thickness of 50 nm to 100 nm is formed on the capacitor insulating film 11.

  A capacitive element 14 is composed of the lower electrode 8, the capacitive insulating film 11, and the upper electrode 12.

  An insulating hydrogen barrier film 13 made of aluminum oxide having a thickness of 5 nm to 150 nm is formed so as to cover the upper electrode 12 and the capacitor insulating film 11.

  According to the semiconductor memory device of the present invention, the conductive oxygen barrier film 8b is reduced by the insulating reaction preventing film 9 formed in contact with the side surface of the lower electrode 8 including the conductive oxygen barrier film 8b. Can be prevented. In addition, there is no shape defect in the conductive oxygen barrier film 8b. As a result, the oxygen barrier property of the conductive oxygen barrier film 8b does not deteriorate, oxygen can be prevented from entering the contact plug 6, and the contact resistance of the contact plug 6 can be prevented from increasing. Further, the hydrogen barrier film 7 can prevent hydrogen from entering the capacitive insulating film 11 from below the lower electrode 8.

  Next, the evaluation result of the contact resistance between the contact plug 6 and the lower electrode 8 in the semiconductor memory device according to the present embodiment, the evaluation result of the contact resistance in the semiconductor memory device in which the reaction preventing film 9 is not formed (comparative example), and Comparison will be described with reference to FIG. Here, the comparative example has the same configuration as the semiconductor memory device according to the present embodiment except that the reaction preventing film 9 is not formed in the semiconductor memory device according to the present embodiment. In the semiconductor memory device and the comparative example according to the present embodiment, the buried insulating film 10 is a silicon oxide film formed by a plasma CVD method.

  FIG. 5 shows measurement results of contact resistance at all points on the 8-inch silicon wafer surface in the semiconductor memory device (present invention) and the comparative example (conventional structure) according to the present embodiment. Here, the contact shape is assumed to be a square having a side of 0.24 μm.

  In the case of the comparative example, the contact resistance was in an open state. This is a configuration in which the lower electrode 8 and the buried insulating film 10 are in direct contact with each other, and therefore, when an insulating film to be the buried insulating film 10 is formed (step corresponding to FIG. 3A in the second embodiment). Due to the reduction action of hydrogen in oxygen, the oxygen barrier property of the oxygen barrier film 8b constituting the lower electrode 8 is lost, and oxygen passes through the lower electrode 8 during high-temperature oxygen annealing necessary for crystallization of a high dielectric material or a ferroelectric material. This is because the diffusion has occurred, the surface of the contact plug 6 has been oxidized, and the contact resistance has become very high.

  On the other hand, in the case of the semiconductor memory device according to the present embodiment, the contact resistance is in the range of 50Ω to 100Ω at all points in the wafer surface, and there is very little variation and low resistance can be realized. Since the lower electrode 8 and the buried insulating film 10 are not in direct contact as described above, the conductive oxygen barrier film 8b can be prevented from being reduced. In addition, there is no shape defect in the conductive oxygen barrier film 8b. As a result, it is possible to prevent the oxygen barrier property of the oxygen barrier film 8b constituting the lower electrode 8 from being lost. For this reason, even during high-temperature oxygen annealing necessary for crystallization of a high dielectric material or a ferroelectric material, It is considered that the contact resistance exhibited an appropriate value because the surface of the contact plug 6 was prevented from being oxidized without being diffused in the lower electrode 8.

(Second Embodiment)
FIG. 2 is a process sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

  Since the method for manufacturing the semiconductor memory device according to the second embodiment is a method for manufacturing the semiconductor memory device described in the first embodiment, among the components shown in FIG. Portions common to the components of the semiconductor memory device described in the embodiment are denoted by the same reference numerals.

  First, as shown in FIG. 2A, an active region 3 including an element isolation region 2 and a source region or a drain region is formed on a semiconductor substrate 1, and a gate insulating film 4a, a gate electrode 4b, and sidewalls 4c are formed. The gate 4 is formed. Subsequently, a silicon oxide film or a silicon nitride film is formed so as to cover the gate 4, and then planarized by a CMP method to form an interlayer insulating film 5 having a thickness of 500 to 1000 nm. Subsequently, an insulating hydrogen barrier film 7 made of silicon nitride having a thickness of 10 nm to 150 nm is formed on the interlayer insulating film 5. Subsequently, a contact hole is formed through the interlayer insulating film 5 and the hydrogen barrier film 7 to expose the active region 3 in the interlayer insulating film 5 by dry etching. Thereafter, low resistance polysilicon doped with tungsten or n-type impurities is formed over the entire surface of the hydrogen barrier film 7 including the inside of the contact hole by a CVD method, and then the hydrogen barrier film 7 is formed by a CMP method. The low resistance polysilicon doped with tungsten or n-type impurities formed thereon is removed to form a contact plug 6 (diameter is 0.24 μm).

Next, as shown in FIG. 2B, a hydrogen barrier material made of TiAlN is formed on the hydrogen barrier film 7 including the contact plug 6 by a sputtering method or a CVD method. An oxygen barrier material in which Ir and IrO ₂ are laminated in order from the lower layer is formed on the hydrogen barrier material by a CVD method, and an electrode made of Pt is formed on the oxygen barrier material by a sputtering method or a CVD method. Deposit material. Thereafter, in order to process the electrode material and the first and second hydrogen barrier materials into desired shapes, dry etching using a gas containing chlorine is performed, so that a conductive oxygen hydrogen barrier made of TiAlN is sequentially formed from the lower layer. A lower electrode 8 made of a laminated film of a film 8a, a conductive oxygen barrier film 8b made of Ir and IrO ₂ and a conductor film 8c made of Pt is formed in this order from the lower layer.

Next, as shown in FIG. 2C, the atmospheric pressure CVD method using TEOS and ozone (O ₃ ) as raw materials over the entire surface of the semiconductor substrate 1 so as to cover at least the side surface of the lower electrode 8. An insulating reaction preventing film 9a (film thickness is 5 nm to 60 nm) made of a film containing a polymer formed by polymerization of TEOS is formed. Here, for example, the flow rate of TEOS is 500 to 1000 cc (standard state), and the ozone concentration is 12 to 15 wt%. In TEOS-O ₃ -based CVD at normal pressure, the introduced ozone molecules are decomposed into oxygen molecules and oxygen radicals under conditions where the flow rate of ozone is large, and TEOS is polymerized by the action of the oxygen radicals to produce multimers. (Oligomer) is formed, and this oligomer is known to be adsorbed on the surface of the underlying film to form a condensed phase (see Applied Physics Vol. 61 No. 11 (1992) pp. 1116-1123). In the embodiment, a film containing a multimer formed by polymerization of TEOS is used as the reaction preventing film 9a.

  Next, as shown in FIG. 3A, a silicon oxide film 10a having a thickness of 400 nm to 600 nm is formed as an insulating film to be a buried insulating film 10 on the reaction preventing film 9a so as to cover the lower electrode 8. Is deposited by CVD. At this time, the reaction preventing film 9a serves to prevent the hydrogen or plasma and the conductive oxygen barrier film 8b from reacting with each other, which is a film containing multimers formed by polymerization of TEOS.

  Next, as shown in FIG. 3B, the reaction preventing film 9a and the silicon oxide film 10a are polished by the CMP method until the surface of the lower electrode 8 is exposed. A buried insulating film 10 and a reaction preventing film 9 are formed to be insulated from each other. The surfaces of the buried insulating film 10 and the reaction preventing film 9 are flattened and are almost the same height as the surface of the lower electrode 8.

Next, as shown in FIG. 4A, a dielectric thin film made of SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (0 ≦ x ≦ 1) is formed on the lower electrode 8 and the buried insulating film 10. Is formed by a metal organic decomposition method (MOD method), a metal organic chemical vapor deposition method (MOCVD method) or a sputtering method. The film thickness of the dielectric thin film is in the range of 12.5 nm to 100 nm. Further, after the dielectric thin film is formed, a heat treatment in the range of 600 ° C. to 800 ° C. is performed in an atmosphere containing oxygen for crystallization. The heat treatment is performed in a furnace or an RTA (Rapid Thermal Anneal) apparatus. Subsequently, an electrode material made of Pt is formed on the upper surface of the dielectric thin film by sputtering or CVD, and then the electrode material made of Pt is processed to form the electrode material and the dielectric thin film into a desired shape. After the resist pattern is formed, the capacitor insulating film 11 and the upper electrode 12 are formed by etching until the surface of the buried insulating film 10 is exposed by a dry etching method using a gas containing chlorine or fluorine. The upper electrode 12 is formed to face the lower electrode 8. The film thickness of the upper electrode 12 is in the range of 50 nm to 100 nm. The lower electrode 8, the capacitive insulating film 11 and the upper electrode 12 constitute a capacitive element 14.

  Next, as shown in FIG. 4B, the upper surface of the upper electrode 12, the side surface of the upper electrode 12 exposed by the etching, the side surface of the capacitor insulating film 11, and the surface of the buried insulating film 10 are covered. An insulating hydrogen barrier film 13 made of aluminum oxide is formed by a CVD method or a sputtering method in a thickness range of 5 nm to 100 nm.

  Although not shown in FIG. 4B, the insulating hydrogen barrier film 13 located on the surface of the buried insulating film 10 is a region other than the region where the capacitive element 14 is formed (for example, the active region 3 and It may be removed by etching in a region where a contact hole for connecting a bit line is formed.

According to the manufacturing method of the semiconductor memory device according to the present embodiment, the buried insulating film 10 is formed by the insulating reaction preventing film 9 formed so as to be in contact with the side surface of the lower electrode 8 including the conductive oxygen barrier film 8b. In the step (step corresponding to FIG. 3A), it is possible to prevent the conductive oxygen barrier film 8b from being reduced by the catalytic action of hydrogen. In addition, there is no shape defect in the conductive oxygen barrier film 8b. As a result, the oxygen barrier property of the conductive oxygen barrier film 8b does not deteriorate, oxygen can be prevented from entering the contact plug 6, and the contact resistance of the contact plug 6 can be prevented from increasing. In particular, when the insulating film 10a to be the buried insulating film 10 is formed by a plasma CVD method, it is possible to effectively prevent the source gas, SiH ₄ or NH _3, from reducing the oxygen barrier film 8b. Further, the hydrogen barrier film 7 can prevent hydrogen from entering the capacitive insulating film 11 from below the lower electrode.

  In the first and second embodiments, as the reaction preventing film 9, a film containing a polymer formed by polymerization of TEOS is used, but a silicon nitride film may be used. Also in this case, the silicon nitride film has an effect of preventing reaction because it has an effect of blocking hydrogen and plasma. Further, no peeling occurs between the insulating reaction preventing film 9 and the hydrogen barrier film 7.

In the first and second embodiments, SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (0 ≦ x ≦ 1) is used as the capacitor insulating film 11, but the present invention is not limited to this, and the bismuth layer shape is used. Any ferroelectric having a perovskite structure may be used. For example, lead zirconate titanate, barium strontium titanate, or tantalum pentoxide may be used.

  In the first and second embodiments, a silicon nitride film is used as the insulating hydrogen barrier film 7, but at least the surface portion of the insulating hydrogen barrier film 7 may be silicon nitride. Further, the insulating film is not limited to the silicon nitride film, and any insulating film having a hydrogen barrier property may be used. In particular, an insulating film not containing aluminum as a constituent element is preferable from the viewpoint of adhesion with the reaction preventing film 9. For example, a silicon oxynitride film may be used.

In the first and second embodiments, as the oxygen barrier film 8b, a laminated film composed of Ir and IrO ₂ is used in order from the lower layer. However, iridium dioxide (IrO ₂ ) and iridium (IrO) formed sequentially from the lower layer are used. ) And iridium dioxide (IrO ₂ ), ruthenium dioxide (RuO ₂ ), and a laminated film composed of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed from the lower layer. Or a laminated film including at least two of them.

  In the first and second embodiments, TiAlN is used as the conductive hydrogen barrier film 7, but titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride ( TaN), tantalum nitride tantalum (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl), or a laminated film including at least two of these. .

  As described above, the present invention is useful for a semiconductor memory device including a capacitor element using a ferroelectric or high dielectric as a capacitor insulating film, and a manufacturing method thereof.

Sectional drawing of the principal part of the semiconductor memory device which concerns on the 1st Embodiment of this invention (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 2nd Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 2nd Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 2nd Embodiment of this invention. The figure for demonstrating the effect of the semiconductor memory device which concerns on the 1st Embodiment of this invention. Sectional drawing of the principal part of the semiconductor memory device concerning the 1st prior art example The figure explaining the subject in the semiconductor memory device concerning the 1st prior art example Sectional drawing of the principal part of the semiconductor memory device concerning the 2nd prior art example Sectional drawing for demonstrating the manufacturing method of the semiconductor memory device concerning a 2nd prior art example The figure explaining the subject in the case of combining a 1st prior art example and a 2nd prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Active region 4 Gate 4a Gate insulating film 4b Gate electrode 4c Side wall 5 Interlayer insulating film 6 Contact plug 7 Hydrogen barrier film 8 Lower electrode 8a Conductive hydrogen barrier film 8b Conductive oxygen barrier film 8c Conductive Body film 9, 9a Insulating reaction prevention film 10 Embedded insulating film 10a Insulating film to be embedded insulating film 11 Capacitor insulating film 12 Upper electrode 13 Hydrogen barrier film 14 Capacitance element

Claims (4)

An interlayer insulating film formed on the substrate;
An insulating first hydrogen barrier film formed on the interlayer insulating film and having at least a surface portion made of silicon nitride;
A contact plug formed through the interlayer insulating film and the first hydrogen barrier film;
A lower electrode including a conductive oxygen barrier film formed on the first hydrogen barrier film and electrically connected to the contact plug;
An insulating reaction preventing film including a multimer formed by contacting TEOS and formed by contacting at least a side surface of the lower electrode;
A buried insulating film formed on and in contact with the insulating reaction preventing film so as to fill the periphery of the lower electrode;
A capacitive insulating film made of a ferroelectric film provided on the lower electrode and the buried insulating film;
An upper electrode formed on the capacitive insulating film,
The insulating reaction preventing film is formed over and in contact with the first hydrogen barrier film,
The buried insulating film includes a polymer formed by polymerizing TEOS in an amount smaller than that of the polymer formed by polymerizing TEOS contained in the insulating reaction preventing film. the semiconductor memory device characterized in that is. The conductive oxygen barrier film, an iridium dioxide (IrO _2), a laminated film made from a sequentially formed iridium from the lower layer (Ir) and iridium dioxide (IrO _2), ruthenium dioxide (RuO _2), and sequentially formed from the lower layer by any one ruthenium (Ru) and of the laminated film consisting of ruthenium dioxide (RuO ₂₎ that is, or claims, characterized in that it is constituted by a laminated film including at least two of these The semiconductor memory device according to Item 1. Forming an interlayer insulating film on the substrate (a);
Forming an insulating first hydrogen barrier film having at least a surface portion made of silicon nitride on the interlayer insulating film;
A step (c) of forming a contact plug so as to penetrate the interlayer insulating film and the first hydrogen barrier film;
Forming a lower electrode including a conductive oxygen barrier film on the first hydrogen barrier film including the contact plug;
Forming an insulating reaction preventing film on the first hydrogen barrier film so as to cover the lower electrode and the first hydrogen barrier film;
A step (f) of forming a buried insulating film on the insulating reaction preventing film so as to cover the lower electrode;
Removing the buried insulating film and the insulating reaction preventing film so as to expose the upper surface of the lower electrode (g);
After the step (g), a step (h) of forming a capacitive insulating film made of a ferroelectric film on the lower electrode and the buried insulating film;
And (i) forming an upper electrode on the capacitive insulating film ,
The step (e) by atmospheric pressure CVD using TEOS and ozone as a raw material, it saw including a step of forming a film comprising a multimer formed TEOS is polymerized,
The buried insulating film includes a polymer formed by polymerizing TEOS in an amount smaller than that of the polymer formed by polymerizing TEOS contained in the insulating reaction preventing film. A method for manufacturing a semiconductor memory device. In the step (h) and the step (i), etching is performed until the surface of the buried insulating film is exposed, thereby forming the capacitive insulating film and the upper electrode.
After the step (h) and the step (i), the upper surface of the upper electrode, the side surface of the upper electrode exposed by the etching, the side surface of the capacitive insulating film, and the surface of the buried insulating film are covered. 4. The method of manufacturing a semiconductor memory device according to claim 3 , further comprising a step (j) of forming an insulating second hydrogen barrier film.

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