JP4002882B2 - Capacitor element, semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a capacitor element having a metal oxide as a capacitor insulating film, a semiconductor memory device having the capacitor element, and a method of manufacturing the same.

  In recent years, with the advancement of digital technology in electronic devices, the tendency to process and store large volumes of data has been promoted, and the functions required for electronic devices have become more sophisticated, and semiconductors used in electronic devices. The miniaturization of the dimensions of the device and the semiconductor elements constituting the semiconductor device is rapidly progressing.

  Along with this, for example, in order to realize high integration of dynamic RAM devices, a technique of using a high dielectric as a capacitive insulating film instead of conventional silicon oxide or silicon nitride has been widely studied and developed. .

  Furthermore, research and development on ferroelectric films having spontaneous polarization characteristics have been actively conducted with the aim of putting into practical use a nonvolatile RAM device capable of high-speed write and read operations at an unprecedented low operating voltage. Yes. In a semiconductor memory device using such a high dielectric material or a ferroelectric material as a capacitor insulating film, a stack type memory cell is used instead of a conventional planar type memory cell for a highly integrated memory element having a memory capacity of a megabit class. It has become like this.

  A conventional semiconductor memory device will be described below with reference to the drawings.

  FIG. 15 shows a cross-sectional structure of a main part of a conventional semiconductor memory device disclosed in Japanese Patent Laid-Open No. 11-8355.

  As shown in FIG. 15, the conventional semiconductor memory device includes a source / drain region 102 formed on a semiconductor substrate 101 and a gate electrode 104 formed on a channel region of the semiconductor substrate 101 with a gate insulating film 103 interposed therebetween. The transistor 105 is formed. An interlayer insulating film 106 covering the entire surface including the transistor 105 is formed on the semiconductor substrate 101, and a contact plug 107 electrically connected to one of the source / drain regions 102 is formed on the interlayer insulating film 106. Is formed.

An insulating hydrogen barrier layer 108 made of silicon nitride (Si ₃ N ₄ ) is formed on the interlayer insulating film 106, and a conductive hydrogen barrier layer made of titanium nitride (TiN) is formed on the upper end portion of the contact plug 107. 109 is formed.

A lower electrode 110 containing iridium dioxide (IrO ₂ ) or ruthenium dioxide (RuO ₂ ) is formed on the insulating hydrogen barrier layer 108 so as to be connected to the conductive hydrogen barrier layer 109.

A buried insulating film 111 made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or the like is formed between the lower electrodes 110 on the insulating hydrogen barrier layer 108. Yes.

On the buried insulating film 111 including the lower electrode 110, capacitive insulation made of a ferroelectric material such as lead zirconate titanate (Pb (Zr, Ti) O ₃ ) or strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ). A film 112 is formed, and an upper electrode 113 containing iridium dioxide or ruthenium dioxide is formed on the capacitor insulating film 112. An insulating hydrogen barrier layer 114 made of silicon nitride or the like is formed on the upper electrode 113.

  However, the conventional semiconductor memory device has the following two problems.

  First, there is a problem that the conductive oxide film made of iridium dioxide or ruthenium dioxide constituting the lower electrode 110 and serving as a barrier against oxygen is reduced by hydrogen generated at the time of manufacture and the barrier property against oxygen deteriorates. is doing.

  Secondly, there is a problem in that the high dielectric or ferroelectric constituting the capacitor insulating film 112 is reduced by hydrogen generated at the time of manufacture, and the electrical characteristics as the capacitor are deteriorated.

  First, the first problem in which the lower electrode having oxygen barrier properties is reduced during manufacturing will be described with reference to FIGS. 16 (a) and 16 (b).

As shown in FIG. 16A, after patterning the lower electrode 110 containing iridium dioxide or ruthenium dioxide, when forming the buried insulating film 111A, monosilane (SiH ₄ ) or ammonia (NH ₃ ) as a source gas is formed. ) Easily reduces iridium dioxide or ruthenium dioxide. This reduction reaction becomes particularly apparent when a plasma CVD method is used as a film forming means for the buried insulating film 111A.

  As a result, the diffusion barrier property against oxygen atoms in the lower electrode 111 is deteriorated, and as shown in FIG. 16B, the capacitive insulating film 112 made of a high dielectric material or a ferroelectric material formed on the lower electrode 110 is formed. At the time of oxygen annealing of about 650 ° C. to 800 ° C. essential for crystallization, oxygen ions diffused from the capacitive insulating film 112 diffuse inside the lower electrode 110 to the interface with the contact plug 107, thereby reducing contact resistance. Increased contact failure occurs.

  Next, a second problem in which a capacitive insulating film made of a high dielectric material or a ferroelectric material is reduced during manufacturing will be described with reference to FIG.

  In an actual semiconductor memory device, as shown in FIG. 15 or FIG. 17, a plurality of capacitive elements and transistors are two-dimensionally arranged in a so-called array. As described above, when the capacitor insulating film 112 of the capacitor elements arranged in an array is formed of a high dielectric material or a ferroelectric material, a metal oxide is often used. Therefore, of the capacitive elements arranged in an array, the reduction of the capacitive element located at the peripheral portion 100 by hydrogen ions is provided on the insulating hydrogen barrier layer 108 provided on the lower part of the capacitive element and on the upper part. This is impossible only with the insulating hydrogen barrier layer 114. This is because, as shown in FIG. 17, although diffusion of hydrogen ions from above and below the semiconductor substrate 101 can be prevented, among the plurality of capacitors arranged in an array, the capacitor located at the peripheral portion 100 This is because diffusion of hydrogen ions from a direction parallel to the substrate surface (lateral direction) cannot be prevented.

  By the way, Japanese Patent Laid-Open No. 2001-237393 discloses a configuration in which one capacitive element in a semiconductor memory device is completely covered with a hydrogen barrier layer, but a plurality of capacitive quanta are arranged on a two-dimensional array. In the semiconductor memory device, the deterioration of the characteristics of the capacitor cannot be prevented unless all of the plurality of capacitors can be completely covered with the hydrogen barrier layer.

  Japanese Patent Application Laid-Open No. 11-126881 discloses a semiconductor memory device in which a plurality of capacitive elements are completely covered with a hydrogen barrier layer. However, this publication does not show means for applying a voltage to the upper electrode 110 shown in FIG. Here, if a contact hole for applying a voltage to the upper electrode 110 is provided, the hydrogen barrier layer 111 covering the upper electrode 110 must be etched. At this time, if etching for opening the hydrogen barrier layer 111 is performed, Japanese Patent Application Laid-Open No. 2001-44376 discloses hydrogen generated during the ashing process of the resist performed after the opening, and subsequent wiring process, that is, filling the plug into the contact hole In addition, it is described that the capacitance element is deteriorated by hydrogen generated by a series of processes such as wiring formation and patterning, wiring sintering process with hydrogen gas, and formation of an insulating film between the wirings.

  As described above, in the semiconductor memory device according to the conventional example, it is difficult to completely cover the memory cell array including the plurality of capacitor elements arranged in an array with the hydrogen barrier layer.

  The first object of the present invention is to solve the above-mentioned conventional problems and maintain the oxygen barrier property of the lower electrode in the capacitive element, and the capacitive insulating film made of a metal oxide of the capacitive element is reduced. The second object is to prevent this, and furthermore, it is possible to reliably prevent the deterioration of the characteristics of the capacitive element even when the memory cell array is covered by one or more blocks. The purpose of 3.

  In order to achieve the first object, the present invention has a configuration in which the side surface of the lower electrode in the capacitive element is covered with a first insulating barrier layer that prevents diffusion of oxygen and hydrogen, and the second object is achieved. Therefore, the side surface of the capacitive insulating film in the capacitive element is covered with a second insulating barrier layer that prevents hydrogen diffusion, and in order to achieve the third object, an insulating barrier layer that prevents hydrogen diffusion is used. The capacitor element is configured to cover one or more blocks included in the memory cell array.

Specifically, engaging Ru capacity element in the present invention, the first object to achieve the, the lower electrode made of a metal oxide formed so as to protrude from the periphery on the lower electrode capacitor insulating film And an upper electrode formed on the capacitor insulating film and a buried insulating film filling the periphery of the lower electrode below the capacitor insulating film . The lower electrode is made of a conductive oxide and is a conductive barrier that prevents diffusion of oxygen. An insulating barrier layer that prevents diffusion of hydrogen is formed so as to include at least one side surface of the conductive barrier layer among the side surfaces of the lower electrode.

According to the capacitive element of the present invention, the insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least the side surface of the conductive barrier layer among the side surfaces of the lower electrode. Diffusion of hydrogen into the lower electrode, which occurs during film formation, is suppressed by the insulating barrier layer formed on the side surface of the lower electrode. As a result, when the conductive barrier layer that prevents diffusion of oxygen that constitutes the lower electrode is made of, for example, a metal oxide, the conductive barrier layer can be prevented from being reduced by hydrogen. Sex can be maintained.

In the capacitive element of the present invention, the conductive barrier layer preferably includes a layer made of a metal oxide.

In the capacitive element of the present invention , the embedded insulating film is preferably formed in an atmosphere containing hydrogen.

In the capacitive element of the present invention , the embedded insulating film is preferably made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

In the capacitive element of the present invention , it is preferable that the insulating barrier layer also prevents oxygen diffusion.

In the capacitor according to the aspect of the invention , it is preferable that the conductive barrier layer includes a stacked film including a first conductive barrier layer that prevents diffusion of oxygen and hydrogen and a second conductive barrier layer that prevents diffusion of oxygen. .

  In this case, the first conductive barrier layer includes titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), and tantalum aluminum nitride ( It is preferable that the film is made of any one of TaAlN) and tantalum aluminum (TaAl) or a laminated film including at least two of them.

In this case, the second conductive barrier layer is formed of iridium dioxide (IrO ₂ ), iridium (Ir) and iridium dioxide (IrO ₂ ) sequentially formed from the lower layer, and ruthenium dioxide (RuO _2). ), And a laminated film including ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed from the lower layer, or a laminated film including at least two of them. Preferably it is.

The capacitive element of the present invention preferably further includes a second insulating barrier layer that is formed on the upper surface of the upper electrode and the side surfaces of the upper electrode, the capacitive insulating film, and the buried insulating film, and prevents hydrogen diffusion.

Semiconductors storage equipment Ru engaged to the present invention is to achieve the first object, it is formed on a semiconductor substrate, formed so as to cover the transistor having a source region and a drain region, a transistor on a semiconductor substrate an interlayer insulating film, a contact plug formed to be connected interlayer insulating film on the source region or the drain region and electrically transistors, Ru engagement with the invention the lower electrode is formed on the contact plug Description And a quantity element.

According to the semiconductor memory device of the present invention includes the engagement Ru capacity element to the present invention, the insulating diffusion of the lower electrode is formed on the side surface of the lower electrode of the hydrogen generated during the formation of the insulator film Suppressed by the barrier layer. As a result, when the conductive barrier layer that prevents diffusion of oxygen constituting the lower electrode is made of, for example, a metal oxide, reduction of the conductive barrier layer by hydrogen can be prevented, thereby preventing deterioration of the characteristics of the capacitor element. be able to.

Manufacturing method of engaging Ru semiconductors memory device of the present invention is to achieve the first object, after forming a gate electrode on a semiconductor substrate, each source region and a drain region on the side of the gate electrode in the semiconductor substrate A first step of forming a transistor by forming, a second step of forming an interlayer insulating film over a semiconductor substrate including the transistor, and the source or drain region electrically connected to the interlayer insulating film. A third step of forming a contact plug, and a fourth step of forming a first conductive film including a conductive barrier layer made of a conductive oxide and preventing diffusion of oxygen on the interlayer insulating film, A fifth step of forming a lower electrode from the first conductive film on the interlayer insulating film by patterning the first conductive film so as to be electrically connected to the contact plug; A sixth step of forming an insulating barrier layer for preventing diffusion of hydrogen so as to cover the upper surface and side surfaces of the lower electrode, and after forming the first insulating film on the insulating barrier layer, A seventh step of planarizing the insulating film and the insulating barrier layer so as to expose the lower electrode; and on the planarized first insulating film and insulating barrier layer including the exposed lower electrode. , An eighth step of forming a second insulating film made of a metal oxide, a second conductive film on the second insulating film, a second conductive film so as to include a lower electrode, By patterning the second insulating film and the first insulating film, the upper electrode is formed from the second conductive film on the lower electrode, the capacitive insulating film is formed from the second insulating film, and the first insulating film is formed. And a ninth step of forming a buried insulating film filling the periphery of the lower electrode from the insulating film.

According to the method for manufacturing a semiconductor memory device of the present invention , the first conductive film is patterned so as to be electrically connected to the contact plug, and the lower electrode is formed from the first conductive film on the interlayer insulating film. Thereafter, an insulating barrier layer for preventing hydrogen diffusion is formed on the interlayer insulating film so as to cover the side surface of the lower electrode. Therefore, before forming the buried insulating film for filling the lower electrode, the insulating barrier layer is formed on the upper surface and the side surface of the lower electrode, so that the conductive barrier layer that prevents the diffusion of oxygen constituting the lower electrode is a metal. In the case of an oxide, the conductive barrier layer can be prevented from being reduced by hydrogen, so that the conductive barrier layer can maintain a barrier property against oxygen.

In the method for manufacturing a semiconductor memory device of the present invention , the buried insulating film is preferably formed in an atmosphere containing hydrogen.

In the method for manufacturing a semiconductor memory device of the present invention, the buried insulating film is made of silicon oxide (SiO 2). ₂ ) Or silicon nitride (Si ₃ N ₄ ).

In the method for manufacturing a semiconductor memory device of the present invention , the fourth step includes a step of forming a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a second conductive barrier layer that prevents diffusion of oxygen. Preferably including the step of forming.

In the method of manufacturing a semiconductor memory device of the present invention, after the ninth step, the second insulating barrier for preventing hydrogen diffusion on the upper surface of the upper electrode and the side surfaces of the upper electrode, the capacitor insulating film, and the buried insulating film is provided. It is preferable to further include a tenth step of forming the layer.

  According to the capacitive element of the present invention, even when the conductive barrier layer that prevents diffusion of oxygen constituting the lower electrode is made of a metal oxide, reduction of the conductive barrier layer by hydrogen can be prevented. The conductive barrier layer can maintain a barrier property against oxygen.

  According to the semiconductor memory device of the present invention, since the capacitor element according to the present invention is included, deterioration of characteristics due to hydrogen during the manufacture of the capacitor element can be prevented.

  According to the method for manufacturing a semiconductor memory device according to the present invention, since the capacitive element according to the present invention is formed, it is possible to prevent deterioration of characteristics due to hydrogen during the manufacturing of the capacitive element.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A shows a cross-sectional configuration of a main part of a semiconductor memory device including a capacitive element according to the first embodiment of the present invention.

  As shown in FIG. 1A, the semiconductor memory device according to the first embodiment includes a plurality of cell transistors 20 made of MOSFETs formed on a semiconductor substrate 11 made of, for example, silicon (Si), and each cell transistor 20. The capacitor element 30 is formed for each cell transistor 20 on the interlayer insulating film 13 covering the substrate. Each cell transistor 20 is partitioned and insulated from each other by a shallow trench isolation (STI) 12 formed on the semiconductor substrate 11.

  Each cell transistor 20 includes a source / drain region 21 formed on the semiconductor substrate 11 and a gate electrode 23 formed on the channel region of the semiconductor substrate 11 via a gate insulating film 22.

  Each capacitive element 30 includes a lower electrode 31, a capacitive insulating film 32, and an upper electrode 33, which are sequentially stacked from the substrate side.

As shown in FIG. 1B, the lower electrode 31 is made of titanium aluminum nitride (TiAlN) having a film thickness of about 40 nm to 100 nm and has a first conductive barrier layer 31a for preventing diffusion of oxygen and hydrogen. A second conductive barrier layer 31b made of iridium (Ir) having a thickness of about 50 to 100 nm and preventing diffusion of oxygen, and a third conductive layer made of iridium dioxide (IrO ₂ ) having a thickness of about 50 to 100 nm and preventing diffusion of oxygen. And a laminated film of a conductive layer 31d made of platinum (Pt) having a thickness of about 50 nm to 100 nm.

The capacitor insulating film 32 has a bismuth layered perovskite structure with a film thickness of about 50 nm to 150 nm. Strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) (where x is 0 ≦ x ≦ 1 The upper electrode 33 is made of platinum having a thickness of about 50 nm to 100 nm.

As shown in FIG. 1A, an interlayer insulating film 13 made of, for example, silicon oxide (SiO ₂ ) is formed on the semiconductor substrate 11 so as to cover each cell transistor 20. A plurality of contacts made of tungsten (W) or polysilicon whose lower end portion is electrically connected to one of the source / drain regions 21 and whose upper end portion is electrically connected to the lower electrode 31 of each capacitor 30. A plug 14 is formed.

The side surface of the lower electrode 31 and the region on the side of the lower electrode 31 on the interlayer insulating film 13 are made of, for example, aluminum oxide (Al ₂ O ₃ ) having a film thickness of about 5 nm to 100 nm, and prevent the diffusion of oxygen and hydrogen. The insulating barrier layer 15 is covered.

  Here, the diameter in the substrate surface direction of the lower electrode 31 is smaller than the dimension of the diameter in the substrate surface direction of the capacitive insulating film 32 and the upper electrode 33, and therefore the peripheral portions of the capacitive insulating film 32 and the upper electrode 33 are the lower electrode. It protrudes from the peripheral part of 31.

A region on the side of the lower electrode 31 and below the protruding portion of the capacitive insulating film 32 is buried with a buried insulating film 16 made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  The buried insulating film 16 electrically insulates the lower electrodes 31 adjacent to each other, and the surface thereof is flattened so as to have almost the same height as the surface of the lower electrode 31.

  The capacitor insulating film 32, the upper electrode 33, and the buried insulating film 16 are formed by etching using the same mask, while the first insulating barrier layer 15 includes the upper electrode 33, the capacitor insulating film 32, and the like. Etched with a different mask.

  The upper surface of the upper electrode 33 and the side surfaces of the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are made of, for example, aluminum oxide having a thickness of about 5 nm to 100 nm, and a second insulating barrier layer that prevents diffusion of hydrogen. 17. At this time, the second insulating barrier layer 17 is in contact with the upper surface of the insulating barrier layer 15 in a region on the side of the lower electrode 31, that is, a region on the lower side of the buried insulating film 16. As a result, the side surface of the lower electrode 31 is covered with the first insulating barrier layer 15 that prevents diffusion of oxygen and hydrogen. In addition, the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are formed without gaps between the first insulating barrier layer 15 that prevents diffusion of oxygen and hydrogen and the second insulating barrier layer 17 that prevents diffusion of hydrogen. Covered.

  Here, the first insulating barrier layer 15 and the second insulating barrier layer 17 are not provided in a region other than the capacitor 30, for example, a region where a contact hole to the source / drain region 21 is formed.

  Hereinafter, a method for manufacturing a semiconductor memory device including the capacitive element configured as described above will be described.

  2 (a) to 2 (c), 3 (a), and 3 (b) show cross-sectional structures in the order of steps of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention. .

  First, as shown in FIG. 2A, a gate insulating film 22 and a gate electrode 23 are formed on a semiconductor substrate 11 made of silicon, and sidewall insulating films are formed on the side surfaces of the gate insulating film 22 and the gate electrode 23. 24 is formed. Subsequently, impurities are implanted into the semiconductor substrate 11 using the gate electrode 23 and the sidewall insulating film 24 as a mask, thereby forming the source / drain region 21. Here, if impurity implantation is performed before the sidewall insulating film 24 is formed, the source / drain region 21 can be configured to have an LDD structure or an extension structure. Thereafter, an interlayer insulating film 13 made of silicon oxide is deposited over the entire surface including the plurality of cell transistors 20 on the semiconductor substrate 11 by CVD. Subsequently, the upper surface of the deposited interlayer insulating film 13 is planarized using a chemical mechanical polishing (CMP) method or the like. Subsequently, a contact hole is formed in one of the source / drain regions 21 of each cell transistor 20 in the interlayer insulating film 13 by a lithography method and a dry etching method, and a conductor film made of tungsten or polysilicon is formed in each contact by a CVD method. Deposit to fill the hole. Subsequently, the deposited conductor film is etched back or chemically mechanically polished to remove the conductor film on the interlayer insulating film 13, thereby forming a plurality of contact plugs 14.

Next, a first conductive barrier layer made of titanium aluminum nitride for preventing diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 including the plurality of contact plugs 14 by sputtering, for example, and made of iridium for preventing diffusion of oxygen. A second conductive barrier layer, a third conductive barrier layer made of iridium dioxide for preventing oxygen diffusion, and a conductive layer made of platinum are sequentially deposited to form a lower electrode formation film. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plug 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. After that, the first insulation which is made of aluminum oxide having a film thickness of about 5 nm to 100 nm and prevents diffusion of oxygen and hydrogen so as to cover the upper surface and the side surface of the lower electrode 31 on the interlayer insulating film 13 by sputtering or CVD. The conductive barrier layer 15 is formed. Here, it is preferable to perform heat treatment in an oxidizing atmosphere after the formation of the first insulating barrier layer 15, because aluminum oxide constituting the first insulating barrier layer 15 is densified. Subsequently, silicon oxide or silicon nitride having a film thickness of about 400 nm to 600 nm is formed so as to cover the first insulating barrier layer 15 by CVD in an atmosphere containing hydrogen using, for example, monosilane (SiH ₄ ) as a raw material. A buried insulating film 16 made of is deposited.

  Next, as shown in FIG. 2B, each of the buried insulating film 16 and the first insulating barrier layer 15 is planarized by using the CMP method until each lower electrode 31 is exposed, thereby making each The periphery of the lower electrode 31 is buried with a buried insulating film 16. Therefore, the upper surface of the lower electrode 31 is almost the same height as the exposed surfaces of the buried insulating film 16 and the first insulating barrier layer 15.

Next, as shown in FIG. 2C, the first insulating barrier layer 15 and the buried insulating film are formed by a metal organic decomposition method (MOD method), a metal organic chemical vapor deposition method (MOCVD method), or a sputtering method. A capacitive insulating film made of strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) having a bismuth layered perovskite structure with a film thickness of about 50 nm to 150 nm over the entire surface of 16 and the lower electrode 31. A formation film 32A is formed. Subsequently, an upper electrode forming film 33A made of platinum having a film thickness of about 50 nm to 100 nm is formed on the capacitor insulating film forming film 32A by sputtering. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide constituting the capacitive insulating film forming film 32A.

  Next, as shown in FIG. 3A, a resist pattern (not shown) is formed on the upper electrode forming film 33A by lithography, and the upper electrode forming film 33A, The capacitor insulating film forming film 32A and the embedded insulating film 16 are sequentially dry-etched to form the upper electrode 33 from the upper electrode forming film 33A and the capacitor insulating film 32 from the capacitor insulating film forming film 32A. As a result, the capacitive element 30 including the lower electrode 31, the capacitive insulating film 32, and the upper electrode 33 electrically connected to the contact plug 14 is formed.

  Here, the first insulating barrier layer 15 is not patterned, and the etching is terminated when the first insulating barrier layer 15 is exposed during the etching of the buried insulating film 16.

  Next, as shown in FIG. 3B, the upper surface and side surfaces of the upper electrode 33, the capacitor insulating film 32, and the buried insulating film 16 are formed on the first insulating barrier layer 15 by CVD or sputtering. A second insulating barrier layer 17 made of aluminum oxide having a thickness of about 5 nm to 100 nm and preventing hydrogen diffusion is formed so as to cover the side surfaces of the first insulating barrier layer 17. As a result, the second insulating barrier layer 17 is in contact with the upper surface of the first insulating barrier layer 15 without a gap in the region on the side of the lower electrode 31, here on the side of the lower side of the buried insulating film 16. Become.

  Note that a region other than the capacitor 30 in the first insulating barrier layer 15 and the second insulating barrier layer 17, for example, a region for forming another contact hole with the source / drain region 21 is removed by etching. .

  As described above, according to the first embodiment, the first insulating barrier layer 15 that prevents the diffusion of oxygen and hydrogen covers the side surface of the lower electrode 31 of the capacitive element 30. It is possible to prevent a conductive oxide such as iridium oxide serving as a barrier from being reduced by hydrogen and deteriorating its oxygen barrier property.

  Furthermore, since the second insulating barrier layer 17 that prevents diffusion of hydrogen covers the entire capacitive element 30 without contact with the first insulating barrier layer 15 that prevents diffusion of oxygen and hydrogen, the capacitive insulating film 32 is covered. It can prevent that the metal oxide which comprises is reduced by hydrogen and the electrical property of the capacitive element 30 deteriorates.

  Hereinafter, the electrical characteristics of the semiconductor memory device according to the first embodiment and the semiconductor memory device according to the conventional example will be compared.

  First, evaluation results of contact resistance between the contact plug 14 and the lower electrode 31 are shown.

  FIG. 4 shows the measurement results of the first embodiment and the conventional example of in-plane contact resistance in a silicon wafer having a diameter of about 20.3 cm (equivalent to 8 inches). As shown in FIG. 4, in the case of the semiconductor memory device according to the conventional example, the contact resistance greatly varies from 45Ω to 7000Ω. This is because iridium dioxide, which is a conductive oxide serving as an oxygen barrier of the lower electrode 110 according to the conventional example, is reduced by hydrogen and the oxygen barrier property deteriorates, which is necessary for crystallization of high dielectrics and ferroelectrics. This is because oxygen diffuses in the lower electrode 110 during the high-temperature oxygen annealing, and the surface of the contact plug 107 is oxidized. On the other hand, in the case of the semiconductor memory device according to the first embodiment, the contact resistance is in the range of 25Ω to 35Ω within the wafer surface, the variation is extremely small, and the resistance value is also 25Ω to 40Ω, realizing low resistance. You can see that it is made.

  Next, evaluation results of reduction resistance in the semiconductor memory device according to the first embodiment are shown.

  FIG. 5 is for evaluation, and shows the respective residual polarization (2Pr) values of the capacitive element 30 before and after the hydrogen annealing treatment at 400 ° C. is performed on the capacitive element 30. As shown in FIG. 5, it can be seen that the capacitive element 30 according to the first embodiment does not substantially change the remanent polarization characteristics even when the hydrogen annealing process is performed, and the reduction by hydrogen can be sufficiently prevented. As described above, the electrical characteristics of the capacitor and the semiconductor memory device according to the first embodiment are remarkably improved.

(Modification of the first embodiment)
FIGS. 6A to 6C are first to third modifications of the semiconductor memory device according to the first embodiment of the present invention. The first insulating barrier covers the lower electrode and its side surface. The cross-sectional structure with the vicinity of the layer is shown. Here, in FIG. 6A to FIG. 6C, the same components as those shown in FIG.

  First, as shown in the first modified example of FIG. 6A, the upper end portion of the first insulating barrier layer 15 that covers the side surface of the lower electrode 31 does not necessarily need to cover the entire side surface of the lower electrode 31. What is necessary is just to form so that the side surface of the 3rd conductive barrier layer 31c which consists of iridium dioxide which is a conductive metal oxide at least may be covered.

  Further, the height of the upper surface of the buried insulating film 16 in this case may be the same as the upper end of the first insulating barrier layer 15 as shown in the first modification of FIG. As shown in the second modification of (b), it may be the same as the upper surface of the conductive layer 31d of the lower electrode 31, and as shown in the third modification of FIG. 6 (c), the first insulating barrier. It may be formed so as to be lower than the upper end of the layer 15.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 shows a cross-sectional configuration of a main part of a semiconductor memory device including a capacitive element according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG.

  As shown in FIG. 7, in the second embodiment, the second insulating barrier layer 17 is formed directly on the interlayer insulating film 13, and the first insulating barrier layer 15A has a gate length of It is divided between the capacitive elements 30 adjacent in the direction.

  FIG. 8A and FIG. 8B show the main steps of the method of manufacturing the semiconductor memory device according to the second embodiment.

  Here, only differences from the first embodiment will be described.

  In the first embodiment, as shown in FIG. 3A, the same mask is used to pattern the embedded insulating film 16 in which the capacitive insulating film 32, the upper electrode 33, and the lower electrode 31 constituting the capacitive element 30 are embedded. In this case, the first insulating barrier layer 15 is not patterned.

  On the other hand, as shown in FIGS. 7 and 8A, in the semiconductor memory device according to the second embodiment, the same process as that of the upper electrode 33 is performed in the etching process for patterning the upper electrode 33, the capacitor insulating film 32, and the like. After the embedded insulating film 16 is etched using the mask, the first insulating barrier layer 15 is etched to form the first insulating barrier layer 15A. At this time, an etching gas mainly composed of fluorocarbon is used for etching the buried insulating film 16 made of silicon oxide or silicon nitride, and chlorine gas is used for etching the first insulating barrier layer 15A made of aluminum oxide. An etching gas having a main component is used.

  Next, as shown in FIG. 8B, in the subsequent step of forming the second insulating barrier layer 17 for preventing hydrogen diffusion, the second insulating barrier layer 17 is formed of the lower electrode 31. And comes into contact with the end face of the first insulating barrier layer 15 located below the buried insulating film 16.

  In the second embodiment as well, a region other than the capacitive element 30 in the first insulating barrier layer 15A and the second insulating barrier layer 17, for example, a region where another contact hole is formed with the source / drain region 21. Is removed by etching.

  As described above, according to the second embodiment, as in the first embodiment, the first insulating barrier layer 15A that prevents diffusion of oxygen and hydrogen covers the side surface of the lower electrode 31 of the capacitive element 30. Therefore, it is possible to prevent a conductive oxide such as iridium oxide which is an oxygen barrier constituting the lower electrode 31 from being reduced by hydrogen and deteriorating its oxygen barrier property.

  Further, since the second insulating barrier layer 17 that prevents diffusion of hydrogen covers the entire capacitive element 30 without contacting with the first insulating barrier layer 15A that prevents diffusion of oxygen and hydrogen, the capacitive insulating film 32 is covered. It can prevent that the metal oxide which comprises is reduced by hydrogen and the electrical property of the capacitive element 30 deteriorates. As a result, also in the second embodiment, a semiconductor memory device including the capacitive element 30 having excellent electrical characteristics similar to the measurement results shown in FIGS. 4 and 5 can be realized.

  The second embodiment also has other effects as described below.

  That is, in the step of removing the insulating barrier layers 15 and 17 formed in the region other than the capacitive element 30 on the interlayer insulating film 13, in the first embodiment, the second insulating barrier layer 17 and the first insulating layer It is necessary to perform etching on two layers of the insulating barrier layer 15. On the other hand, in the second embodiment, since only the second insulating barrier layer 17 needs to be etched, the etching time can be greatly shortened. In addition, on the interlayer insulating film 13, although a step is generated between a portion where the capacitor element 30 is provided and a portion where the capacitor element 30 is not provided, the etching pattern is shortened, so that the resist pattern is thinned above the capacitor element 30. Even at the portion, the resist is difficult to disappear during etching, and the process margin can be expanded.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 9A to FIG. 9C are semiconductor memory devices according to the third embodiment of the present invention, and FIG. 9A is a plan configuration of a cell block comprising a plurality of cells constituting a memory cell array. FIG. 9B shows a cross-sectional configuration taken along line IXb-IXb in FIG. 9A, and FIG. 9C shows a cross-sectional configuration taken along line IXc-IXc in FIG. 9 (a) to 9 (c), the same components as those shown in FIG.

As shown in FIG. 9A, on the main surface of the semiconductor substrate 11, for example, 2 ⁿ or (2 ⁿ +1) pieces (where n is a number) along the gate electrode (word line) 23 of the cell transistor 20. The cell block 50 including the lower electrode 31 (which is an integer of 3 or more) is disposed. The capacitive insulating film 32 and the upper electrode 33 of the capacitive element 30 are formed for each cell block 50 so as to cover the plurality of lower electrodes 31 included in the cell block 50.

  Further, as shown in FIGS. 9A and 9C, the second insulating barrier layer 17 covers the two cell blocks 50 adjacent to each other, and the side portion in the direction in which the gate electrode 23 extends. Is in contact with the interlayer insulating film 13. Further, as shown in FIG. 9B, the second insulating barrier layer 17 is formed in the direction intersecting the gate electrode 23 in each cell block 50, that is, on the gate length direction side, as in the second embodiment. The side portion is in contact with the interlayer insulating film 13.

  Thus, the side surface of the lower electrode 31 in the capacitive element 30 is covered with the first insulating barrier layer 15A, and the upper surface of the upper electrode 33 of the capacitive element including the side surface of the embedded insulating film 16 that embeds the lower electrode 31 is included. The side surfaces of the capacitor insulating film 32 and the side surfaces of the capacitor insulating film 32 are covered by the second insulating barrier layer 17 in units of cell blocks (here, in units of two blocks). At this time, the second insulating barrier layer 17 is in contact with the first insulating barrier layer 15A located below the buried insulating film 16 at its end face.

  In addition, as shown in FIGS. 9A and 9C, the upper electrode 33 is electrically connected to any one of the plurality of lower electrodes 31 with respect to the capacitive insulating film 32 of each cell block 50. An opening 32a is provided so as to be connected to the upper electrode 33, and an upper electrode plug 33a is formed by filling a part of the upper electrode 33 in the opening 32a. Here, as an example, the lower electrode 31 positioned at the right end is used as the upper electrode connection electrode 31A, so that the contact plug 14, the upper electrode connection electrode 31A, and the upper electrode plug 33a are connected from the source / drain region 21 of the cell transistor 20. It is possible to apply a predetermined voltage to the upper electrode 33 via the.

  Thus, unlike the cell transistor (first transistor) 20 that is electrically connected to the lower electrode 31 of the capacitive element 30 via the contact plug (first contact plug) 14, the upper electrode connection electrode 31A. Does not constitute the capacitive element 30. Accordingly, the cell transistor (second transistor) 20 electrically connected to the upper electrode connection electrode 31A via the contact plug (second contact plug) 14 is different in operation from the first transistor.

  Thus, in the third embodiment, an operating voltage can be applied to the upper electrode 33 via the cell transistor 20, so that the upper surface of the upper electrode 33, that is, the second insulating barrier layer 17 is applied. There is no need to open contact holes. For this reason, it is not necessary to provide an opening in the second insulating barrier layer 17 covering the cell block 50, so that a resist ashing process, a plug filling process, and a wiring process after the opening are not required. As a result, after the second insulating barrier layer 17 is formed, the capacitive element 30 is not exposed to hydrogen, so that deterioration of the characteristics of the capacitive element 30 can be prevented.

  In the third embodiment, the second insulating barrier layer 17 covers the two cell blocks 50. However, the present invention is not limited to this, and any configuration that covers one or more cell blocks 50 is acceptable. .

  In addition, for the electrical connection between the upper electrode 33 and the cell transistor 20, the upper electrode connection electrode 31A is not necessarily interposed, and the upper electrode plug 33a and the contact plug 14 may be directly connected. However, since all the capacitive elements 30 included in the cell block 50 have the same structure, it is preferable to interpose the upper electrode connection electrode 31A having the same structure as the lower electrode 31 because the process is simplified.

  Hereinafter, a method for manufacturing a semiconductor memory device including the capacitor element and the upper electrode connection electrode configured as described above will be described with reference to the drawings.

  10 (a) to 10 (c), 11 (a), and 11 (b) show a method of manufacturing a semiconductor memory device according to the third embodiment of the present invention. The cross-sectional structure of the order of the process in the IXc-IXc line is shown.

  First, the gate insulating film 22, the gate electrode 23, and the sidewall insulating film 24 shown in FIG. 9B are selectively formed on the semiconductor substrate 11 made of silicon, and then the gate electrode 23 in the semiconductor substrate 11 is formed. A plurality of cell transistors 20 are formed by forming the source / drain regions 21 in the regions on both sides of the cell.

  Next, as shown in FIG. 10A, an interlayer insulating film 13 made of silicon oxide such as BPSG is deposited on the entire surface including the plurality of cell transistors 20 on the semiconductor substrate 11 by CVD. Subsequently, the upper surface of the deposited interlayer insulating film 13 is planarized by a CMP method or the like. Subsequently, a contact hole is formed in one of the source / drain regions 21 of each cell transistor 20 in the interlayer insulating film 13 by a lithography method and a dry etching method, and a conductor film made of tungsten or polysilicon is formed in each contact by a CVD method. Deposit to fill the hole. Subsequently, a plurality of contact plugs 14 are formed by removing the conductor film on the interlayer insulating film 13 from the deposited conductor film by an etch back method or a CMP method. Next, a first conductive barrier layer 31a made of titanium aluminum nitride that prevents diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 including the formed contact plug 14, for example, by sputtering, and iridium that prevents diffusion of oxygen. A second conductive barrier layer made of, a third conductive barrier layer made of iridium dioxide that prevents diffusion of oxygen, and a conductive layer made of platinum are sequentially deposited to form a lower electrode formation film. Here, the film thickness of the first conductive barrier layer 31a that prevents diffusion of oxygen and hydrogen is approximately 40 nm to 100 nm, and the second conductive barrier layer 31b and the second conductive barrier layer 31b that prevent diffusion of oxygen. In addition, the film thickness of the conductive layer is about 50 nm to 100 nm. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plug 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. Thereafter, a first method for preventing diffusion of oxygen and hydrogen is formed of aluminum oxide having a thickness of about 20 nm to 200 nm so as to cover the upper surface and the side surface of the lower electrode 31 on the interlayer insulating film 13 by sputtering or CVD. An insulating barrier layer 15 is formed. Here, it is preferable to perform heat treatment in an oxidizing atmosphere after the formation of the first insulating barrier layer 15, because aluminum oxide constituting the first insulating barrier layer 15 is densified. Subsequently, a buried insulating film made of silicon oxide or silicon nitride having a thickness of about 400 nm to 600 nm so as to cover the first insulating barrier layer 15 by a CVD method using monosilane as a raw material and containing hydrogen. A film 16 is deposited.

  Next, as shown in FIG. 10B, by planarizing the buried insulating film 16 and the first insulating barrier layer 15 until the lower electrode 31 is exposed using the CMP method, The periphery of the electrode 31 is buried with the buried insulating film 16. Therefore, the upper surface of the lower electrode 31 is almost the same height as the exposed surfaces of the buried insulating film 16 and the first insulating barrier layer 15.

Next, as shown in FIG. 10C, the film thickness is 50 nm over the entire surface on the first insulating barrier layer 15, the buried insulating film 16, and the lower electrode 31 by MOD, MOCVD, or sputtering. forming a capacitor insulating film forming film 32A made of tantalum niobate, strontium bismuth _{(SrBi 2 (Ta 1-x} Nb x) 2 O 9) having a bismuth layered perovskite structure of about ～150Nm. Subsequently, the upper portion of the upper electrode connection electrode 31A in the formed capacitor insulating film formation film 32A is selectively removed by lithography and dry etching. As a result, an opening 32a is formed in the capacitor insulating film formation film 32A, and the upper electrode connection electrode 31A is exposed from the formed opening 32a. Subsequently, an upper electrode forming film 33A made of platinum with a film thickness of about 50 nm to 150 nm is formed by sputtering so as to fill the opening 32a on the capacitive insulating film forming film 32A. As a result, the opening 32a is filled with platinum to form the upper electrode plug 33a, and the upper electrode connecting electrode 31A and the upper electrode 33 are electrically connected by the upper electrode plug 33a. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide constituting the capacitive insulating film forming film 32A.

  Next, as shown in FIG. 11A, using a resist mask (not shown) for masking each cell block 50, the upper electrode formation film 33A, the capacitor insulation film formation film 32A, the buried insulation film 16, and The first insulating barrier layer 15 is sequentially dry-etched to form the upper electrode 33 from the upper electrode forming film 33A and the capacitive insulating film 32 from the capacitive insulating film forming film 32A. At this time, a first insulating barrier layer 15A obtained by patterning the first insulating barrier layer 15 is obtained.

  Next, as shown in FIG. 11B, the upper surface and side surfaces of the upper electrode 33 and the capacitor insulating film 32 patterned on the interlayer insulating film 13 for each cell block 50 by the CVD method or the sputtering method, respectively. And a second insulating barrier layer that prevents diffusion of hydrogen and is made of aluminum oxide having a thickness of about 5 nm to 100 nm over the entire surface so as to cover the side surface of the embedded insulating film 16 and the end surface of the first insulating barrier layer 15A. 17 is formed. As a result, the second insulating barrier layer 17 is in contact with the end face of the first insulating barrier layer 15A located below the buried insulating film 16 around the cell block 50. Subsequently, as shown in FIG. 9A, the formed second insulating barrier layer 17 is patterned by a dry etching method so as to include two cell blocks 50 adjacent to each other. However, the patterning of the second insulating barrier layer 17 is not necessarily performed.

  As a modified example of the manufacturing method according to the third embodiment, the upper electrode 33, the capacitor insulating film 32, and the like shown in FIG. 11A are replaced with the cell block 50 as in the manufacturing method according to the first embodiment. In the patterning process every time, the first insulating barrier layer 15 is not patterned, and the first process is continuously performed with the second insulating barrier layer 17 in the subsequent process shown in FIG. The insulating barrier layer 15 may be patterned.

( Reference example of the present invention )
Hereinafter, reference examples of the present invention will be described with reference to the drawings.

12A to 12C show a semiconductor memory device according to a reference example of the present invention. FIG. 12A shows a planar configuration of a cell block including a plurality of cells constituting a memory cell array. FIG. 12B shows a cross-sectional configuration taken along line XIIb-XIIb in FIG. 12A, and FIG. 12C shows a cross-sectional configuration taken along line XIIc-XIIc in FIG. In FIGS. 12A to 12C, the same components as those shown in FIGS. 9A to 9C are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIGS. 12B and 12C, the first insulating barrier layer 45 according to the reference example is formed only on the interlayer insulating film 13, and therefore the contact plug 14 is formed between the interlayer insulating films 13. The insulating film 13 and the first insulating barrier layer 45 are formed so as to penetrate therethrough. Further, the first conductive barrier layer 31 a constituting the lower electrode 31 of the capacitive element 30 is formed on the first insulating barrier layer 45.

Here, as in the first to third embodiments, it is preferable to use aluminum oxide, titanium aluminum oxide, or tantalum aluminum oxide as the first insulating barrier layer 45 that prevents diffusion of oxygen and hydrogen. Silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiON) is preferably used. When silicon nitride or silicon oxynitride is used, the formation of the contact hole when forming the contact plug 14 is easier than aluminum oxide or the like.

  Also, as shown in FIG. 12A, the second insulating barrier layer 17 is formed so as to cover the two cell blocks 50 adjacent to each other. Further, as shown in FIG. 12B, the second insulating barrier layer 17 is in contact with the interlayer insulating film 13 in the direction intersecting with the gate electrode 23 in each cell block 50. Thus, the lower electrode 31 of the capacitive element 30 includes the side surface of the embedded insulating film 16 in which the lower electrode 31 is embedded, and the upper surface and the side surface of the upper electrode 33 of the capacitive element and the side surface of the capacitive insulating film 32 have the second insulating property. The barrier layer 17 covers the cell block unit (here, 2 block units). At this time, the second insulating barrier layer 17 is in contact with the first insulating barrier layer 15 located below the buried insulating film 16 at its end face.

  Further, similarly to the third embodiment, an opening 32a is provided so that the upper electrode 33 is electrically connected to any one of the plurality of lower electrodes 31, and the upper electrode 33 is provided in the opening 32a. The upper electrode plug 33a is formed by being partially filled. Therefore, an operating voltage can be applied to the upper electrode 33 via the cell transistor 20 without opening the second insulating barrier layer 17 that covers the upper surface and side surfaces of the cell block 50. Accordingly, the resist ashing process, the plug filling process, and the wiring process after the opening are not required, and therefore, the capacitor element 30 is not exposed to hydrogen after the second insulating barrier layer 17 is formed. Degradation of the characteristics of the element 30 can be prevented.

In the reference example , as in the third embodiment, the second insulating barrier layer 17 covers the two cell blocks 50. However, the present invention is not limited to this, and one or more cell blocks 50 are included. What is necessary is just the structure covered.

  Further, it is not always necessary to interpose the upper electrode connection electrode 31 </ b> A for electrical connection between the upper electrode 33 and the cell transistor 20.

  Hereinafter, a method for manufacturing a semiconductor memory device including the capacitor element and the upper electrode connection electrode configured as described above will be described with reference to the drawings.

13 (a) to 13 (c), 14 (a), and 14 (b) show a method of manufacturing a semiconductor memory device according to a reference example of the present invention, and XIIc-XIIc in FIG. 12 (a). The cross-sectional structure of the order of the process in a line is shown.

  First, the gate insulating film 22, the gate electrode 23, and the sidewall insulating film 24 shown in FIG. 12B are selectively formed on the semiconductor substrate 11 made of silicon, and then the gate electrode 23 in the semiconductor substrate 11 is formed. A plurality of cell transistors 20 are formed by forming the source / drain regions 21 in the regions on both sides of the cell.

  Next, as shown in FIG. 13A, an interlayer insulating film 13 made of silicon oxide such as BPSG is deposited on the entire surface including the plurality of cell transistors 20 on the semiconductor substrate 11 by CVD. Subsequently, the upper surface of the deposited interlayer insulating film 13 is flattened by a CMP method or the like, and then made of, for example, silicon nitride or aluminum oxide having a thickness of about 20 nm to 200 nm by a CVD method or a sputtering method. A first insulating barrier layer 45 that prevents diffusion is formed. Subsequently, a contact hole is formed in one of the source / drain regions 21 of each cell transistor 20 in the interlayer insulating film 13 and the first insulating barrier layer 45 by lithography and dry etching, and tungsten or A conductor film made of polysilicon is deposited so as to fill each contact hole. Subsequently, a plurality of contact plugs 14 are formed by removing the conductor film on the interlayer insulating film 13 from the deposited conductor film by an etch back method or a CMP method. Thereafter, a first conductive barrier layer 31a made of titanium aluminum nitride that prevents diffusion of oxygen and hydrogen is formed on the interlayer insulating film 13 including the formed contact plug 14 by sputtering, for example, from iridium that prevents diffusion of oxygen. A second conductive barrier layer, a third conductive barrier layer made of iridium dioxide for preventing oxygen diffusion, and a conductive layer made of platinum are sequentially deposited to form a lower electrode formation film. Here, the film thickness of the first conductive barrier layer 31a that prevents diffusion of oxygen and hydrogen is approximately 40 nm to 100 nm, and the second conductive barrier layer 31b and the second conductive barrier layer 31b that prevent diffusion of oxygen. In addition, the film thickness of the conductive layer is about 50 nm to 100 nm. Subsequently, the lower electrode forming film is patterned by the lithography method and the dry etching method so as to include the contact plug 14 to form a plurality of lower electrodes 31 made of the lower electrode forming film. Subsequently, a buried insulating film 16 made of silicon oxide or silicon nitride having a thickness of about 400 nm to 600 nm is formed so as to cover the plurality of lower electrodes 31 by, for example, a CVD method using monosilane as a raw material and containing hydrogen. accumulate.

  Next, as shown in FIG. 13B, the periphery of each lower electrode 31 is buried around the buried insulating film 16 by planarizing the buried insulating film 16 until the lower electrode 31 is exposed using the CMP method. Embed by Therefore, the upper surface of the lower electrode 31 is almost the same height as the exposed surface of the buried insulating film 16.

  Next, as shown in FIG. 13C, a bismuth layered perovskite structure having a thickness of about 50 nm to 150 nm is formed on the entire surface of the buried insulating film 16 and the lower electrode 31 by the MOD method, the MOCVD method, or the sputtering method. A capacitive insulating film forming film 32A made of strontium bismuth tantalum niobate is formed. Subsequently, the upper portion of the upper electrode connection electrode 31A in the formed capacitor insulating film formation film 32A is selectively removed by lithography and dry etching. As a result, an opening 32a is formed in the capacitor insulating film formation film 32A, and the upper electrode connection electrode 31A is exposed from the formed opening 32a. Subsequently, an upper electrode forming film 33A made of platinum with a film thickness of about 50 nm to 150 nm is formed by sputtering so as to fill the opening 32a on the capacitive insulating film forming film 32A. As a result, the opening 32a is filled with platinum to form the upper electrode plug 33a, and the upper electrode connecting electrode 31A and the upper electrode 33 are electrically connected by the upper electrode plug 33a. Thereafter, heat treatment is performed in an oxygen atmosphere at a temperature of about 650 ° C. to 800 ° C. to crystallize the metal oxide constituting the capacitive insulating film forming film 32A.

  Next, as shown in FIG. 14A, using a resist mask (not shown) for masking each cell block 50, the upper electrode formation film 33A, the capacitor insulation film formation film 32A, the buried insulation film 16, and The first insulating barrier layer 45 is sequentially subjected to dry etching to form the upper electrode 33 from the upper electrode forming film 33A and the capacitive insulating film 32 from the capacitive insulating film forming film 32A.

  Next, as shown in FIG. 14B, the upper surface and the side surface of the upper electrode 33 patterned on the interlayer insulating film 13 for each cell block 50 and the capacitive insulating film 32 by the CVD method or the sputtering method, respectively. And a second insulating barrier layer made of aluminum oxide having a thickness of about 5 nm to 100 nm to prevent hydrogen diffusion over the entire surface so as to cover the side surface of the embedded insulating film 16 and the end surface of the first insulating barrier layer 45. 17 is formed. As a result, the second insulating barrier layer 17 is in contact with the end surface of the first insulating barrier layer 45 located below the buried insulating film 16 around the cell block 50. Subsequently, as shown in FIG. 12A, the formed second insulating barrier layer 17 is patterned by a dry etching method so as to include two cell blocks 50 adjacent to each other. However, the patterning of the second insulating barrier layer 17 is not necessarily performed.

As a modification of the manufacturing method according to the reference example , the upper electrode 33 and the capacitor insulating film 32 shown in FIG. 14A are patterned for each cell block 50 as in the manufacturing method according to the first embodiment. In this step, the first insulating barrier layer 45 is not patterned, and in the subsequent step shown in FIG. The barrier layer 45 may be patterned.

In the first to third embodiments and the reference example , strontium bismuth tantalum niobate (SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ ) is used for the capacitor insulating film 32, but this is not limitative. However, any ferroelectric having a bismuth layered perovskite structure may be used. For example, lead zirconate titanate, barium strontium titanate, or tantalum pentoxide may be used.

In the first to third embodiments and reference examples , aluminum oxide (Al ₂ O ₃ ) is used for the first insulating barrier layers 15, 15 A, and 45. Instead, titanium oxide is used. Aluminum (TiAlO) or tantalum aluminum oxide (TaAlO) may be used. In this way, these metal oxides including aluminum oxide can almost completely prevent diffusion of oxygen and hydrogen from the buried insulating film 16 to the lower electrode 31 from the side surface direction. However, as described above, for the first insulating barrier layer 45 according to the reference example , it is preferable to use silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiON) because of its ease of workability.

Similarly, the second insulating barrier layer 17 may use titanium aluminum oxide (TiAlO) or tantalum aluminum oxide (TaAlO) instead of aluminum oxide (Al ₂ O ₃ ). In this way, hydrogen diffusion from the direction perpendicular to and parallel to the substrate surface with respect to the capacitive insulating film 32 can be almost completely suppressed.

In the lower electrode 31 according to the first to third embodiments and the reference example , titanium aluminum nitride (TiAlN) is used as the first conductive barrier layer 31a. Instead, titanium aluminum (TiAlN) is used. ), Titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl), or TiAlN It is preferable that it is comprised by the laminated film containing at least 2 of these. In this way, it is possible to prevent oxygen from diffusing into the contact plug 14 during high-temperature oxygen annealing for crystallization of the high dielectric material or the ferroelectric material constituting the capacitive insulating film 32, and the lower electrode. Hydrogen diffusion from the substrate direction from 31 to the capacitive insulating film 32 can be prevented.

Further, iridium (Ir) is used for the second conductive barrier layer 31b constituting the lower electrode 31, and iridium dioxide (IrO ₂ ) is used for the third conductive barrier layer 31c. I can't.

That is, as the second and third conductive barrier layers 31b and 31c, a single-layer film made of iridium dioxide (IrO ₂ ), a single-layer film made of ruthenium dioxide (RuO ₂ ), and ruthenium ( Any of a laminated film made of Ru) and ruthenium dioxide (RuO ₂ ) may be used. Furthermore, it may be constituted by a further laminated film including at least two of these monolayer films and laminated films, including laminated films made of iridium (Ir) and iridium dioxide (IrO ₂ ). In this case, oxygen is diffused to the contact plug 14 at the time of high-temperature oxygen annealing for crystallization of the high dielectric material or the ferroelectric material constituting the capacitive insulating film 32, and the diffused oxygen is contact plug 14. It is possible to prevent the contact resistance from increasing by oxidizing the surface.

In the first to third embodiments and reference examples , silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) is used for the buried insulating film 16 that fills the region on the side of the lower electrode 31. For this reason, the lower electrodes 31 adjacent to each other are electrically insulated from each other and can be easily flattened.

FIG. 3A is a structural cross-sectional view showing a main part of a semiconductor memory device including a capacitive element according to the first embodiment of the present invention.

(B) is a cross-sectional view showing the lower electrode of the capacitive element according to the first embodiment of the present invention.
(A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor memory device based on the 1st Embodiment of this invention. (A) And (b) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor memory device based on the 1st Embodiment of this invention. 4 is a graph showing a result of measurement of contact resistance between a contact plug and a lower electrode of a capacitive element in the semiconductor memory device according to the first embodiment of the present invention in comparison with a conventional example. 5 is a graph showing measurement results of remanent polarization before and after performing hydrogen annealing of the capacitive element in the semiconductor memory device according to the first embodiment of the present invention. (A)-(c) shows the lower electrode and the vicinity of the 1st insulating barrier layer which covers the side surface in the semiconductor memory device concerning the modification of the 1st Embodiment of this invention, (a) is the 1st. It is a structure sectional view concerning the 1st modification, (b) is a composition sectional view concerning the 2nd modification, and (c) is a composition sectional view concerning the 3rd modification. FIG. 5 is a structural cross-sectional view showing a main part of a semiconductor memory device including a capacitive element according to a second embodiment of the present invention. (A) And (b) shows the manufacturing method of the semiconductor memory device based on the 2nd Embodiment of this invention, and is a structure sectional drawing of the process different from 1st Embodiment. (A)-(c) shows the principal part of the semiconductor memory device based on the 3rd Embodiment of this invention, (a) is a top view which shows the cell block which comprises a memory cell array, (b) is ( It is sectional drawing in the IXb-IXb line of a), (c) is sectional drawing in the IXc-IXc line of (a). (A)-(c) is the structure cross-sectional view of the order of the process in the IXc-IXc line | wire of Fig.9 (a) which shows the manufacturing method of the semiconductor memory device concerning the 3rd Embodiment of this invention. (A) And (b) shows the manufacturing method of the semiconductor memory device based on the 3rd Embodiment of this invention, and is the structure sectional drawing of the order of the process in the IXc-IXc line | wire of Fig.9 (a). (A)-(c) shows the principal part of the semiconductor memory device based on the reference example of this invention, (a) is a top view which shows the cell block which comprises a memory cell array, (b) is (a). It is sectional drawing in the XIIb-XIIb line, (c) is sectional drawing in the XIIc-XIIc line of (a). (A)-(c) shows the manufacturing method of the semiconductor memory device based on the reference example of this invention, and is a structure cross-sectional view of the order of the process in the XIIc-XIIc line | wire of Fig.12 (a). (A) And (b) shows the manufacturing method of the semiconductor memory device which concerns on the reference example of this invention, and is a structure sectional drawing of the order of the process in the XIIc-XIIc line | wire of Fig.12 (a). It is a structure sectional view showing the important section of the conventional semiconductor memory device. (A) And (b) is typical structure sectional drawing showing a mode that a malfunction arises in the lower electrode of the capacitive element in the conventional semiconductor memory device. FIG. 10 is a schematic cross-sectional view showing a state in which a defect occurs in a capacitive insulating film of a capacitive element in a conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Shallow trench isolation 13 Interlayer insulation film 14 Contact plug 15 1st insulating barrier layer 15A 1st insulating barrier layer 16 Buried insulating film 17 2nd insulating barrier layer 20 Cell transistor 21 Source / drain region 22 Gate insulating film 23 Gate electrode 24 Side wall insulating film 30 Capacitor element 31 Lower electrode 31A Upper electrode connection electrode 31a First conductive barrier layer 31b Second conductive barrier layer 31c Third conductive barrier layer 31d Conductive layer 32 capacitive insulating film 32a opening 32A capacitive insulating film forming film 33 upper electrode 33A upper electrode forming film 33a upper electrode plug 45 first insulating barrier layer 50 cell block

Claims (15)

A lower electrode;
A capacitive insulating film made of a metal oxide formed on the lower electrode so as to protrude from its peripheral edge ;
An upper electrode formed on the capacitive insulating film;
A buried insulating film filling the periphery of the lower electrode under the capacitive insulating film ,
The lower electrode includes a conductive barrier layer made of a conductive oxide and preventing oxygen diffusion,
A first insulating barrier layer made of titanium aluminum oxide (TiAlO) or tantalum aluminum oxide (TaAlO) is formed so as to be in contact with at least the side surface of the conductive barrier layer among the side surfaces of the lower electrode. A capacitive element characterized by being made.   The capacitive element according to claim 1, wherein the conductive barrier layer includes a layer made of a metal oxide.   The capacitive element according to claim 1, wherein the buried insulating film is formed in an atmosphere containing hydrogen. The capacitive element according to claim 1, wherein the embedded insulating film is made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).   The capacitive element according to claim 1, wherein the first insulating barrier layer also prevents diffusion of oxygen.   2. The conductive barrier layer includes a laminated film including a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a second conductive barrier layer that prevents diffusion of oxygen. Capacitor element described in 1.   The first conductive barrier layer includes titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium nitride silicide (TiSiN), tantalum nitride (TaN), tantalum nitride silicide (TaSiN), tantalum aluminum nitride (TaAlN), And a tantalum aluminum (TaAl), or a laminated film including at least two of them. The second conductive barrier layer includes iridium dioxide (IrO ₂ ), a laminated film of iridium (Ir) and iridium dioxide (IrO ₂ ) sequentially formed from the lower layer, ruthenium dioxide (RuO ₂ ), and the lower layer. It is characterized by being constituted by any one of laminated films formed of ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) sequentially formed or by a laminated film including at least two of them. The capacitive element according to claim 6. 9. A second insulating barrier layer that is formed on the upper surface of the upper electrode and on the side surfaces of the upper electrode, the capacitor insulating film, and the buried insulating film, and further prevents hydrogen from diffusing. The capacitive element according to any one of the above. A transistor formed on a semiconductor substrate and having a source region and a drain region;
An interlayer insulating film formed on the semiconductor substrate so as to cover the transistor;
A contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the transistor;
A semiconductor memory device comprising: the capacitor element according to claim 1, wherein the lower electrode is formed on the contact plug. A first step of forming a transistor by forming a gate electrode on a semiconductor substrate and then forming a source region and a drain region respectively on the side of the gate electrode in the semiconductor substrate;
A second step of forming an interlayer insulating film on the semiconductor substrate including the transistor;
A third step of forming a contact plug electrically connected to the source region or the drain region in the interlayer insulating film;
A fourth step of forming a first conductive film comprising a conductive barrier layer made of a conductive oxide and preventing diffusion of oxygen on the interlayer insulating film;
A fifth step of forming a lower electrode from the first conductive film on the interlayer insulating film by patterning the first conductive film so as to be electrically connected to the contact plug;
A first insulating barrier layer made of titanium aluminum oxide (TiAlO) or tantalum aluminum oxide (TaAlO) is formed on the interlayer insulating film so as to cover the upper surface and side surfaces of the lower electrode, and prevents diffusion of hydrogen. A sixth step;
Forming a first insulating film on the first insulating barrier layer, and then planarizing the first insulating film and the first insulating barrier layer so as to expose the lower electrode. 7 steps,
On the planarized first insulating film and first insulating barrier layer including the exposed lower electrode, a second insulating film made of a metal oxide, and the second insulating film An eighth step of forming a second conductive film on the substrate;
An upper electrode is formed from the second conductive film on the lower electrode by patterning the second conductive film, the second insulating film, and the first insulating film so as to include the lower electrode. And a ninth step of forming a capacitive insulating film from the second insulating film and forming a buried insulating film filling the periphery of the lower electrode from the first insulating film. Device manufacturing method. 12. The method of manufacturing a semiconductor memory device according to claim 11, wherein the first insulating film to be the buried insulating film is formed in an atmosphere containing hydrogen. 13. The method for manufacturing a semiconductor memory device according to claim 11, wherein the buried insulating film is made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).   The fourth step includes a step of forming a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a step of forming a second conductive barrier layer that prevents diffusion of oxygen. A method of manufacturing a semiconductor memory device according to claim 11. After the ninth step, a tenth step of forming a second insulating barrier layer for preventing hydrogen diffusion on the upper surface of the upper electrode and the side surfaces of the upper electrode, the capacitor insulating film and the buried insulating film The method of manufacturing a semiconductor memory device according to claim 11, further comprising:

Images