WO2005122407A1 - Schema de synchronisation comprenant des diviseurs de frequence couples - Google Patents

Schema de synchronisation comprenant des diviseurs de frequence couples Download PDF

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Publication number
WO2005122407A1
WO2005122407A1 PCT/IB2005/051877 IB2005051877W WO2005122407A1 WO 2005122407 A1 WO2005122407 A1 WO 2005122407A1 IB 2005051877 W IB2005051877 W IB 2005051877W WO 2005122407 A1 WO2005122407 A1 WO 2005122407A1
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WO
WIPO (PCT)
Prior art keywords
frequency
synchronization
output signal
signal
phase
Prior art date
Application number
PCT/IB2005/051877
Other languages
English (en)
Inventor
Markus Neumann
Ralf Burdenski
Christian Wuensch
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Intellectual Property & Standards Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Intellectual Property & Standards Gmbh filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2005122407A1 publication Critical patent/WO2005122407A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H03J1/0041—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers
    • H03J1/005—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers in a loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to a method and apparatus for providing synchronization of an output signal to a reference signal, to be used for reference frequency synchronization in a mobile terminal, for example.
  • Radio communication devices require generation of stable operating frequencies in order to function properly.
  • stability has been obtained by using a crystal oscillator as a reference oscillator to provide a reference frequency.
  • local oscillators of radio terminals are phase-locked to the reference frequency.
  • crystal oscillators by themselves cannot provide a sufficiently constant frequency to meet the frequency stability requirements of the radio terminal.
  • the output frequency of a crystal oscillator varies over temperature.
  • non-linearities in the control path of the reference oscillator may cause frequency deviations.
  • Radio terminals may also require frequency correction to precisely center a radio transceiver operating frequency onto a base station channel frequency. Frequency deviations may occur due to Doppler shifts caused by movements of the terminal or due to frequency offsets at the base stations.
  • AFC automatic frequency control
  • Temperature compensation of crystal oscillators is known in the art. Generally, these methods incorporate compensation circuits composed of analog or digital devices and are used to provide a relatively constant output frequency over temperature. Typically, these circuits are incorporated within the crystal oscillator and the output of the oscillator is applied as a reference frequency to all frequency synthesizers or local oscillators of the radio terminal and as processing clock to other circuit components such as a baseband processing unit.
  • a reference frequency is synchronized to a comparative frequency information emitted from the cellular network and included in a synchronization information.
  • Known arrangements for reference frequency synchronization comprise a voltage-controlled reference crystal oscillator.
  • frequency adjustment is obtained by applying a control voltage generated in the mobile terminal.
  • the control information is derived in the mobile terminal based on the synchronization information emitted by the network.
  • the known frequency tracking mechanism requires corresponding circuitry which involves costs and space.
  • synchronization of the reference frequency is accomplished by coupling two frequency dividing means, wherein one of the frequency dividing means is included in a phase-locked loop arrangement. Due to the provision of the second frequency dividing means which is controlled only by the first control information, the adjustment or tracking function can be provided in the phase-locked loop arrangement so that the reference frequency of the reference oscillator does not have to be changed. In the following this reference frequency is also called "uncorrected reference frequency".
  • the control circuitry for the reference oscillator can thus be dispensed with. Moreover, only one control circuit is necessary for frequency tracking, and the fact that the exact reference frequency is available in the receiver arrangement is advantageous for integrated analog/digital converters or digital interfaces. Additionally, the frequency divider offset is independent from the set or selected receiving channel, so that fast synchronization can be obtained after switching to a new channel. The same frequency divider offset is also applicable for transmission channels. Then, the exact reference frequency is the reference for the generation of the transmit signal when a transmit section is provided.
  • the reference oscillator used for generating the reference frequency may be a crystal oscillator, and may be a non-controllable fixed- frequency oscillator.
  • the predetermined nominal division ratio can be derived from the ratio between the nominal channel frequency, which is defined by the corresponding communication system, and the nominal reference frequency.
  • the frequency of the output signal corresponds to the generated exact reference frequency when the apparatus has reached synchronization state. It is to be noted that, in the synchronization state, the frequency of the output signal may deviate from the nominal reference frequency if the received channel frequency has changed during transmission due to a Doppler shift, fading effect, or the like or due to frequency offsets at the base stations.
  • the control means may be connected to a programming interface for programming the first and second frequency dividing means. A change of the frequency can thus be achieved by reprogramming the phase-locked loop arrangement, while the change of frequency is then based on the step response obtained by the phase- locked loop arrangement.
  • switching means may be provided for connecting either the uncorrected reference frequency or the output signal to an output of the synchronization apparatus.
  • the uncorrected reference frequency may be switched by the switching means to a controlling unit for activation and initialization.
  • the controlling unit can be used for initialization and/or setting of at least one of the first and second frequency dividing means.
  • the output signal may be supplied to a baseband processing unit which comprises calculating means for calculating the synchronization error based on a frequency offset.
  • the synchronization can thus be achieved by calculating the frequency offset at the baseband processing unit and setting the additional frequency divider offset of the first frequency dividing means based thereon, e.g. via a programming interface.
  • any changes of the predetermined nominal division ratio are set in both first and second frequency division functions simultaneously.
  • any influence introduced by a change of the predetermined nominal division ratio at one frequency division function e.g. due to a phase-frequency modulation or the like, is also set at the other frequency division function to prevent any influence on the output signal.
  • filter means may be provided for limiting the spectral composition of the output signal.
  • the filter means may comprise a bandpass filter. The provision of the filter means leads to the advantage of reduced noise and/or jitter and/or frequency changes caused by modulation inherent to the preceding circuitry, and to a balanced duty rate of the output signal.
  • Fig. 1 shows a schematic block diagram of a synchronization scheme according to the present invention
  • Fig. 2 shows a schematic block diagram of a mobile terminal with a synchronization mechanism according to the preferred embodiment in a situation directly after switching on the arrangement
  • Fig. 3 shows the mobile terminal of Fig. 2 in a situation after a synchronized state has been reached
  • Fig. 4 shows a flow diagram relating to a transfer procedure from the initial state indicated in Fig. 2 to the synchronized state indicated in Fig. 3
  • Fig. 5 shows a schematic block diagram of a circuit enhancement of the preferred embodiment shown in Figs. 2 and 3.
  • Fig. 1 shows a schematic block diagram indicating the synchronization mechanism underlying the preferred embodiment.
  • the synchronization of the reference frequency in the mobile terminal or mobile user equipment is accomplished by a configuration consisting of two coupled frequency dividers 35 and 9, wherein a first frequency divider 35 is arranged in a phase- locked loop circuitry 30 to which an uncorrected reference signal is supplied.
  • This uncorrected reference signal for the phase-locked loop circuitry 30 is generated by a simple crystal oscillator 2 having no means or circuitry for frequency control.
  • the setting of the first frequency divider 35 and the second frequency divider 9 and their configuration is performed by a control unit or mechanism 40 in a certain sequence which enables the user equipment to synchronize its generated reference frequency f ref to a frequency information (N.k)*f ref or a frequency correction information received from the cellular network by a corresponding receiver unit 50 to which the output signal of the phase-locked loop circuitry 30 is supplied e.g. for mixing or other synchronized receiving purposes.
  • the receiver unit 50 generates a digital receiving signal DRS which is further processed in a subsequent unit (not shown).
  • the reference signal generated by the crystal oscillator 2 has a frequency error ⁇ which is compensated by a corresponding offset division ratio set by the control unit 40 at the first frequency divider 35.
  • a synchronized or corrected exact reference frequency f ref can be obtained without requiring any adjustment of the crystal oscillator 2 itself.
  • the crystal oscillator 2 may be replaced by any suitable reference oscillator which generates a fixed frequency.
  • the above synchronization mechanism will be described in more detail based on a so-called "zero-IF-receiver" arrangement, which is a superheterodyne (superhet) receiver with an intermediate frequency (IF) of 0 Hz.
  • IF intermediate frequency
  • a synchronization signal H is received by means of an antenna 1, is converted by a subsequent receiver arrangement 10 into a baseband frequency, and is decoded and evaluated in a subsequent baseband processing unit 20.
  • a mixer 12 is arranged in the receiver arrangement 10 following the connected antenna 1.
  • the mixer 12 is followed by a low pass filter 13 for band limitation of the converted receiving signal, and by an analog-to- digital converter 14 for converting the converted receiving signal into a digital receiving signal.
  • the conversion signal C for the mixer 12 is generated by a connected voltage- controlled oscillator 7, which is part of a phase-locked loop.
  • the phase-locked loop comprises a frequency divider 8, for example a fractional-N- frequency divider, a directly following offset frequency divider 17, a phase-frequency comparator 5, and a loop filter 6.
  • a reference crystal oscillator 2 serves to generate the uncorrected reference frequency B, which is used as phase comparison frequency supplied to the phase- frequency comparator 5.
  • the phase-locked loop arrangement serves to converge the frequency of the frequency-divided signal E to the uncorrected reference frequency B when the steady state has been reached.
  • the reference crystal oscillator 2 does not require any control circuit for frequency variation or frequency tracking, respectively.
  • the required exact reference frequency is designated by f re f and its absolute precision is predefined by the respective communication system.
  • the uncorrected reference frequency B of the reference crystal oscillator 2 deviates from the exact reference frequency f ref by a reference frequency error ⁇ .
  • a coupled frequency divider 9 which should be the same type and of the same resolution than divider 8, is connected to the output of the voltage-controlled oscillator 7.
  • the dividing ratio N.k of the coupled frequency divider exactly corresponds to the dividing ratio N.k of the frequency divider 8 at all time. It can thus be followed that the difference between the ratio of the conversion signal C and the output signal D of the coupled frequency divider 9 and the ratio of the conversion signal C and the frequency-divided signal E of the phase- locked loop is only dependent from the dividing ratio of the offset frequency divider 17 following the frequency divider 8.
  • the dividing ratio of the offset frequency divider 17 is designated by (1 - ⁇ ), where ⁇ will be designated as frequency divider offset ⁇ throughout the following description.
  • the nominal dividing ratio N.k can be derived from the ratio of the mobile radio channel frequency of the received signal to the nominal reference frequency.
  • the dividing ratios are set by a programming interface 11 which is connected to the frequency divider 8 and the coupled frequency divider 9 via a control connection F for programming of the dividing ratio N.k, and to the offset frequency divider 17 via another control connection G for programming of the frequency divider offset ⁇ . If modulation is applied by means of divider-ratio changes this divider-ratio changes should be programmed in frequency divider 8 and coupled frequency divider 9 simultaneously.
  • the setting procedure is performed by a radio controller 16 arranged in the baseband processing unit 20. Furthermore, a selection switch 3 is controlled by the programming interface 11.
  • the selection switch 3 either connects the uncorrected reference frequency B of the reference crystal oscillator 2 or the output signal D of the coupled frequency divider 9 to the baseband processing unit 20, particularly to a baseband receiver 4 provided in the baseband processing unit 20.
  • the baseband receiver 4 receives the digital receiving data from the analog-to- digital converter 14 of the receiver arrangement 10 for post-processing and decoding.
  • a frequency offset calculator 15 is connected to the baseband receiver 4 where the synchronization information originally emitted by the network is decoded.
  • the frequency offset calculator 15 calculates a frequency offset information A based on which the radio controller 16 sets or initializes the programming interface 11 of the receiver arrangement 10.
  • the frequency divider offset ⁇ of the offset frequency divider 17 is continuously tracked based on the obtained frequency offset information.
  • the situation shown in Fig. 2 corresponds to a state directly after switching on the power supply to the arrangement.
  • the uncorrected reference frequency B of the reference crystal oscillator 2 with its reference frequency error ⁇ is connected via the selection switch 3 to the baseband processing unit 20, so that the baseband processing unit 20 can start up.
  • the coupled frequency divider 9 does not deliver an output signal D before the radio controller 16 of the baseband processing unit 20 has been initialized.
  • the frequencies of the signals B, D, and E all equal to the value f re f + ⁇ .
  • the conversion signal C required for frequency conversion at the mixer 12 is obtained from the uncorrected reference frequency B which is multiplied by the nominal division ratio N.k of the frequency divider 8 by using the phase- locked loop consisting of blocks 5, 6, 7, 8, and 17, while the frequency divider offset ⁇ is set to zero.
  • the frequency of the conversion signal C amounts to N.k*(f ref + ⁇ ).
  • the frequency of the error signal A obtained at the frequency offset calculator 15 of the baseband processing unit 20 amounts to (N.k)* ⁇ . This corresponds to the reference frequency error ⁇ at the reference crystal oscillator 2 multiplied by the nominal division ratio N.k at the frequency divider 8.
  • Ultimate target of the arrangement according to the preferred embodiment is that the output signal D of the coupled frequency divider 9 and thus the signal forwarded to the baseband processing unit 20 exactly corresponds to the exact reference frequency, i.e., the frequency of the output signal D amounts to f ref .
  • the mixer 12 is operated by the exact nominal conversion frequency, such that the frequency of the conversion signal C shall amount to f ref *(N.k).
  • the reference frequency error ⁇ can be derived at the baseband processing unit 20 from the frequency offset information A, due to the fact that the nominal division ratio N.k and ⁇ is known.
  • ⁇ is either 0 in initial state or known from previous setting.
  • the frequency divider offset ⁇ of the offset frequency divider 17 subsequently can be programmed or set according to equation (1).
  • the conversion signal C exactly corresponds to the value f ref *(N.k), which corresponds to the exact conversion frequency of the mixer 12.
  • the conversion signal C comprises the two components
  • the programming interface 11 controls the selection switch 3 to connect the output signal D of the coupled frequency divider 9 to the baseband processing unit 20.
  • the selection switch 3 is controlled to connect, from now on, the output signal D of the coupled frequency divider 9 to the baseband processing unit 20.
  • This step response is steady, steadily differentiable and damped with respect to frequency changes and in accordance to common design criteria of phase- locked loops.
  • the frequency transfer of the initially erroneous output signal D of the coupled frequency divider 9 towards the exact reference frequency f ref is also steady, steadily differentiable and the frequency transition is continuous.
  • the reference frequency error ⁇ changes with time.
  • the frequency offset information A of the frequency offset calculator 15 may temporarily deviate from zero.
  • a reprogramming of the frequency divider offset ⁇ is performed in order to set the frequency offset of the receiving signal baseband frequency to zero, which corresponds to a reference frequency tracking function for compensating any reference frequency error ⁇ .
  • any temporary changes of the synchronization information emitted by the network and received by the mobile terminal which may be caused by doppler effects and frequency deviations due to frequency offsets at the base stations can not be distinguished from changes of the uncorrected reference frequency and are therefore regarded to be represented by the reference frequency error ⁇ .
  • the above preferred embodiment can be generalized in that the frequency divider 8 and the offset frequency divider 17 are combined to a single frequency divider with a division ratio (N.k) - ⁇ , wherein ⁇ designates an additive frequency divider offset. Similar to the above described function of the start of synchronization, the additional frequency divider offset ⁇ is initially programmed to zero.
  • Fig. 4 shows a schematic flow diagram relating to the change or transfer procedure from the initial state according to Fig. 2 to the synchronized state according to Fig. 3.
  • Fig. 4 depicts a way in which the reference frequency is tracked during the operation of the mobile terminal.
  • step SI 00 the mobile terminal is switched on for reference frequency synchronization.
  • step S101 the selection switch 3 connects the uncorrected reference frequency B of the reference crystal oscillator 2 to the baseband processing unit 20 for activation thereof.
  • step SI 02 the frequency divider 8 and the coupled frequency divider 9 are set or programmed to the nominal division ratio N.k, and the frequency divider offset ⁇ of the offset frequency divider 17 is set to zero in this initial state.
  • the voltage-controlled oscillator 7 generates a conversion signal C for the mixer 12, which is still erroneous at this initial point in time.
  • step SI 04 the selection switch 3 is switched so as to connect the output signal D of the coupled frequency divider, which at this time corresponds to the uncorrected reference frequency B, with delayed phase, of the reference crystal oscillator 2, to the baseband processing unit 20.
  • decision step SI 05 it is checked whether the frequency offset information A is zero or not. If the frequency offset information A is zero, the procedure jumps to step Si l l where a synchronized operating state is assumed and a waiting time is started. After that the procedure returns to step SI 05 for again checking frequency offset information A.
  • step SI 06 If it is determined in step SI 05 that the frequency offset information A is not equal zero it is proceeded with step SI 06.
  • the reference frequency error ⁇ of the uncorrected reference frequency B can be obtained by evaluating the frequency offset information A obtained at the frequency offset calculator 15.
  • the frequency divider offset ⁇ required for synchronization is determined by using equation (1) and is set at the offset frequency divider 17 in step 107.
  • step SI 08 the voltage-controlled oscillator 7 changes the frequency of the conversion signal C to the exact conversion frequency of the mixer 12. Again, this change procedure is carried out in accordance with the transfer function or step response of the phase-locked loop.
  • step SI 09 the exact reference frequency is available at the output of the coupled frequency divider 9, and is forwarded to the baseband processing unit 20. Consequently, it is determined in step SI 10 that the frequency offset information A is zero, and a synchronized operating state is entered.
  • Fig. 5 shows a schematic block diagram of a circuit enhancement in the circuit of the preferred embodiment shown in Figs. 2 and 3, with the purpose of providing a filtering function for filtering the output signal D of the coupled frequency divider 9. According to Fig. 5, the output signal D of the coupled frequency divider 9 is limited in its spectral composition and thus enhanced in its spectral purity by a subsequent filter circuit 60, which may be a bandpass filter.
  • the filter circuit 60 is arranged between the coupled frequency divider 9 and the change switch 3.
  • the filter circuit 60 could as well be arranged between the selection switch 3 and the baseband processing unit 20.
  • the output signal of the reference crystal oscillator 2 would be delayed by the propagation time of the filter circuit 60 before arriving at the baseband receiver 4.
  • the present invention provides the advantage that physical, discrete, analog circuits for frequency tracking at the reference crystal oscillator circuits, such as tuning elements filter and decoupling circuits, can be dispensed with, which leads to savings in costs and space. Furthermore, only one control loop is required for frequency tracking without any underlying control loop of a clock phase-locked loop in the baseband processing unit 20. In the receiver arrangement 10 the correct reference frequency is provided, which is advantageous for integrated analog-to-digital converters or digital interfaces. The jitter is moderate due to the provision of fractional N-dividers, as the effective division ratio is substantially higher as a result of the derivation from the voltage-controlled oscillator, as compared to the use of a clock phase- locked loop in the baseband processing unit 20.
  • the change of the frequency of the output signal D forwarded to the baseband processing unit 20 occurs steady, steadily differentiable and damped according to the step response generated by the phase-locked loop.
  • the above preferred embodiment as depicted in Figs. 2, 3 and 4 provides the advantage that the frequency divider offset ⁇ is independent from the set mobile radio channel. It is noted that the present invention is not restricted to the above preferred embodiment and generalized embodiment, but can be applied in any receiver arrangement, such as for example superheterodyne receivers, where a clock frequency, reference frequency or other control frequency, which is derived in a terminal device or other device, is synchronized to a comparison frequency derived from or contained in a synchronization information broadcast from a network.
  • GSM Global System for Mobile communication
  • UMTS Universal Mobile Communications System
  • CDMA Code Division Multiple Access
  • DECT Digital Enhanced Cordless Telephone
  • Bluetooth Bluetooth systems
  • radio communication standard any other radio communication standard

Abstract

La présente invention concerne un appareil et un procédé qui permettent de synchroniser un signal de sortie par rapport à un signal de référence. Selon l'invention, on effectue la synchronisation en constituant deux systèmes de moyens de division de fréquence ou fonctions de division de fréquence couplées, une division de fréquence faisant partie d'un agencement en boucle à verrouillage de phase. Le signal de référence de l'agencement en boucle à verrouillage de phase est fourni par un simple oscillateur à quartz dépourvu de moyens de régulation de fréquence. Le réglage et la configuration des diviseurs de fréquence s'effectuent selon une séquence prédéterminée qui permet à l'équipement utilisateur de synchroniser sa fréquence de référence par rapport à des informations de correction de fréquence reçues émises par le réseau.
PCT/IB2005/051877 2004-06-10 2005-06-08 Schema de synchronisation comprenant des diviseurs de frequence couples WO2005122407A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04102638 2004-06-10
EP04102638.6 2004-06-10

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WO2005122407A1 true WO2005122407A1 (fr) 2005-12-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1956708A1 (fr) * 2007-01-31 2008-08-13 NEC Electronics Corporation Appareil de réception

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111486A (en) * 1989-03-15 1992-05-05 Motorola, Inc. Bit synchronizer
EP0583800A1 (fr) * 1989-08-25 1994-02-23 Anritsu Corporation Oscillateur contrôlé par une tension
EP0726662A2 (fr) * 1995-02-08 1996-08-14 Mitsubishi Denki Kabushiki Kaisha Récepteur et émetteur-récepteur
US5859570A (en) * 1994-09-29 1999-01-12 Mitsubishi Denki Kabushiki Kaisha Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111486A (en) * 1989-03-15 1992-05-05 Motorola, Inc. Bit synchronizer
EP0583800A1 (fr) * 1989-08-25 1994-02-23 Anritsu Corporation Oscillateur contrôlé par une tension
US5859570A (en) * 1994-09-29 1999-01-12 Mitsubishi Denki Kabushiki Kaisha Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL
EP0726662A2 (fr) * 1995-02-08 1996-08-14 Mitsubishi Denki Kabushiki Kaisha Récepteur et émetteur-récepteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1956708A1 (fr) * 2007-01-31 2008-08-13 NEC Electronics Corporation Appareil de réception

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