WO2005107202A1 - タイミング再生回路および受信装置 - Google Patents
タイミング再生回路および受信装置 Download PDFInfo
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- WO2005107202A1 WO2005107202A1 PCT/JP2004/006209 JP2004006209W WO2005107202A1 WO 2005107202 A1 WO2005107202 A1 WO 2005107202A1 JP 2004006209 W JP2004006209 W JP 2004006209W WO 2005107202 A1 WO2005107202 A1 WO 2005107202A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/084—Equal gain combining, only phase adjustments
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
Definitions
- the present invention relates to a receiving device constituting a digital wireless communication system, and more particularly, to a timing recovery circuit in a receiving device that performs timing recovery using a preamble signal.
- a PSK modulated signal is received by two antennas, each PSK modulated signal is individually detected, and as a result, a baseband phase signal 4 and received signal power are obtained.
- the detection is performed by, for example, a limiter / bandpass filter or a mixer.
- each baseband phase signal obtained above is oversampled with a quadruple of the symbol frequency to generate baseband reception phase data. Then, of the two baseband reception phase data, the baseband reception phase data of the branch having the larger received signal power is selected.
- the selected baseband reception phase data is selected.
- the timing recovery processing processing of the conventional timing recovery circuit, which will be described later, is performed using the data, and the baseband phase signal at the Nyquist point is sampled in the oversampling processing. Control. Further, a reproduction symbol clip for extracting Nyquist point data from the selected baseband reception phase data is generated.
- the diversity receiving apparatus extracts Nyquist point data from the selected baseband reception phase data using the reproduced symbol clock generated above.
- the processing of the timing reproduction circuit at the time of the timing reproduction will be described in detail.
- the odd sequence synthesized symbol frequency component data obtained from the phase fluctuation amount at the odd sample interval and the phase fluctuation amount at the even sample interval are obtained.
- the even-number sequence synthesized symphony frequency component data are obtained.
- the odd-sequence synthesized symbol frequency component data and the even-sequence synthesized symbol component frequency component data since the absolute value operation corresponding to the multiplication process is performed, the odd-sequence synthesized symbol frequency component data and the even-sequence synthesized data are calculated.
- the symbol frequency component data has a symbol frequency component for any transmission data sequence.
- the cosine wave component and the sine wave component of the symbol period are respectively added to the synthesized symbol frequency component data obtained by adding the odd-sequence synthesized symbol frequency component data and the even-sequence synthesized symbol frequency component data.
- the symbol frequency component of the symbol frequency component data is frequency-converted to a DC component to obtain a complex DC in-phase component and a complex DC quadrature component.
- averaging is performed on the complex DC in-phase component and the complex DC quadrature component, respectively, and the inverse tangent of the averaged DC in-phase component and complex DC quadrature component is obtained. Is estimated.
- timing recovery circuit shifts the recovered symbol clock and the recovered quadrupled clock by the timing phase difference estimated above to obtain the Nyquist clock.
- the conventional diversity receiver can extract Nyquist point data from an arbitrary PSK-modulated transmission data sequence.
- Patent Literature 1 Patent No. 3286885 No.3, No.3, S. et al., In the conventional timing recovery circuit described in Patent Literature 1, the timing is assumed on the assumption that the received signal is an arbitrary data sequence subjected to PSK modulation. In order to perform reproduction, it is necessary to perform a multiplication process when obtaining odd-sequence synthesized symbol frequency component data and even-sequence synthesized symbol frequency component data, which is a case where a preamble signal that is a known pattern is received. However, there was a problem that it was difficult to establish timing synchronization at high speed due to loss of data.
- the present invention has been made in view of the above, and an object of the present invention is to provide a timing recovery circuit that realizes high-speed and high-accuracy timing synchronization in a receiving device using one or more antennas.
- the timing recovery circuit is a timing recovery circuit that performs timing recovery using PSK-modulated preamble signals received by N (N is a natural number) branches of antennas.
- N is a natural number
- Power weighting coefficient calculation means (corresponding to power weighting coefficient calculation unit 12) for individually sampling signal power at arbitrary time intervals and calculating power weighting coefficients for N branches based on the obtained received signal power data.
- Weighting multiplying means (corresponding to multipliers 13-1 to 13-N) for individually multiplying the phase variation amount of each of the branches and the corresponding power weighting coefficient by:
- a combined phase variation calculating means (corresponding to the adding section 14) for combining the results to calculate a combined phase variation is provided.
- the composite phase variation is multiplied by a cosine wave component and a sine wave component of a two-symbol period individually to extract a real component and an imaginary component of a half-symbol frequency component complex signal.
- Symbol frequency component extraction means (corresponding to a 1/2 symbol frequency component extraction unit 15); and averaging means (averaging) for individually averaging the real component and the imaginary component of the 1/2 symbol frequency component complex signal.
- Preamble timing that determines the argument between the real component and the imaginary component of the ⁇ ⁇ ⁇ ⁇ symbol frequency component complex signal after averaging, and sets the phase twice as the argument of the argument.
- a preamble timing phase complex signal calculation means (corresponding to the preamble timing phase complex signal calculation unit 17) for calculating a phase complex signal.
- a ⁇ multiplied clock having a clock speed that is about ⁇ ( ⁇ is a natural number of 2 or more) times the symbol rate is divided, and the divided clock is divided into a phase corresponding to the argument of the complex signal.
- the reproduction symbol clock generation means (corresponding to the phase shift control frequency dividing section 18), which generates a reproduction symbol clock by shifting the phase by an amount, is provided.
- the preamplifier is used for performing the timing estimation by using the combined phase variation obtained by increasing the gain of the branch combining by applying the preamp phase variation calculating means and the combined phase variation calculating means. High-speed and high-accuracy timing estimation is possible when receiving a signal.
- the timing is reproduced, and when the preamble signal reception is completed, the timing phase at the time of receiving the preamble is retained and the reference phase is multiplied.
- the pre-amble is divided to generate a reproduced symbol clock and a reproduced U-time pulse, so even when random data is received after preamble reception is completed, the highly accurate timing phase estimated at the time of preamble reception is received. Synchronous state can be maintained.
- FIG. 1 is a diagram illustrating a configuration example of a timing recovery circuit according to the first embodiment
- FIG. 2 is a diagram illustrating a configuration example of a reception device according to the first embodiment
- FIG. FIG. 4 is a diagram showing an example of the operation timing of the section
- FIG. 4 is a diagram showing an example of the configuration of a phase variation calculating section for a blow amplifier
- FIG. 5 is an example of a difference value inputted to a phase offset removing section.
- FIG. 6 is a diagram illustrating an example of a difference value output from the phase offset removing unit.
- FIG. 7 is a diagram illustrating a configuration example of the power weighting coefficient calculating unit.
- FIG. 1 is a diagram illustrating a configuration example of a timing recovery circuit according to the first embodiment
- FIG. 2 is a diagram illustrating a configuration example of a reception device according to the first embodiment
- FIG. FIG. 4 is a diagram showing an example of the operation timing of the section
- FIG. 4 is a
- FIG. 9 is a diagram showing a configuration example of a preamble timing phase complex signal calculation unit.
- FIG. 9 is a diagram showing a configuration example of a phase shift control / frequency division unit.
- FIG. 10 is a diagram showing a rising edge detection.
- FIG. 11 is a diagram showing an operation example of a unit, and
- FIG. FIG. 12 is a diagram illustrating a configuration example of a timing reproduction circuit.
- FIG. 12 is a diagram illustrating a configuration example of a receiver according to Embodiment 2.
- FIG. 13 is an example of an operation timing of a timing reproduction unit.
- FIG. 14 is a diagram showing a configuration example of a timing phase complex signal calculation unit.
- FIG. 15 is a diagram showing an example of operation timing of a timing reproduction unit.
- FIG. 10 is a diagram showing a configuration example of a phase shift control / frequency division unit.
- FIG. 10 is a diagram showing a rising edge detection.
- FIG. 11 is a diagram showing an
- FIG. 17 is a diagram illustrating a configuration example of a receiving device according to a third embodiment.
- FIG. 17 is a diagram illustrating a configuration example of a timing recovery circuit according to the third embodiment.
- FIG. FIG. 11 is a diagram illustrating a configuration example of a timing recovery circuit of No. 3; BEST MODE FOR CARRYING OUT THE INVENTION
- Embodiment 1 In the first embodiment, a timing recovery circuit for receiving a PSK-modulated signal containing data including a preamble signal of two symbol periods with one or more receiving antennas and performing timing recovery, and using the timing recovery circuit to perform data recovery.
- a receiver for demodulation (particularly, a diversity receiver when two or more receiving antennas are used) will be described.
- FIG. 1 is a diagram showing a configuration example of a timing recovery circuit according to Embodiment 1 having N (N is an integer of 1 or more) receiving antennas.
- This timing recovery circuit consists of a reception antenna 1-1-1_N, a detection unit 2-1 1-2_N, a sampling unit 3-1 1-3-N, 4-1 1-4-N, and a timing recovery unit. 5 and.
- the timing reproducing unit 5 includes a brimble phase variation calculating unit 11-1 to 11 -N, a power weighting coefficient calculating unit 12, a multiplying unit 13-1 to 13 -N, Section 14, 1/2 symbol frequency component extraction section 15, averaging section 16, preamble timing phase complex signal calculation section 17, phase shift control Z dividing section 18, reference And a clock generator 19.
- FIG. 2 is a diagram showing a configuration example of the receiving apparatus of the first embodiment including the timing reproduction circuit.
- This receiving apparatus further includes a Nyquist point extraction unit 21-1-1-2-1-N and a diversity / demodulation unit 22 in addition to the configuration of the timing recovery circuit.
- the receiving apparatus receives a PSK modulated signal with N (N is a natural number) receiving antennas 11 1 to 1 1 N, and detectors 2-1 to 2-N convert the signal of each branch into Detect and individually obtain the baseband phase signal and the received signal power.
- N is a natural number
- the sampling units 3-1 to 3-N use the received signal powers detected by the corresponding detection units 2_1 to 2-N to convert the received signal power of the reproduced U-fold clock generated by the timing recovery unit 5 to be described later. Sampling is performed at the rising edge, and the received signal power data of each branch is output.
- U is a natural number of 2 or more.
- the corresponding detection sections 2-1 to The baseband phase signal detected at 2-N is sampled at the rising edge of the reference S-time clock generated by the timing recovery unit 5 described later, and the baseband phase data of each branch is output.
- S is a natural number of 2 or more.
- the timing reproducing unit 5 performs a multiplication process and a frequency division process on the original clock of the receiving device, and generates a reference S-time clock having a clock speed S times the symbol rate. Furthermore, when the preamble signal is received, the received signal power data of each branch output from the sampling units 3-1 to 3-N and the baseband phase data of each branch output from the sampling units 4-1 to 4_N And a reproduction symportal lock synchronized with the Nyquist of the received signal and having the same speed as the symphonolate rate, and a U-time synchronized with the Nyquist of the received signal and the symbol rate based on and And a recovered U-fold clock having a clock speed of
- a known preamble signal since a known preamble signal is used, there is no need to perform a multiplication process, and deterioration due to a multiplication loss can be reduced, so that high-speed and highly accurate timing estimation is possible.
- the Nyquist point extraction units 21-1 to 21-N synchronize the baseband phase signals detected by the corresponding detection units 2-1 to 2-N and the received signal power with the Nyquist point of the received signal. Sampling is performed at the rising edge of the reproduced symbol clock, and Nyquist point baseband phase data and Nyquist point received signal power data of each branch are output.
- the diversity / demodulation section 22 performs diversity combining based on the Nyquist point baseband phase data and the Nyquist point received signal power data of each branch output from the Nyquist point extraction sections 21-1 to 21-N. Furthermore, it demodulates the received signal after diversity combining and outputs demodulated data.
- the sampling units 3-1 to 3-N in the above-mentioned receiving apparatus sample the received signal power detected by the corresponding detection units 2-1 to 2-N at the rising edge of the recovered U-fold clock.
- the clock used for sampling is not particularly limited.
- a reference clock generated by multiplying or dividing the original clock may be used.
- the sampling sections 411 to 4-1N in the receiving apparatus described above use the baseband phase signals detected by the corresponding detection sections 2-1 to 2-N as the rising edges of the reference S-times clock.
- the description has been given of the case where sampling is performed using the sampling method there is no particular limitation on the clock used for sampling. For example, if the sampling rate is twice or more the symbol rate, the playback clock generated by the timing playback unit 5 is used. You can also use
- the reference clock generation unit 19 performs frequency division processing or multiplication processing on the original clock of the receiving apparatus, and the frequency is approximately T times the symbol rate.
- a reference T-times clock having a clock speed of and a reference S times clock having a clock speed of about S times the symbol rate is a natural number of 2 or more.
- the phase variation per specific time with respect to the baseband phase data of each branch sampled by the corresponding sampling unit 411-4-1N Is calculated. For example, if a [1001] pattern of ⁇ / 4 shift QPSK (Quadrature Phase Shift Keying) modulation, which performs differential encoding, is applied as a brimble signal, the amount of phase variation when the preamble signal is received will be described later.
- the signal has a 2-symbol cycle as shown in Fig. 5. Since the preamble signal is a known signal, it is not necessary to perform the multiplication process when calculating the amount of phase variation.
- the power weighting coefficient calculation unit 12 calculates a power weighting coefficient indicating the likelihood of the reception signal of each branch based on the reception signal power data of each branch sampled by the sampling units 3_1 to 3-N. calculate.
- the multipliers 13-1 to 13 -N multiply the phase variation of the corresponding branch by the power weighting coefficient and output the multiplication result.
- the multiplier 13 3; ⁇ 1 3—Multiplication of each branch output from N The result is added for a predetermined branch, and the combined phase variation obtained by this addition is output.
- the combined phase fluctuation is also obtained as a signal in a two-symbol cycle like the above-described phase fluctuation.
- the preamble phase variation calculator 11 1 1 1 to 1 1 1 N does not perform the multiplication process when calculating the phase variation, the addition loss here is also small, and the addition multiplication loss is small. Many gains can be obtained.
- the 1/2 symbol frequency component extractor 15 multiplies the combined phase variation, which is a signal of 2 symbol periods, by the cosine wave component and the sine wave component of 2 symbol periods, respectively, and calculates 1 / It converts the frequency of the two-symbol frequency component to a DC component and outputs the real component of the half-symbol frequency component complex signal and the imaginary component of the half-symbol frequency component complex signal.
- the averaging unit 16 averages the real component of the above] ./ 2 symbol frequency component complex signal and the imaginary component of the 1Z2 symbol frequency component complex signal. Note that the deviation angle ⁇ 6 between the real component of the averaged 1/2 symbol frequency component complex signal and the imaginary component of the averaged 1/2 symbol frequency component complex signal is the Nyquist point per two symbol periods. The timing phase difference between the reference and the reference S times clock is shown.
- the preamble timing phase complex signal calculator 17 calculates the phase twice as large as the declination ⁇ ⁇ from the real component of the averaged 1/2 symbol frequency component complex signal and the imaginary component of the 12 symbol frequency component complex signal. Generates a preamble timing phase complex signal having a declination angle. “2 ⁇ 0” indicates a timing phase difference between the Nyquist point and the reference S-fold clock per symbol period.
- the phase shift control ⁇ frequency divider 18 divides the reference ⁇ multiplied clock to generate a clock approximately equal to the symbol rate and a clock approximately U times the symbol rate. Furthermore, the phase of the symbol that is about the same as the divided symbol rate and the rate of the symbol that is about U times the symbol rate are shifted by 2 X ⁇ ⁇ with respect to the symbol period, respectively. Generate playback symbol clock and playback U-fold clock.
- the reference S-time clock and the reference ⁇ -time clock are clocks generated from the same original clock and are synchronized with each other. Therefore, the reproduced symbol clock and the reproduced U times clock generated as described above are synchronized with the Nyquist point.
- the timing reproducing unit 5 of the present embodiment applies the brimble phase fluctuation amount calculating unit 111-1-1 1_N and the adding unit 14 to obtain a large gain of branch combining. Since timing estimation is performed using the combined phase variation, high-speed and high-accuracy timing estimation can be performed when receiving a preamble signal.
- the timing reproducing section 5 of the present embodiment cannot perform timing estimation when transmission data is random data.
- the timing reproduction is performed by using the timing reproduction unit 5 when the preamble signal is received.
- the phase is maintained and the frequency of the reference T-fold clip is divided to generate a reproduced symbol clip and a reproduced U-fold clip.
- FIG. 3 is a diagram showing an example of the operation timing of the timing reproducing unit 5.
- timing reproduction unit 5 generates two types of reproduction clocks (reproduction clock and reproduction U-fold clock), the number of reproduction clocks is not limited, and one or more reproduction clocks are generated. If possible.
- the operation of the preamble phase variation calculator 11_n will be described, but the other preamble phase variation calculators operate similarly.
- the one-sample delayer 3 1 — N, 32— n, 33— n, 34— n delay the baseband phase data sampled by the sampling unit 41 n by one period at the reference S times Output.
- the subtractor 35_n subtracts the baseband phase data to which a delay of one cycle has been added by the reference S times clock from the baseband phase data to which the delay of three cycles has been added by the reference S times clock, and
- the difference value (phase variation) is output.
- the difference value has a length of one 180 [degree] to 180 [degree] by a calculation of modulo 360 [degree].
- the subtractor 36-n subtracts the baseband phase data without delay from the baseband phase data delayed by four cycles by the reference S times clock, and the difference value (phase variation amount) Is output. Also in this case, the difference value has a value of one 180 [degree] to: 180 [degree] by calculation of the module port 360 [degree].
- the phase offset remover 37_n sets the sum of the upper and lower limit values of the difference value after the phase offset removal in the no-noise state close to 0 to the difference value output from the subtractor 35-n. Give the phase offset amount.
- the output signal after the phase offset has a value of -180 [degree] to 180 [degree] by modulo 360 [degree] calculation.
- FIG. 5 is a diagram showing an example of the difference value input to the phase offset removing unit 37-n (or 38-n).
- FIG. 6 is a diagram showing the phase offset removing unit 37-n (or 38-n).
- FIG. 7 is a diagram showing an example of a difference value output from the). For example, as shown in Fig.
- the upper limit of the difference value of the [1001] pattern of ⁇ / 4 shift QP SK modulation that performs differential coding is about ⁇ / 4
- the lower limit is about 1 3 ⁇ 4 It becomes.
- the difference value has an upper limit of about ⁇ / 2 and a lower limit of about 1 ⁇ 2, as shown in FIG. That is, even when noise is added, calculating the modulo 360 [degree] reduces the occurrence frequency of the phase and ⁇ between the +180 [degree] and one 180 [degree] of the difference value.
- the reproduction clock characteristics are poor due to this phase jump. I can reduce the dung.
- phase offset remover 38-n sets the sum of the upper and lower limit values of the difference value after phase offset removal to 0 in the noise-free state with respect to the difference value output from the subtractor 36-n. Gives a phase offset amount that makes it closer.
- the output signal after the phase offset has a value of -180 [degree] to 180 [degreej] by the calculation of modulo 360 [degree].
- the adder 39-n adds the output results of the phase offset removers 37_n and 38_n, and as a result of the addition, the phase fluctuation amount is reduced by 1 360 [degree] to 360 [degree].
- the preamble phase fluctuation amount calculation unit 11 — n of the present embodiment performs the processing of the phase offset removal unit to make the difference value of the baseband phase data +1.80 [degree] and 1 1 Since the frequency of occurrence of the phase jump between 80 [degree] can be reduced, the deterioration of the reproduction clock characteristic due to the phase jump of the difference value of the baseband phase data can be reduced.
- the interval for calculating the difference may be any time.
- the preample phase variation calculator calculates the phase variation by combining two differences of the difference between the four clock periods and the difference between the two clock periods, but the phase variation is one or more. Can be obtained from the difference between the clock intervals. For example, by calculating the amount of phase change using a plurality of differences between different clock intervals, the S / N ratio of the amount of phase change is increased, so that the reproduction clock characteristics can be improved.
- FIG. 7 is a diagram showing an example of the configuration of the power weighting coefficient calculation unit 12, in which the maximum value detection unit 41, the averaging units 42, 43-1, to 43-N, and the normalization unit 4 4 1:!
- the maximum value detection unit 41 selects the reception signal power data of all N branches sampled by the sampling units 3-1 to 3-N. Detect maximum received signal power data.
- the averaging section 42 outputs reference received signal power data obtained by averaging the maximum received signal power data.
- the averaging units 4 3 _ 1 to 4 3—N average the received signal power data sampled by the corresponding sampling units 3-1 to 3—N for each branch, and Calculate average received signal power data.
- the normalizing units 44_1 to 44-N normalize the average received signal power data of each branch based on the reference received signal power data, and output the normalized result. For example, when the received signal power data is expressed in a logarithmic notation, a division operation or the like is performed on the normal signal, and when the received signal power data is in a logarithmic notation, a subtraction operation or the like is performed.
- the coefficient conversion units 45-1 to 45-N convert the normalized results output from the corresponding normalization units 441-1 to 441-N into power weighting coefficients.
- the sampling units 46_1 to 461-1N sample the power weighting coefficients output from the corresponding coefficient conversion units 45-1-45-N at the rising edge of the reference S-times clock, and The sampling result is output.
- the power weighting factor calculation unit 12 of the present embodiment calculates the power weighting factor corresponding to each branch by using the normalization units 441-1 to 441-N
- the average received signal power data is normalized using the reference received signal power data.
- sampling units 46-1 to 46-N are data of the power weighting coefficient and the phase variation of each branch output from the preamble phase variation calculator 11-1 to 11-N. This is for aligning the change timing. For example, sump This is unnecessary when the ring section 3_1 to 3-N and the sampling section 4-1 to 4-N use the same clock.
- FIG. 8 is a diagram illustrating a configuration example of a preamble timing phase complex signal calculation unit 17, which includes an arc tangent unit 51, a double phase calculation unit 52, and a complex signal calculation unit 53. ing.
- preamble timing phase complex signal calculating section 17 of the present embodiment first, arc tangent section 51 outputs averaged 1 Z 2 symbol frequency component complex signal output from averaging section 16. The declination ⁇ between the real component and the imaginary component of the averaged 1Z2 symbol frequency component complex signal is calculated.
- the double phase calculation unit 52 calculates “2X ⁇ ” which is twice the phase of the argument ⁇ ⁇ .
- the complex signal calculator 53 calculates the real component and the imaginary component of the complex signal having the phase of “2 X ⁇ 0” and the predetermined amplitude ⁇ , and calculates the preamble timing and the real component R of the complex signal. And the imaginary component I.
- the real component R and the imaginary component I can be expressed by equations (1) and (2), respectively.
- the real component and the imaginary component of the preamble timing phase complex signal calculated by the preamble timing phase complex signal calculation unit 17 of the present embodiment both have a value of ⁇ or less, and are represented by a small number of bits. it can. Thereby, the circuit scale of the timing reproducing unit 5 can be reduced.
- FIG. 9 is a diagram showing an example of the configuration of the phase shift control / frequency divider 18, which includes a T-ary counter 61, a reference symbol periodic cosine / sine wave generator 62, and a phase shifter 63.
- FIG. 10 is a diagram showing an operation example of the rising edge detection unit 64.
- the phase shift control / frequency divider 18 of the present embodiment operates at the clock speed of the T-ary counter 61 and the reference T times clock, and counts the counter value D that repeatedly counts from 0 to (T-1). Output. Since the reference T-times clock has a clock rate about T times the symbol rate, the repetition period in which the counter value D is counted from 0 to (T-1) is about the same as the symbol rate.
- the reference symbol periodic cosine wave Z sine wave generator 62 generates the cosine wave component C o and the sine wave component S i obtained by the equations (3) and (4) based on the counter value D.
- the phase shifter 63 has an amplitude A, and a cosine wave C s obtained by shifting the cosine wave component C o by the timing phase difference “2X ⁇ 0”. Is calculated.
- the cosine wave C s is a signal synchronized with the Nyquist point of the received signal data.
- the real component of the preamble timing phase complex signal is in operation while the timing recovery unit 5 is operating. Since the R and the imaginary component I change in a specific time unit, the phase of the cosine wave is discontinuous for a moment, and this is a signal that generates “phase jump”.
- the rising edge detector 64 detects the timing synchronized with the Nyquist point of the received signal data based on the timing at which the value of the cosine wave C s changes from negative to positive (change timing of the hard decision clock shown in FIG. 10). Generates a rising edge detection pulse generated at. However, even if the hard decision clock is affected by the phase jump of the cosine wave C s, the rising edge detection unit 64 uses the rising edge interval counter 65 as shown in FIG. The time elapsed since the last rising edge detection pulse was counted is a predetermined time (the number of reference T times clocks) ) If shorter, no rising edge detection pulse is generated.
- the reference T-fold clock is used based on the rising edge detection pulse.
- a reproduced symbol clock is generated by dividing the frequency to 1 ZT times.
- the frequency divider 67 generates a reproduced U-fold clock by dividing the reference T-fold clock to a U / T-fold speed based on the rising edge detection pulse.
- the phase shift control Z dividing section 18 of the present embodiment has a function of ignoring the rising edge of a specific period from the detection of the rising edge of the cosine wave Cs obtained by the phase shifting section 63. I decided. As a result, erroneous detection of a rising edge caused by a phase jump of the cosine wave Cs is reduced, and a stable reproduced symbol clock and a reproduced U-fold clock can be obtained.
- the rising edge detection unit 64 of the phase shift control / frequency division unit 18 detects the reception signal based on the timing at which the value of the cosine wave C s output from the phase shift unit 63 changes from negative to positive.
- the rising edge detection pulse generated at the timing synchronized with the Nyquist point of the signal data was generated.However, the rising edge detection pulse is not limited to this.For example, the rising edge is detected based on the timing at which the value of the cosine wave Cs changes from positive to negative. A detection pulse may be generated.
- the phase shift control frequency divider 18 generates two types of reproduction clocks (reproduction clock and reproduction U-fold clock). However, the number of reproduction clocks generated is not limited, and one or more reproduction clocks are generated. As long as it can generate a lock.
- the timing recovery unit 5 can perform highly accurate timing estimation, the data extracted by the Nyquist point extraction units 21-1 to 21-N As a result, it is possible to suppress deterioration of the SZN ratio due to the estimation error of the reproduced symbol peak and deterioration due to the influence of intersymbol interference to a small level, and obtain good demodulation characteristics.
- a PSK-modulated signal having a data format prepended with a preamble signal is received by one or more receiving antennas.
- a preamble signal is received
- the signal in the first embodiment is received.
- the timing playback unit 5 shown High-speed and high-precision timing estimation is performed using the same configuration.After that, when the received signal has shifted from the preamble signal to the random data section, the estimated timing phase at the time of receiving the preamplifier is used as the initial value, and the random data Apply the timing recovery process for This makes it possible to realize faster and more accurate timing estimation and to obtain good clock tracking characteristics.
- FIG. 11 is a diagram showing a configuration example of a timing recovery circuit according to a second embodiment having N (N is an integer of 1 or more) and number of reception antennas.
- the timing recovery circuit according to the present embodiment includes a timing recovery unit 5a to which a timing recovery process at the time of random data reception is added.
- the timing recovery unit 5a has a configuration in addition to the configuration of the timing recovery unit 5 described above. , Random pattern phase variation calculator 7 1—1 to 7 1—N, multiplier 7 2—1 to 7 2—N, adder 73, symbol frequency component extractor 74, timing phase And a complex signal calculation unit 75.
- FIG. 12 is a diagram showing a configuration example of a receiving apparatus according to the second embodiment including the timing recovery circuit. Note that the configuration is the same as that of FIG. 2 except that the timing reproducing unit 5a is applied.
- timing reproduction section 5a of the second embodiment will be described with reference to FIG.
- the random pattern phase variation calculating section 71-1-1-71N is sampled by the corresponding sampling section 41-1 to 41-N (for example, Then, the phase variation per specific time with respect to the baseband phase data of each branch, which is V (V is a natural number of 3 or more) times the symbol rate, is calculated, that is, the random pattern phase variation.
- V is a natural number of 3 or more
- the signal is calculated by performing a doubling process such as an absolute value operation to remove a modulation component, and is, for example, a signal having a symbol frequency component.
- the multipliers 72-1 to 72-N multiply the random pattern phase variation of the corresponding branch by the power weighting coefficient.
- the calorie calculation unit 73 obtains the combined phase variation amount for the random pattern by adding the multiplication result of each branch by a predetermined plant.
- the random pattern combined phase variation is a signal having a symbol frequency component similarly to the random pattern phase variation.
- the symbol frequency component extraction unit 74 multiplies the cosine wave component and the sine wave component of the symbol period by the random pattern composite phase variation having the symbol frequency component, respectively.
- the frequency component of the symbol frequency component is converted into a DC component, and the real component of the symbol frequency component complex signal and the imaginary component of the symbol frequency component complex signal are output.
- To calculate the cosine wave component and the sine wave component of the symbol period it is necessary to operate at a speed three times or more the symbol rate.
- the timing phase complex signal calculation section 75 outputs the preamble timing phase complex signal output from the preamble timing phase complex signal calculation section 17 as a timing phase complex signal at the time of preamble reception. Then, when the received signal shifts from the preamble signal to the random data section, the timing phase complex signal calculation section 75 sets the brimble timing phase complex signal as an initial value and averages the symbol frequency component complex signal. And outputs the value obtained as a timing phase complex signal.
- phase shift control / frequency divider 18 generates a reproduced symbol clock and a reproduced U-fold clock using the timing phase complex signal output from the timing phase complex signal calculator 75.
- the timing phase complex signal calculating section 75 outputs the preamble timing phase complex signal as it is, Although the process of averaging the number-component complex signal and the switching of are described as the time when the received signal switches from the preamble signal to the random data, the present invention is not limited to this, and the switching timing of the process is arbitrary.
- the timing reproducing section 5a has a function S that presupposes that a preamble signal is added to the beginning of each burst data, and a function of maintaining a timing phase as shown in FIG.
- FIG. 14 is a diagram showing a configuration example of the timing phase complex signal calculation section 75, and includes IIR (Infinite Impulse Response) filters 81, 82, a selection signal generation section 83, and selectors 84, 8 5 and.
- IIR Infinite Impulse Response
- timing phase complex signal calculating section 75 of the present embodiment first, an IIR filter 81, a real component of a timing phase complex signal output from a selector 84 described later, and a symbol frequency component extracting section 74 The averaging process is performed using the symbol frequency component output from the real number component of the complex signal.
- the IIR filter 8 2, the imaginary component of the timing phase complex signal output from the selector 85 described later, and the imaginary component of the symbol frequency component complex signal output from the symbol frequency component extraction unit 74 are Averaging processing is performed by using
- the selection signal generation section 83 for example, when a briumple signal is received (see FIG. 15), the selection phase is output from the preamble timing phase complex signal calculation section 17 to the selectors 84 and 85. A selection signal for selecting a signal to be output is output. When a random pattern is received (see Fig. 15), a selection signal for selecting a signal output from the IIR filters 81 and 82 is output.
- FIG. 15 is a diagram showing an example of the operation timing of the timing reproducing unit 5a.
- the selector 84 selects the preamble timing according to the selection signal.
- the signal output from the phase complex signal calculator 17 or the signal output from the IIR filter 81 is selected and output.
- the selector 85 selects and outputs either the signal output from the preamble timing phase complex signal calculation unit 17 or the signal output from the IIR filter 82 according to the selection signal. I do.
- the timing phase complex signal calculating section 75 of the present embodiment selects a preamplifier timing phase complex signal when receiving a preamble signal in the same manner as in the first embodiment, and converts the received signal from the preamble signal to random data.
- a value obtained by averaging the symbol frequency component complex signal during random data reception is selected as the timing phase complex signal, with the preamble timing phase complex signal during preamble reception as the initial value.
- timing phase complex signal calculation unit 75 by applying the timing phase complex signal calculation unit 75, high-speed and high-precision timing estimation at the time of receiving a preamplifier by the above-mentioned timing reproduction unit 5 is realized. Good clock tracking characteristics can be obtained when receiving random data.
- the addition unit in the timing recovery unit selects the amount of phase variation to be used for addition based on the branch control signal indicating the signal of the branch to be used. Also, in the third embodiment, the diversity / demodulation unit selects Nyquist point baseband phase data and Nyquist point received signal power data to be used for the diversity synthesis based on the branch control signal.
- Embodiment 1 or Embodiment 2 processing different from Embodiment 1 or Embodiment 2, that is, processing for selecting the amount of phase variation used for addition, and Nyquist point baseband phase data and Nyquist point received signal power used for diversity combining will be described. The process of selecting data will be described.
- FIG. 16 is a diagram showing a configuration example of the receiving apparatus according to the third embodiment, and includes a timing reproducing unit 5 b having a function of selecting whether to use the weighted phase variation for addition for each branch. And a diversity / demodulation unit 91 having a function of selecting, for each branch, whether to use the Nyquist point baseband phase data and the Nyquist point received signal power data for diversity combining.
- FIG. 17 is a diagram showing a configuration example (corresponding to the first embodiment) of the timing recovery circuit according to the third embodiment, in which whether or not the weighted phase variation is used for addition is selected for each branch.
- An addition unit 101 having a function of performing
- FIG. 18 is a diagram showing a configuration example (corresponding to the second embodiment) of the timing recovery circuit according to the third embodiment, in which whether or not the weighted phase variation is used for addition is selected for each branch. And an adder 102 having a function of selecting, for each branch, whether to use the weighted random pattern phase fluctuation amount for addition.
- the phase used for addition is selected from among the weighted phase fluctuations output from the multiplication units 13-1 to 13-N.
- the fluctuation amount is selected, the timing is estimated using the synthesized phase fluctuation amount obtained by synthesizing the selected phase fluctuation amount, and the reproduction clock is output (corresponding to the first embodiment).
- the weighted random pattern phase variation output from the multipliers 72-1 to 72-N is selected from the following.
- the random pattern phase variation used for the addition is selected, the timing is estimated using the random pattern combined phase variation obtained by combining the selected random pattern phase variation, and the above-described combined phase variation, and the reproduction clock is calculated. Output.
- the Nyquist point baseband phase output from the Nyquist point extraction sections 21-1 to 21-N Nyquist point baseband phase data and Nyquist point received signal power data used for diversity combining are selected from the data and the Nyquist point received signal power data, and the result of the diversity combining based on the selected data is demodulated.
- the multiplication section 13 3; ! is performed based on the addition section 101 branch control signal.
- the phase variation to be used for addition is selected from the weighted phase variation output from ⁇ 13-N, and then the combined phase variation is calculated using the selected phase variation.
- the addition section 102 further performs multiplication sections 72-1-1 to 72-N based on the branch control signal.
- the random pattern phase variation to be used for addition is selected from the weighted random pattern phase variation output from the above, and then the random pattern combined phase variation is used using the selected random pattern phase variation. Is calculated.
- the independent branch control signals may be input to the timing recovery unit 5b and the diversity Z demodulation unit 91, respectively.
- the common branch control signal is input to the adders 101 and 102, independent branch control signals may be input to the respective adders.
- the branch control signal controls the used branch at two points, the timing recovery section 5b and the diversity Z demodulation section 91.
- the present invention is not limited to this.
- the branch used may be controlled by one or more of N, the sampling unit 4-1 to 4-N, and the Nyquist point extraction unit 21-1 to 21-N.
- the adding unit 101, the adding unit 102, the preamble phase variation calculating unit 111-1-1N, the power weighting coefficient calculating unit 12, the multiplying unit 1 3 _ 1 to 1 3—N, Multiplication unit 7 2—1 to 7 2—N It is also possible to control the branch to be used at one or more places.
- the timing recovery circuit according to the present invention is useful for a communication device configuring a digital wireless communication system, and is particularly suitable for a reception device that performs high-speed and high-precision timing recovery using a preamble signal. ing.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Radio Transmission System (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
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Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200480004969.0A CN1795652A (zh) | 2004-04-28 | 2004-04-28 | 定时再生电路及接收装置 |
| JP2006519140A JP4430073B2 (ja) | 2004-04-28 | 2004-04-28 | タイミング再生回路および受信装置 |
| PCT/JP2004/006209 WO2005107202A1 (ja) | 2004-04-28 | 2004-04-28 | タイミング再生回路および受信装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| PCT/JP2004/006209 WO2005107202A1 (ja) | 2004-04-28 | 2004-04-28 | タイミング再生回路および受信装置 |
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| WO2005107202A1 true WO2005107202A1 (ja) | 2005-11-10 |
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| JP (1) | JP4430073B2 (ja) |
| CN (1) | CN1795652A (ja) |
| WO (1) | WO2005107202A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007295397A (ja) * | 2006-04-26 | 2007-11-08 | Mitsubishi Electric Corp | ダイバーシチ受信装置 |
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| CN103281057A (zh) * | 2013-04-28 | 2013-09-04 | 康力电梯股份有限公司 | 一种输入信号的滤波方法 |
| CN107294625B (zh) * | 2016-03-31 | 2020-09-18 | 北京紫光展锐通信技术有限公司 | 信号功率估计方法及装置、接收机 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321679A (ja) * | 1996-05-31 | 1997-12-12 | Fujitsu Ltd | ダイバーシチ受信装置 |
| JP2001217888A (ja) * | 2000-02-04 | 2001-08-10 | Mitsubishi Electric Corp | タイミング再生装置および復調器 |
| JP2002094588A (ja) * | 2000-09-19 | 2002-03-29 | Oki Electric Ind Co Ltd | クロック再生装置 |
| JP2002101139A (ja) * | 2000-09-22 | 2002-04-05 | Hitachi Kokusai Electric Inc | 復調方法 |
-
2004
- 2004-04-28 JP JP2006519140A patent/JP4430073B2/ja not_active Expired - Fee Related
- 2004-04-28 CN CN200480004969.0A patent/CN1795652A/zh active Pending
- 2004-04-28 WO PCT/JP2004/006209 patent/WO2005107202A1/ja not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321679A (ja) * | 1996-05-31 | 1997-12-12 | Fujitsu Ltd | ダイバーシチ受信装置 |
| JP2001217888A (ja) * | 2000-02-04 | 2001-08-10 | Mitsubishi Electric Corp | タイミング再生装置および復調器 |
| JP2002094588A (ja) * | 2000-09-19 | 2002-03-29 | Oki Electric Ind Co Ltd | クロック再生装置 |
| JP2002101139A (ja) * | 2000-09-22 | 2002-04-05 | Hitachi Kokusai Electric Inc | 復調方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007295397A (ja) * | 2006-04-26 | 2007-11-08 | Mitsubishi Electric Corp | ダイバーシチ受信装置 |
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|---|---|
| JPWO2005107202A1 (ja) | 2008-03-21 |
| JP4430073B2 (ja) | 2010-03-10 |
| CN1795652A (zh) | 2006-06-28 |
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