WO2005098912A1 - 半導体ウェーハの製造方法及びその方法で製造された半導体ウェーハ - Google Patents
半導体ウェーハの製造方法及びその方法で製造された半導体ウェーハ Download PDFInfo
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- WO2005098912A1 WO2005098912A1 PCT/JP2005/006268 JP2005006268W WO2005098912A1 WO 2005098912 A1 WO2005098912 A1 WO 2005098912A1 JP 2005006268 W JP2005006268 W JP 2005006268W WO 2005098912 A1 WO2005098912 A1 WO 2005098912A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910000077 silane Inorganic materials 0.000 claims abstract description 9
- 230000003247 decreasing effect Effects 0.000 claims abstract description 3
- 235000012431 wafers Nutrition 0.000 claims description 144
- 238000001947 vapour-phase growth Methods 0.000 claims description 51
- 239000007789 gas Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 18
- 238000000407 epitaxy Methods 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 7
- 238000007654 immersion Methods 0.000 claims description 7
- 239000002253 acid Substances 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000012071 phase Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 33
- 238000007740 vapor deposition Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 239000002994 raw material Substances 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 22
- 239000000758 substrate Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000007547 defect Effects 0.000 description 12
- 239000000126 substance Substances 0.000 description 6
- 239000011800 void material Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 3
- 239000003513 alkali Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Definitions
- the present invention relates to a method for manufacturing a semiconductor wafer by forming an epitaxial layer on the surface of a wafer having a trench structure and inside the trench by a vapor phase growth method.
- the present invention also relates to a semiconductor wafer manufactured by this method.
- an epitaxy film is formed on a semiconductor substrate including the inside of a trench by an epitaxy growth method, and a portion of the epitaxy film is subjected to an etching process and an epitaxy.
- a method of manufacturing a semiconductor substrate in which film formation processing is repeated a plurality of times and embedded in an epitaxial film in which trenches are stacked (for example, see Patent Document 1) is disclosed.
- an opening in the trench is widened by etching a part of the epitaxial film, so that when the epitaxial film is formed in this state, the opening of the trench is reduced. Can be blocked. As a result, it is possible to suppress the occurrence of poor embedding (cavity) in the trench!
- Patent Document 1 Japanese Unexamined Patent Publication No. 2001-196573 (Claim 4, Specification [0015], Specification [001 6])
- Patent Document 1 In the conventional method of manufacturing a semiconductor substrate disclosed in Patent Document 1, it is necessary to perform epitaxy at a low initial layer force for autodoping control. There was a problem that the throughput was slow and the throughput was poor.
- a first object of the present invention is to reduce the amount of impurities diffused from the semiconductor to the epitaxial layer inside the trench in a stepwise manner, thereby reducing the resistivity of the epitaxial layer inside the trench in a stepwise manner.
- An object of the present invention is to provide a wafer manufactured by such a method.
- a second object of the present invention is to remove the natural oxide film and organic substances formed on the inner surface of the trench and on the surface of the epitaxial layer inside the trench, thereby stably forming the epitaxial layer inside the trench by a vapor phase growth method.
- An object of the present invention is to provide a method for manufacturing a semiconductor wafer and a wafer manufactured by the method, which can be formed homogeneously.
- a third object of the present invention is to provide a method for manufacturing a semiconductor wafer, which can reduce the occurrence of voids which are likely to be formed near the center of a trench and can smooth the surface of an epitaxial layer formed inside the trench. And a wafer manufactured by the method.
- a fourth object of the present invention is to manufacture a semiconductor wafer by growing an epitaxial layer by a vapor phase growth method at a relatively low temperature, whereby the amount of autodoping from the semiconductor to the epitaxial layer itself can be reduced.
- An object of the present invention is to provide a method and a wafer manufactured by the method.
- the invention according to claim 1 uses a vapor deposition method while supplying a silane gas as a source gas into a trench 16 of a semiconductor wafer 10 having a trench structure.
- Growing the epitaxial layer 17 stepwise in a temperature range of ⁇ 1150 ° C, or at a predetermined rate after the stepwise temperature reduction. This is a method for manufacturing a semiconductor wafer in which the epitaxial layer 17 is filled in the trench 16.
- the temperature for forming the epitaxial layer 17 inside the trench 16 by the vapor phase growth method is reduced by a stepwise force or stepwise. Since it is lowered at a predetermined speed after the reduction, the amount of impurities diffused from the semiconductor wafer 10 to the epitaxial layer 17 decreases stepwise.
- the invention according to claim 2 is the invention according to claim 1, and further includes a trench of the semiconductor wafer 10 at a first temperature in a range of 900 to 1150 ° C., as shown in FIGS. 16) forming a first layer 11 on the inner surface by a vapor phase growth method, and forming a vapor phase on the surface of the first layer 11 in the trench 16 at a second temperature in the range of 850 to 1100 ° C lower than the first temperature. Forming a second layer 12 by a growth method, and forming a third layer on the surface of the second layer 12 in the trench 16 by a vapor phase growth method at a third temperature lower than the second temperature in a range of 800 to 50 ° C. Forming a trench 13 and filling the inside of the trench 16 with an epitaxy layer 17 composed of a first layer 11, a second layer 12 and a third layer 13.
- the second temperature lower than the first temperature is formed. Since the second layer 12 was formed on the surface of the first layer 11 in the trench 16 by a vapor phase growth method at a temperature, the diffusion amount of impurities from the semiconductor wafer 10 to the first layer 11 and the first layer 11 The amount of diffusion of impurities from the second layer 12 into the second layer 12 is smaller when the second layer 12 is formed than when the first layer 11 is formed.
- the inside of the trench 16 is formed by vapor phase growth at a third temperature lower than the second temperature. Since the third layer 13 was formed on the surface of the second layer 12, the amount of impurity diffusion from the semiconductor wafer 10 to the first layer 11, the amount of impurity diffusion from the first layer 11 to the second layer 12, The diffusion amount of impurities from the second layer 12 to the third layer 13 is smaller when the third layer 13 is formed than when the second layer 12 is formed.
- the invention according to claim 8 is the invention according to any one of claims 2 to 7, and further includes a state in which a trench 16 is formed in the semiconductor substrate 10 as shown in FIG. 6
- the inner surface of the trench 16 is alkalined at an etching rate of 0.1 to lnmZ.
- water After washing with a mixed solution of a solution and hydrogen peroxide solution, it is characterized by being immersed in hydrofluoric acid for 0.1 to 60 minutes for washing.
- each of the layers 11 to 13 of the epitaxial layer 17 is stably and uniformly formed by a vapor phase growth method. Can be formed.
- the invention according to claim 9 is the invention according to claim 8, and further includes a third layer 13 or a third layer 13 for completely filling the inside of the trench 16 of the semiconductor wafer 10, as shown in FIG.
- the trench 16 is widened by immersion in an acid-based or alkaline-based etchant having an etching rate of 0.1 to 1 mZ for 0.1 to 10 minutes.
- the third layer 13 or the fourth layer for completely filling the inside of the trench 16 grows rapidly inside the widened trench 16, so that the trench Epitaxial layer 17 can be filled inside trench 16 without forming a void near the center of 16.
- the invention according to claim 10 is the invention according to claim 1, wherein a preferable temperature for growing the epitaxial layer by a vapor phase growth method is in a range of 650 to 950 ° C. .
- the invention according to claim 11 is the invention according to claim 1, wherein a further preferable temperature for growing the epitaxial layer by a vapor phase growth method is in a range of 400 ° C to 650 ° C.
- the temperature for growing the epitaxial layer by the vapor phase growth method is low, the amount of auto-doping from the semiconductor to the epitaxial layer is further reduced. That is, impurities contained in semiconductor wafers It becomes more difficult to diffuse into the taxi layer.
- the invention according to claim 12 is, as shown in FIG. 1, a semiconductor wafer 10 manufactured by the method according to any one of claims 1 to 11.
- the semiconductor wafer 10 according to the twelfth aspect does not generate voids near the center of the trench 16 and has desired electrical characteristics.
- a silane gas is supplied as a source gas into a trench of a semiconductor wafer having a trench structure at a temperature of 400 to 1150 ° C by a vapor phase epitaxy method.
- a vapor phase epitaxy method By growing the epitaxy layer while gradually lowering the temperature or decreasing the temperature at a predetermined rate after the temperature is gradually lowered, the inside of the trench is filled with the epitaxy layer.
- the amount of impurities diffused into the epitaxial layer decreases stepwise.
- the resistivity of the epitaxial layer inside the trench can be changed stepwise, and the effect of autodoping from the semiconductor can be suppressed, so that desired electrical characteristics can be obtained.
- the present invention reduces the initial growth temperature. As a result, the epitaxial growth can be performed efficiently.
- the present invention provides, in comparison with the conventional method of manufacturing a semiconductor substrate in which the trench filling property is poor, As the epitaxial growth progresses and the trench width becomes narrower, the temperature is set to a low temperature at which the trench is easily buried, so that the trench burying property can be improved.
- a first layer is formed on the inner surface of the trench of the semiconductor wafer by a vapor deposition method, and at a second temperature lower than the first temperature, the first layer surface in the trench is formed by the vapor deposition method.
- a second layer is formed, and a third layer is formed on the surface of the second layer in the trench at a third temperature lower than the second temperature by a vapor phase epitaxy method. If the semiconductor layer is filled with the epitaxial layer composed of the third layer, the diffusion amount of the impurities contained in the semiconductor wafer into the epitaxial layer is increased in a stepwise manner as the force of the first layer moves toward the third layer via the second layer.
- the present invention is particularly effective when an epitaxial layer is grown inside a trench by a vapor phase growth method using a low resistivity semiconductor wafer containing a large amount of impurities.
- the inner surface of the trench is reduced to 0.
- Cleaning with an aqueous solution of alkaline solution and aqueous hydrogen peroxide at an etching rate of l to lnmZ and then cleaning with hydrofluoric acid removes the natural oxide film and organic substances covering the inner surface of the trench.
- Each layer can be formed stably and homogeneously by the vapor deposition method.
- the third or fourth layer Before forming the third or fourth layer to completely fill the inside of the trench of the semiconductor wafer, use an acid-based or alkaline-based etchant having an etching rate of 0.1 to 1 ⁇ mZ for 0.1 to 1 ⁇ mZ. : If the trench is widened by immersion for LO minutes, the third or fourth layer force to completely fill the inside of the trench will grow rapidly inside the widened trench. As a result, the inside of the trench can be filled with the epitaxial layer without forming a void near the center of the trench.
- the temperature at which the epitaxial layer is grown by vapor phase growth is in the range of 650 ° C to 950 ° C or 400 ° C to 650 ° C, the temperature at which the epitaxial layer is grown by vapor phase growth is Since it is low, the amount of auto-doping in the semiconductor-epitaxial layer is reduced. As a result, desired electrical characteristics of the semiconductor wafer can be obtained.
- FIG. 1 is a fragmentary cross-sectional view showing the inside of a trench of a semiconductor wafer according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing temperature conditions for manufacturing the semiconductor wafer.
- FIG. 3 is a fragmentary cross-sectional view showing the inside of a trench of a semiconductor wafer according to a second embodiment of the present invention.
- FIG. 4 is a diagram showing temperature conditions for manufacturing the semiconductor wafer.
- FIG. 5 is a cross-sectional view of a main part showing the inside of a trench of a semiconductor wafer according to a third embodiment of the present invention.
- FIG. 7 is a cross-sectional view of a principal part showing the inside of a trench of a semiconductor wafer according to a fourth embodiment of the present invention.
- [ 8 ] is a diagram showing temperature conditions for manufacturing the semiconductor wafer. Explanation of reference numerals
- a silane gas is supplied as a source gas to the surface of the wafer 10 and the inside of the trench 16 while the vapor phase is formed.
- the epitaxy layer 17 is grown by gradually lowering the temperature in a temperature range of 400 to 1150 ° C. by a growth method.
- the surface of the wafer 10 is covered with the epitaxial layer 17, and the inside of the trench 16 is filled with the epitaxial layer 17.
- the entire temperature range for growing the epitaxial layer 17 by the vapor phase growth method was limited to the range of 400 to 1150 ° C.
- the wafer 10 is placed in a reactor, and the surface of the wafer 10 and the trench are heated at a first temperature in the range of 900 to 1150 ° C., preferably 950 to 100 ° C.
- the first layer 11 is formed on the inner surface 16 by a vapor growth method.
- the reason why the first temperature was limited to the range of 900 to 1150 ° C was that if the temperature was lower than 900 ° C, there was a problem that polycrystallization and defects increased, and if the temperature exceeded 1150 ° C, the profile deteriorated due to autodoping. This is a car that has a problem that the problem occurs.
- Examples of the vapor phase growth method include a chemical vapor deposition method (CVD method) and a physical vapor deposition method (PVD method), but the crystallinity, mass productivity, simplicity of equipment, It is preferable to grow the epitaxial layer 17 by the CVD method from the viewpoint of ease of forming the device structure.
- the reactor when growing Epitakisharu layer 17 by the CVD method also, so that the pressure in the furnace is 1. 3 X 10 one 5 ⁇ 1. OX 10 _ 1 MPa , a silane gas Monoshira Ngasu ( SiH), disilane gas (SiH), trichlorosilane gas (SiHCl), dichlorosilane
- SiH C1 monochlorosilane gas
- SiCl silicon tetrachloride gas
- silicon is deposited on the surface of the wafer 10 and the inner surface of the trench 16 to form an epitaxial layer 17.
- the thickness w of the first layer 11 is (WZ20) ⁇ w ⁇ (W / l 0), preferably (WZ15) ⁇ w ⁇ (WZ12).
- the reason why the thickness w of the first layer 11 is limited to the range of (WZ20) ⁇ w ⁇ (WZlO) is that if the thickness is less than WZ20, defects increase due to wafer surface properties. Beyond that, there is a problem that the profile is deteriorated due to auto-doping.
- the thickness of the first layer 11 is determined by the temperature and pressure in the reactor, the flow rate of the source gas introduced into the reactor, the reaction time of the wafer 10 with the source gas, and the like.
- the growth of the first layer 11 is stopped, and the temperature in the reaction furnace is lowered to a second temperature in the range of 850 to 1100 ° C, preferably 900 to 1,050 ° C, lower than the first temperature.
- a second layer 12 is formed on the surface of the first layer 11 on the wafer 10 and on the surface of the first layer 11 in the trench 16 by vapor phase epitaxy.
- the second layer 12 is preferably formed by the same method as the first layer 11 described above.
- the reason why the second temperature was limited to the range of 850 to: L 100 ° C is that if the temperature is lower than 850 ° C, there is a problem such as polycrystallization and the number of defects increases.
- the thickness w of the second layer 12 is (WZ10) ⁇ w ⁇ (W / 5), preferably (WZ8) ⁇ w ⁇ (W / 6).
- the growth of the second layer 12 is stopped, and the temperature in the reactor is lowered to a third temperature in the range of 800 to 50 ° C, preferably 850 to 1000 ° C, which is lower than the second temperature.
- a third layer 13 is formed on the surface of the second layer 12 on the wafer 10 and the surface of the second layer 12 in the trench 16 by a vapor phase growth method. It is filled with an epitaxal layer 17 consisting of 12 and a third layer 13.
- the third layer 13 is preferably formed by the same method as the first layer 11 and the second layer 12.
- the etching rate is 0.1 to 11117 minutes, preferably 0.2 minute.
- the trench 16 is widened by being immersed in an acid-based or alkaline-based etching solution having a content of 0.5 mZ for 0.1 to 10 minutes, preferably 5 to 8 minutes.
- the third layer 13 for completely filling the inside of the trench 16 grows rapidly inside the widened trench 16, so that the void is not formed near the center of the trench 16, and the inside of the trench 16 is not formed.
- the epitaxial layer 17 can be filled.
- the reason why the etching rate is limited to the range of 0.1 to 1 ⁇ mZ is that if it is less than 0.1 mZ, there is a problem that the etching processing time is increased, and if it exceeds ⁇ , the control in wet etching is performed. This is because there is a problem that it becomes difficult.
- the reason why the immersion time in the acid-based or alkali-based etchant is limited to the range of 0.1 to: LO minutes is that the trench is not sufficiently opened in less than 0.1 minute, and exceeds 10 minutes. This is because there is a problem that the trench shape is broken.
- the trench 16 After cleaning the inner surface with a mixture of aqueous alkali solution and aqueous hydrogen peroxide at an etching rate of 0.1 to 1 nmZ, preferably 0.3 to 0.8 nmZ, 0.1 to 60 minutes by hydrofluoric acid Wash by immersion for about 2 to 4 minutes.
- the reason why the immersion time in hydrofluoric acid is limited to the range of 0.1 to 60 minutes is that the surface of the wafer 10 and the inner surface of the trench 16 are covered with a natural oxide film or an organic substance by the above-mentioned leaving, so that these natural oxide films are used. This is because the first to third layers 11 to 13 of the epitaxial layer 17 can be formed stably and uniformly by removing organic substances.
- the reason why the etching rate is limited to the range of 0.1 to Lnm / min is that 0.1. If the amount is less than InmZ, there is a problem that the etching process is prolonged, and if the amount exceeds InmZ, generation of particles and surface roughness are caused. This is because there is a defect.
- the silicon wafer 10 In the silicon wafer 10 manufactured as described above, after forming the first layer 11 on the surface of the wafer 10 and the inner surface of the trench 16 by the vapor phase growth method at the first temperature, the silicon wafer 10 having the first temperature lower than the first temperature is formed. Since the second layer 12 was formed on the surface of the first layer 11 on the wafer 10 and the surface of the first layer 11 in the trench 16 by the vapor phase growth method at a temperature of 2, diffusion of impurities from the wafer 10 to the first layer 11 was performed. The amount and the amount of diffusion of impurities from the first layer 11 to the second layer 12 are smaller when the second layer 12 is formed than when the first layer 11 is formed.
- the third temperature lower than the second temperature is obtained. Since the third layer 13 was formed on the surface of the second layer 12 on the wafer 10 and the surface of the second layer 12 in the trench 16 by the vapor phase growth method, the diffusion amount of impurities from the wafer 10 to the first layer 11 was The amount of impurity diffusion from the first layer 11 to the second layer 12 and the amount of impurity diffusion to the third layer 13 also increase when the third layer 13 is formed. Less than an hour.
- the amount of diffusion of impurities contained in the wafer 10 into the epitaxial layer 17 decreases stepwise from the first layer 11 to the third layer 13 via the second layer 12, so that the amount of impurities diffused from the wafer 10 becomes smaller.
- the effect of autodoping on the epitaxial layer 17 can be suppressed, and desired electrical characteristics can be obtained.
- the present invention is particularly effective when the epitaxial layer 17 is grown on the surface of the wafer 10 and inside the trench 16 by vapor phase growth using the low resistivity wafer 10 doped with a large amount of impurities such as boron. It is.
- the first to fourth layers 21 to 24 are formed on the surface of the silicon substrate 20 and the inner surface of the trench 26 by vapor deposition while supplying silane gas as a source gas.
- the first to third layers 21 to 23 are formed in the same manner as the first to third layers of the first embodiment. Concretely, first, the ENO 20 is placed in a reactor at 900-1150 ° C., preferably at a first temperature in the range of 950-1100 ° C., and the surface and trench of the wafer 20 are removed. 26.
- the first layer 21 is formed on the inner surface by vapor phase epitaxy.
- the thickness w of the first layer 21 is set in the range of (W / 20) ⁇ w ⁇ (WZ10), preferably (WZl5) ⁇ w ⁇ (WZ12) .
- the growth of the first layer 21 is stopped, and the temperature in the reaction furnace is reduced to 850 to lower than the first temperature: L100 ° C, preferably to the second temperature in the range of 900 to 1,050 ° C.
- a second layer 22 is formed on the surface of the first layer 21 on the wafer 20 and on the surface of the first layer 21 in the trench 26 by a vapor deposition method.
- the thickness w of this second layer 22 is (WZ10) ⁇ w ⁇ (WZ5), preferably
- the growth of the second layer 22 is stopped, and the temperature in the reactor is lowered to a third temperature in the range of 800 to 50 ° C, preferably 850 to 1000 ° C, which is lower than the second temperature.
- a third layer 23 is formed on the surface of the second layer 22 on the wafer 20 and on the surface of the second layer 22 in the trench 26 by a vapor deposition method.
- the thickness w of this third layer 23 is (WZlO) ⁇ w ⁇ (WZ5), preferably (WZ8
- the thickness w of the third layer 23 is set to (WZlO) ⁇ w ⁇ (W / 6) ⁇ w ⁇ (W / 6).
- the thickness w of the third layer 23 is set to (WZlO) ⁇ w ⁇ (W / 6)
- the reason for limiting to the range of 5) is that there is a defect that defects are increased below WZlO, and that there is a problem that the profile is deteriorated due to autodoping above WZ5.
- the growth of the third layer 23 is stopped, and the temperature in the reactor is lowered to 750 to 100 ° C lower than the third temperature, preferably to a fourth temperature in the range of 800 to 950 ° C.
- the fourth layer 24 is formed on the surface of the third layer 23 on the wafer 20 and the surface of the third layer 23 in the trench 26 by a vapor phase growth method, so that the inside of the trench 26 is formed by the first layer 21, the second layer 22, It is filled with an epitaxial layer 27 consisting of a third layer and a fourth layer 24.
- the fourth layer 24 is preferably formed by the same method as the first to third layers 21 to 23.
- the reason why the fourth temperature was limited to the range of 750 to 1000 ° C was that, when the temperature was lower than 750 ° C, there was a problem such as polycrystallization and an increase in defects. Because there is.
- the configuration is the same as that of the first embodiment.
- the etching rate is 0.1 to 11117 minutes, preferably 0.2.
- the trench 26 is widened by being immersed in an acid-based or alkaline-based etching solution having a content of 0.5 mZ for 0.1 to 10 minutes, preferably 5 to 8 minutes.
- the fourth layer 24 for completely filling the inside of the trench 26 grows quickly inside the widened trench 26, so that no void is formed near the center of the trench 26.
- the epitaxial layer 27 can be filled.
- the inner surface of the trench 26 is washed with a mixed solution of an alkaline aqueous solution and a hydrogen peroxide solution at an etching rate of 0.1 to LnmZ, preferably 0.5 to 0.8 nmZ, and then washed with hydrofluoric acid.
- the surface of the wafer 20 and the inner surface of the trench 26 are covered with the natural oxide film and the organic material by the above-mentioned leaving, and by removing the natural oxide film and the organic material, the first layer 27 of the epitaxial layer 27 is removed.
- the fourth layers 21 to 24 stably and uniformly.
- the silicon wafer 20 manufactured as described above, after the first layer 21 is formed on the surface of the wafer 20 and the inner surface of the trench 26 by the vapor phase growth method at the first temperature, the silicon wafer 20 having the first temperature lower than the first temperature is formed. Since the second layer 22 was formed on the surface of the first layer 21 on the wafer 20 and the surface of the first layer 21 in the trench 26 by the vapor phase growth method at a temperature of 2, diffusion of impurities from the wafer 20 to the first layer 21 was performed. The amount and the amount of impurity diffusion from the first layer 21 to the second layer 22 are smaller when the second layer 22 is formed than when the first layer 21 is formed.
- the third temperature lower than the second temperature is applied. Since the third layer 23 was formed on the surface of the second layer 22 on the wafer 20 and the surface of the second layer 22 in the torch 26 by the vapor phase growth method, the amount of impurity diffusion from the wafer 20 to the first layer 21 was determined. The amount of impurity diffusion from the first layer 21 to the second layer 22 and the amount of impurity diffusion from the second layer 22 to the third layer 23 are larger when the third layer 23 is formed than when the second layer 22 is formed. Less than time.
- the diffusion amount of impurities contained in the wafer 20 into the epitaxial layer 27 decreases stepwise from the first layer 21 to the fourth layer 24 via the second layer 22 and the third layer 23.
- the effect of autodoping on the epitaxial layer 27 from the wafer 20 can be further suppressed as compared with the first embodiment, and desired electrical characteristics can be obtained.
- the present invention is particularly effective when the epitaxial layer 27 is grown on the surface of the wafer 20 and the inside of the trench 26 by vapor phase growth using a low resistivity wafer 20 doped with a large amount of impurities such as boron. It is.
- FIG. 5 and FIG. 6 show a third embodiment of the present invention.
- the first to third layers 31 to 33 are formed on the surface of the silicon wafer 30 and the inner surface of the trench 36 by vapor phase growth while supplying silane gas as a source gas.
- the first and second layers 31, 32 are formed similarly to the first and second layers of the first embodiment. Specifically, first, the wafer 30 is placed in a reactor, and vapor phase growth is performed on the surface of the wafer 30 and the inner surface of the trench 36 at a first temperature in the range of 900 to 1150 ° C., preferably 950 to 100 ° C.
- a first layer 31 is formed by a method.
- the thickness w of the first layer 31 is set in the range of (WZ20) ⁇ w ⁇ (WZ10), preferably (WZl5) ⁇ w ⁇ (WZ12).
- the growth of the first layer 31 is stopped, and the temperature in the reactor is lowered from the first temperature to 850 to: L100 ° C, preferably to the second temperature in the range of 900 to 1,050 ° C.
- a second layer 32 is formed on the surface of the first layer 31 on the wafer 30 and on the surface of the first layer 31 in the trench 36 by a vapor deposition method.
- the thickness w of the second layer 32 is (WZ10) ⁇ w ⁇ (WZ5), preferably
- the growth of the second layer 32 is stopped, and the temperature is lowered at a rate of 1 to LOO ° CZ, preferably 6 to 10 ° CZ from the second temperature until the temperature reaches 800 ° C. , @Aha 30 Second Layer 32 Table
- a third layer 33 is formed on the surface and the surface of the second layer 32 in the trench 36 by vapor phase epitaxy, and the inside of the trench 36 is an epitaxy layer composed of the first layer 31, the second layer 32 and the third layer 33. Fill with 37.
- the reason why the cooling rate at the time of forming the third layer 33 is limited to the range of 1 to: LOO ° CZ is that if the temperature is less than 1 ° CZ, the growth time is prolonged.
- the minimum temperature when forming the third layer 33 is limited to 800 ° C. is that the epitaxial layer 37 does not grow on the surface of the wafer 30 and the inner surface of the trench 36 at a temperature lower than 800 ° C.
- the thickness of the third layer 33 is w, 2w
- the third layer 33 has better characteristics than the third layer of the first embodiment in terms of the uniformity of the profile. Operations other than those described above are substantially the same as the operations in the first embodiment, and thus, repeated description will be omitted.
- the first to fourth layers 41 to 44 are formed on the surface of the silicon wafer 40 and the inner surface of the trench 46 by vapor phase growth while supplying silane gas as a source gas.
- the first to third layers 41 to 43 are formed in the same manner as the first to third layers of the second embodiment.
- the ENO 40 is placed in a reactor at 900-1150 ° C., preferably at a first temperature in the range of 950-1100 ° C. and the surface of the wafer 40 and the trench.
- the first layer 41 is formed on the inner surface of the substrate 46 by a vapor growth method.
- the thickness w of the first layer 41 is set in the range of (W / 20) ⁇ w ⁇ (WZlO), preferably (WZ15) ⁇ w ⁇ (WZ12).
- the growth of the first layer 41 is stopped, and the temperature in the reactor is reduced to a second temperature in the range of 850 to 1050 ° C, preferably 900 to 1000 ° C, which is lower than the first temperature.
- a second layer 42 is formed on the surface of the first layer 41 on the wafer 40 and on the surface of the first layer 41 in the trench 46 by a vapor deposition method.
- the thickness w of this second layer 42 is (WZlO) ⁇ w ⁇ (WZ5), preferably
- the growth of the second layer 42 is stopped, and the temperature in the reactor is lowered to a third temperature in the range of 800 to 1000 ° C., preferably 850 to 950 ° C. lower than the second temperature.
- a third layer 43 is formed on the surface of the second layer 42 on the wafer 40 and on the surface of the second layer 42 in the trench 46 by vapor phase epitaxy.
- the thickness w of this third layer 43 is (WZlO) ⁇ w ⁇ (WZ5), preferably (WZ8)
- a fourth layer 44 is formed by a method, and the inside of the trench 46 is filled with an epitaxial layer 47 including a first layer 41, a second layer 42, a third layer 43, and a fourth layer 44.
- the reason why the temperature lowering rate at the time of forming the fourth layer 44 is limited to the range of 1 to 100 ° CZ is that if the temperature is less than 1 ° CZ, the growth time is prolonged. If it exceeds, there is a problem that the number of defects increases.
- the configuration is the same as that of the second embodiment.
- the fourth layer 44 has characteristics superior to the fourth layer of the third embodiment in terms of the dopant profile.
- the operation other than the above is substantially the same as the operation of the second embodiment, and thus the description thereof will not be repeated.
- the entire temperature range when growing an epitaxial layer inside the trench of a semiconductor wafer by vapor phase growth is 750 to 1150 ° C. 650-950 ° C.
- the first temperature is set to 850 to 950 ° C
- the second temperature is set to be lower than the first temperature.
- the third temperature is lower than the second temperature, 650-750 ° C.
- the first temperature is set to 850 to 950 ° C
- the second temperature is set to be lower than the first temperature.
- the third temperature is 750-850 ° C. lower than the second temperature
- the fourth temperature is 650-800 ° C. lower than the third temperature.
- the entire temperature range when growing the epitaxial layer inside the trench of the semiconductor wafer by the vapor phase growth method is 750 to 1150 ° C.
- the force may be 400-650 ° C.
- the first temperature is set to 500 to 650 ° C
- the second temperature is set lower than the first temperature.
- the third temperature is lower than the second temperature! ⁇ 400-550 ° C.
- the first temperature is set to 550 to 650 ° C
- the second temperature is set to be lower than the first temperature.
- the third temperature is 450-550 ° C. lower than the second temperature
- the fourth temperature is 400-500 ° C. lower than the third temperature. In these cases, the temperature at which the epitaxial layer is grown by the vapor phase growth method is lower, and the autodoping from the semiconductor wafer to the epitaxial layer is further reduced, so that better electric characteristics can be obtained.
- the silicon wafer is described as the semiconductor wafer.
- a GaAs wafer, an InP wafer, a ZnS wafer, or a ZnSe wafer may be used.
- first and third embodiments three epitaxy layers are formed inside the trench, and in the second and fourth embodiments, four epitaxy layers are formed inside the trench. Two or five or more epitaxy layers may be formed inside the trench.
- the present invention is applied to obtain desired electrical characteristics of the semiconductor wafer by changing the resistivity of the epitaxial layer inside the trench in a stepwise manner and suppressing the influence of autodoping on the semiconductor wafer. It can.
- the present invention is effective when a low resistivity semiconductor wafer doped with a large amount of impurities such as boron is used to grow an epitaxial layer on the surface of the semiconductor wafer and inside the trench by a vapor phase growth method. It is.
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EP05727725.3A EP1734565B1 (en) | 2004-04-05 | 2005-03-31 | Method for manufacturing semiconductor wafer |
US10/562,235 US7776710B2 (en) | 2004-04-05 | 2005-03-31 | Manufacturing method of semiconductor wafer having a trench structure and epitaxial layer |
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JP2004110634A JP3961503B2 (ja) | 2004-04-05 | 2004-04-05 | 半導体ウェーハの製造方法 |
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JP4788519B2 (ja) * | 2006-08-07 | 2011-10-05 | 株式会社デンソー | 半導体基板の製造方法 |
US20090273102A1 (en) * | 2005-10-06 | 2009-11-05 | Syouji Nogami | Semiconductor Substrate and Method for Manufacturing the Same |
JP5011881B2 (ja) | 2006-08-11 | 2012-08-29 | 株式会社デンソー | 半導体装置の製造方法 |
JP2009176784A (ja) * | 2008-01-22 | 2009-08-06 | Covalent Materials Tokuyama Corp | 薄膜エピタキシャルウェーハの製造方法 |
JP5336956B2 (ja) * | 2008-07-31 | 2013-11-06 | 株式会社日立国際電気 | 半導体装置の製造方法及び基板処理装置 |
US20120273916A1 (en) | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
WO2010109892A1 (ja) | 2009-03-26 | 2010-09-30 | 株式会社Sumco | 半導体基板、半導体装置及び半導体基板の製造方法 |
CN103503155B (zh) * | 2011-04-27 | 2018-11-30 | 飞兆半导体公司 | 用于功率器件的超结结构及制造方法 |
JP6150075B2 (ja) * | 2014-05-01 | 2017-06-21 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
US10002780B2 (en) * | 2016-05-17 | 2018-06-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of manufacturing a semiconductor structure |
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JP2001196573A (ja) * | 1999-10-28 | 2001-07-19 | Denso Corp | 半導体基板とその製造方法 |
JP2003218037A (ja) * | 2002-01-21 | 2003-07-31 | Denso Corp | 半導体基板の製造方法 |
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US3189494A (en) * | 1963-08-22 | 1965-06-15 | Texas Instruments Inc | Epitaxial crystal growth onto a stabilizing layer which prevents diffusion from the substrate |
DE3684539D1 (de) * | 1985-09-06 | 1992-04-30 | Philips Nv | Herstellungsverfahren einer halbleitervorrichtung. |
US5227330A (en) * | 1991-10-31 | 1993-07-13 | International Business Machines Corporation | Comprehensive process for low temperature SI epit axial growth |
JP3918565B2 (ja) * | 2002-01-21 | 2007-05-23 | 株式会社デンソー | 半導体装置の製造方法 |
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JP2001196573A (ja) * | 1999-10-28 | 2001-07-19 | Denso Corp | 半導体基板とその製造方法 |
JP2003218037A (ja) * | 2002-01-21 | 2003-07-31 | Denso Corp | 半導体基板の製造方法 |
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JP2005294711A (ja) | 2005-10-20 |
US20070128836A1 (en) | 2007-06-07 |
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EP1734565B1 (en) | 2016-05-11 |
EP1734565A4 (en) | 2010-12-01 |
US7776710B2 (en) | 2010-08-17 |
JP3961503B2 (ja) | 2007-08-22 |
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