WO2005091269A2 - Ensemble circuit electrique pour dispositif d'affichage - Google Patents

Ensemble circuit electrique pour dispositif d'affichage Download PDF

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Publication number
WO2005091269A2
WO2005091269A2 PCT/IB2005/050769 IB2005050769W WO2005091269A2 WO 2005091269 A2 WO2005091269 A2 WO 2005091269A2 IB 2005050769 W IB2005050769 W IB 2005050769W WO 2005091269 A2 WO2005091269 A2 WO 2005091269A2
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WO
WIPO (PCT)
Prior art keywords
signal
calibration
coupled
input terminal
driver
Prior art date
Application number
PCT/IB2005/050769
Other languages
English (en)
Other versions
WO2005091269A3 (fr
Inventor
Adrianus Sempel
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to CN2005800077322A priority Critical patent/CN101421777B/zh
Priority to EP05708907.0A priority patent/EP1728240B1/fr
Priority to US10/598,765 priority patent/US7791570B2/en
Priority to KR1020067018348A priority patent/KR101123197B1/ko
Priority to JP2007502468A priority patent/JP4977005B2/ja
Publication of WO2005091269A2 publication Critical patent/WO2005091269A2/fr
Publication of WO2005091269A3 publication Critical patent/WO2005091269A3/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages

Definitions

  • the invention relates to an electrical circuit arrangement for a display device comprising an input terminal for receiving a first signal, a first memory element, and a driver element for outputting a second signal in accordance with said first signal via an output terminal.
  • US 2001/0052606 discloses a display device comprising a matrix of pixels at crossings of row and column electrodes.
  • the pixels each comprise a current mirror circuit to cope with transistor uniformity issues resulting from differences between drive transistors with respect to the charge carrier mobility and threshold voltage.
  • the currents in these types of display devices are very small, and the voltages required to drive pixels differ widely for pixels to be driven subsequently. This results in the disadvantage of long programming times for the display pixels, which are required to charge any parasitic capacitances with the very small currents. As these long programming times are not always available, the light emitted from the display pixels may not accurately reflect the current signal applied to the display pixel.
  • This object is achieved by providing an electrical circuit arrangement for a display device, wherein said arrangement comprises an input terminal for receiving a first signal; a first memory element for storing information about the first signal; a driver element coupled to the first memory element for outputting a second signal via an output terminal in accordance with the information about the first signal; and a calibration circuit coupled between the driver element and the input terminal for matching a potential difference between the driver element and the input terminal during a calibration phase prior to receiving the first signal.
  • the calibration circuit comprises a calibration switch for coupling the input terminal to a calibration voltage.
  • the voltage at the input terminal reaches in a relatively very short time the value of the calibration voltage. So, during the calibration phase the calibration circuit matches the difference between this calibration voltage and the potential of the driver element.
  • the switch may be a common calibration switch for all calibration circuits coupled to the input terminal.
  • the calibration switch may be controlled by a display controller.
  • the calibration circuit further comprises a calibration transistor coupled with its main terminals between the input terminal and the driver element, and a second memory element coupled to a gate of the calibration transistor.
  • the calibration transistor carries during the calibration phase through its main terminals a current corresponding to the first signal of the previous programming phase.
  • the second memory element is set during this calibration phase to such a value, that the gate of the transistor receives a voltage, which results in the desired current, so corresponding to the previous first signal, through the main terminals while the voltage difference between its main terminals matches the voltage difference between the input terminal and the driver element.
  • the calibration circuit may further comprise a switch coupled between one of the main terminals and the gate of the calibration transistor. This switch may be closed during the calibration phase to couple the potential of the driver element to the second memory element. A further switch may be coupled between the driver element and the output terminal in order to block an output current, forming the second signal as provided by the driver element, from flowing to the output terminal during the calibration and programming phase. Another switch may be coupled between the driver element and the calibration circuit. This switch may be closed during the calibration and the programming phase to couple the output current to the calibration transistor.
  • the first memory element is arranged in a current mirror circuit.
  • Current mirror circuits facilitate in replication of an input signal to an identical output signal.
  • the driver element may be a drive transistor having a gate connected to said first memory element, and a main terminal coupled to the calibration circuit, the gate further being coupled via a switch to the main terminal of the drive transistor.
  • the first memory element may comprise a capacitor.
  • the invention further relates to a column driver comprising an electrical circuit arrangement as described above. This element of a display device typically receives a first signal that is to be quickly and accurately converted to a second signal.
  • the invention further relates to a display device comprising a plurality of display pixels comprising an electrical circuit arrangement as described above.
  • Another aspect of the invention provides a product comprising the display device according to the invention and signal processing circuitry.
  • the product may be a handheld device such as a mobile phone, a Personal Digital Assistant (PDA) or a portable computer as well as a device such as a monitor for a Personal Computer, a television set, or a display on e.g. a dashboard of a car.
  • PDA Personal Digital Assistant
  • the invention finally relates to a method for addressing a display pixel. Further dependent claims define advantageous embodiments.
  • the invention will be further illustrated with reference to the attached drawings, which show a preferred embodiment according to the invention. It will be understood that the invention is not in any way restricted to this specific and preferred embodiment.
  • Fig. 1 shows a product comprising an active matrix display device
  • Fig. 2 shows a schematical illustration of an active matrix display device shown in Fig. 1
  • Fig. 3 shows detailed illustrations for a display pixel and a driver part of a column driver for an active matrix display as shown in Fig. 2
  • Fig. 4 shows two display pixels as shown in Fig. 3 along a column electrode of the display shown in Fig. 2
  • Fig. 5 shows an active matrix display device incorporating a display pixel according to an embodiment of the invention
  • Figs. 6A-6C show various stages in the operation of the active matrix display device according to an embodiment of the invention.
  • Fig. 1 shows a product 1 comprising an active matrix display device 6 and signal processing circuitry SP.
  • the display device 6 comprises an active matrix display panel 2 having a plurality of display pixels 3 arranged in a matrix of rows 4 and columns 5.
  • the display panel 2 is an active matrix display comprising display pixels 3 containing polymer light emitting diodes (PLEDs) or small molecule light emitting diodes (SMOLEDs).
  • PLEDs polymer light emitting diodes
  • SMOLEDs small molecule light emitting diodes
  • the display panel 2 may be a high resolution display panel as the available programming times in such display panels are very small.
  • the product 1 may be a television receiver, in which case the signal processing circuitry SP may include circuitry for receiving a television signal and converting the television signal into a format for driving a data input 10 of the display device 6.
  • the product 1 may be a handheld device such as a mobile phone or PDA, a portable computer or a monitor for a personal computer or any other product with a display device.
  • the signal processing circuitry SP may include data processing circuitry and circuitry for processing of images to be displayed into a format suitable for driving the data input 10.
  • Fig. 2 shows a schematical illustration of an active matrix display device 6, comprising e.g. a PLED display panel 2 of product 1 as shown in Fig. 1.
  • the display device 6 comprises a display controller 7, including a row selection circuit 8 and a column driver 9 including driver parts 9A for driving the respective columns 5 (see Fig. 1) of display pixels 3.
  • a data signal comprising information or data such as for (video)images to be presented on the display panel 2, is received via a data input 10 by the display controller 7.
  • the data may be written as driver programming currents Idat via line 13, the column driver 9 and data lines 1 1 to the appropriate display pixels 3 for each column 5.
  • FIG. 3 shows an electrical circuit arrangement for a current programmable display pixel 3 wherein a first signal is applied as a current Ip r0g via the column electrode 1 1.
  • a driving transistor T2 is used in both programming the display pixel 3 and in driving an emissive element 14, such as a PLED element, via terminal 15.
  • the application of the programming current over the column electrode 1 1 is indicated by a current source I prog , representing the driver part 9A.
  • a transistor T4 connects a capacitor C with a current carrying electrode of the driving transistor T2 while the emissive element 14 is isolated from the driving transistor T2 by a transistor T3.
  • the data input programming current is forced through T2 while the capacitor C is charged or discharged depending on the previously programmed value to reach the associated gate-source voltage V GS for T2.
  • the drain current of the driving transistor T2 is fed as a second signal to the emissive element 14.
  • the memory function of the capacitor C assures that the current is a copy of the programming current signal received over line 1 1.
  • the current I through the driving transistor T2 is equal to I pr0g which is proportional to ⁇ (V-Vt) 2 , wherein ⁇ is the mobility of the charge carriers, Vt the threshold voltage of the driving transistor T2 and V the gate-source voltage of the driving transistor T2. It is assumed here that the current I from the driving transistor T2 is indeed identical to the programming current I prog , which is a reasonable approximation for a display pixel 3 with a current mirror circuit.
  • the programming voltage Vp r0g representing the voltage that results from the application of the programming current I pr og therefore yields:
  • V prog V ec -Vt-V(I prog / ⁇ )
  • V cc is the voltage supplied to the power line.
  • the current mirror circuit of the display pixel 3 shown in Fig. 3 has the advantageous feature that at low frequencies, despite differences in mobility ⁇ and threshold voltages Vt of the driving transistors between the various display pixels 3, the current I
  • lght will hereinafter also be called the second signal.
  • Each driver part 9A may apply the same circuit arrangement as described above for the display pixels. In this case (see Fig. 2) the column driver 9 receives data in the form of the driver programming currents I at (corresponding to the first signal) via line 13.
  • Each of the driver parts 9A may be programmed sequentially by its corresponding part of the driver programming currents I dat - After the sequential programming of the driver parts 9A, each of the driver parts 9A may simultaneously provide its programming current I pr0 g to the data line 11 coupled to it. So, in case the electrical circuit arrangement is applied to a driver part 9A, the programming current I prog , being the resulting output of the arrangement, corresponds to the second signal as mentioned in the description of the current programmable display pixel 3.
  • Fig. 4 shows two display pixels 3 as shown in Fig. 3 of all the display pixels 3 along the column electrode 11 of the display panel 2. For reasons of clarity the transistors Tl, T3 and T4 have been drawn as switches SI, S3 and S4.
  • the mobilities ⁇ and threshold voltages Vt of the driving transistors T2 determine the voltage V prog on the column electrode 11 as the display pixel circuits stabilize for a given programming current I prog .
  • the voltage Vp r og may differ significantly.
  • the corresponding switch SI is closed and the voltage V pro g at the column electrode 11 will stabilize at a certain value depending on the first programming current and the characteristics of T2 of this display pixel 3. If subsequently the upper display pixel 3 is programmed, SI of the lower display pixel 3 opens while SI of the upper display pixel 3 is closed.
  • the voltage V prog is likely to stabilize at a different value compared to the voltage for the lower display pixel 3 because the characteristics of the driving transistor T2 of the upper display pixel 3 are presumably different from those of the driving transistor T2 of the lower display pixel 3.
  • the programming currents I prog are typically low, i.e. in the order of nanoamperes in the dark region to microamperes at full brightness of the emissive element 14.
  • the line capacitance of the column electrode 11 may be in the order of 100 pF.
  • a programming current of 10 nanoamperes results in a period of 10 milliseconds to bring the column electrode 1 1 to the required voltage V prog .
  • Such long stabilization times limit operation of the display panel 2 at high frequencies, requiring relatively short programming times.
  • the capacitance of the column electrode 11 increases, yielding worse performance.
  • the trend to use higher resolutions and the use of highly efficient organic LED material results in a decrease of the programming currents for each display pixel 3.
  • Fig. 5 is a schematic illustration of the basic idea of the invention.
  • An electrical circuit arrangement A for a display pixel 3 or a driver part 9A as used in a display device 6 as shown in Fig. 2 comprises an input terminal 1 1 , 13 respectively, for receiving as first signal the current I pr0 g or Idat and an output terminal 15 or 11, respectively, for outputting as the second signal the current I ⁇ , g h . or Ip r0 g for a display pixel 3 or a driver part 9A, respectively.
  • the arrangement A further contains a first memory element Ml coupled to a driver D for outputting the second signal I- lgh t or I prog in accordance with the first signal I pr0g or Idat, and a second memory element M2 connected to a calibration circuit S for matching a potential difference between the driver D and the input terminal 1 1, 13 by storing data in the second memory element M2 related to said first signal I prog or Idat-
  • the first signal I prog or I at is received at the input terminal 1 1, 13 and stored in the first memory element Ml during a programming phase.
  • a second signal liig h t or Ip rog is generated from the driver element D in accordance with the first signal I pr ⁇ g or I at during an output phase.
  • the data relating to the first signal I prog or Idat are stored in the second memory element M2 during a calibration phase.
  • the data relating to the first signal may be transferred via the calibration circuit to the second memory M2 or may be transferred via a direct coupling of the first memory Ml and the second memory M2 (not shown).
  • the data stored in the second memory M2 are used to preset the calibration circuit. This preset involves the setting of a voltage across the calibration circuit which matches the difference between the potential of the input terminal 11, 13 and the driver D. This setting is done during the calibration phase to such a value, that it carries the current corresponding to the previously received first signal.
  • the further first signal does not differ from the previous one, there is no change of the potential of the input terminal 11, 13, required and as a consequence, there is for example, no delay in the programming phase caused by the charging of the line capacitance by the programming current I pr og. So, if subsequently a further first signal is received at the input terminal 11,13 a potential of said input terminal 11,13 only changes if the further first signal differs from the previously received first signal or the data stored in M2 are not yet in accordance with the data relating to the first signal although the further first signal is identical to the original or previous first signal.
  • the calibration phase may be skipped if the further first signal does not differ from the previously received first signal.
  • Figs. 6A-6C show an application of the basic arrangement A displayed in Fig. 5 for a display pixel 3. It should however be appreciated that the invention is by no means limited to this specific application.
  • the display pixel 3 is shown in the output phase.
  • the voltage over the capacitor C may cause T2 to drive the current emissive element 14 via the second terminal 15 with a second signal I. lgh t as a result of a previously received first signal I prog of which data are stored at the capacitor C.
  • the invention does not require that light is emitted from the emissive element 14.
  • T2 corresponds to the driver element D and the capacitor C corresponds to the first memory element Ml of Fig. 5.
  • Fig. 6B the calibration phase is shown.
  • the data relating to the previous first signal I pr0 g are transferred to the capacitor C ca ⁇ by closing switches S 1 and S5 prior to reception of a first signal I prog at the column electrode 1 1.
  • the capacitor C ca ⁇ corresponds to the second memory element M2 in Fig. 5.
  • This calibration phase may be triggered by the display controller 7 actuating switches SI and S5.
  • S3 is open.
  • Switch S4 is open such that the display pixel 3 is not programmed by charging or discharging the capacitor C.
  • the switch S ca ⁇ is closed applying a calibration voltage V ca ⁇ of e.g.
  • Fig. 6C illustrates the programming phase wherein the display pixel 3 is programmed by charging the capacitor C to the adequate voltage. Accordingly, S5 is opened, switch S4 is closed and switch S3 remains opened. Further the switch S ca
  • the capacitor Ccai ensures maintenance of the input state on the column electrode 11 after opening of the switch Sea l . As S5 is opened the gate voltage of the calibration transistor T ca ⁇ will remain constant at the value previously calibrated. As a result of the current the drain current of Tea) equals the programming current of the previously applied first signal.
  • the actual programming current will now flow through T ca ⁇ , SI and T2 such that the voltage over the capacitor C increases or decreases to a value where the current through the driving transistor T2 is equal to the programming current I pr og. If the display pixel 3 should not emit light for a particular percentage of the frame time when it is not addressed, i.e. a reduced duty cycle applies, the switch S3 should be open for this percentage of the frame time.
  • the calibration phase described above may be executed row-wise for each column 5. However, it is advantageous to execute the calibration phase for more than one row 4 of display pixels 3 at the time or even for the whole display panel 2 at once. The latter option requires the charge on C ca ⁇ to be sufficiently stable, i.e.
  • a result of the calibration phase displayed in Fig. 6B is that the display pixels 3 can be quickly and accurately current programmed as a result of the calibration with the previously applied current signal. Further, if substantially the same current signals are received as subsequent first signals for a particular display pixel 3 at the input terminal 11, the remaining error in the current output to the emissive element 14 will reduce as a result of the recursive action provided by the presence of the first and second memory elements C and C ca ⁇ .
  • a disadvantage of the active matrix display device 6 according to the invention is the increase in the area accommodated by circuitry for each display pixel 3 which is detrimental for the aperture of the display pixel.
  • the invention can be applied in active current-addressed matrix displays as described above and allows poor initial matching of the driver transistors T2 between the display pixels 3. Also field emission display drivers can advantageously use the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

Ensemble circuit électrique (A) conçu pour un dispositif d'affichage (6) et comprenant une borne d'entrée (11, 13), un premier élément de mémoire (M1); un élément d'attaque (D) couplé au premier élément de mémoire (M1) et un circuit d'étalonnage (S) couplé entre l'élément d'attaque (D) et la borne d'entrée (11, 13). L'information associée au premier signal (Iprog, Idat) reçue par l'intermédiaire de la borne d'entrée (11, 13) est mémorisée dans le premier élément de mémoire (M1). L'élément d'attaque produit un deuxième signal (Ilight, Iprog) par l'intermédiaire d'une borne de sortie (15, 11) selon l'information mémorisée dans le premier élément de mémoire (M1). Ce circuit d'étalonnage (S) équilibre une différence de potentiel entre l'élément d'attaque (D) et la borne d'entrée (11, 13) pendant une phase d'étalonnage préalable à la réception du premier signal (Iprog; Idat).
PCT/IB2005/050769 2004-03-12 2005-03-02 Ensemble circuit electrique pour dispositif d'affichage WO2005091269A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2005800077322A CN101421777B (zh) 2004-03-12 2005-03-02 显示装置的电路装置
EP05708907.0A EP1728240B1 (fr) 2004-03-12 2005-03-02 Ensemble circuit electrique pour dispositif d'affichage
US10/598,765 US7791570B2 (en) 2004-03-12 2005-03-02 Electrical circuit arrangement for a display device
KR1020067018348A KR101123197B1 (ko) 2004-03-12 2005-03-02 표시장치를 위한 전기회로 장치
JP2007502468A JP4977005B2 (ja) 2004-03-12 2005-03-02 表示装置用電気回路配置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04101031 2004-03-12
EP04101031.5 2004-03-12

Publications (2)

Publication Number Publication Date
WO2005091269A2 true WO2005091269A2 (fr) 2005-09-29
WO2005091269A3 WO2005091269A3 (fr) 2009-01-29

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US (1) US7791570B2 (fr)
EP (1) EP1728240B1 (fr)
JP (1) JP4977005B2 (fr)
KR (1) KR101123197B1 (fr)
CN (1) CN101421777B (fr)
TW (1) TWI413042B (fr)
WO (1) WO2005091269A2 (fr)

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TWI386909B (zh) * 2008-12-31 2013-02-21 Princeton Technology Corp 顯示器驅動電路及調整顯示器之輸出亮度的方法
TWI393115B (zh) * 2008-12-31 2013-04-11 Princeton Technology Corp 顯示器驅動電路及調整顯示器輸出亮度的方法
CN115568288B (zh) * 2021-04-30 2023-10-31 瑞萨设计(英国)有限公司 电流驱动器

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US7791570B2 (en) 2010-09-07
WO2005091269A3 (fr) 2009-01-29
EP1728240B1 (fr) 2013-08-21
US20070182684A1 (en) 2007-08-09
EP1728240A2 (fr) 2006-12-06
CN101421777B (zh) 2012-07-04
TW200540749A (en) 2005-12-16
KR20070003915A (ko) 2007-01-05
CN101421777A (zh) 2009-04-29
KR101123197B1 (ko) 2012-03-19
JP2007529033A (ja) 2007-10-18
TWI413042B (zh) 2013-10-21
JP4977005B2 (ja) 2012-07-18

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