WO2005059765A1 - Convertisseur a interface bus apte a convertir un protocole de bus amba ahb en protocole de bus de type i960 - Google Patents

Convertisseur a interface bus apte a convertir un protocole de bus amba ahb en protocole de bus de type i960 Download PDF

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Publication number
WO2005059765A1
WO2005059765A1 PCT/CN2003/001085 CN0301085W WO2005059765A1 WO 2005059765 A1 WO2005059765 A1 WO 2005059765A1 CN 0301085 W CN0301085 W CN 0301085W WO 2005059765 A1 WO2005059765 A1 WO 2005059765A1
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Prior art keywords
bus
interface
ahb
signal
module
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PCT/CN2003/001085
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English (en)
French (fr)
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WO2005059765A8 (fr
Inventor
Xiaokun Xiong
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Zte Corporation
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Application filed by Zte Corporation filed Critical Zte Corporation
Priority to CNA2003801107063A priority Critical patent/CN1879096A/zh
Priority to PCT/CN2003/001085 priority patent/WO2005059765A1/zh
Priority to AU2003289615A priority patent/AU2003289615A1/en
Priority to GB0611994A priority patent/GB2424104A/en
Priority to US10/583,397 priority patent/US7975092B2/en
Publication of WO2005059765A1 publication Critical patent/WO2005059765A1/zh
Publication of WO2005059765A8 publication Critical patent/WO2005059765A8/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Definitions

  • Bus interface conversion device from AMBA AHB bus protocol to i 960-1 i ke bus protocol
  • the invention relates to the design of digital interface conversion in the field of integrated circuit design, and more particularly to a bus interface conversion device based on the AMBA AHB bus protocol to the i960-Iike bus protocol in the field of ARM embedded microprocessor application design. Background technique
  • each chip or device has an interface for communication with the outside world. Due to technical, market, and other historical reasons, various chip devices follow different protocol standards or bus specifications. When chips or devices with different interfaces need to communicate with each other, interface conversion or protocol conversion becomes an indispensable step. Because of its inherent advantages, the AMBA AHB bus protocol has quickly become popular in the industry with the emergence of the embedded CPU core provider ARM in the field of embedded RISC microprocessors. The AMBA AHB bus protocol is an open standard. Has become the de facto standard for system-on-chip SoC construction and IP library development. i960 is a series of microprocessors provided by Intel Corporation for embedded applications. There are many interface devices based on i960 or i960-Hke bus interface protocol.
  • FIG. 1 The basic transmission mode of the AMBA AHB bus protocol is shown in Figure 1, Figure 2, and Figure 3.
  • Figure 1 is the most basic reading and writing situation
  • Figure 2 is the situation including waiting
  • Figure 3 is the situation of several consecutive reading and writing.
  • the i960-like bus protocol is shown in Figure 4, Figure 5.
  • Figure 4 shows the read operation
  • Figure 5 shows the write operation. Summary of the invention
  • the purpose of the present invention is to provide a protocol from AMBA AHB bus to i960-Hke bus.
  • the protocol bus interface conversion device completes the conversion from AMBAAHB bus to i960-like bus, and supports two working modes: AMBAAHB bus interface and i960-like bus interface working under the same frequency clock and working under different frequency clock.
  • a bus interface conversion device from AMBA AHB bus protocol to i960-like bus protocol including: AHB interface, used to complete interface processing of AMBA AHB bus co-test; i960-like interface, used to complete i960-like bus protocol Interface processing; a main controller for converting a bus protocol between the AHB interface and the i960-like interface.
  • the AHB interface includes: an AHB bus signal registration module for determining and registering control signals from the AMBA AHB bus; an AHB bus signal response module for generating a corresponding indication signal of the AMBA AHB bus protocol
  • the i960-like interface includes: a bus interface multiplexing request module for generating a bus interface multiplexing request signal; a bus multiplexing module for completing output from AHB to an i960-like address bus and output from AHB to i960 -like data bus multiplexing.
  • the AHB bus signal register module further includes: an AHB bus write buffer module, configured to buffer write data and a write address from the AHB bus; the AHB bus write buffer module includes two buffers: an address Area and data area; the AHB bus write buffer module has an enable end, and the buffer size of the address area and data area of the AHB bus write buffer module can be configured through the AHB bus.
  • an AHB bus write buffer module configured to buffer write data and a write address from the AHB bus
  • the AHB bus write buffer module includes two buffers: an address Area and data area
  • the AHB bus write buffer module has an enable end, and the buffer size of the address area and data area of the AHB bus write buffer module can be configured through the AHB bus.
  • the AHB bus signal response module is configured to generate AMBA AHB bus feedback signals HREADYout and HRESP.
  • the i960-like interface has a function of accessing an external bus request and response, which may be connected to a bus interface multiplexing controller, and then connected to the i960-like bus after bus multiplexing; the i960-like interface Can be directly connected to the i960-Hke bus.
  • the bus interface multiplexing request module determines whether to send a bus request signal to the bus interface multiplexing controller according to a status indication signal from the main controller, and decides whether to send a bus request signal to the bus interface multiplexing controller according to a response signal from an i960-like bus. Stop sending a bus request signal to the bus interface multiplexing controller.
  • the address data multiplexing output bus of the bus multiplexing module is connected to the top-level interconnect logic module and multiplexed with the ADS-IN signal into a tri-state bidirectional address data bus signal through a tri-state gate.
  • the main controller has two clocks with the same frequency as the AHB bus clock and the i960-like bus clock, respectively.
  • the clock frequency of the AHB bus may be N times the clock frequency of the i960-Iike bus, and N is a natural number greater than or equal to 1.
  • the main controller has a state machine for indicating the current state of the main controller, and the state machine has three states: an idle state, a read operation state, and a write operation state.
  • the clock of the i960-like interface may be configured into a normal mode and a low power consumption mode.
  • the clock of the i960-like interface is sent by a bus request sent by the bus interface multiplexing request module. Dynamic signal control.
  • the clock of the i960-like interface is valid.
  • the i960-like interface The bus clock is kept high and stopped.
  • the bus interface conversion device provided by the present invention from the AMBAAHB bus protocol to the i96 (ike bus protocol) adopts a technology that supports the same frequency clock and different frequency clock, so that the AMBA AHB bus clock can be N of the i960-like bus clock frequency. (N is a natural number greater than or equal to 1), so that the performance of the CPU core on the side of the AHB bus can be fully utilized and utilized, and is not completely limited by i96 (the clock frequency on the ike interface side.
  • N is a natural number greater than or equal to 1
  • Figure 1 is the basic read and write timing diagram of the AMBAAHB bus
  • Figure 2 is a read and write timing diagram of the AMBAAHB bus with wait
  • Figure 3 is a timing diagram of the AMBAAHB bus with several consecutive read and write cycles
  • Figure 4 is a timing diagram of the read operation of the i960-like bus
  • Figure 5 is a timing diagram of the write operation of the i960-like bus
  • 6 is a system functional block diagram of a bus interface conversion device from an AMBAAHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention
  • FIG. 7 is a block diagram of a bus interface conversion device from an AMBAAHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention
  • Figure 8 is an error response timing diagram of the AMBAAHB bus
  • FIG. 9 is a timing diagram of generating an ALE signal of the i960-Hke bus protocol from a bus interface conversion device of an AMBA AHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention
  • FIG. 10 is a circuit diagram of an address and data signal multiplexing bus, input and output signal multiplexing bus in a bus interface conversion device from an AMBA AHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention. detailed description
  • FIG 1 is the basic read and write timing diagram of the AMBA AHB bus.
  • the AMBA AHB bus is a two-stage pipeline operation.
  • Figure 2 is a read and write timing diagram of the AMBA AHB bus with wait. As shown in Figure 2, when the HREADY signal is low, the values of the control signal and the data bus remain unchanged, until the HCLK clock signal is taken to the high level of the HREADY signal.
  • FIG. 3 is a timing diagram of the AMBA AHB bus with several consecutive read and write cycles. From Figure 3, it can be more clearly seen that the AMBA AHB bus is a two-stage pipeline operation, and at the same time, it can be learned that IDLE state transition may not necessarily exist between two adjacent operations.
  • Figure 4 is a timing diagram of the read operation of the i% 0-like bus. It can be seen from FIG. 4 that when the ALE signal is valid (high level), the signal width is half of the PCLK clock period; the BLAST signal is a chip select signal, which can be expanded according to actual needs, thereby deciding from the AMBAAHB bus protocol to The number of i960-like interfaces provided by the bus interface conversion device of the i960-like bus protocol; the RDYRCV signal is a three-state input signal relative to this embodiment, which is low-effective, and a pull-up resistor must be added when the signal enters the chip pins, otherwise The embodiment does not work properly; wait It is determined by when the other end of the i960-like bus returns the RDYRCV signal; the ADS signal is a tri-state data address bus, the ADDR above is an output address bus signal relative to this embodiment, and the following DATAin is an input data bus signal relative to this embodiment; The BE1 signal is the first bit of the ADDR address bus,
  • Figure 5 is a timing diagram of the write operation of the i960-Hke bus. It can be seen from FIG. 5 that when the ALE signal is valid (high level), the signal width is half of the PCLK clock period; the BLAST signal is a chip select signal, which can be expanded according to actual needs to determine the i960-like interface provided in this embodiment.
  • the RDYRCV signal is a tri-state input signal relative to this embodiment, which is low-effective.
  • This signal needs to be connected with a pull-up resistor when entering the chip pins, otherwise this embodiment cannot work normally; the wait period is from the other end of the i960-like bus It is determined when to return the RDYRCV signal; the ADS signal is a tri-state data address bus, the ADDR above is an output address bus signal relative to this embodiment, and the subsequent DATAout is also an output data bus signal relative to this embodiment; the BE1 signal is the ADDR address bus.
  • the first bit is ADDR [1].
  • FIG. 6 is a system functional block diagram of a bus interface conversion device from an AMBAAHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention.
  • the bus interface conversion device from the AMBA AHB bus protocol to the i960-like bus protocol in this embodiment is composed of the following functional parts:
  • AHB interface 602 One side of the AHB interface is connected to the AMBA AHB bus, and the AHB SLAVE interface is implemented, which fully complies with the AMBAV2.0 specification, and the other side is connected to the main controller; the main controller 604: the main controller completes most of the protocols Conversion
  • i960-like interface 606 One side of the i960-like interface is connected to the main controller, and the other side is connected to the i960-Iike bus. It is worth noting that the i960-like interface has the function of requesting and responding to external buses. The i960-like bus is directly connected. It can also be multiplexed with other interface controllers and then connected to the i960-like bus to save chip pin resources and reduce costs. Two different connection methods increase the use of Flexibility
  • the top-level interconnect logic module 608 combines the above several functional parts to complete the module packaging, and at the same time completes the multiplexing from the AHB output to the i960-like output bus and the i960-like input to the AHB input bus.
  • 7 is a block diagram of a bus interface conversion device from an AMBAAHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention. As shown in FIG. 7, the bus interface conversion device from the AMBA AHB bus protocol to the i960-like bus protocol in this embodiment specifically includes five functional first-level sub-modules and one second-level sub-module.
  • the AHB interface functions include:
  • the AHB bus signal registration module 702 is configured to judge and register control signals from the AMBA AHB bus;
  • the AHB bus signal response module 704 is configured to generate a response indication signal of a corresponding AMBA AHB bus protocol
  • the AHB bus signal registration module 702 further includes:
  • AHB bus write buffer module 706, configured to buffer write data and write addresses from the AHB bus
  • the functions of the main controller include: The main controller module 708, which completes most of the protocol conversion.
  • the functions of the i960-like interface include:
  • the bus interface multiplexing request module 710 is configured to generate a bus interface multiplexing request signal; the bus multiplexing module 712 is configured to complete the restoration of an address bus output from AHB to i960-like and a data bus output from AHB to i960-like use.
  • the AHB bus signal registration module 702 of the AHB interface completes the function of judging the control signals (HTRANS, HSEL, HREADYJN) from the AMBA AHB bus and confirming whether there is an access instruction from the AMBAAHB bus. After that, control signals and address signals from the AMBA AHB bus are registered. If the access from the AMBA- AHB bus is a write operation, a write instruction signal with a clock cycle width will be generated to determine the write buffer setting of the system. If the write buffer is enabled, the registered address and corresponding write data are stored in Write buffer module. The address signal is decoded according to actual needs to generate an internal signal for generating a BLAST signal corresponding to the i960-like bus protocol.
  • the depth CJ0EPTH of the AHB bus write buffer module 706 can be configured through the AHB bus.
  • the configuration value is a power of 2 and the maximum is 128.
  • the write and read clocks of the buffer are all clocked on the AHB bus.
  • the write buffer has a full flag FifoFull and an empty flag FifoEmpty output.
  • the AHB bus signal register module 702 controls the write buffer module 706. As long as the empty flag FifoEmpty of the write buffer is low, that is, the write data to be converted in the write buffer, the AHB bus signal register module 702 will automatically generate a clock cycle.
  • Read instructions send the data in the write buffer to the main controller module 708 for bus protocol conversion and transmission, and wait for the RDYRCV_reg (i960-like bus clock is used to register the RDY CY signal for one shot) After the signal is low, the next read instruction is generated to read data from the write buffer to the main controller module 708, until the empty flag FifoEmpty of the write buffer becomes high, that is, there is no write data to be converted in the write buffer.
  • the write buffer module 706 has an enable terminal and can be configured through the AHB bus. When the write buffer module 706 is configured to be invalid, the write data is directly sent to the main controller module 708, and the write buffer is bypassed.
  • the AHB bus signal response module 704 of the AHB interface completes the generation of the AMBA AHB bus feedback signals HREADYout and HRESP signals.
  • the HREADYout signal is composed of two signals, NONHSIZE_HREADYout and HSIZE_ HREADYout.
  • the generation logic of NONHSIZE_ HREADYout is: Judgment and confirmation from the AMBAAHB bus control signals (HTRANS, HSEL, HREADY_ IN). First determine whether there is an access instruction from the AMBA-AHB bus and determine whether it is a read operation or a write operation.
  • the NONHSIZE_HREADYou signal If it is a read operation, immediately pull the NONHSIZE_HREADYou signal low; if it is a write operation, determine the write sent from the AHB bus signal register module 702 In the state of the buffer, if the write buffer is enabled and not full, the NONHSIZE_HREADYou signal is set high. If the write buffer is not enabled or enabled but is full, then the NONHSIZE_HREADYou signal is pulled low. Then judge the RDYRCV signal from the i960-like bus and the AD_GEN_wrbusy_re signal from the main controller module 708 (the generation method is described in the main controller module later).
  • the read operation of the AHB bus makes the NONHSIZE_HREADYou signal go low Yes, it is determined that the AD_GEN_wrbusy_reg signal is low, which means idle, and at the same time, the RDYRCV signal becomes low, and then the NONHSIZE_HREADYout signal is pulled high. At this time, all the data in the write buffer is completely idle, The data read from i960-like has also been sent to the AHB read bus after conversion; if the write operation of the AHB bus makes The NONHSIZE_HREADYou signal goes low. When the write buffer is enabled, the NO HSIZE_HREADYout signal is pulled high after the write buffer is full and the signal goes from high to low.
  • the NONHSIZE_HREADYout signal is pulled high.
  • HSIZE— HREADYout is for the waiting of two clock cycles when there is an HSIZE error, and the logic and logical combination of NONHSIZE— HREADYout and HREADYout are combined to form a waiting of two clock cycles, which meets the AMBA AHB bus protocol standard in this case (see figure 8);
  • the HRESP signal generally returns an OKAY response, but it returns an ERROR response when HSIZE is not a required bit width access, and its timing conforms to the AMBA AHB bus protocol standard in this case (see Figure 8).
  • the bus interface reuse request module 710 of the i960-like interface determines whether the write buffer is enabled. If the write buffer is not enabled, it is determined that there are access instructions (including read and write operation instructions) from the AMBA-AHB bus. Sends a bus application request signal REQUEST_BIU to the bus interface multiplex controller (Bus Interface Unit), and then judges and detects the AMBA AHB bus control signal HREADYJ.
  • REQUEST_BIU Bus interface multiplex controller (Bus Interface Unit)
  • the interface multiplexing controller BIU sends a bus request request signal REQUEST_BIU; if the write buffer is enabled, it is determined that the AD_GEN_state status indication signal from the main controller indicates read or write to the bus interface multiplexing controller
  • the BIU sends a bus request request signal REQUEST_BIU, and then judges and detects the RDYRCV_reg signal from the i960-like bus. If the RDYRCV_reg signal is detected as a logic low level, it stops sending to the bus interface multiplexing controller BIU. Bus application request signal REQUEST_BIU.
  • the top-level input signal GRANT-BIU from the bus interface multiplexing controller BIU can be kept valid, that is, logic High level, so that the work of the conversion controller will not be affected by the bus request signal REQUEST_BIU sent by this module;
  • the bus request signal REQUEST_BIU sent by this module can be used as a control according to the initialization configuration information from the AHB bus Signal, dynamically control the i960-Iike bus clock output by this interface conversion controller, i960-like bus clock when there is communication from AHB to i960-like Effectively, the i960-like bus clock is automatically set to a constant high and stopped when there is no communication, thereby saving power consumption of a chip or module connected to this embodiment through the i960-like bus.
  • the main controller module 708 implements most of the protocol conversion functions, performs inversion and timing conversion on the registered AMBA AHB bus control signals, and generates internal control signals for controlling the generation of the i960-Iike bus protocol signals, because the i960-like bus
  • the AMBA AHB bus clock and the i960-like bus clock must be switched at the same frequency and different frequencies (that is, N times the frequency). These factors guide the control signal.
  • the timing must be strict, otherwise there will be a bus conflict or logic instability; the main controller module 708 has a state machine with a total of three states, IDLE, READ-STATE and WRITE -STATE).
  • the AD_GEN_state state indication signal indicates an idle state, a read operation state, or a write operation state.
  • the state machine changes from an idle state to a read operation state or a write operation state.
  • a J ⁇ > r detects that the RDYRCV_reg signal from the i960-like bus is low.
  • the state machine changes from a read operation state or a write operation state to an idle state. From the read operation state or the write operation state to the next read operation state or the write operation state must pass through the idle state, which is not continuous and uninterrupted when multiplexing the bus with other interface controllers through the bus interface multiplexing controller BIU.
  • the external bus is occupied by the ground, so that other possible higher priority AHB SLAVE modules can obtain the external bus occupying right in time.
  • From the idle state ⁇ write operation state has higher priority than from the idle state ⁇ read operation state, thereby ensuring that the read operation is always completed with the write buffer empty when the write buffer is enabled, that is, If there is data in the write buffer, then the read operation from the AHB needs to wait until the data in the write buffer is converted, and then perform the conversion. The reason for this is to maintain storage consistency.
  • the AD_GEN_wrbusy signal When the state machine is in a write operation state, the AD_GEN_wrbusy signal is high, and this signal is registered with the i960-like bus clock to generate an AD_GEN_wrbusy_reg signal, which is provided to the AHB bus signal response module 704.
  • Two clocks are used in this module, which are on the same frequency as the AHB bus clock and the i960-like bus clock.
  • the state machine logic uses the AHB bus clock, and the i960-like bus clock is used to generate the internal control signals used to control the generation of i960-like bus protocol signals.
  • the two clocks are at different frequencies, at the intersection of the two clock domains, the high frequency clock of the AHB bus is used to synchronize the low frequency clock domain of the i960-like bus. Now synchronized.
  • the bus multiplexing module 712 of the i960-like interface completes the multiplexing function of the output address bus and the output data bus.
  • the control signal is the AD_ADDNOTDATA (indicate the address at high level and data at low level) control signal generated by the main controller;
  • the generated address data multiplexing output bus ADS_OUT is connected to the top-level module of this embodiment, and is multiplexed with the ADS_IN signal through a tri-state gate to a tri-state bidirectional address data bus signal ADS.
  • the control signal is generated by the main controller.
  • AD_OUT—EN indicates output at high level and input at low level
  • FIG. 8 is the HRESP ⁇ : response timing diagram of the AMBAAHB bus. It can be seen that HREPS is an ERROR response of two clock cycles, and the time when the HREADY signal is low is also two clock cycles.
  • FIG. 9 is a timing diagram of generating an ALE signal of an i960-like bus protocol by a bus interface conversion device from an AMBA AHB bus protocol to an i960-like bus protocol according to an embodiment of the present invention.
  • FBCLK-N is the inverting clock of FBCLK (FBCLK clock and i960-like bus clock are at the same frequency). This figure shows the case where the clock of the AMBAAHB bus interface and the clock of the i960-like bus interface are at the same frequency.
  • FIG. 10 is a circuit diagram of an address and data signal multiplexing bus, input and output signal multiplexing bus in a bus interface conversion device from an AMBA AHB bus protocol to an i960-Iike bus protocol according to an embodiment of the present invention.
  • MUX is a two-to-one selector group that completes the multiplexing of the output address bus and the output data bus. This part of the logic is completed in the bus multiplexing module 712 of the i960-like interface shown in Figure 7.
  • IOBUF is a two-way three-way State buffer group, which multiplexes the output bus signal ADS_ OUT and the input bus signal ADS_IN into a three-state bidirectional address data bus signal ADS of the i960-like bus protocol. Because it contains a high-impedance state, this part of the logic is in the top module 608 carry out.

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Description

从 AMBA AHB总线协议到 i 960- 1 i ke总线协议 的总线接口转换装置
技术领域
本发明涉及集成电路设计领域中的数字接口转换的设计， 尤其涉及基 于 ARM 嵌入式微处理器应用设计领域中的 AMBA AHB 总线协议到 i960-Iike总线协议的总线接口转换装置。 背景技术
在集成电 域， 每颗芯片或者设备均具有和外界通讯的接口， 由于 技术、 市场和其他历史原因， 各种芯片设备遵循不同的协议标准或者总线 规范。 当具有不同接口的芯片或者设备需要相互连接通讯时， 接口转换或 者协议转换成为必不可少的步骤。 AMBA AHB总线协议由于自身固有的 优点，现在已经随着嵌入式 CPU核的提供者 ARM公司在嵌入式 RISC微 处理器领域的异军突起而在业界迅速流行开来， AMBA AHB总线协议是 一个开放标准， 已成为片上系统 SoC构建和 IP库开发的事实标准。 i960 是 Intel公司为嵌入式应用而提供的一系列微处理器，现在已经有众多.的接 口设备基于 i960或者 i960-Hke总线接口协议。 现在业界早已有从 PCI协 议到 i960(或者 i960-like )的接口总线协议转换桥，但目前还没有从 AMBA AHB到 i960-like的接口总线协议的并且同时支持同频和不同频时钟的转 换控制器。
AMBA AHB总线协议基本传输方式见图 1， 图 2， 图 3。 其中图 1是 最基本的读写情况； 图 2是含等待的情况； 图 3是连续几个读写的情况。 i960-like总线协议见图 4, 图 5。 图 4是读操作情况， 图 5是写操作情况。 发明内容
本发明的目的在于提供一种从 AMBA AHB总线协议到 i960-Hke总线 协议的总线接口转换装置， 完成从 AMBAAHB总线到 i960-like总线的转 换， 支持 AMBAAHB总线接口和 i960-like总线接口在同频时钟下工作和 在不同频时钟下工作两种工作模式。
为了实现本发明的以上目的， 所采取的技术方案为：
一种从 AMBA AHB总线协议到 i960-like总线协议的总线接口转换装 置，包括: AHB接口，用于完成 AMBA AHB总线协试的接口处理； i960-like 接口， 用于完成 i960-like总线协议的接口处理; 主控制器， 用于完成所述 AHB接口和所述 i960-like接口之间的总线协议的转换。 其中， 所述 AHB 接口包括： AHB总线信号寄存模块，用于完成对来自 AMBA AHB总线的 控制信号的判断和寄存； AHB总线信号响应模块，用于产生相应的 AMBA AHB总线协议的应 旨示信号； 所述 i960-like接口包括： 总线接口复用 请求模块， 用于产生总线接口复用请求信号； 总线复用模块， 用于完成从 AHB输出到 i960-like的地址总线和从 AHB输出到 i960-like的数据总线的 复用。
优选地，所述 AHB总线信号寄存模块还包括： AHB总线写緩冲模块， 用于对来自 AHB总线的写数据和写地址进行緩存；所述 AHB总线写緩沖 模块包括两个緩冲区： 地址区和数据区； 所述 AHB总线写緩冲模块具有 使能端，可通过 AHB总线来配置所述 AHB总线写緩冲模块的地址区和数 据区的緩冲区大小。
优选地， 所述 AHB总线信号响应模块用于产生 AMBA AHB总线回 馈信号 HREADYout和 HRESP。
优选地， 所述 i960-like接口具有访问外部总线请求和响应的功能， 其 可以与一个总线接口复用控制器相连， 进行总线复用后再与 i960-like总线 相连； 所述 i960-like接口可以直接与 i960-Hke总线相连。
优选地， 所述总线接口复用请求模块根据来自所述主控制器的状态指 示信号确定是否向所述总线接口复用控制器发送总线请求信号， 并根据来 自 i960-like总线的应答信号决定是否停止向所述总线接口复用控制器发送 总线请求信号。 优选地， 所述总线复用模块的地址数据复用输出总线连接到所述顶层 互连逻辑模块， 并同 ADS-IN信号通过三态门复用为三态双向地址数据总 线信号。
优选地， 所述主控制器具有两个分别与 AHB总线时钟和 i960-like总 线时钟同频的时钟。
优选地， 所述 AHB总线的时钟频率可以是 i960-Iike总线时钟频率的 N倍， N为大于等于 1的自然数。
优选地， 所述主控制器具有一个状态机， 用于指示所述主控制器的当 前状态， 所述状态机具有三个状态： 空闲态、 读操作态和写操作态。
优选地，所述 i960-like接口的时钟可以配置为正常模式和低功耗模式， 在低功耗模式下， 所述 i960-like接口的时钟由所述总线接口复用请求模块 发送的总线请求信号动态控制， 在有从 AHB总线到 i960-Hke总线的通讯 时， 所述 i960-like接口的时钟有效， 在没有从 AHB总线到 i960-like总线 的通讯时， 将所述 i960-like接口的总线时钟恒置高停止掉。
本发明所提供的从 AMBAAHB总线协议到 i96( ike总线协议的总线 接口转换装置， 由于采用了支持同频时钟和不同频时钟的技术， 使得 AMBA AHB总线时钟可以是 i960-like总线时钟频率的 N倍（ N是大于等 于 1的自然数）， 从而可以使 AHB总线一侧的 CPU核的性能得以充分完 全的发挥和利用， 不完全受限于 i96( ike接口一侧的时钟频率。 附图说明
相信通过以下结合附图对本发明具体实现方式的说明， 能够使人们更 好地了解本发明上述的特点、 优点和目的。 '
图 1是 AMBAAHB总线的基本的读写时序图；
图 2是 AMBAAHB总线含等待的读写时序图；
图 3是 AMBAAHB总线含连续几个读写周期的时序图；
图 4是 i960-like总线的读操作时序图；
图 5是 i960-like总线的写操作时序图； 图 6是根据本发明的实施例的从 AMBAAHB总线协议到 i960-like总 线协议的总线接口转换装置的系统功能框图；
图 7是根据本发明的实施例的从 AMBAAHB总线协议到 i960-like总 线协议的总线接口转换装置的模块图；
图 8是 AMBAAHB总线的错误响应时序图；
图 9 是根据本发明的一个实施例的从 AMBA AHB 总线协议到 i960-like总线协议的总线接口转换装置实现 i960-Hke总线协议的 ALE信 号产生时序图；
图 10 是根据本发明的一个实施例的从 AMBA AHB 总线协议到 i960-like总线协议的总线接口转换装置中地址和数据信号复用总线、 输入 和输出信号复用总线电路图。 具体实施方式
下面结合附图对本发明的优选实施例进行详细的说明。
图 1是 AMBA AHB总线的基本的读写时序图。 其中 AMBA AHB总 线是二级流水线操作。
图 2 是 AMBA AHB 总线含等待的读写时序图。 如图 2 所示， 在 HREADY信号为低时控制信号和数据总线的数值保持不变， 直到 HCLK 时钟信号采到 HREADY信号变高为止。
图 3是 AMBA AHB总线含连续几个读写周期的时序图。 从图 3可以 更明显的看出， AMBA AHB总线是二级流水线操作， 同时可以得知两个 相邻的操作中间不一定有 IDLE状态过渡。
图 4是 i%0-like总线的读操作时序图。从图 4可以看出， ALE信号有 效时（高电平）信号宽度为 PCLK时钟周期的一半； BLAST信号就是片 选信号，可以根据实际需要进行扩展，从而决定本实施例的从 AMBAAHB 总线协议到 i960-like总线协议的总线接口转换装置所带 i960-like接口的路 数； RDYRCV信号相对本实施例为三态输入信号， 低有效， 该信号进入 芯片管脚时需要加上拉电阻， 否则本实施例不能正常工作； wait等待周期 由 i960-like总线另外一端何时返回 RDYRCV信号决定； ADS信号为三态 数据地址总线，上面标的 ADDR相对本实施例为输出地址总线信号， 而后 面的 DATAin相对本实施例是输入数据总线信号； BE1信号就是 ADDR地 址总线的第 1比特， 即 ADDR[1】。
图 5是 i960-Hke总线的写操作时序图。从图 5可以看出， ALE信号有 效时 (高电平)信号宽度为 PCLK时钟周期的一半； BLAST信号就是片选信 号， 可以根据实际需要进行扩展， 从而决定本实施例所带 i960-like接口的 路数； RDYRCV信号相对本实施例为三态输入信号， 低有效， 该信号进 入芯片管脚时需要加上拉电阻， 否则本实施例不能正常工作； wait等待周 期由 i960-like总线另外一端何时返回 RDYRCV信号决定； ADS信号为三 态数据地址总线，上面标的 ADDR相对本实施例为输出地址总线信号， 而 后面的 DATAout相对本实施例也是输出数据总线信号； BE1 信号就是 ADDR地址总线的第 1比特， 即 ADDR[1】。
图是 6根据本发明的实施例的从 AMBAAHB总线协议到 i960-like总 线协议的总线接口转换装置的系统功能框图。 如图 6所示， 本实施例的从 AMBA AHB总线协议到 i960-like总线协议的总线接口转换装置由以下几 个功能部分組成：
AHB接口 602: AHB接口一侧和 AMBA AHB总线相接， 实现 AHB SLAVE接口， 完全符合 AMBAV2.0规范， 另一侧和主控制器相接； 主控制器 604: 主控制器完成绝大部分协议转换；
i960-like接口 606: i960-like接口一侧和主控制器相接， 另一侧和 i960-Iike总线相连， 值得注意的是 i960-like接口具备访问外部总线请求和 响应功能， 既可以直接和 i960-like总线直接相接， 也可以和其他接口控制 器进行总线复用后再与 i960-like总线相接来达到节省芯片引脚资源， 降低 成本的目地， 两种不同的连接方式增加了使用的灵活性；
顶层互连逻辑模块 608, 把上述几个功能部分组合在一起， 完成模块 的封装， 同时完成从 AHB输出到 i960-like的输出总线和从 i960-like输入 到 AHB的输入总线的复用。 图 7是根据本发明的实施例的从 AMBAAHB总线协议到 i960-like总 线协议的总线接口转换装置的模块图。 如图 7所示， 本实施例的从 AMBA AHB总线协议到 i960-like总线协议的总线接口转换装置具体包括 5个功 能一级子模块和一个二级子模块。
其中， 实现 AHB接口功能的包括：
AHB总线信号寄存模块 702, 用于完成对来自 AMBA AHB总线的控 制信号进行判断和寄存；
AHB总线信号响应模块 704, 用于产生相应的 AMBA AHB总线协议 的应答指示信号；
其中， AHB总线信号寄存模块 702还包括：
AHB总线写緩冲模块 706, 用于对来自 AHB总线的写数据和写地址 进行緩存；
实现主控制器功能的包括： 主控制器模块 708, 完成大部分协议转换； 实现 i960-like接口功能的包括：
总线接口复用请求模块 710, 用于产生总线接口复用请求信号； 总线复用模块 712, 用于完成从 AHB输出到 i960-like的地址总线和 从 AHB输出到 i960-like的数据总线的复用。
所述每个模块的具体功能、 构建方法和相互联系如下：
AHB接口的 AHB总线信号寄存模块 702完成对来自 AMBA AHB总 线的控制信号（HTRANS, HSEL, HREADYJN )进行判断确认是否有 来自 AMBAAHB总线的访问指示的功能; 在确定有来自 AMBA一 AHB总 线的访问指示后， 寄存来自 AMBA AHB总线的控制信号和地址信号。 如 果来自 AMBA— AHB总线的访问是写操作，就会产生一个时钟周期宽度的 写指示信号， 判断系统的写緩冲设置， 如果写緩冲使能， 就将寄存的地址 和对应写数据存入写緩冲模块。 并根据实际需要对地址信号进行译码， 生 成用于产生 i960-like总线协议对应的 BLAST信号的内部信号。
AHB总线写緩冲模块 706的深度 CJ0EPTH可以通过 AHB总线配置， 配置值为 2的幂， 最大为 128。 一共有两个緩冲区， 分别是地址区和数据 区， ——对应。 緩冲区的写入和读出时钟均采用 AHB总线同频时钟。 写 緩冲具有满标识 FifoFull和空标识 FifoEmpty输出。 AHB总线信号寄存模 块 702控制写緩冲模块 706, 只要写緩冲的空标识 FifoEmpty为低电平， 即写緩冲中有待转换的写数据， AHB总线信号寄存模块 702会自动产生一 个时钟周期的读指示， 将写緩冲中的数据送至主控制器模块 708进行总线 协议转换传输，等待收到 i960-like总线时钟的 RDYRCV—reg (用 i960-like 总线时钟对 RDY CY信号寄存了一拍）信号为低后产生下一个读指示从 写緩冲中读数据到主控制器模块 708, 只到写緩沖的空标识 FifoEmpty变 为高电平为止， 即写緩冲中没有待转换的写数据了。 写緩冲模块 706具有 使能端， 可以通过 AHB总线配置。 当写緩冲模块 706配置为无效时， 写 数据就直接送达到主控制器模块 708, 写緩冲被旁路掉。
AHB接口的 AHB总线信号响应模块 704完成 AMBA AHB总线回馈 信号 HREADYout 和 HRESP信号的生成。 其中 HREADYout信号由 NONHSIZE_HREADYout and HSIZE— HREADYout两个信号组合而成， NONHSIZE— HREADYout的产生逻辑是：对来自 AMBAAHB总线控制信 号 (HTRANS , HSEL , HREADY— IN)进行判断确认。 首先确定有来自 AMBA一 AHB总线的访问指示并判断是读操作还是写操作，如果是读操作， 立即就将 NONHSIZE_HREADYou信号拉低；如果是写操作，判断从 AHB 总线信号寄存模块 702送来的写緩冲的状态，如果写緩沖使能并且没有满， 就将 NONHSIZE—HREADYou信号置高， 如果写緩冲没有使能或者使能 但已经满了， 就将 NONHSIZE—HREADYou 信号拉低。 然后对来自 i960-like 总线的 RDYRCV 信号和来自 主控制器模块 708 的 AD_GEN_wrbusy_re 信号 (其产生方式在后面的主控制器模块中讲)进行 判断确认，如果是 AHB总线的读操作使 NONHSIZE_HREADYou信号变 低的， 就在确定 AD—GEN—wrbusy—reg 信号为低即表示空闲并且同时 RDYRCV信号变低有效后才把 NONHSIZE一 HREADYout信号拉高，这时 写緩沖的数据全部转换完成已经处在空闲状态，从 i960-like读入的数据也 已经经过转换后送达了 AHB 读总线； 如果是 AHB 总线的写操作使 NONHSIZE_HREADYou信号变低的 ,写緩冲是使能的情况就在写緩冲的 已经满状态信号从高变低后将 NO HSIZE_HREADYout信号拉高， 写緩 冲是没有使能的情况下就在确定来自 i960-like总线的 RDYRCV信号变低 有效后将 NONHSIZE_HREADYout信号拉高。 HSIZE— HREADYout针对 有 HSIZE 错误 时 产 生 两 个 时 钟 周 期 的 等 待 ， 再 和 NONHSIZE— HREADYout逻辑与组合成信号 HREADYout,形成两个时钟 周期的等待， 从而符合该情况下的 AMBA AHB总线协议标准 (见图 8); HRESP信号一般情况下回馈 OKAY响应， 只是在 HSIZE不是表示要求 的比特位宽访问时回馈 ERROR响应，其时序符合该情况下的 AMBA AHB 总线协议标准 (见图 8)。
i960-like接口的总线接口复用请求模块 710判断写緩冲是否使能， 如 果写緩冲没有使能， 在确定有来自 AMBA—AHB 总线的访问指示 (包括读 和写两种操作指示)就向总线接口复用控制器 (Bus Interface Unit)发送总线 申请请求信号 REQUEST— BIU， 然后对来自 AMBA AHB总线控制信号 HREADYJ 进行判断检测， 如果检测到 HREADY—IN为逻辑高电平， 就停止向总线接口复用控制器 BIU 发送总线申请请求信号 REQUEST一 BIU;如果写緩沖使能，就确定来自主控制器的 AD—GEN— state 状态指示信号指示为读或者写时就向总线接口复用控制器 BIU发送总线 申请请求信号 REQUEST— BIU,然后对来自 i960-like总线的 RDYRCV—reg 信号进行判断检测， 如果检测到 RDYRCV—reg信号为逻辑低电平， 就停 止向总线接口复用控制器 BIU发送总线申请请求信号 REQUEST—BIU。 如果本实施例不和其他类似总线接口控制器复用总线而直接同 i960-Hke总 线相接， 则可将顶层来自总线接口复用控制器 BIU 的输入信号 GRANT—BIU恒置为有效， 即逻辑高电平， 这样转换控制器的工作就不会 受本模块发出的总线请求信号 REQUEST—BIU 的影响； 另外根据来自 AHB 总线的初始化配置信息可以将本模块发出的总线请求信号 REQUEST—BIU 作为控制信号， 动态控制本接口转换控制器输出的 i960-Iike总线时钟， 在有从 AHB到 i960-like的通讯时 i960-like总线时钟 有效， 无通讯时自动将 i960-like 总线时钟恒置高停止掉， 从而节省通过 i960-like总线和本实施例相接的芯片或者模块的功耗。
主控制器模块 708 实现绝大部分协议转换的功能， 对寄存的 AMBA AHB总线控制信号进行逆辑和时序转换， 产生用于控制 i960-Iike总线协 议信号生成的内部控制信号 , 因为 i960-like总线除了数据地址复用总线， 而且输入输出也是复用总线的， 另外还要考虑 AMBA AHB 总线时钟和 i960-like总线时钟同频和不同频（即 N倍频 )的切换， 这些因素导制控制 信号的时序必须严格， 否则要产生总线冲突或者逻辑不稳定； 主控制器模 块 708 有一个状态机， 共有三个状态， 空闲态（IDLE)、 读操作态 (READ一 STATE)和写操作态 (WRITE一 STATE)。 AD— GEN— state状态指示 信号指示是空闲态、 读操作态或者写操作态。 一旦有来自 AHB总线信号 寄存模块 702的读写指示， 状态机便从空闲态变化到读操作态或者写操作 态， 一 J§> r测到来自 i960-like总线的 RDYRCV—reg信号为低， 状态机便 从读操作态或者写操作态变化到空闲态。 从读操作态或者写操作态到下一 次读操作态或者写操作态都要经过空闲态 , 这是为了在和其它接口控制器 通过总线接口复用控制器 BIU复用总线时不一直连续不间断地占用外部 总线， 从而使其它可能的优先级更高的 AHB SLAVE模块可以及时的获得 外部总线占用权。 从空闲态^写操作态的优先级高于从空闲态^读操 作态， 从而保证在写緩冲使能的情况下读操作总是在写緩冲为空的情况下 完成的， 也就是说如果写緩冲里有数据， 这时从 AHB来的读操作需要等 到写緩沖里的数据^转换完后再进 转换， 这样做的原因是为了保持 存储一致性。 当状态机处于写操作状态时， AD—GEN—wrbusy信号为高电 平，用 i960-like总线时钟对此信号寄存一拍生成 AD—GEN— wrbusy_reg信 号， 提供给 AHB总线信号响应模块 704。 本模块中用到两个时钟， 分别和 AHB总线时钟和 i960-like总线时钟同频。状态机逻辑使用和 AHB总线时 钟， 而产生用于控制 i960-like 总线协议信号生成的内部控制信号用 i960-like总线时钟。 当这两个时钟不同频时， 在两个时钟域逆辑交接处， 采用 AHB总线的高频时钟同步 i960-like总线的低频时钟域逆辑的方式实 现同步。
i960-like接口的总线复用模块 712完成输出地址总线和输出数据总线 的复用功能， 其控制信号就是主控制器产生的 AD_ADDNOTDATA (高电 平时指示地址，低电平时指示数据)控制信号;'生成的地址数据复用输出总 线 ADS一 OUT连接到本实施例的顶层模块， 同 ADS一 IN信号通过三态门复 用为三态双向地址数据总线信号 ADS, 其控制信号就是主控制器产生的 AD一 OUT— EN (高电平时指示输出， 低电平时指示输入)控制信号。
图 8是 AMBAAHB总线的 HRESP^:响应时序图，可以看出 HREPS 是两个时钟周期的 ERROR响应， HREADY信号为低的时间也是两个时 钟周期。
图 9 是根据本发明的一个实施例的从 AMBA AHB 总线协议到 i960-like总线协议的总线接口转换装置实现 i960-like总线协议的 ALE信 号产生时序图。 FBCLK—N是 FBCLK的反相时钟（ FBCLK时钟和 i960-like 总线时钟同频），该图所示为 AMBAAHB总线接口的时钟和 i960-like总线 接口的时钟同频的情况。
图 10 是根据本发明的一个实施例的从 AMBA AHB 总线协议到 i960-Iike总线协议的总线接口转换装置中地址和数据信号复用总线、 输入 和输出信号复用总线电路图。 其中 MUX是个 2选 1的选择器组， 完成对 输出地址总线和输出数据总线的复用， 这部分逻辑在图 7所示的 i960-like 接口的总线复用模块 712中完成； IOBUF是个双向三态緩冲器组，将输出 总线信号 ADS— OUT和输入总线信号 ADS_IN复用为 i960-like总线协议的 三态双向地址数据总线信号 ADS， 由于包含高阻态， 这部分逻辑在顶层模 块 608中完成。
以上虽然通过一些示例性的实施例对本发明的从 AMBA AHB总线协 议到 i960-like总线协议的总线接口转换装置进行了详细的描述，但是以上 这些实施例并不是穷举的， 本领域技术人员可以在本发明的精神和范围内 实现各种变化和修改。 因此， 本发明并不限于这些实施例， 本发明的范围 仅由所附权利要求为准。

Claims

权 利 要 求
1. 一种从 AMBA AHB总线协议到 i960-like总线协议的总线接口转 换装置， 其特征在于， 该装置包括：
AHB接口， 用于完成 AMBA AHB总线协议的接口处理；
i960-Iike接口， 用于完成 i960-like总线协议的接口处理；
主控制器， 用于完成所述 AHB接口和所述 i960-Hke接口之间的总线 协议的转换。
其中， 所述 AHB接口包括：
AHB总线信号寄存模块，用于完成对来自 AMBA AHB总线的控制信 号的判断和寄存；
AHB总线信号响应模块，用于产生相应的 AMBA AHB总线协议的应 答指示信号；
所述 i960-like接口包括：
总线接口复用请求模块， 用于产生总线接口复用请求信号； 总线复用模块， 用于完成从 AHB输出到 i960-like 的地址总线和从 AHB输出到 i960-like的数据总线的复用。
2. 如权利要求 1所述的装置， 其特征在于， 所述 AHB总线信号寄存 模块还包括：
AHB总线写緩冲模块， 用于对来自 AHB总线的写数据和写地址进行 緩存。
3. 如权利要求 2所述的装置， 其特征在于， 所述 AHB总线写緩冲模 块包括两个緩冲区： 地址区和数据区。
4. 如权利要求 2所述的装置， 其特征在于， 所述 AHB总线写緩沖模 块具有使能端，可通过 AHB总线来配置所述 AHB总线写緩冲模块的地址 区和数据区的緩冲区大小。
5. 如权利要求 1所述的装置， 其特征在于， 所述 AHB总线信号响应 模块用于产生 AMBA AHB总线回馈信号 HREA Yout和 HRESP。
6. 如权利要求 1所述的装置， 其特征在于， 所述 i960-like接口具有 访问外部总线请求和响应的功能， 其可以与一个总线接口复用控制器相 连， 进行总线复用后再与 i960-like总线相连。
7. 如权利要求 1所述的装置， 其特征在于， 所述 i960-like接口可以 直接与 i960-like总线相连。
8. 如权利要求 1所述的装置，其特征在于， 所述总线接口复用请求模 块根据来自所述主控制器的状态指示信号确定是否向所述总线接口复用 控制器发送总线请求信号， 并根据来自 i960-like总线的应答信号决定是否 停止向所述总线接口复用控制器发送总线请求信号。
9. 如权利要求 1所述的装置，其特征在于， 所述总线复用模块的地址 数据复用输出总线连接到所述顶层互连逗辑模块， 并同 ADS-IN信号通过 三态门复用为三态双向地址数据总线信号。
10. 如权利要求 1所述的装置， 其特征在于， 所述主控制器具有两个 分别与 AHB总线时钟和 i960-like总线时钟同频的时钟。
11. 如权利要求 1所述的装置， 其特征在于， 所述 AHB总线的时钟 频率可以是 i960-like总线时钟频率的 N倍， N为大于等于 1的自然数。
12. 如权利要求 1所述的装置， 其特征在于， 所述主控制器具有一个 状态机， 用于指示所述主控制器的当前状态， 所述状态机具有三个状态： 空闲态、 读操作态和写操作态。
13. 如权利要求 1所述的装置， 其特征在于， 所述 i960-like接口的时 钟可以配置为正常模式和低功耗模式， 在低功耗模式下， 所述 i960-like接 口的时钟由所述总线接口复用请求模块发送的总线请求信号动态控制， 在 有从 AHB总线到 i960-like总线的通讯时，所述 i960-like接口的时钟有效， 在没有从 AHB总线到 i960-like总线的通讯时， 将所述 i960-like接口的总 线时钟恒置高停止掉。
PCT/CN2003/001085 2003-12-18 2003-12-18 Convertisseur a interface bus apte a convertir un protocole de bus amba ahb en protocole de bus de type i960 WO2005059765A1 (fr)

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