WO2005048550A1 - Appareil recevant des donnees, appareil emettant des donnees, appareil emettant/recevant des donnees, et systeme de transmission de donnees - Google Patents

Appareil recevant des donnees, appareil emettant des donnees, appareil emettant/recevant des donnees, et systeme de transmission de donnees Download PDF

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Publication number
WO2005048550A1
WO2005048550A1 PCT/JP2004/016737 JP2004016737W WO2005048550A1 WO 2005048550 A1 WO2005048550 A1 WO 2005048550A1 JP 2004016737 W JP2004016737 W JP 2004016737W WO 2005048550 A1 WO2005048550 A1 WO 2005048550A1
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WO
WIPO (PCT)
Prior art keywords
signal
data
unit
data transmission
transmission
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Application number
PCT/JP2004/016737
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English (en)
Japanese (ja)
Inventor
Yuji Mizuguchi
Toshitomo Umei
Takashi Akita
Hirotsugu Kawata
Noboru Katta
Original Assignee
Matsushita Electric Industrial Co., Ltd.
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Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2005048550A1 publication Critical patent/WO2005048550A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation

Definitions

  • Data receiving apparatus data transmitting apparatus, data transmitting / receiving apparatus, and data transmission system
  • the present invention relates to a data receiving device, a data transmitting device, a data transmitting / receiving device, and a data transmission system, and more specifically, in a ring network in which a plurality of devices are connected in a ring, according to a predetermined protocol.
  • the present invention relates to a data receiving device, a data transmitting device, and a data transmitting and receiving device included in a system that transmits data in one direction, and the data transmission system.
  • a physical topology is one ring topology, and a plurality of nodes are connected in one ring topology to form a one-way ring LAN, audio equipment, navigation Aiming for integrated connection with devices or information terminals.
  • a communication protocol of the information system used in the ring LAN for example, Media Oriented Systems Transport (hereinafter referred to as MOST).
  • MOST Media Oriented Systems Transport
  • the MOST refers to the method of constructing a distributed system that is unique only to the communication protocol.
  • the data of the MOST network is transmitted on a frame-by-frame basis, and frames are transmitted in the negative direction one after another in each node.
  • the radiation noise may cause a malfunction to another electronic device mounted in a car or the like, and the influence of the radiation noise on other devices. It is also necessary to transmit correctly without receiving Therefore, in a conventional ring-type LAN using MO ST, each node is connected by an optical fiber cable. The noise resistance is improved while preventing the generation of electromagnetic waves.
  • telecommunication is performed using an inexpensive cable such as a twisted pair wire or coaxial cable, and radiation noise is reduced and noise resistance is reduced.
  • FIG. 19 is a block diagram showing the configuration of the data transmission system.
  • the data transmission system includes data transmission devices 100a-100— and transmission paths 300a-3000005.
  • the data transmission device 100a is set as a master for clock synchronization, and the other data transmission devices 100b to 100 ⁇ are set as slaves.
  • the respective data transmission devices 100a-100 ⁇ are connected in a ring shape by the transmission paths 300a-300 ⁇ . Data is transmitted in the direction of the arrow according to the communication protocol of the MOST between each data transmission device 100 a-100 ⁇ .
  • the data transmission using the 8-value mapped digital data refers to multi-level data transmission in which data is transmitted by allocating data of 1 bit or more to the signal level as one data symbol, and the signal level is allocated in 8 stages. It is a method of transmission (for details, refer to WO 02Z30077 pamphlet).
  • data transmission scheme using four-value mapping or data using five-value mapped data is also conceivable.
  • a data transmission system that switches the data transmission method in accordance with the use situation becomes necessary.
  • Such switching of the data transmission scheme is generally performed based on the sequences as shown in FIG. 20 and FIG.
  • the switching of the data transmission method will be described in detail below with reference to FIGS. 20 and 21.
  • the data transmission device 100a which is a master, is connected to another data transmission device and a clock.
  • a lock signal for synchronization is generated and transmitted to the data transmission apparatus 100b.
  • the data transmission device 100b having received the lock signal regenerates the acquired lock signal and establishes clock synchronization with the data transmission device 100a.
  • the data transmission device 100b generates a lock signal and transmits it to the data transmission device 100c.
  • the data transmission device 100c-100n performs the same operation as the data transmission device 100b.
  • the lock signal transmitted by the data transmission device 100 ⁇ reaches the data transmission device 100a, and the data transmission device 100a receiving the lock signal reproduces the lock signal acquired and establishes clock synchronization with the data transmission device 100 ⁇ . Do.
  • clock synchronization is established between the data transmission devices 100a and 100 ⁇ .
  • the data transmission device 100a creates a training signal for setting a determination level which is a reference of data determination, and transmits the training signal to the data transmission device 100b.
  • the training signal transmitted here may be a training signal for eight-value mapping or a training signal for another system, but here, a training signal for eight-value mapping is used. It is assumed that a second signal is transmitted.
  • the data transmission apparatus 100b having received the training signal uses the acquired training signal to set a determination level as a reference of data determination for 8-value mapping. Then, the data transmission device 100b creates a training signal for 8-value mapping and transmits it to the next data transmission device 100c. Thereafter, the data transmission device 100 c-100 ⁇ performs the same operation as the data transmission device 100 b.
  • the training signal transmitted from the data transmission device 100 ⁇ reaches the data transmission device 100 a, and using the acquired training signal, the judgment level which is the reference of the data judgment for the data transmission device 100 a for eight-value mapping is Set As a result, the data transmission device 100 a-100 ⁇ in the data transmission system sets a determination level which is a reference of data determination for 8-value mapping.
  • data transmission apparatus 100a transmits an identification signal for notifying another data transmission apparatus 100b-100 eta whether data transmission is to be performed by eight-value mapping or another method.
  • Send to The data transmission apparatus 100b that has received the identification signal determines which method is used to transmit data based on the received identification signal.
  • the data transmission device 100b determines whether the Generates an identification signal and transmits it to the data transmission apparatus 100c.
  • the data transmission device 100 c-100 ⁇ performs the same operation as the data transmission device 100 b.
  • the identification signal transmitted from the data transmission device 100 ⁇ ⁇ is received by the data transmission device 100 a.
  • each data transmission device 100a-100 ⁇ in the data transmission system recognizes the data transmission method.
  • the data transmission device 100a creates a training signal of the data transmission method recognized by each data transmission device, and transmits it to the data transmission device 100b. Thereafter, in each data transmission device, the same processing as the above-mentioned training processing is performed. As a result, the determination level that is the basis of the data determination of the data transmission method used for communication is set to each data transmission device 100a-100. After that, communication of data is started in the data transmission system.
  • the first training process is performed after the synchronization process by the lock signal, and the data transmission method is performed using the determination level set by the training process.
  • An identification process to notify is performed.
  • the second training process is performed with the training signal for the data transmission method identified in the identification process, and the force data communication is started. That is, in the conventional data transmission system, two training processes were required. This is a force that the conventional data transmission system described above can not perform the identification process for identifying the data transmission method until after the training process is performed.
  • an identification process for notifying a data transmission method at the time of clock synchronization process For example, by performing clock synchronization processing using a lock signal in which identification information is embedded in advance before the first training processing is performed, data transmission in which the data transmission apparatus 100a-10 On performs data communication with the identification information is performed. It is conceivable to notify the method. In this case, the first training process is performed with the training signal for the data transmission method indicated by the identification information, and data communication in the data transmission system is started. [0015] For example, two types of patterns are considered as a lock signal in which the identification information is embedded.
  • the first lock signal is a signal in which one cycle has eight symbol powers and signal levels “+1” and “one 1” are alternately repeated in each symbol.
  • the second lock signal has eight cycles per symbol, and the signal level "+1” and “one 1” are alternately repeated for each symbol, and the fifth symbol is the signal level "+7",
  • the sixth symbol is a signal whose signal level is “one seven”. If the two types of patterns of such lock signals can be distinguished by the data transmission apparatus on the receiving side, the above identification processing can be performed in the clock synchronization processing.
  • FIG. 22 is an example of transmission waveforms of a lock signal, a training header signal, a training signal, and transmission data transmitted between the data transmission device 100a and ⁇ .
  • the transmission waveform shown in FIG. 22 is provided with a training header signal to distinguish between the lock signal and the training signal.
  • the training header signal is also 3 symbol power, and is a signal in which the same signal level "+ 7" is continuous to distinguish from other signals.
  • the mouth signal is the above-mentioned second lock signal.
  • the symbol received by the difference value with respect to the previous symbol value in order to cancel the overall signal level change (voltage change) when transmitting from the transmitting side. Determine the value.
  • the determination level is not set. That is, each data transmission apparatus can not make detailed determination of the signal level of data. Therefore, each data transmission apparatus needs to distinguish the first and second lock signals by the determination of the signal level of the data being larger or smaller than the threshold value.
  • the difference value “14” between the signal levels “+7” and “one 7” is a large value
  • the difference value “2” between the signal levels “+2” and “one two” is a small value It is necessary to set a threshold that can be determined to identify the pattern of the lock signal.
  • the state of the transmission line 300a-300 ⁇ ⁇ provided between each data transmission device 100a-100 ⁇ is bad, etc., and the data transmission environment is bad!
  • the signal level of the received training header signal may fluctuate. . That is, since the difference value with respect to the training header signal fluctuates from "0", it may exceed the threshold for discriminating from the lock signal, and the training header signal may not be detected.
  • the data transmission apparatus since the data transmission apparatus can not detect the training signal, the setting of the determination level can not be set, and data communication between the data transmission apparatuses can not be performed.
  • Similar problems may occur in the case of using the mouth signal having a section in which the adjacent symbols have the minimum difference value according to the force mapping method described using the example in which the identification information is embedded in the lock signal.
  • an object of the present invention is to provide a data receiving apparatus, a data transmitting apparatus, and a data transmitting and receiving apparatus capable of reliably detecting a training header signal for discriminating between a lock signal and a trailing signal transmitted in initialization processing. To provide an apparatus and a data transmission system.
  • the present invention adopts the following configuration.
  • the reference numerals in parentheses, step numbers, and the like indicate correspondence relationships with the embodiments described later to facilitate understanding of the present invention, and do not limit the scope of the present invention.
  • the data reception device (5) of the present invention is connected to another data transmission device (1) via the transmission line (80), and each symbol of transmission data is transmitted at a plurality of signal levels (eight values), It is mapped to one side and receives the transmitted signal.
  • the data receiving apparatus includes a training signal in which at least a plurality of signal levels of the transmission signal is formed with a known variation pattern and a header signal (training header signal) given at the beginning of the training signal. ) Is transmitted from another data transmission device (S19, S59). 0 Data receiver The difference between the signal level corresponding to the symbol in the received transmission signal and the signal level of the symbol immediately before that symbol.
  • the absolute value of the difference value calculated by the difference calculation unit (54) that calculates (dd) in the order of reception, and the difference calculation unit are each set against a predetermined threshold. At least two of the results (582) in which the magnitude determination unit classifies into two values, and the variation pattern of the training signal or the header signal. And a training signal detection unit (58) for detecting reception of a training signal or a header signal by detecting (583) a match with the part (584).
  • the training signal detection unit is a numerical value string (582) in which the magnitude judgment unit distinguishes into two values and is arranged in the order of reception, and a difference value for at least a part of the variation pattern of the header signal.
  • the absolute value is compared with the header pattern (584) described in advance by a predetermined number of large or small binary values (583), and when both match, the reception of the header signal is detected.
  • the variation pattern of the header signal may be generated by being mapped to the same signal level a predetermined number of times consecutively after being mapped to the maximum and minimum levels a predetermined number of times alternately among a plurality of signal levels (FIG. 4). ). In this case, the header pattern is described at least once, after the large of the two values is described a predetermined number of times consecutively (FIG. 15 (b)).
  • the variation pattern of the header signal is alternately mapped to the maximum and minimum levels of the plurality of signal levels a predetermined number of times, and then mapped to the same signal level a predetermined number of times in succession and generated.
  • the training signal detection unit distinguishes the large / smallness determination unit continuously into at least a plurality of large binary values at least a plurality of times
  • the training signal detection unit detects the reception of the header signal when the large / small determination unit distinguishes the binary value Do.
  • the header signal and the training signal are formed with a first variation pattern in which a plurality of signal levels are known, and a clock component for establishing synchronization with another data transmission device.
  • the first lock signal including the power does not hold even if it is continuously transmitted after being transmitted from another data transmission device (S16, S57).
  • the data receiving apparatus reproduces the clock component of the first lock signal to establish synchronization with another data transmission apparatus, and a plurality of binary values distinguished by the magnitude determination section.
  • the apparatus further comprises a lock signal identification unit (71) that identifies the first lock signal by detecting a result and a match with at least a portion of the first variation pattern.
  • the variation pattern of the header signal is alternately mapped to the maximum and minimum levels of a plurality of signal levels a predetermined number of times, and then mapped to the same signal level a predetermined number of times consecutively and generated.
  • the detection unit detects the reception of the header signal when the magnitude judgment unit distinguishes at least 4 times after the magnitude judgment unit distinguishes at least 4 times as large.
  • the header signal and the training signal are formed with a first variation pattern in which a plurality of signal levels are known, and a clock component for establishing synchronization with another data transmission device.
  • a second lock signal which is formed with a first lock signal including the second lock pattern or a second variation pattern different from the first variation pattern, and includes a clock component, and is transmitted continuously after being transmitted by another data transmission device. I will not hesitate even if it is done.
  • the data receiving apparatus reproduces the clock component of the first or second lock signal to establish synchronization with another data transmission apparatus;
  • a lock signal identification unit for identifying the first or second lock signal by detecting a match between the result of the first and second fluctuation patterns and at least a part of the first and second fluctuation patterns.
  • the maximum and minimum levels among the plurality of signal levels are generated after a predetermined number of consecutive mapping operations in which the difference value is the minimum and the positive and negative of the plurality of signal levels are alternated.
  • the second variation pattern is generated by repeating the pattern to be mapped once each (Fig.
  • the second variation pattern is a series of mapping in which the difference value is the smallest among the multiple signal levels and the positive and negative of the difference are alternating.
  • Figure 5 Generated ( Figure 5).
  • the variation pattern of the header signal is alternately mapped to the maximum and minimum levels of the plurality of signal levels a predetermined number of times, and then mapped to the same signal level a predetermined number of times consecutively and generated.
  • the large / small judging unit distinguishes at least 4 times of the large binary value consecutively, the reception of the header signal is detected when the large / small judgment unit distinguishes small binary.
  • a determination level setting unit (57) for setting a determination level for distinguishing and determining the difference values calculated by the difference calculation unit using the training signal, and the difference calculation unit A difference value determination unit (54) that distinguishes and determines each of the calculated difference values based on the determination level set by the determination level setting unit, and reversely maps and transmits the determination result output by the difference value determination unit. Decode transmit data symbols sent in the signal Even if the reverse mapping unit (55) is further provided, it does not force. Also, when the training signal is transmitted for a predetermined time from transmission of the header signal (fixed length), the data receiving apparatus sets the determination level in response to the training signal detection unit detecting reception of the header signal.
  • the semi-IJ fixed reflector setting unit detects the end of the training signal based on the count by the counter (S22, S61), and sets the final judgment level.
  • the transmission data is a signal of a data format defined by MOST (Media Oriented Systems Transport).
  • MOST Media Oriented Systems Transport
  • the data transmission apparatus (6) of the present invention is connected to another data transmission apparatus via a transmission path, and transmission symbols are formed by mapping each symbol of transmission data to! / Send
  • the data transmission apparatus transmits a first lock signal that transmits a first lock signal including a clock component for forming a plurality of signal levels with a known first variation pattern and establishing synchronization with another data transmission apparatus.
  • Section (671) a header signal transmission section (673) for transmitting a header signal having a plurality of signal levels formed in a third variation pattern different from the first variation pattern, and a plurality of signal levels known.
  • a training signal transmission unit (674) for transmitting a training signal formed by the fourth variation pattern, a transmission data signal transmission unit (61 to 66) for transmitting a transmission data signal to which transmission data is mapped, and A control unit (676) for selecting a first lock signal to be transmitted to another data transmission device based on a predetermined condition, and a first lock signal selected by the control unit being transmitted to the other data transmission device;
  • the head A transmission unit (675, 63-66) for continuously transmitting to the other data transmission apparatus in the order of the signal, the training signal, and the transmission data signal, and the third variation pattern is the maximum and minimum among the plurality of signal levels.
  • the present invention is characterized in that it is mapped to the level a predetermined number of times alternately and then mapped to the same signal level a predetermined number of times in succession.
  • the maximum is selected among the plurality of signal levels. And it is generated by repeating the pattern that is mapped once to the minimum level respectively.
  • a second lock signal transmission unit (672) for transmitting a second lock signal including a clock component in which a plurality of signal levels are formed with a second fluctuation pattern different from the first fluctuation pattern is provided. Even if it prepares, it does not use power.
  • the control unit selects one of the first and second lock signals to be transmitted to another data transmission apparatus based on a predetermined condition, and the transmission unit selects the first and second lock signals selected by the control unit. After transmitting one of the signals to the other data transmission apparatus, the transmission data signal is transmitted to the other data transmission apparatus successively in the order of the header signal, the training signal, and the transmission data signal.
  • the maximum and minimum levels among the plurality of signal levels are
  • the second variation pattern is generated by repeating the pattern to be mapped, and the second variation pattern is continuously generated mapping in which the difference value between the adjacent symbols of the plurality of signal levels is minimum and the positive and negative of the difference value is alternated.
  • the control unit may further control the timing at which the transmission unit switches each signal to be transmitted to another data transmission apparatus.
  • the control unit controls the transmission unit to transmit a header signal (S19).
  • the control unit transmits the header signal to another data transmission apparatus (S19), and after a predetermined time has elapsed (S22), transmits the transmission data signal (S22).
  • S23 controls the transmission unit.
  • the transmission data is a signal of a data format defined by MOST.
  • the data transmission / reception device (1) of the present invention is connected to another data transmission device via a transmission path in a ring configuration, and each symbol of transmission data is mapped to a plurality of signal levels.
  • the data transmitting / receiving apparatus includes a test signal including a training signal in which at least a plurality of signal levels of the transmission signal are respectively formed with known variation patterns and a header signal attached to the beginning of the training signal.
  • Signal transmitter (67) that transmits the signal to another data transmission device, the signal level corresponding to the symbol in the transmission signal received by the other data transmission device and the signal of the symbol immediately before that symbol
  • a difference calculation unit that calculates difference values with the level in the order of reception, and an absolute value of the difference value calculated by the difference calculation unit is greater than or equal to a predetermined threshold.
  • a training signal is detected by detecting coincidence between a plurality of small / high / low judging units for discriminating with small binary values, a plurality of results obtained by the large / small judgment units for binary discrimination, and a variation pattern of the training signal or the header signal. Or a training signal detection unit for detecting reception of a header signal.
  • the test signal transmission unit maps the variation pattern of the header signal alternately to the maximum and minimum levels of a plurality of signal levels a predetermined number of times, and then maps the same signal level a predetermined number of times consecutively.
  • the training signal detection unit detects the reception of the header signal when the magnitude determination unit determines that the binary magnitude is at least a plurality of times consecutively and then determines that the magnitude determination unit classifies the binary magnitude.
  • the test signal transmission unit is configured to generate a first lock signal including a clock component for forming synchronization with another data transmission device, in which a plurality of signal levels are formed with a known first variation pattern.
  • the header signal and training signal may be transmitted continuously.
  • the data transmission / reception device reproduces the clock component of the first lock signal received by the transmission data signal transmission unit that transmits the transmission data signal obtained by mapping the transmission data to the other data transmission device and the other data transmission device.
  • a clock recovery unit that establishes synchronization with the data transmission apparatus; and a first lock signal by detecting a match between a plurality of results that the magnitude determination unit classifies into two values and at least a portion of the first variation pattern.
  • an inverse mapping unit for decoding a symbol of the transmission data transmitted with the determination result in the inverse mapping to transmission signals, further comprising.
  • test signal transmission unit is formed with a first variation pattern in which a plurality of signal levels are known, and a first lock signal including a clock component for establishing synchronization with another data transmission device.
  • the header signal and the training signal may not be continuously transmitted after the second lock signal which is formed with the second fluctuation pattern different from the first fluctuation pattern and contains the clock component.
  • the data transmission / reception device A transmission data signal transmission unit for transmitting the transmitted transmission data signal to another data transmission device, and the clock component of the first or second lock signal received by the other data transmission device, to be transmitted to the data transmission device
  • the first or second lock signal is detected by detecting coincidence between a clock recovery unit that establishes synchronization, a plurality of results of which the magnitude determination unit distinguishes into two values, and at least a part of the first and second fluctuation patterns.
  • the lock signal identification unit for identification, the determination level setting unit for setting the determination level for separately determining the difference value calculated by the difference calculation unit using the training signal, and the difference calculation unit A difference value determination unit that distinguishes and determines each of the calculated difference values based on the determination level set by the determination level setting unit and a determination result output from the difference value determination unit And an inverse mapping unit for decoding a symbol of the transmission data transmitted by the transmission signal Te Ngushi comprises the further.
  • the test signal transmission unit transmits the first synchronization signal after the synchronization with the reference clock is established.
  • the second lock signal is transmitted to another data transmission apparatus (S16), and after the clock recovery unit establishes synchronization with the other data transmission apparatus (S18), a header signal and a trailing signal are transmitted (S19).
  • the transmission data signal transmission unit transmits the transmission data signal after setting the determination level (S21) using the training signal that the determination level setting unit also receives (S20) other data transmission device power (S21). S23).
  • the test signal transmission unit receives the data transmission device power received by the clock recovery unit (S52). After establishing synchronization with another data transmission apparatus using the first or second lock signal (S53), the same signal as the received first or second lock signal is selected (S55, S56) and transmitted (S57) After the training signal detection unit detects the reception of another data transmission device power header signal (S58), the header signal and the training signal are transmitted (S59), and the transmission data signal transmission unit sets the determination level. The transmission data signal is transmitted after the unit respectively sets the determination level (S60) using the training signal received by the other data transmission apparatus (S62).
  • the test signal transmission unit also transmits the training signal and the transmission power of the header signal for a predetermined time. Even if you send it, it won't go wrong.
  • the data transmission / reception device further includes a counter that counts a predetermined time for transmitting the training signal in response to the training signal detection unit detecting reception of the header signal (S20, S58), and the determination level
  • the setting unit detects the end of the training signal received by the other data transmission device based on the count by the counter (S22, S61), sets the final determination level, and the transmission data signal transmission unit After the determination level setting unit sets the final determination level, the transmission data signal is transmitted.
  • the transmission data is a signal of a data format defined by MOST.
  • the data transmission system of the present invention includes a plurality of data transmission devices connected in a ring shape via a transmission line, and each data transmission device mutually transmits each symbol of transmission data to a plurality of signal levels. Transmits / receives the transmission signal mapped in any way.
  • the data transmission device includes a training signal in which at least a plurality of signal levels of the transmission signal are respectively formed with a known variation pattern and a header signal added to the head of the training signal at each initial operation.
  • a test signal transmission unit that transmits a test signal to another data transmission device, and a difference value between the signal level corresponding to the symbol in the transmission signal received from the other data transmission device and the signal level of the symbol immediately before that symbol
  • the difference calculation unit calculates the reception order in the order of reception, the size determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit with a large or small binary value with respect to a predetermined threshold, and the size determination unit distinguishes into two values. By detecting a match between the multiple results and at least a portion of the variation pattern of the training signal or the header signal. And a training signal detection unit for detecting reception of the training signal or the header signal.
  • the test signal transmission unit maps the variation pattern of the header signal alternately to the maximum and minimum levels of the plurality of signal levels a predetermined number of times, and then maps and generates the same signal level a predetermined number of times in succession. Even if I do not use force.
  • the training signal detection unit detects the reception of the header signal when the magnitude determination unit distinguishes the binary value at least a plurality of times consecutively and then distinguishes the magnitude value of the magnitude determination unit.
  • the test signal transmission unit is formed with a first variation pattern in which a plurality of signal levels are known, and includes a first lock signal including a clock component for establishing synchronization with the data transmission apparatus. After transmitting the signal, it is not difficult to transmit the header signal and the training signal continuously.
  • the data transmission apparatus transmits a transmission data signal to which another transmission data is mapped to another data transmission apparatus, and the clock component of the first lock signal received by the other data transmission apparatus.
  • a clock recovery unit that establishes synchronization with the data transmission apparatus, and detects a match between a plurality of results that the magnitude determination unit distinguishes into two values and at least a part of the first variation pattern.
  • a lock signal identification unit that identifies a lock signal, and a determination level setting unit that sets a determination level for separately determining the difference value calculated by the difference calculation unit using the training signal
  • a difference value determination unit that determines the difference value calculated by the difference calculation unit based on the determination level set by the determination level setting unit
  • an inverse mapping unit for decoding a symbol of the transmission data transmitted in the transmission signal by inverse mapping the judgment result of force, further comprising.
  • a test signal transmission unit of a data transmission device set as a master that transmits a transmission signal synchronized to a held reference clock to another data transmission device is a reference clock and After synchronization is established, the first lock signal is transmitted to the other data transmission device, and after the clock recovery unit establishes synchronization with the other data transmission device, the header signal and training signal are transmitted and set as the master.
  • the transmission data signal transmission unit of the data transmission apparatus transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from the other data transmission apparatus.
  • the same signal as the received first lock signal is selected and transmitted, and the training signal detection unit transmits the other data.
  • Device power After detecting the reception of the header signal, the transmission data signal transmitter of the data transmission device that transmits the header signal and the training signal and is set as the slave receives the judgment level setting unit from another data transmission device. After setting the judgment level using the training signal, the transmission data signal is Send.
  • the test signal transmission unit is a first lock signal having a plurality of signal levels formed with a known first variation pattern and including a clock component for establishing synchronization with the data transmission apparatus, or
  • the header signal and the training signal are not continuously transmitted after transmitting the second lock signal which is formed with the second fluctuation pattern different from the first fluctuation pattern and contains the power clock component.
  • the data transmission apparatus transmits a transmission data signal, to which each transmission data is mapped, to the other data transmission apparatus, and a transmission data signal transmission unit, and the other data transmission apparatus receives the first or second lock signal received.
  • a clock regenerating unit that reproduces a clock component to establish synchronization with the data transmission apparatus, a plurality of results that the magnitude determination unit classifies into two values, and coincidence with at least a part of the first and second variation patterns Set a judgment level to distinguish and judge the difference value calculated by the difference calculation unit using the lock signal identification unit that identifies the first or second lock signal by detecting the signal and the training signal. And the difference value calculated by the difference calculation unit, based on the determination level set by the determination level setting unit. Value determination unit, and an inverse mapping unit which demaps the determination result difference value determination unit outputs to decode the symbols of the transmission data transmitted in the transmission signal, comprising the further.
  • a test signal transmission unit of a data transmission device set as a master that transmits a transmission signal synchronized to a held reference clock to another data transmission device is a reference clock and After synchronization is established, the first or second lock signal is transmitted to the other data transmission apparatus, and after the clock recovery unit establishes synchronization with the other data transmission apparatus, the header signal and the training signal are transmitted.
  • the transmission data signal transmission unit of the data transmission device set as the master transmits the transmission data signal after the judgment level setting unit respectively sets the judgment level using the training signal received from the other data transmission device. .
  • the test signal transmission unit of the data transmission device in which the other data transmission device is set as a slave of the clock synchronization as the master of the clock synchronization Device power Use the received first or second lock signal to After synchronization with the data transmission device is established, the same signal as the received first or second lock signal is selected and transmitted, and the training signal detection unit detects the reception of the header signal of the other data transmission device receiver.
  • the transmission data signal transmission unit of the data transmission apparatus which transmits the header signal and the training signal and is set to the slave uses the training signal received by the determination level setting unit to the other data transmission apparatus power. After each setting, transmit data signal.
  • the transmission data is a signal of a data format defined by MOST.
  • the data receiving apparatus of the present invention it is possible to reliably detect a header signal or a training signal for distinguishing between the lock signal and the training signal transmitted in the initial operation. This is because the header signal can be identified by the determination whether the absolute value of the difference value for each data signal level is larger or smaller than the threshold value, even before the data receiving apparatus performs training processing. Therefore, even if the difference value with respect to the header signal to be received fluctuates, since the margin can be formed with respect to the threshold value, the header signal can be detected surely.
  • the training signal detection unit compares the header pattern with a numerical value sequence that is classified into binary values by the magnitude determination unit and arranged in a predetermined number in the reception order, and when both match, detects reception of the header signal. Can be easily obtained by the above configuration.
  • the training signal detection unit can easily receive the header signal by detecting that the magnitude determination unit has made a distinction between binary values after the magnitude determination unit has made a distinction between binary magnitudes at least a plurality of times consecutively. It can be detected reliably.
  • the header signal can be reliably detected while identifying the type of the lock signal.
  • the final determination level can be determined according to the end of the training signal.
  • the data transmitting apparatus of the present invention it is possible to transmit a test signal which can reliably detect a header signal by the data receiving apparatus described above.
  • training processing can be started after clock synchronization processing with the other data transmission device is completed. Furthermore, when the header signal and the training signal each have a fixed length, the training process can be terminated by time control to start data communication.
  • FIG. 1 is a block diagram showing a configuration of a data transmission system according to an embodiment of the present invention.
  • FIG. 2 is a functional block diagram showing a configuration of the data transmission apparatus 1 of FIG.
  • FIG. 3 is a block diagram showing a configuration of a test signal generation unit 67 of FIG.
  • FIG. 4 is a diagram for explaining an example of transmission waveforms of a test signal TS composed of a lock signal, a training header signal, and a training signal.
  • FIG. 5 is a diagram for explaining an example of a transmission waveform of a first lock signal.
  • FIG. 6 is a diagram for explaining an example of a transmission waveform of a second lock signal.
  • FIG. 7 is a view for explaining an example of a transmission waveform of a training signal.
  • FIG. 8 is a diagram showing a first example of a transmission waveform pattern in which the second lock signal and the training header signal are output without interruption.
  • FIG. 9 is a diagram showing a second example of a transmission waveform pattern in which the second lock signal and the training header signal are output without interruption.
  • FIG. 10 is a diagram showing a third example of the transmission waveform pattern in which the second lock signal and the training header signal are output without interruption.
  • FIG. 11 is a block diagram showing a configuration of the pattern identification unit 71 of FIG.
  • FIG. 12 shows the difference value dd output from the difference calculation unit 54 of FIG. 2 and the first RO of FIG.
  • FIG. 13 is a diagram for explaining the operation of the shift register 712 of FIG.
  • FIG. 14 is a block diagram showing a configuration of a training signal detection unit 58 of FIG.
  • 15 is a diagram showing the difference value dd output from the difference calculation unit 54 of FIG. 2 and data stored in the ROM 584 of FIG.
  • FIG. 16 is a diagram for explaining the operation of the shift register 582 of FIG.
  • FIG. 17 is a flowchart showing the initialization operation of the first half performed by the data transmission apparatus 1 set as the master and the slave in the data transmission system of FIG.
  • FIG. 18 is a flow chart showing a second half initialization operation performed by the data transmission apparatus 1 set as a master and a slave in the data transmission system of FIG.
  • FIG. 19 is a block diagram showing the configuration of a conventional data transmission system.
  • FIG. 20 is a sequence diagram of the first half showing a conventional data transmission method switching method.
  • FIG. 21 is a sequence diagram of the second half showing a conventional data transmission method switching method.
  • FIG. 22 is a diagram showing an example of transmission waveforms of the lock signal, training header signal, training signal, and transmission data transmitted between the data transmission device 100a and ⁇ in FIG.
  • the data transmission system includes a plurality of data transmission devices, and a transmission / reception unit including a transmission unit and a reception unit is configured in each of the data transmission devices.
  • a transmission / reception unit including a transmission unit and a reception unit is configured in each of the data transmission devices.
  • FIG. 1 is a block diagram showing the configuration of the data transmission system.
  • the data transmission system has a physical topology as a ring 'topology, and forms a one-way ring LAN by connecting a plurality of nodes in a ring' topology.
  • each node is configured by six stages of data transmission devices la-If, and transmission paths 80a-80f are respectively connected in a ring type, and data to be transmitted is transmitted through transmission paths 80a-80f.
  • a system will be described which is transmitted in one direction via
  • Each data transmission device la-If performs processing based on the data transmitted from the data transmission system, and outputs the result to the data transmission system (for example, audio equipment, navigation equipment, or Information terminal equipment) 10a to 10f are connected.
  • the respective data transmission devices la-If and the connected devices 10a-10f are physically configured.
  • MO Data to be transmitted using ST as a communication protocol is transmitted using a frame as a basic unit, and frames are transmitted in the-direction one after another between each data transmission apparatus 1. That is, the data transmission device la outputs data to the data transmission device lb through the transmission line 80a. Also, the data transmission device lb outputs data to the data transmission device lc via the transmission line 80b. Also, the data transmission device lc outputs data to the data transmission device Id via the transmission line 80c. Also, the data transmission device Id outputs data to the data transmission device le via the transmission line 80d.
  • MOST Media Oriented Systems Transport
  • the data transmission device le outputs data to the data transmission device If via the transmission line 80e. Then, the data transmission device If outputs data to the data transmission device la via the transmission path 80f.
  • the transmission paths 80a-80f inexpensive cables such as twisted wire pairs or coaxial cables are used, and the data transmission devices 1 communicate with each other.
  • the data transmission device la is a master that transmits data by the clock of the own device, and the other data transmission device lb-If has a frequency based on the clock generated by the master. It is a slave to lock.
  • FIG. 2 is a functional block diagram showing the configuration of the data transmission apparatus 1. Note that the plurality of data transmission devices la-If described above have the same configuration, respectively, and these are collectively referred to as the data transmission device 1.
  • the data transmission device 1 includes a controller 2, a microcomputer (MPU) 3, and a transmission / reception unit 4.
  • MPU microcomputer
  • MOST transmission / reception unit 4
  • a connected device 10 Connected to the controller 2 is a connected device 10 that performs processing based on data transmitted through the data transmission system and outputs the result to the data transmission system. Then, as one of the functions, the controller 2 converts data from the connected connected device 10 into a protocol defined by the MOST, and outputs digital data TX to the transmission / reception unit 4. In addition, the controller 2 receives the digital data RX output from the transmission / reception unit 4 and transmits the data to the connected connection device 10.
  • the MPU 3 transmits the controller 2 based on each transmission mode of the data transmission apparatus 1.
  • the receiver 4 and the connection device 10 are controlled.
  • the MPU 3 controls the reset function of the data transmission apparatus 1, transmission method control (switching of 8-value Z4 mapping etc.), power control (switching of energy saving mode), master Z slave selection processing, scramble transmission function, etc. Do.
  • the transmission / reception unit 4 is typically constituted by an LSI, and includes a reception unit 5, a transmission unit 6, and a clock control unit 7.
  • the receiver 5 receives an electrical signal from another data transmission apparatus 1 input from the transmission path 80, converts the electrical signal into a digital signal RX, and outputs the digital signal RX to the controller 2. Further, the receiver 5 reproduces the clock component contained in the electric signal and outputs the clock component to the clock controller 7.
  • the transmitting unit 6 converts the digital data TX output from the controller 2 into an electrical signal based on the clock of the clock control unit 7, and outputs the electrical signal to another data transmission apparatus 1 via the transmission path 80. .
  • the clock control unit 7 controls the system clock of the data transmission apparatus 1.
  • the clock used by the transmission / reception unit 4 is output based on the clock used by the data transmission device 1 of the previous stage reproduced by the reception unit 5 or the clock of the controller 2.
  • the clock control unit 7 outputs the clock reproduced by the transmission PLL (Phase Locked Loop), and when the data transmission device 1 is a slave, the clock controller 7 reproduces the clock by the reception PLL. Output the clock.
  • the transmission PLL Phase Locked Loop
  • Transmitter 6 includes selector 61, S / P (serial Z parallel) converter 62, mapping unit 63, roll-off filter 64, DAC (digital 'analog' converter) 65, differential driver 66, and a test signal.
  • the generator 67 is included.
  • the transmitter 6 converts the digital data TX output from the controller 2 into an analog electrical signal having a signal level obtained by multi-value mapping (for example, 8-value mapping or 4-value mapping), and outputs the converted signal to the transmission path 80.
  • multi-value mapping for example, 8-value mapping or 4-value mapping
  • Selector 61 selects data (for example, digital data TX or digital data RX) to be transmitted from transmission unit 6 based on the clock controlled by clock control unit 7 and outputs it to SZP conversion unit 62. .
  • the SZP conversion unit 62 converts serial digital data output from the selector 61 into parallel data for every two bits in order to perform multi-level transmission.
  • the mapping unit 63 maps the parallel data of every 2 bits converted by the S / P conversion unit 62 to any one of! / Total 8 symbols based on the above system clock, and outputs it to the roll-off filter 64. Do. In this mapping, in order to perform clock recovery in the other data transmission apparatus 1 arranged on the receiving side, parallel data of every 2 bits are alternately divided into upper 4 symbols and lower 4 symbols among 8 symbols.
  • mapping is performed by the difference with the previous value.
  • the mapping unit 63 maps the test signal TS output from the test signal generation unit 67 as it is or based on the above-mentioned system clock to! /, Or one of the eight-valued symbols, to perform the rolloff filter 64.
  • Output to As to whether or not the mapping unit 63 maps the test signal TS it may be determined according to the test signal TS output from the test signal generation unit 67.
  • the eight-value mapping method in order to enable reception regardless of variations or differences in DC components among the respective data transmission devices 1, parallel data of the previous symbol value and the above-mentioned two bits ( Determination (mapping) of transmission symbol values based on transmission data).
  • the transmission symbol values are “+7”, “+5”, “+3”, “+1”, “ ⁇ 1”, “ ⁇ 1”, “ ⁇ 3”, “one five”, and “one seven”. It is defined to map to any of the signal levels. For example, when the previous symbol value is “one 1” and the transmission data “00” is mapped, the transmission symbol value is “+7” and the difference value with the previous symbol value is “+8”.
  • the transmission symbol values are mapped to alternate with the polarity of the previous symbol value so that their positive and negative values are alternated. Also, the transmission data is mapped to be uniquely determined for the difference value with the previous symbol value.
  • the roll-off filter 64 is a waveform shaping filter for suppressing band limitation of the electric signal to be transmitted and intersymbol interference.
  • the roll-off filter 64 is configured of an FIR filter.
  • the DAC 65 converts the band-limited signal by the roll-off filter 64 into an analog signal.
  • the differential driver 66 amplifies the strength of the analog signal output from the DAC 65, converts it into a differential signal, and sends it to the transmission line 80.
  • the differential driver 66 has two lines 1 of the transmission line 80 The electric signal to be sent is sent to one side (plus side) of the transmission line 80 to the set of conductors, and a signal that is opposite in polarity to the electric signal is sent to the other side (minus side) of the transmission line 80.
  • the electrical signals of the positive side and the negative side are transmitted as one pair in the transmission path 80, the electrical signals of the respective electrical signals cancel each other's changes, and the transmission path 80 Noise and external power can be reduced.
  • the test signal generation unit 67 generates a test signal TS in order to perform initialization in cooperation with another data transmission apparatus 1 at the time of initialization processing such as when the power is turned on.
  • the test signal TS includes a clock recovery signal (hereinafter referred to as a lock signal) for establishing synchronization on the receiving side, a trailing header signal (for example, the maximum or minimum signal level continues for a predetermined period), and reception And a training signal for setting a determination level as a reference of data determination with another data transmission apparatus 1 disposed on the side.
  • the training signal is a known data pattern among the data transmission devices 1 and includes all the above-mentioned transmission symbol values.
  • the test signal TS generated by the test signal generation unit 67 is sent to the mapping unit 63. The details and the like of the transmission waveform of the test signal TS will be described later.
  • the receiver 5 includes a clock recovery unit 50, a differential receiver 51, an ADC (analog-digital 'converter) 52, a roll-off filter 53, a difference calculation unit 54, a reverse mapping unit 55, and a PZS (parallel Z serial). ) A conversion unit 56, a determination level setting unit 57, a training signal detection unit 58, a teacher signal generation unit 59, a pattern identification unit 71, and a determination unit 72.
  • a conversion unit 56 A conversion unit 56, a determination level setting unit 57, a training signal detection unit 58, a teacher signal generation unit 59, a pattern identification unit 71, and a determination unit 72.
  • the differential receiver 51 converts the differential signal input from the transmission line 80 into a voltage signal and outputs the voltage signal to the ADC 52.
  • positive and negative electrical signals are transmitted as one pair with respect to one pair of conducting wires of the transmission line 80, and the differential receiver 51 has the bus side and the negative side. It is effective against external electrical influences in order to judge the difference signal.
  • the ADC 52 converts the voltage signal output from the differential receiver 51 into a digital signal.
  • the roll-off filter 53 is an FIR filter for waveform shaping that removes noise from the digital signal output from the ADC 52, and is combined with the above-described roll-off filter 64 on the transmission side to provide a roll-off characteristic without intersymbol interference.
  • the difference calculation unit 54 uses a roll-off filter 53 based on the data symbol timing detected by the clock reproduction unit 50 described later. The difference value dd between the received symbol value output and the previous symbol value is also calculated. Then, the difference calculation unit 54 performs data determination for each difference value dd based on the determination level set by the determination level setting unit 57, and outputs the determination value to the reverse mapping unit 55. In this way, the DC voltage difference between the devices when transmitting from the transmitting side to the receiving side data transmission device 1 is canceled by determining the received symbol value by the difference value dd from the previous symbol value. be able to.
  • the reverse mapping unit 55 decodes the data before mapping by the mapping unit 63 on the transmission side using the above determination value. By the reverse mapping process in the reverse mapping unit 55, the judgment value is converted into parallel data.
  • the PZS conversion unit 56 converts the parallel data converted by the reverse mapping unit 55 into serial digital data RX, and outputs it to the controller 2
  • Clock recovery unit 50 recovers the clock of the transmission path by recovering the clock component of the signal received from transmission path 80 output from ADC 52, and becomes the maximum or minimum point of the transmission waveform described above. Detect data symbol timing.
  • the clock regenerated by the clock regeneration unit 50 is used as a clock for the entire reception unit 5.
  • the clock regenerated by the clock regeneration unit 50 is output to the clock control unit 7 and used as a reference clock input of the receiving PLL.
  • the determination level setting unit 57 sets a determination level for determining the difference value dd as a threshold with respect to the difference value dd calculated by the difference calculation unit 54.
  • the training signal detection unit 58 detects a training header signal included in the test signal TS transmitted from the other data transmission device 1 and detects a training signal received following this training header signal. The detailed configuration of the training signal detection unit 58 will be described later.
  • the teacher signal generation unit 59 has the same data pattern as the training signal received subsequently to the training header signal, and is in synchronization with the training signal. Output MS to the judgment level setting unit 57.
  • the determination level setting unit 57 calculates the determination level based on the teacher signal MS and the difference value dd calculated with respect to the trailing signal.
  • the pattern identification unit 71 and the determination unit 72 pattern-identify the information embedded in the lock signal transmitted from the data transmission apparatus connected to the previous stage, and determine the information based on the identification result. Do. Specifically, the pattern identification unit 71 identifies the pattern of the lock signal to be transmitted on the basis of a combination of magnitudes with respect to the absolute value of the difference value. Then, the determination unit 72 determines whether the lock signal transmitted is the first lock signal or the second lock signal based on the identification result output from the pattern identification unit 71, and the determination result is generated as a test signal. Output to part 67. For example, the information embedded in the lock signal can notify the data transmission method (8-value Z4 value mapping).
  • FIG. 3 is a block diagram showing the configuration of the test signal generator 67
  • FIGS. 4 and 10 are diagrams for explaining an example of a transmission waveform of the test signal TS.
  • test signal generating unit 67 includes first lock signal generating unit 671, second lock signal generating unit 672, training header signal generating unit 673, training signal generating unit 674, selector 675, and switching instruction. It has a part 676.
  • the test signal generator 67 outputs data (data (data) representing each signal in order to transmit the test signal TS composed of the lock signal, the training header signal, and the training signal shown in FIG. The symbol is output to the mapping unit 63.
  • the first lock signal generation unit 671 outputs data for generating the first lock signal as shown in FIG. 5 to the selector 675.
  • FIG. 5 is a graph showing the transmission waveform of the first lock signal output from the data transmission device 1.
  • the first lock signal is for each data transmission device
  • This signal is used when one-power S clock synchronization is taken, and information for notifying the data transmission system 1 of the data transmission method is embedded.
  • the first lock signal notifies the lower data transmission apparatus 1 that communication is to be performed using eight-level mapped data.
  • the first lock signal is a signal in which one cycle is also eight symbol power, and the signal level "+1" and "one 1" are alternately repeated in each symbol.
  • Second lock signal generation unit 672 outputs data for generating a second lock signal as shown in FIG. 6 to selector 675.
  • 6 shows the data output from the data transmission apparatus 1.
  • 2 is a graph showing a transmission waveform of a lock signal.
  • the second lock signal is also a signal used when each data transmission apparatus 1 obtains clock synchronization, and information in which the data transmission system is notified to each data transmission apparatus 1 is embedded. It is For example, the second lock signal notifies the lower data transmission apparatus 1 that communication is to be performed using 4-value mapped data.
  • the second lock signal has eight symbol powers in one cycle, and the signal level “+1” and “one 1” are alternately repeated in each symbol, and the seventh symbol is signal level “+7”, The eighth symbol is a signal whose signal level is “one seven”.
  • the training header signal generator 673 outputs data for generating a training header signal as shown in FIG. 4 to the selector 675.
  • the training header signal is disposed between the mouth signal and the training signal, and is a signal provided to distinguish between the two.
  • the training header signal consists of 12 symbols, and in the 1st symbol to the 9th symbol, the signal levels “1” and “7” are alternately repeated, and the 10th symbol to the 12th symbol is the signal level “ It is a signal that has become constant at + 7J.
  • the training signal generator 674 outputs data for generating a training signal as shown in FIG. 7 to the selector 675.
  • FIG. 7 is a graph showing the transmission waveform of the training signal output from the data transmission device 1.
  • the training signal is a signal for setting the determination level for four-value mapping or setting the determination level for eight-value mapping in the data transmission apparatus 1 in the subsequent stage.
  • the training signal generation unit 674 creates a training signal for 4-value mapping or 8-value mapping according to the instruction from the MPU 3 when the own device is a master, and when the own device is a slave. According to the instruction of the determination unit 72, a tracing signal for 4-value mapping or 8-value mapping is created.
  • Fig. 7 shows a training signal for 8-value mapping.
  • a training signal is generated by S / P conversion of an M series (xl7 + x3 + 1: initial value: 1100000000 0000000) and mapping to eight values.
  • the training signal is transmitted for 65,536 symbols (216 symbols), and the training signal to be transmitted has a fixed length.
  • the selector 675 selects and maps one of the first lock signal, the second lock signal, the training header signal, and the training signal according to the instruction from the switching instruction unit 676. Output to section 63.
  • the selection order for outputting the test signal TS is the order of the second lock signal, the trailing header signal, and the training signal in order. These are uninterrupted mapping without breaking the law of alternately mapping the upper and lower symbols. Output to section 63.
  • switching instruction unit 676 determines the type of signal selected by selector 675.
  • a transmission waveform pattern in which the second lock signal and the training header signal are output without interruption will be described with reference to FIG. 8 to FIG.
  • the training header signal is sent out after clock synchronization has been established using the lock signal.
  • the lock signal is switched to the training header signal and output to the subsequent data transmission device.
  • the lock signal is switched to the training header signal and output to the subsequent data transmission device in response to the reception detection of the data transmission device power training header signal of the former stage (each detailed The operation will be described later).
  • the lock signal does not have a fixed length, and in the case of the second lock signal in particular, a plurality of patterns occur in the portion connected to the training header signal.
  • the connection portion between the training header signal and the training signal has a fixed pattern since both have a fixed length.
  • the difference to the signal level “one seven” of the start symbol of the training header signal The value changes from “2” ⁇ “8” ⁇ “14” (state in Figure 8). Also, when the signal level up to the final symbol of the second lock signal is “+7” ⁇ “one seven” ⁇ “+1”, the difference value up to the signal level “one seven” of the start symbol of the training header signal is It changes from “14” ⁇ “8” ⁇ “8” (state in Figure 9).
  • the difference value up to the signal level “one 7” of the start symbol of the training header signal is “ It changes from 2 ” ⁇ “ 2 ” ⁇ “ 8 ”(state in Figure 10).
  • FIG. 11 is a block diagram showing the configuration of the pattern identification unit 71
  • FIG. 12 is a diagram showing the difference value dd from which the difference calculation unit 54 is also output and the data stored in the first ROM 714 and the second ROM 717.
  • FIG. 13 is a diagram for explaining the operation of the shift register 712. is there.
  • pattern identification unit 71 includes magnitude determination unit 711, shift register 712, first comparator 713, first ROM 714, first counter 715, second comparator 716, second ROM 717, and second counter. Includes 718.
  • the difference calculation unit 54 reads the value of the symbol of the digital signal output from the ADC 52 based on the clock regenerated by the clock regeneration unit 50, and reads it immediately before the value of the symbol read.
  • the difference value dd with the value of the symbol is calculated, and the difference value dd is output to the magnitude determination unit 711. More specifically, since the first lock signal shown in FIG. 5 is such that the signal levels “+1” and “one 1” are alternately repeated for each symbol, the difference calculation unit 54 , The difference value dd shown in FIG. 12 (a) is output.
  • the difference calculation unit 54 outputs the difference value dd shown in FIG. 12 (b).
  • the magnitude determination unit 711 determines whether the absolute value of the difference value dd output from the difference calculation unit 54 is larger than a predetermined threshold value. More specifically, for example, when the threshold value is 5 and the difference value dd shown in FIG. 12 (a) is input, the magnitude judgment unit 711 outputs the input difference value dd. Data “S” indicating that the absolute value of “is smaller than the threshold value” is output to shift register 712. On the other hand, when the difference value dd shown in FIG. 12 (b) has been input, the magnitude determination unit 711 determines that the difference value dd is smaller than the threshold value at “+2” and “one”.
  • the data “S” indicating “V,” is output to the shift register 712, and the data “L” indicating “greater than the threshold value” is output to the part where the difference value dd is “+8” and “1-14”. Is output to the shift register 712. Note that, typically, the magnitude judgment unit 711 outputs data “0” in the case of data “S” and outputs data “1” in the case of data “L”.
  • the shift register 712 stores data of a predetermined number of bits, and erases data by one bit from the old one each time data is newly input from the size determination unit 711 (FIF O Method) to update internal data. More specifically, as shown in FIG. 13, in this embodiment, shift register 712 can store 8-bit data. Then, as shown in FIG. 13 (a) -FIG. 13 (c), when a bit indicating data "S" is newly input to shift register 712, data "S" is the oldest data. Discard the bit that indicates the other The area storing the bits is sequentially advanced.
  • FIG. 12 (c) shows data stored in the first ROM 714.
  • the first ROM 714 stores data for detecting that the lock signal received by the data transmission device 1 is the first lock signal.
  • eight bits of data “S” are stored in series in the first ROM 714.
  • the first comparator 713 determines whether the data stored in the shift register 712 matches the data stored in the first ROM 714 each time 1-bit data is input to the shift register 712. Determine if When the two data match, the first comparator 713 outputs data “1” indicating that the two match to the first counter 715. On the other hand, when the two data do not match, the first comparator 713 outputs, to the first counter 715, data “0” indicating that the two do not match.
  • the first counter 715 counts the number of data “1” output from the first comparator 713, and when the number of counts reaches a predetermined number (for example, 16), outputs that effect to the determination unit 72. .
  • FIG. 12 (d) shows data stored in the second ROM 717.
  • the second ROM 717 stores data for detecting that the lock signal received by the data transmission device 1 is the second lock signal.
  • 8-bit data is stored in the second ROM 717
  • the fifth and seventh data "X" 1S sixth data “L” 1S other data "S” Are stored in series
  • the data "X” indicates that the data of the shift register 712 for judging coincidence may be either "S” or "L”. This is because, as shown in FIG. 12 (b), the absolute value of the difference value before and after the difference value “1 14” is “8”, and the data “L” or “S” is set according to the setting of the threshold value.
  • the second comparator 716 determines whether the data stored in the shift register 712 matches the data stored in the second ROM 717 every time 1-bit data is input to the shift register 712. Determine if Then, if the two data match, the second comparator 716 , And outputs to the second counter 718 data "1" indicating that there is a match. On the other hand, if the two data do not match, the second comparator 716 outputs, to the second counter 718, data “0” indicating that the two do not match.
  • Second counter 718 counts the number of data “1” output from second comparator 716, and when the number of counts reaches a predetermined number (for example, 16), outputs that effect to determination unit 72. .
  • the determination unit 72 determines that the lock signal transmitted from the data transmission device in the previous stage is the first one. 1 Determine whether it is the lock signal or the second lock signal. That is, based on the information embedded in the lock signal, the determination unit 72 determines a data transmission method (eight-value Z4-value mapping) or the like to perform communication.
  • the data transmission apparatus 1 discriminates the first lock signal and the second lock signal by a powerful judgment that the absolute value of the difference value for each signal level is larger or smaller than the threshold. doing.
  • FIG. 14 is a block diagram showing the configuration of the training signal detection unit 58
  • FIG. 15 is a diagram showing the data output from the difference calculation unit 54 and the data stored in the ROM 584. These are diagrams for explaining the operation of the shift register 582.
  • the training signal detection unit 58 includes a magnitude determination unit 581, a shift register 582, a comparator 583, a ROM 584, and a counter 585.
  • the difference calculation unit 54 reads the value of the symbol of the digital signal output from the ADC 52 based on the clock regenerated by the clock regeneration unit 50, and reads it immediately before the value of the symbol read. A difference value dd with the value of the symbol is calculated, and the difference value dd is output to the magnitude judgment unit 581. More specifically, the first lock signal shown in FIG. Since the signal levels “+1” and “one 1” are alternately repeated for each symbol, the difference calculator 54 outputs the data shown in FIG. 15 (a). On the other hand, the training header signal shown in FIG. 4 changes to signal levels “+7”, “one seven”, “+7”, “one seven”, “+7”, “+7”. Therefore, the difference calculation unit 54 outputs the data shown in FIG. 15 (a).
  • the magnitude determination unit 581 determines whether the absolute value of the difference value dd output from the difference calculation unit 54 is larger than a predetermined threshold. More specifically, for example, if the data shown in FIG. 15 (a) is input, assuming that the above threshold is 5, the magnitude judgment unit 581 determines that the difference value dd is “one 14” and “one”. For the part of “+14”, data “L” indicating “more than threshold” is output to shift register 582, and when the absolute value of difference value dd is “0”, “less than threshold”! Data “L” indicating “/,” is output to shift register 582. Note that, typically, the magnitude judgment unit 581 outputs data “0” in the case of data “S”, and outputs data “1” in the case of data “L”.
  • shift register 582 stores data of a predetermined number of bits, and 1 bit from the old one each time data is newly input from size determination unit 581. Erases data by the amount (FIFO method) and updates internal data. More specifically, as shown in FIG. 16, in this embodiment, the shift register 582 can store 5-bit data. Then, as shown in FIG. 16 (a) -FIG. 16 (c), when a bit indicating data "L” or "S" is newly input to shift register 582, data which is the oldest data is input. The bits indicating "L” are discarded, and the area storing the other bits is sequentially advanced.
  • FIG. 15 (b) shows data stored in the ROM 584.
  • the ROM 584 stores data for detecting that the signal received by the data transmission device 1 is a training header signal. As shown in FIG. 15 (b), 5-bit data is stored in the ROM 584. Fifth, data "S” and data “L” are stored in series.
  • the comparator 583 determines whether or not the data stored in the shift register 582 matches the data stored in the ROM 584 each time 1-bit data is input to the shift register 582. Do. Then, when the two data match, the comparator 583 outputs data “1” indicating that the data match to the counter 585, the teacher signal generation unit 59, and the MPU 3. On the other hand, if the two data do not match, the comparator 583 sets the counter 585 and And outputs to the teacher signal generation unit 59 data “0” indicating that the force has not matched.
  • the counter 585 starts counting in response to the input of the data “1” output from the comparator 583. Then, the counter 585 detects the end of reception of the training signal having a fixed length by counting, and when reception of the training signal is ended, outputs that effect to the determination level setting unit 57. For example, the counter 585 detects the end of the training signal by counting 65536 symbols that the training signal has.
  • the data transmission apparatus 1 identifies the training header signal by the determination of the absolute value of the difference value for each signal level being greater than or less than the threshold! There is. That is, even if the difference value with respect to the received training header signal fluctuates by “0” force, the training header signal can be detected with certainty because it has a margin for the threshold.
  • the shift register 582 described above can store 5-bit data, the reason will be described. In order to reliably detect the training header signal, it must be distinguished from the second lock signal. As shown in FIG. 12 (b), in the second lock signal, the difference value before and after the difference value "14" is "+ 8", and the absolute value "8" of the difference value is the setting of the above threshold. Is a value that can be fluidly changed to data "L” or "S". That is, when the second lock signal is determined by the magnitude determination unit 581, the data “S” may be input to the shift register 582 after the data “L” continues three times.
  • shift register 582 does not use the determination of data of 6 bits or more, which is sufficient if it can store at least 5 bits of data.
  • the detection of the training header signal does not have to be the method as described above.
  • the teacher signal generation unit 59 outputs a teacher signal MS synchronized with the training signal to the determination level setting unit 57.
  • the determination level setting unit 57 receives the difference value dd calculated for the training signal by the difference calculation unit 54, and the determination level setting unit 57 uses the input difference value dd and the teacher signal MS. The setting of the determination level is started. Then, when the determination level setting unit 57 outputs from the counter 585 that the reception of the training signal is completed, the setting of the determination level ends.
  • FIGS. 17 and 18 are flowcharts showing initialization operations performed by the data transmission apparatus 1 set as the master and the slave in the data transmission system.
  • the data transmission device la is a master and the other data transmission device lb-In is a slave and only the respective constituent elements are shown
  • reference symbols a- n are used for the respective reference numerals. To distinguish.
  • each component is referred to generically, it shall be described without a-n attached to the reference code.
  • the power of the data transmission system is turned on by turning on the power of all the data transmission devices la-In connected to the data transmission system (steps S11 and S51).
  • the processes in steps S11 and S51 may be processes in which the reset state of the data transmission system is released or the like in addition to the power on of the entire system.
  • the MPU 3a of the master data transmission device la determines a data transmission method for data communication in the data transmission system (step S12).
  • the MPU 3a determines one of the four-value mapping and the eight-value mapping! / As the data transmission method.
  • the master data transmission device la is the MPU of its own device.
  • step 3a it is determined whether or not the data transmission scheme value value mapping determined in step SI 2 is satisfied (step S13). Then, the MPU 3a proceeds the process to the next step S14 if it is an eight-value mapping, and advances the process to the next step S15 if it is a four-value mapping.
  • step S14 the master data transmission device la selects the first lock signal in which the information to start the communication based on the 8-value mapped data is selected, and the process proceeds to the next step S16.
  • the operation performed in the data transmission device la in step S14 will be described in detail.
  • the MPU 3a When communication based on eight-value mapped data is started, the MPU 3a notifies the switching instruction unit 676a of the test signal generating unit 67a to that effect. In response to this notification, the switching instruction unit 676a controls the selector 675a to output the first lock signal output from the first lock signal generation unit 671a. Thereby, the test signal generation unit 67a selects the first lock signal.
  • step S15 the master data transmission device la selects the second lock signal in which the information to start communication by the 4-value mapped data is selected, and the process proceeds to the next step S16. Advance. The operation performed in the data transmission device la in step S15 will be described in detail below.
  • the MPU 3a When communication based on the four-value mapped data is started, the MPU 3a notifies the switching instruction unit 676a of the test signal generation unit 67a to that effect. In response to this notification, the switching instructing unit 676a controls the selector 675a to output the second lock signal output from the second lock signal generating unit 672a. Thereby, the test signal generation unit 67a selects the second lock signal.
  • step S16 the master data transmission device la establishes synchronization with its own reference clock, and then transmits the lock signal selected in step S14 or S15 using the clock with which synchronization has been established.
  • the lock signal output from the selector 675a is subjected to mapping processing in the mapping unit 63a, and given processing is performed between the roll-off filter 64a and the differential driver 66a, and the data transmission device lb in the subsequent stage is processed. Sent to.
  • step S51 the slave data transmission apparatus lb is Waiting for reception of the lock signal transmitted from the data transmission device la (step S52). Then, when the data transmission device lb receives the lock signal transmitted from the master data transmission device la, the process proceeds to the next step S53.
  • step S53 the data transmission apparatus lb of the slave performs clock synchronization processing using the received lock signal.
  • step S54 determines whether the received lock signal is the first lock signal. Then, if the data transmission device lb is the first lock signal, the process proceeds to the next step S55, and if it is not the first lock signal, the process proceeds to the next step S56.
  • the processing performed in the slave data transmission apparatus lb will be described in detail below in steps S53 and S54.
  • the lock signal transmitted from the data transmission device la in the previous stage is subjected to predetermined processing by the differential receiver 5 lb of the data transmission device lb and the ADC 52 b, and the clock recovery unit 50 b and the roll-off filter 53 b are processed. It is output.
  • the clock recovery unit 50 recovers the clock component included in the received lock signal. By establishing this clock as a reception clock to be used by the receiver 5 and the clock controller 7, clock synchronization processing in step S53 is performed.
  • roll-off filter 53b performs a predetermined process and outputs a lock signal to difference calculation unit 54b.
  • the difference calculating unit 54b calculates the difference value dd between the symbols of the lock signal based on the clock reproduced by the clock reproducing unit 50b, and outputs the difference value dd to the pattern identifying unit 71b and the training signal detecting unit 58b. .
  • the magnitude determination unit 71 lb of the pattern identification unit 71 b determines whether the absolute value of each difference value dd output from the difference calculation unit 54 b is larger than the above-described threshold value, and shifts the determination result. Output to register 712b. Specifically, when the above threshold value is 5, the magnitude judgment unit 71 lb outputs data “S” eight times as the judgment result for the difference value dd shown in FIG. 12 (a). In addition, the size determination unit 711b outputs data "S" four times as a determination result for the difference value dd shown in FIG. 12B, and then outputs data "L” three times, and then outputs data "S". Is output once. In response to these, one of the above two types of determination results is output to the shift register 712 b one bit at a time.
  • the first comparator 713 b includes data indicating the first lock signal stored in the 1st ROM 714 b, and The data stored in the shift register 712 b is compared every time 1 bit of data is input, and if they match, the data “1” is output to the first counter 715 b.
  • the second comparator 716b compares the data indicating the second lock signal stored in the second ROM 717b with the data stored in the shift register 712b every time one bit of data is input, If so, the data "1" is output to the second counter 718b.
  • the first counter 715 b counts the number of data “1” output from the first comparator 713 b.
  • the second counter 718 b counts the number of data “1” output from the second comparator 716 b. Then, when the number of counted data “1” reaches the predetermined number of times, both counters notify the determination unit 72 b to that effect.
  • the determination unit 72b determines whether the shift counter force has been notified as well. Then, when notified by the first counter 715b, the determination unit 72b determines that the first lock signal has been received, and recognizes that communication using data mapped to eight values is performed in the data transmission system. On the other hand, when notified by the second counter 718b, the judging unit 72b judges that the second lock signal has been received, and the data transmission system communicates with the four-value mapped data. Recognize. Then, the determination unit 72b notifies each component in the data transmission apparatus lb such as the test signal generation unit 67b and the MPU 3b of the recognition result. The same difference value dd is also output to the training signal detection unit 58b. As described above, since the lock signal is not confused with the training header signal, the training signal detection unit 58b outputs the lock signal. Do not detect the training header signal while receiving
  • step S55 test signal generation unit 67b selects the first lock signal, and the process proceeds to the next step S57.
  • test signal generation unit 67b selects the second lock signal, and the process proceeds to the next step S57.
  • the processes performed in steps S55 and S56 are the same as steps S14 and S15 except that the instruction from MPU 3a is changed to the notification from determination unit 72b, so detailed description will be omitted. Do.
  • step S57 the lock signal selected by the test signal generation unit 67b is output from the transmission / reception unit 4b of the data transmission device lb to the data transmission device lc in the subsequent stage. Also in the slave data transmission device lc-In, the above-described state described in the operation of the data transmission device lb is The processes in steps S52 to S57 are similarly performed. Then, the data transmission device In outputs the lock signal to the data transmission device la of the master.
  • step S16 the data transmission device la of the master waits for the reception of the lock signal transmitted from the data transmission device In at the previous stage (step S17).
  • step S18 clock synchronization processing is performed using the received lock signal (step S18).
  • step S18 is the same as the process of step S53, and thus the detailed description will be omitted.
  • the data transmission apparatus la of the master outputs a training header signal and a training signal according to the data transmission method determined in step S12 above to the data transmission apparatus lb of the subsequent stage (step S19). .
  • the operation performed in the data transmission device la in step S19 will be described in detail below.
  • the MPU 3a After confirming the completion of the clock synchronization process of step S18, the MPU 3a first performs a process of transmitting a tracing header signal from the data transmission device la.
  • the MPU 3a notifies the switching instructing unit 676a of the test signal generating unit 67a that the training header signal is to be selected.
  • the switching instruction unit 676a controls the selector 675a to output the training header signal output from the training header signal generator 673a.
  • the test signal generation unit 67a selects a training header signal.
  • the MPU 3a performs processing of transmitting a training header signal from the data transmission device la, and transmits processing of a training signal from the data transmission device la after a predetermined time has elapsed.
  • the training header signal has a fixed length (for example, 12 symbols)
  • switching to processing for transmitting a training signal is automatically performed based on the passage of time.
  • the MPU 3a notifies the switching instructing unit 676a of the test signal generating unit 67a that the training signal is to be selected.
  • the switching instructing unit 676a controls the selector 675a to output the training signal output from the training signal generating unit 674a.
  • the test signal generation unit 67a selects a training signal.
  • Training header signals and training signals output from these selectors 675a are sequentially mapped by the mapping section 63a, subjected to predetermined processing between the roll-off filter 64a and the differential driver 66a, and transmitted to the data transmission apparatus lb of the subsequent stage.
  • step S57 the slave data transmission apparatus lb waits for reception of the training header signal transmitted from the data transmission apparatus la of the preceding stage (step S58).
  • step S58 the process proceeds to the next step S59.
  • the process performed in the slave data transmission apparatus lb in step S58 will be described in detail.
  • the training header signal transmitted from the data transmission device la of the previous stage is subjected to predetermined processing by the differential receiver 51b of the data transmission device lb, the ADC 52b, and the roll-off filter 53b, and the difference calculator 54b. Output. Difference calculation unit 54b calculates the difference value dd between the symbols of the training header signal based on the established reception clock, and outputs the difference value dd to pattern identification unit 71b and training signal detection unit 58b. It will
  • the magnitude determination unit 581b of the training signal detection unit 58b determines whether the absolute value of each difference value dd output from the difference calculation unit 54b is larger than the above-described threshold value, and shifts the determination result. Output to register 582b. Specifically, when the threshold value is 5, the magnitude determination unit 581b outputs data “L” four times as a determination result for the difference value dd shown in FIG. Is output once. In response to these, one of the above two types of determination results is output to the shift register 582b one bit at a time.
  • the comparator 583b compares the data indicating the training header signal stored in the ROM 584b with the data stored in the shift register 582b every time 1 bit of data is input, and when the data match, the data It outputs “1” to the teacher signal generation unit 59 b, the counter 585 b, and the MPU 3 b. Then, in response to receiving data "1" from the comparator 583b, the teacher signal generation unit 59b outputs a teacher signal MS synchronized with the training signal to the determination level setting unit 57b. On the other hand, the counter 585b starts counting in response to the input of the data "1" output from the comparator 583b.
  • the same differential value dd is output to the pattern identification unit 71b, as described above, the training header signal is mixed with the lock signal. Because they are not the same, the pattern identification unit 71b does not detect the first or second lock signal while receiving the training header signal.
  • step S59 the data transmission apparatus lb outputs a training header signal and a training signal according to the data transmission method notified in step S54 to the data transmission apparatus lc in the subsequent stage, and the process is performed in the next step. Proceed to S60.
  • the process performed in step S59 is the same as that in step S19 except that the process is performed in response to the input of data "1" output from the comparator 583b by the MPU 3b, and thus the detailed description is omitted.
  • the slave data transmission device lc-In the processes of steps S58 and S59 described above in the operation of the data transmission device lb are similarly performed. Then, the data transmission device In outputs the training header signal and the training signal to the data transmission device la of the master.
  • step S60 the data transmission apparatus lb sets the determination level, and the process proceeds to the next step S61.
  • the operations performed in the data transmission apparatus lb in step S60 will be described in detail.
  • the teacher signal generation unit 59b In response to receiving the data “1” from the comparator 583b, the teacher signal generation unit 59b outputs a teacher signal MS synchronized with the training signal to the determination level setting unit 57b.
  • the determination level setting unit 57b receives the difference value dd calculated for the training signal by the difference calculation unit 54b, and the determination level setting unit 57b uses the input difference value dd and the teacher signal MS to execute the above. Start setting the judgment level.
  • step S61 the counter 585b of the data transmission apparatus lb determines whether or not the count started from the process of step S58 has reached a specified number. For example, the signal processing unit 585b detects the end of the training signal by setting the count number corresponding to 65,536 symbols of the training signal to the above specified number. Then, if the count of the counter 585b has not reached the specified number, the data transmission apparatus lb returns the process to the above step S60 and continues the determination level setting. On the other hand, when the count of the counter 585b reaches the specified number, the data transmission apparatus lb determines that the reception of the training signal transmitted from the data transmission apparatus la in the previous stage is completed, and the process proceeds to the next step S62. Advance.
  • step S19 the master data transmission device la waits for reception of the training header signal transmitted from the data transmission device In of the preceding stage (step S20). Then, when the data transmission device la receives the training header signal to which the data transmission device In power is also transmitted, the process proceeds to the next step S21.
  • the process of step S20 is the same as the process of step S58, and thus the detailed description is omitted.
  • step S21 the data transmission device la sets the determination level and proceeds to the next step.
  • the counter 585a of the data transmission apparatus la determines whether or not the count started from the process of step S20 has reached a specified number. Then, when the count of the counter 585a has not reached the specified number, the data transmission device la returns the process to the above-mentioned step S21 and continues the determination level setting. On the other hand, when the count of the counter 585a reaches the specified number, the data transmission device la determines that the reception of the training signal transmitted from the data transmission device In in the previous stage is completed, and the process proceeds to the next step S23.
  • steps S21 and S22 are the same as the processes of steps S60 and S61, and thus detailed description will be omitted.
  • the training header signal for distinguishing between the lock signal and the training signal transmitted in the initialization process can be detected reliably.
  • the training header signal can be roughly determined based on whether the absolute value of the difference value for each data signal level is larger or smaller than the threshold value, even before the data transmission device is training processing. This is because identification is possible, and even if the difference value for the received training header signal fluctuates from "0", the training header signal must be detected reliably because it has a margin for the threshold. it can.
  • the minimum difference value between adjacent symbols for example, the difference value “1 2” or “+2”.
  • the training signal detection unit 58 and the pattern identification unit 71 do not use force even if they configure some components in common.
  • the respective size determination units 581 and 711 perform the same operation in parallel in the initialization operation of the data transmission device 1.
  • the shift registers 582 and 712 have been described with different numbers of stored bits, they can be configured with the same number of bits, in which case the same is true in the initialization operation of the data transmission apparatus 1. The actions will be done in parallel. Therefore, the training signal detection unit 58 and the pattern identification unit 71 can be realized with a configuration in which the size determination unit and the shift register are common components. In this case, the same operation as described above can be performed by configuring three comparators that compare the data stored in the common shift register with the data stored in each of the three ROMs.
  • the training signal detector 58 detects the training header signal. However, other signals may be detected depending on the configuration of the test signal TS. For example, the training signal detection unit 58 detects a part of the training signal.
  • the master data transmission device la determines in the MPU 3a of its own device whether or not the data transmission method power value mapping determined in step S12 is a force or not, and the MPU 3a If it is 8-value mapping, the process proceeds to the next step S14. If it is 4-value mapping, the process proceeds to the next step S15. Also, the data transmission device lb of the slave performs clock synchronization processing using the received lock signal, and determines whether the received lock signal is the first lock signal or not, and is the first lock signal. If so, the process proceeds to the next step S55, and if it is not the first lock signal, the process proceeds to the next step S56. However, when the data transmission method is determined in advance, the step of making these determinations is unnecessary.
  • the test signal generation unit 67 shown in FIG. 3 may include only one of the first port lock signal generation unit 671 and the second lock signal generation unit 672.
  • the pattern identification unit 71 and the determination unit 72 shown in FIG. 2 also pattern-identify the information embedded in the lock signal transmitted from the data transmission device connected in the previous stage, and based on the identification result, the information It goes without saying that there is no need to have the function to determine Industrial applicability
  • the data receiving apparatus, data transmitting apparatus, data transmitting / receiving apparatus, and data transmission according to the present invention use lock signals and training signals in the initialization operation of performing communication using multilevel electric signals and the like.
  • Devices included in the system that can reliably detect the header signal transmitted between them, connect each device by a transmission path with a ring type etc., set the determination level to each other, and perform one-way electrical communication And it is useful as the said system etc.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Avant même qu'un appareil transmettant des données (1) exécute un traitement d'apprentissage, un motif de la partie détectant le signal d'apprentissage (58) identifie un signal d'en-tête d'apprentissage par utilisation d'une détermination générale se rapportant au fait de savoir si le niveau de signal d'une donnée est supérieur ou inférieur à une valeur de seuil. Il en résulte que, même si le niveau de signal d'un signal d'en-tête d'apprentissage reçu varie, le signal d'en-tête d'apprentissage peut être détecté sans faute en raison de la marge pour la valeur de seuil.
PCT/JP2004/016737 2003-11-12 2004-11-11 Appareil recevant des donnees, appareil emettant des donnees, appareil emettant/recevant des donnees, et systeme de transmission de donnees WO2005048550A1 (fr)

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JP2003383020A JP2005150970A (ja) 2003-11-12 2003-11-12 データ受信装置、データ送信装置、データ送受信装置、およびデータ伝送システム
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09205466A (ja) * 1996-01-29 1997-08-05 Kokusai Electric Co Ltd シンボル判定装置
WO2002030078A1 (fr) * 2000-10-05 2002-04-11 Matsushita Electric Industrial Co., Ltd. Procede d'initialisation et emetteur de donnees
JP2004023309A (ja) * 2002-06-14 2004-01-22 Matsushita Electric Ind Co Ltd データ送信装置、データ受信装置、データ符号化方法、及びデータ復号化方法、
WO2004059931A1 (fr) * 2002-12-25 2004-07-15 Matsushita Electric Industrial Co., Ltd. Systeme et dispositif de transmission de donnees

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09205466A (ja) * 1996-01-29 1997-08-05 Kokusai Electric Co Ltd シンボル判定装置
WO2002030078A1 (fr) * 2000-10-05 2002-04-11 Matsushita Electric Industrial Co., Ltd. Procede d'initialisation et emetteur de donnees
JP2004023309A (ja) * 2002-06-14 2004-01-22 Matsushita Electric Ind Co Ltd データ送信装置、データ受信装置、データ符号化方法、及びデータ復号化方法、
WO2004059931A1 (fr) * 2002-12-25 2004-07-15 Matsushita Electric Industrial Co., Ltd. Systeme et dispositif de transmission de donnees

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