WO2005020313A1 - Substrat a transistors en couches minces et son procede de production - Google Patents

Substrat a transistors en couches minces et son procede de production Download PDF

Info

Publication number
WO2005020313A1
WO2005020313A1 PCT/CN2003/000702 CN0300702W WO2005020313A1 WO 2005020313 A1 WO2005020313 A1 WO 2005020313A1 CN 0300702 W CN0300702 W CN 0300702W WO 2005020313 A1 WO2005020313 A1 WO 2005020313A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
terminal portion
gate
forming
thin film
Prior art date
Application number
PCT/CN2003/000702
Other languages
English (en)
Chinese (zh)
Inventor
Ko-Chin Yang
Original Assignee
Quanta Display Inc.
Quanta Display Japan Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quanta Display Inc., Quanta Display Japan Inc. filed Critical Quanta Display Inc.
Priority to AU2003255127A priority Critical patent/AU2003255127A1/en
Priority to PCT/CN2003/000702 priority patent/WO2005020313A1/fr
Publication of WO2005020313A1 publication Critical patent/WO2005020313A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present invention relates to a method for manufacturing a thin film transistor array (Thin Film Transistor Array) substrate, and more particularly, to a method for manufacturing a thin film transistor array substrate capable of reducing the number of photomasks.
  • Thin Film Transistor Array Thin Film Transistor Array
  • the thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer.
  • the thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array and a pixel electrode (corresponding to each thin film transistor). Pixel Electrode).
  • the above thin film transistor includes a gate, a channel layer, a drain, and a source, and is used as a switching element of a liquid crystal display unit.
  • the first photomask manufacturing process is used to define a first metal layer to form components such as a scanning wiring and a gate of a thin film transistor.
  • the second photomask manufacturing process defines the channel layer and ohmic contact layer of the thin film transistor.
  • the third photomask manufacturing process is used to define the second metal layer to form the data wiring and the source / drain of the thin film transistor. member.
  • the fourth photomask manufacturing process is used to pattern the protective layer.
  • the fifth photomask manufacturing process is used to pattern the transparent conductive layer to form a pixel electrode.
  • a U.S. Patent No. 5,407,845 discloses a thin film transistor manufacturing process with four photomasks.
  • the first photomask manufacturing process is used to define a first metal layer to form scan wiring and Thin-film transistor gate and other components.
  • Second photomask The fabrication process is used to define the active layer (channel layer) and the channel protective layer formed on the active layer. After that, a part of the thickness of the sidewall of the channel protective layer is removed using an anisotropic etching manufacturing process, and then the channel protective layer is used as A mask is implanted so that the sides of the active layer are doped with ions.
  • the third photomask manufacturing process is used to pattern the second metal layer and the indium tin oxide layer to define components such as data wiring, source / drain and pixel electrodes.
  • the fourth photomask is used to pattern the protective layer.
  • the protective metal layer is used as a mask to remove the second metal layer of the pixel electrode to expose the indium tin oxide layer at the pixel electrode.
  • an object of the present invention is to provide a method for manufacturing a thin film transistor array substrate, so as to reduce the number of photomasks used in a thin film transistor manufacturing process, thereby reducing manufacturing costs.
  • Another object of the present invention is to provide a method for manufacturing a thin film transistor array substrate, so as to provide a thin film transistor manufacturing process which is different from the conventional four photomasks.
  • the invention provides a method for manufacturing a thin film transistor array substrate.
  • This method firstly forms a gate on a substrate, a scanning wiring electrically connected to the gate, and a common line parallel to the scanning wiring, and simultaneously A first terminal portion is formed at the edge, wherein the end of the scanning wiring is electrically connected to the first terminal portion, and the common line is used as a lower electrode of the pixel storage capacitor.
  • a gate insulating layer is formed on the substrate to cover the gate, the scan wiring, the common line, and the first terminal portion.
  • a channel layer and an ohmic contact layer are formed on the gate insulating layer above the gate.
  • a transparent conductive layer is formed on the substrate, and a metal layer is formed on the transparent conductive layer.
  • a metal layer and a transparent conductive layer are patterned to define a source / drain, a data wiring, a pixel area, and a second terminal portion, wherein the data wiring is electrically connected to the source, and its ends are The two terminal portions are electrically connected, and the gate, the channel layer and the source / drain constitute a thin film transistor.
  • a protective layer is formed on the substrate, and the pixel region and the second terminal portion and the gate insulating layer above the first terminal portion are exposed.
  • the protective layer as a mask, the metal region of the pixel region and the second terminal portion and the gate insulating layer above the first terminal portion are removed, exposing the transparent conductive layer of the pixel region and the second terminal portion and the first terminal. Transparent conductive layer exposed in the pixel region That is the pixel electrode.
  • the pixel electrode formed above the common line serves as a conductive electrode of the pixel storage capacitor.
  • a transparent conductive layer may be selectively formed on the surfaces of the gate, the scan wiring, the common line, and the first terminal portion, the purpose of which is to protect the first terminal portion.
  • the surface is not damaged by subsequent etching manufacturing processes. If the transparent conductive layer is not formed, the gate electrode, the scanning wiring, the common line, and the first terminal portion need to be made of a metal material that is not etched.
  • the present invention further provides a method for manufacturing a thin film transistor array substrate.
  • This method first forms a gate on a substrate, a scanning wiring electrically connected to the gate, and a common line parallel to the scanning wiring, and simultaneously A first terminal portion is formed at one edge, wherein the end of the scanning wiring is electrically connected to the first terminal portion, and the common line is used as a lower electrode of the pixel storage capacitor.
  • a gate insulating layer is formed on the substrate to cover the gate, the scan wiring, the common line, and the first terminal portion.
  • a channel material layer and an ohmic contact layer are formed on the gate insulating layer, and a photoresist layer is formed on the ohmic contact layer, wherein the photoresist layer exposes the first terminal portion, and the photoresist layer corresponds to The thickness of the place where the gate is formed on the substrate is thicker than the thickness of other parts.
  • the photoresist layer as a mask, the ohmic contact layer, the channel material layer, and the gate insulation layer on the first terminal portion are removed to expose the first terminal portion.
  • the first photoresist layer is a channel material layer and an ohmic contact layer covering the gate.
  • the first photoresist layer is used as a mask to pattern the ohmic contact layer and the channel material layer, and a channel layer and the patterned ohmic contact layer are defined on the gate insulating layer above the gate.
  • a transparent conductive layer is formed on the substrate, and a metal layer is formed on the transparent conductive layer.
  • the metal layer and the transparent conductive layer are patterned to define the source / drain, the data wiring, the second terminal portion, and the pixel area, and at the same time, a conductive block is defined on the exposed first terminal portion.
  • the wire is electrically connected to the source, and its end is electrically connected to the second terminal portion.
  • the conductive block on the first terminal portion at the end of the scanning wiring is electrically connected to the data wiring.
  • a protective layer is formed on the substrate to expose the pixel area and the second terminal. A metal layer of the first portion and a conductive block on the first terminal portion.
  • the metal layer of the pixel region and the second terminal portion and the metal layer of the conductive block are removed, and the transparent conductive layer of the pixel region and the second terminal portion and the transparent conductive layer of the conductive block are exposed, and
  • the transparent conductive layer exposed in the pixel area is the pixel electrode, and the transparent conductive layer of the conductive block on the first terminal portion is electrically connected to the data wiring.
  • the pixel electrode formed above the common line serves as an upper electrode of the pixel storage capacitor.
  • a transparent conductive layer may be selectively formed on the surface of the gate, the scan wiring, the common line, and the first terminal portion, and the purpose is to protect the first conductive layer.
  • the surface of one terminal portion is not damaged by the subsequent etching manufacturing process. If the transparent conductive layer is not formed, the gate electrode, the scanning wiring, the common line, and the first terminal portion need to be made of a metal material that is not etched.
  • the manufacturing method of the thin film transistor array substrate provided by the present invention only needs to use four photomasks, so the number of photomasks required for a thin film transistor manufacturing process can be reduced, thereby reducing the manufacturing cost.
  • the second photomask manufacturing process is used to define a channel layer and an ohmic contact layer, and even in another embodiment, the second photomask The manufacturing process can also expose the first terminal portion at the same time.
  • the second photomask manufacturing process of the well-known four photomask thin film transistor manufacturing process is used to define the active layer (channel layer) and the channel protection layer. Therefore, the four photomask manufacturing process of the present invention is different from Well-known methods.
  • the manufacturing method of the thin film transistor array substrate proposed by the present invention requires only four photomask manufacturing processes, and the second photomask manufacturing process is different from the known technology.
  • the method of the present invention can also There is an electrical connection relationship between the scanning wiring and the data wiring. In this way, it will facilitate the convenience of the electrostatic discharge protection circuit or other circuit designs.
  • FIG. 1 is a top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. Intention
  • FIGS. 2A to 2E are schematic cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • 3A to 31 are schematic cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to another preferred embodiment of the present invention.
  • FIG. 1 is a schematic top view showing a thin film transistor array substrate according to a preferred embodiment of the present invention
  • FIG. 2A to FIG. 2E are a thin film transistor array according to a preferred embodiment of the present invention
  • a schematic cross-sectional view of the manufacturing process of the substrate is a cross-sectional view taken from I to I in FIG. 1.
  • a substrate 200 is provided.
  • the substrate 200 is, for example, a glass substrate or a plastic substrate.
  • a first metal layer is formed on the substrate 200
  • a first photomask manufacturing process is performed to define a gate 206, a scan wiring 202 electrically connected to the gate 206, and a common line 214 parallel to the scan wiring 202 And a first terminal portion 212a formed at the edge of the substrate 200.
  • the first terminal portion 212a is electrically connected to the scanning wiring 202, and is subsequently used to be electrically connected to the driving circuit.
  • the common line 214 is then used as the lower electrode of the pixel storage capacitor 250.
  • the material of the first metal layer is, for example, chromium (&), tungsten (W), tantalum
  • Ti titanium
  • Mo molybdenum
  • Al aluminum
  • an additional layer of transparent conductive layer 201 may be selectively formed on the surfaces of the gate electrode 206, the scan wiring 202, the common line 214, and the first terminal portion 212a.
  • the material is, for example, indium tin oxide (ITO) or indium zinc oxide
  • IZO IZO
  • a transparent conductive layer (not shown) is deposited on the first metal, and then the transparent conductive layer and the first metal layer are patterned together, and Define gate 206, scan wiring 202, and common line 214 And the first terminal portion 212a, and the transparent conductive layer 201 formed on the surface of the gate 206, the scan wiring 202, the common line 214, and the first terminal portion 212a. If the transparent conductive layer 201 is not formed, the first metal layer needs to be made of a metal material that is not etched.
  • a gate insulating layer 205 is formed on the substrate 200 to cover the first metal layer (including the gate 206, the scan wiring 202, the common line 214, and the first terminal portion 212a).
  • the material of the gate insulating layer 205 is, for example, silicon nitride, silicon oxide, or silicon oxynitride.
  • a channel material layer (not shown) and an ohmic contact layer (not shown) are formed over the substrate 200, and a second photomask manufacturing process is performed to insulate the gate above the gate 206
  • a layer 205 defines a channel layer 208 and an ohmic contact layer 209.
  • the material of the channel layer 208 is, for example, amorphous silicon
  • the material of the ohmic contact layer 209 is, for example, doped amorphous silicon.
  • a transparent conductive layer (not shown) and a second metal layer (M2) (not shown) are sequentially deposited on the substrate 200, and then a third photomask manufacturing process is performed to: The second metal layer and the transparent conductive layer are patterned to define the data wiring 204 and the source / drain electrodes 210a / 210b.
  • the circuit is electrically connected.
  • the defined data wiring 204, source / drain 210a / 210b, and second terminal portion 212b are two layers having a metal layer (upper layer) and a transparent conductive layer 215 (lower layer). structure.
  • the defined pixel region 260 is also a two-layer structure, which includes a lower transparent conductive layer 215 and an upper metal layer 210C.
  • the material of the second metal layer is, for example, chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (A1), or an alloy
  • the material of the transparent conductive layer 215 is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).
  • a protective layer (not shown) is formed over the substrate 200, and a fourth photomask manufacturing process is performed to form a patterned protective layer 211, where the protective layer 211 is a gate insulating layer 212a that exposes the pixel region 260, the second terminal portion 212b, and the first terminal portion 212a.
  • the material of the protective layer 211 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or an organic material.
  • the metal layer not covered by the protective layer 211 is removed, which includes the metal layer 210c in the pixel region 260 and the metal layer of the second terminal portion 212b, and the first terminal portion is removed.
  • the gate insulating layer 205 above 212 exposes the transparent isoelectric layer 215 in the pixel region 260, the transparent conductive layer 215 of the second terminal portion 212b, and the first terminal portion 212 (or the transparent conductive layer on the first terminal portion 212).
  • Layer 201 wherein the transparent conductive layer 215 exposed in the pixel region 260 is the pixel electrode 216. In this way, the fabrication of a thin film transistor array substrate is completed.
  • the previously formed common line 214 is used as the lower electrode of the pixel storage capacitor 250, so the pixel electrode 216 formed above the common line 214 is used as the upper electrode of the pixel storage capacitor 250, and is formed on the common line 214 and the pixel electrode 216
  • the gate insulation layer 205 in between serves as a capacitor dielectric layer.
  • the first photomask is used to define a first metal layer to form a gate, a scan wiring, a common line, and a first ⁇ terminal ⁇ One terminal portion.
  • the second photomask manufacturing process is to define the channel layer and the ohmic contact layer.
  • the third photomask manufacturing process is used to define the second metal layer and the transparent conductive layer to define the data wiring, the source / drain, the pixel region and the second terminal portion.
  • the fourth photomask is used to pattern the protective layer.
  • the second metal layer in the pixel region can be removed to expose the transparent conductive layer to form a pixel electrode, and the gate insulating layer on the first terminal portion can be removed to The first terminal portion is exposed.
  • a schematic cross-sectional view of a manufacturing process of a body tube array substrate is a schematic cross-sectional view taken along I- ⁇ in FIG. 1.
  • a first metal layer (not shown) is formed on the substrate 200, and a first photomask manufacturing process is performed to define the gate electrode 206, and the gate electrode 206.
  • the scan wiring 202 electrically connected, the common line 214 parallel to the scan wiring 202, and the first terminal portions 212a formed at the two edges of the substrate 200.
  • the first terminal portion 212a is electrically connected to the scanning wiring 202, and is subsequently used to electrically connect to the driving circuit.
  • the common line 214 is subsequently used as the lower electrode of the pixel storage capacitor 250.
  • the material of the first metal layer is, for example, chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Ai), or an alloy.
  • an additional layer of transparent conductive layer 201 can be selectively formed on the surfaces of the gate electrode 206, the scan wiring 202, the common line 214, and the first terminal portion 212a.
  • transparent conductive layer 201 can be selectively formed on the surfaces of the gate electrode 206, the scan wiring 202, the common line 214, and the first terminal portion 212a. Examples are indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the gate 206, the scan wiring 202, the common line 214, and the first terminal portion 212a, and the transparent conductive layer 201 formed on the surfaces of the gate 206, the scan wiring 202, the common line 214, and the first terminal portion 212a are defined. If the transparent conductive layer 201 is not formed, the first metal needs to be made of a metal material that is not etched.
  • a gate insulating layer 205 is formed on the substrate 200 to cover the first metal layer (including the gate 206, the scanning wiring 202, the common line 214, and the first terminal portion 212a).
  • the material of the gate insulating layer 205 is, for example, silicon nitride, silicon oxide, or silicon oxynitride
  • a channel material layer 268 and an ohmic contact layer 269 are formed on the gate insulating layer 205.
  • This second photomask manufacturing process includes first forming a photoresist layer 310 on the ohmic contact layer 269, and setting a photomask 300 above the photoresist layer 310.
  • the photomask 300 has an exposure area 302 and half exposure. Region 304 and a non-exposed region 306.
  • the exposed region 302 corresponds to the place where the first terminal portion 212a is formed on the substrate 200
  • the non-exposed region 306 corresponds to the place where the gate 206 is formed on the substrate 200
  • the semi-exposed region 304 It corresponds to other parts on the substrate 200.
  • a lithography manufacturing process is performed to pattern the photoresist layer 310 to form a patterned photoresist layer 310a.
  • the photoresist layer 310a exposes the ohmic contact layer 269 above the terminal portion 212 and covers
  • the thickness of the photoresist layer 310a above the gate electrode 206 is thicker than the thickness of the photoresist layer 310a in other portions.
  • an etching step is performed using the photoresist layer 310a as an etching mask to remove the ohmic contact layer 269, the channel material layer 268, and the gate insulation layer 205 above the first terminal portion 212a, exposing the first terminal. 212a (or the transparent conductive layer 201 on the first terminal portion 212a).
  • a photoresist ashing step is performed to remove a part of the thickness of the photoresist layer 310a to form a photoresist layer 310b.
  • the formed photoresist layer 310b is an ohmic contact layer 269 overlying the gate 206 .
  • an etching step is performed to pattern the ohmic contact layer 269 and the channel material layer 268, and the channel layer 208 and the ohmic contact layer 209 are defined.
  • a transparent conductive layer (not shown) and a second metal layer (M2) (not shown) are sequentially deposited on the substrate 200, and then a third photomask manufacturing process is performed for patterning.
  • the second metal layer and the transparent conductive layer define the data wiring 204, the source 210a, the drain 210b, the pixel region 260, and the second terminal portion 212b, and at the same time, the conductive is defined on the exposed first terminal portion 212a Block 219.
  • the data wiring 204 is electrically connected to the source 210a, and its end is electrically connected to the second terminal portion 212.
  • the second terminal portion 212b is subsequently used to be electrically connected to the driving circuit.
  • the defined data wiring 204, the source 210a, the drain 210b, and the second terminal portion 212b have a two-layer structure including a metal layer (upper layer) and a transparent conductive layer 215 (lower layer).
  • the defined pixel region 260 is also a two-layer structure, which includes a lower layer The transparent conductive layer 215 and the upper metal layer 210c.
  • the conductive block 219 on the first terminal portion 212a also includes a lower transparent conductive layer 215 and an upper metal layer 210d, and the conductive block 219 on the first terminal portion 212a is electrically connected to the data wiring 204.
  • the material of the second metal layer is, for example, chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum, (Mo), aluminum (A1), or an alloy
  • the material of the transparent conductive layer 215 is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the ohmic contact layer 209 exposed by the second metal layer is removed, and the channel layer 208 is exposed.
  • a protection layer (not shown) is formed on the substrate 200, and a fourth photomask manufacturing process is performed to form a patterned protection layer 211, wherein the protection layer 211 exposes the pixel region 260, the second terminal portion 212b, and the conductive block 219 above the first terminal portion 212a.
  • the material of the protective layer 211 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or an organic material.
  • the metal layer not covered by the protective layer 211 is removed, which includes 210c in the pixel region 260 and the metal layer of the second terminal portion 212b, and the first terminal portion 212a is removed at the same time.
  • the metal layer 210d of the conductive block 219 is exposed, and the transparent conductive layer 215 in the pixel region 260, the transparent conductive layer 215 of the second terminal portion 212b, and the transparent conductive layer 215 on the first terminal 212a are exposed, wherein the pixel region 260
  • the exposed transparent conductive layer 215 is the pixel electrode 216, and the transparent conductive layer 215 above the first terminal portion 212 is the contact layer 216a.
  • the contact layer 216a above the first terminal portion 212a is electrically connected to the data wiring 204.
  • the scanning wiring 202 and the data wiring 204 are electrically connected.
  • the A conductive block 219 (including a metal layer 210d and a transparent conductive layer 215) is defined on the first terminal portion 212a, and there is electrical conductivity between the conductive block 219 on the first terminal portion 212a at the end of the scanning wiring 202 and the data wiring 204 Connected off Department.
  • the scan wiring 202 and the data wiring 204 can still be formed by the contact layer 216a (that is, the transparent conductive layer 215 formed on the first terminal portion 212a). Electrical connection relationship.
  • the scan wiring 202 (the first metal layer) and the data wiring 204 (the second metal layer) have an electrical connection relationship, which will facilitate the convenience of the electrostatic discharge protection circuit and other circuit designs.
  • the protection circuit is composed of two thin film transistors, and their respective gates and sources are electrically connected to each other, thereby forming two reverse diodes. Therefore, if the design of such an electrostatic discharge protection circuit is to be used, the first metal layer and the second metal layer must be electrically connected.
  • the common line 214 formed previously is used as the lower electrode of the pixel storage capacitor 250, so the pixel electrode 216 formed above the common line 214 is used as the upper electrode of the pixel storage capacitor 250, and is formed on the common line 214 and the pixel electrode 216
  • the gate insulating layer 205 is a capacitor dielectric layer.
  • the first photomask is used to define a first metal layer to form a gate, a scan wiring, a common line, and a first ⁇ terminal ⁇ One terminal portion.
  • the second photomask manufacturing process is used to define the channel layer and the ohmic contact layer and expose the first terminal portion.
  • the third photomask manufacturing process is used to define the second metal layer and the transparent conductive layer to define the data wiring, the source / drain, the pixel region, the second terminal portion and the conductive block.
  • the fourth photomask is used to pattern the protective layer.
  • the second metal layer in the pixel region can be removed, the transparent conductive layer is exposed, and a pixel electrode is formed.
  • the metal layer of the conductive block on the first terminal portion is removed to expose the transparent conductive layer.
  • the method for manufacturing a TFT array substrate of the present invention only requires four photomasks, the number of photomasks required for a thin film transistor manufacturing process can be reduced, thereby reducing manufacturing costs.
  • the second photomask manufacturing process is used to define a channel layer and an ohmic contact layer, and even
  • the second photomask manufacturing process can also expose the first terminal portion at the same time
  • the thin film transistor manufacturing of four photomasks is well-known: the second process of L photomask manufacturing process is used to define the active Layer (channel layer) and channel protection layer, so the four photomask manufacturing process of the present invention is a method different from the known technology.
  • the manufacturing method of the thin film transistor array substrate provided by the present invention requires only four photomask manufacturing processes, and the second photomask manufacturing process is different from the known technology.
  • the method of the present invention can also There is an electrical connection relationship between the scanning wiring and the data wiring. In this way, it will facilitate the convenience of the electrostatic discharge protection circuit or other circuit designs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de production d'un substrat à transistors en couches minces, lequel comprend les opérations consistant à: former une grille et une ligne de balayage électriquement reliée à la grille sur un substrat; former une couche d'isolation de grille sur le substrat; former une couche canal sur la couche d'isolation de grille placée sur la grille; former, de façon séquentielle, une couche conductrice transparente et une couche métallique sur le substrat; structurer la couche métallique et la couche transparente pour définir des sources/drains/lignes de données et régions de pixels; former une couche protectrice sur le substrat pour que la couche métallique soit exposée dans les régions de pixels, enlever la couche métallique dans les régions de pixels à l'aide d'une couche protectrice servant de masque pour former des électrodes de pixels. Etant donné, que selon l'invention, on ne fait appel qu'à quatre étapes de masquage, les coûts de fabrication d'un tel substrat sont réduits.
PCT/CN2003/000702 2003-08-21 2003-08-21 Substrat a transistors en couches minces et son procede de production WO2005020313A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003255127A AU2003255127A1 (en) 2003-08-21 2003-08-21 Thin film transistor array substrate and its manufacturing method
PCT/CN2003/000702 WO2005020313A1 (fr) 2003-08-21 2003-08-21 Substrat a transistors en couches minces et son procede de production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2003/000702 WO2005020313A1 (fr) 2003-08-21 2003-08-21 Substrat a transistors en couches minces et son procede de production

Publications (1)

Publication Number Publication Date
WO2005020313A1 true WO2005020313A1 (fr) 2005-03-03

Family

ID=34201004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2003/000702 WO2005020313A1 (fr) 2003-08-21 2003-08-21 Substrat a transistors en couches minces et son procede de production

Country Status (2)

Country Link
AU (1) AU2003255127A1 (fr)
WO (1) WO2005020313A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1257304A (zh) * 1998-12-12 2000-06-21 三星电子株式会社 供液晶显示器用薄膜晶体管阵列面板及其制造方法
US6107640A (en) * 1996-07-02 2000-08-22 Lg Electronics Inc. Semiconductor device for a thin film transistor
CN1379452A (zh) * 2001-04-04 2002-11-13 三星Sdi株式会社 薄膜晶体管及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107640A (en) * 1996-07-02 2000-08-22 Lg Electronics Inc. Semiconductor device for a thin film transistor
CN1257304A (zh) * 1998-12-12 2000-06-21 三星电子株式会社 供液晶显示器用薄膜晶体管阵列面板及其制造方法
CN1379452A (zh) * 2001-04-04 2002-11-13 三星Sdi株式会社 薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
AU2003255127A1 (en) 2005-03-10

Similar Documents

Publication Publication Date Title
US6927105B2 (en) Thin film transistor array substrate and manufacturing method thereof
JP5380037B2 (ja) 半導体装置の作製方法
TWI382452B (zh) 薄膜電晶體陣列面板及其製造方法
US7049215B2 (en) Thin film transistor array panel and fabricating method thereof
US7098062B2 (en) Manufacturing method of pixel structure of thin film transistor liquid crystal display
US6338988B1 (en) Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step
JP2001066638A (ja) 液晶表示装置およびその製造方法
US20090108260A1 (en) Pixel structure and method for manufacturing the same
JP4578402B2 (ja) 薄膜トランジスタ基板及びその製造方法
US8405082B2 (en) Thin film transistor array substrate and manufacturing method thereof
US6913957B2 (en) Method of fabricating a thin film transistor array panelsubstrate
TWI360012B (en) Thin film transistor array panel
JP2006018281A (ja) 薄膜トランジスタ表示板の製造方法
JPH10206892A (ja) アクティブマトリクス型液晶表示装置およびその製造方 法
JP2003517641A (ja) アクティブマトリクスデバイスの製造方法
JP2008098642A (ja) 薄膜トランジスタ基板の製造方法
JP2006295121A (ja) 薄膜トランジスタを用いた液晶表示装置及びその製造方法
US8288212B2 (en) Pixel structure of a thin film transistor liquid crystal display and fabricating method thereof
JPH11352515A (ja) 液晶表示装置およびその製造方法
JP2005064344A (ja) 薄膜半導体装置の製造方法、薄膜半導体装置、電気光学装置及び電子機器
JP3114303B2 (ja) 薄膜トランジスタパネル及びその製造方法
WO2005020313A1 (fr) Substrat a transistors en couches minces et son procede de production
US7651876B2 (en) Semiconductor structures and method for fabricating the same
JP2006285163A (ja) 薄膜トランジスタアレイの製造方法
JP4795555B2 (ja) 画像表示装置の製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP