WO2004107263A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2004107263A1 WO2004107263A1 PCT/JP2003/006829 JP0306829W WO2004107263A1 WO 2004107263 A1 WO2004107263 A1 WO 2004107263A1 JP 0306829 W JP0306829 W JP 0306829W WO 2004107263 A1 WO2004107263 A1 WO 2004107263A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- capacitor
- semiconductor device
- wiring board
- sealing portion
- coil
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
- G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7865—Means for transporting the components to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Definitions
- the present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a technology effective when applied to an IC (Integrated circuit) force.
- the I C force is the force that the IC chip is built into a flat rectangular thin plate (force body).
- a contact-type IC card is an IC card that can supply power and exchange signals through connection terminals exposed on the surface of the card body.
- the IC chip of the contact type IC card is built in the card body while being mounted on the back side of the wiring board having the connection terminals.
- the non-contact type IC card is an IC card that can supply power by electromagnetic waves (wireless) and exchange signals through an antenna built into the body of the card.
- the contact / non-contact type IC card is a combination of the contact type and the non-contact type, and has a contact and non-contact type IC chip built into a single card body, Some IC chips have both contact and non-contact faces. Above contact / non-contact type I C force
- a configuration in which an antenna about the size of a connection terminal, an IC chip, and a capacitor connected in parallel to the antenna are mounted on the component mounting surface of the board provided on the back surface of the connection terminal (See, for example, JP-A-2002-207982).
- the sealing resin for sealing the IC chip mounted on the component mounting surface of the IC module substrate has a partial opening for exposing the antenna connection terminal formed on the component mounting surface.
- an IC card structure having a configuration in which a transmitting and receiving coil for an antenna is connected to an exposed portion of an antenna connection terminal (see, for example, JP-A-2003-67695).
- a card-type semiconductor device such as an IC card, how to improve its communication characteristics is one of the important issues.
- An object of the present invention is to provide a technique capable of improving communication characteristics of a card type semiconductor device.
- the present invention provides a semiconductor chip on which an integrated circuit is formed, a wiring board on which the semiconductor chip is mounted, and a non-contact type electronic device electrically connected to the semiconductor chip through wiring of the wiring board.
- a non-contact type face in the card body wherein the non-contact type face includes a coil having a function as an antenna, and a capacitor connected in parallel to the coil to form a resonance circuit.
- the wiring board is connected to the wiring board by soldering.
- FIG. 1 is an overall plan view of an example of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is an enlarged cross-sectional view of a main part taken along line X1-X1 in FIG.
- FIG. 3 is an overall plan view showing a main part removed from the semiconductor device of FIG.
- FIG. 4 is an enlarged sectional view of a main part taken along line X1-X1 in FIG.
- FIG. 5 is an overall plan view of an example of a contact surface of a main part of the semiconductor device in FIG.
- FIG. 6 is an overall plan view of an example of a mold surface of a main part of the semiconductor device of FIG.
- FIG. 7 is an overall plan view of an example of the mold surface from which the sealing portion of FIG. 6 has been removed.
- FIG. 8 is a sectional view taken along the line Y1-Y1 in FIGS.
- FIG. 9 is a cross-sectional view taken along line X2-X2 in FIG.
- FIG. 10 shows a capacitor constituting a non-contact type device of the semiconductor device of FIG.
- FIG. 3 is a circuit diagram showing a connection relationship between a sensor and a coil.
- FIG. 11 is an enlarged cross-sectional view (along line X3-X3 in FIG. 7) of an example of the capacitor of the semiconductor device in FIG.
- FIG. 12 is an overall plan view of the mold surface shown in FIG. 7 with the semiconductor chip and the capacitor of the semiconductor device removed.
- FIG. 13 is an explanatory diagram showing an arrangement of antenna connection terminals in a main part of the semiconductor device of FIG. 1 and a state of a connection relationship between the antenna connection terminals and the coil.
- FIG. 14 is an explanatory diagram showing, for comparison, another arrangement of the antenna connection terminals examined by the present inventors.
- FIG. 15 is a flowchart of an example of a manufacturing process of the semiconductor device of FIG.
- FIG. 16 is an enlarged plan view of a main part of an example of a wiring substrate base used in the manufacturing process of the semiconductor device of FIG.
- FIG. 17 is an enlarged plan view of an essential part of an example of the contact surface of the wiring board mother body in FIG.
- FIG. 18 is an enlarged plan view of an essential part of an example of the mold surface of the wiring board mother body in FIG.
- FIG. 19 is an explanatory diagram of an example of an assembling apparatus used in the capacitor mounting step of the semiconductor device of FIG.
- FIG. 20 is an enlarged plan view of a main part of the wiring substrate matrix during the manufacturing process of the semiconductor device of FIG.
- FIG. 21 is an explanatory view of an example of an assembling apparatus used in a semiconductor chip mounting step of the semiconductor device of FIG.
- FIG. 22 is an enlarged plan view of a main part of the wiring substrate body after the wire bonding step of the semiconductor device of FIG.
- FIG. 23 is an enlarged plan view of a main part of the wiring substrate body after the molding process of the semiconductor device of FIG.
- FIG. 24 is a plan view of an example of a mold surface of a wiring board during a manufacturing process of a semiconductor device according to another embodiment of the present invention.
- Fig. 25 shows the plane of the mold surface of the wiring board after mounting the capacitor in Fig. 24.
- FIG. 26 is a plan view of an example of a mold surface of a wiring board during a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
- FIG. 27 is a plan view of the mold surface of the wiring board after the capacitors are mounted in FIG.
- FIG. 28 is a plan view of an example of a mold surface of a wiring board before a chip is mounted during a manufacturing process of a semiconductor device according to another embodiment of the present invention.
- FIG. 29 is a plan view of an example of the mold surface of the wiring board after the semiconductor chip and the internal capacitor are mounted in FIG.
- FIG. 30 is a plan view of an example of the mold surface of the wiring board after forming the sealing portion in FIG.
- FIG. 31 is a plan view of an example of the mold surface of the wiring board after mounting the external capacitor in FIG.
- FIG. 32 is an overall plan view of an example of a mold surface after one capacitor is mounted on a wiring board during a manufacturing process of a semiconductor device according to another embodiment of the present invention.
- FIG. 33 is an overall plan view of an example of a mold surface after two capacitors are mounted on a wiring board during a manufacturing process of a semiconductor device according to another embodiment of the present invention.
- the semiconductor device includes, for example, a credit card, a cash card, an ETC (Electronic Toll Collection system) system card, a commuter pass, a public phone card, a mobile phone card, an authentication card, and the like. It is an IC (Integrated Circuit) card that is being used in various fields such as finance, transportation, communications, distribution and authentication.
- FIG. 1 shows an example of an overall plan view of an IC card 1 according to the first embodiment.
- FIG. 2 is an enlarged cross-sectional view of a main part taken along line X1-X1 in FIG.
- FIG. 3 is an overall plan view of the IC card 1 shown in FIG. 1 with the IC module 2 removed
- FIG. 4 is an enlarged cross-sectional view of a main part taken along the line X1-X1 in FIG.
- the IC card 1 is, for example, an evening card in which a contact type and a non-contact type are integrated, and its outer shape is a rectangular plane slightly smaller than a business card size (91 mm ⁇ 55 mm). It has a thin plate shape.
- the external dimensions of the Ic force 1 are, for example, 85.6 mm ⁇ 54 mm in length (longitudinal dimension) ⁇ width (short dimension), and 0.76 mm in thickness.
- the IC module 2 of the IC card 1 is a main circuit section having an IC chip (semiconductor chip) 3.
- the plurality of module terminals 4 of the IC module 2 are exposed to the outside, and Wiring board 5 for mounting 3 etc. and IC chip 3 Sealing portion 6 a for sealing etc. are fitted to the card body 7 in such a state that they are fitted into the stepped recesses 7 a of the card body 7. Fixed.
- the antenna connection terminal 8a is connected to the connection terminal Lt at both ends of the antenna coil L via a conductive adhesive material 10 such as a silver (Ag) containing paste or the like, and is electrically connected. Have been.
- the coil L for the antenna is formed in a loop shape along the outer periphery of the card body 7 (see the broken line in FIG. 3). By providing the coil L in the card body 7 in this manner, the loop of the coil L can be enlarged, so that the gain of the antenna can be improved, and the IC card 1 and an external transmitting / receiving unit (reader / writer) can be provided.
- the range (directivity) of wireless signal exchange with (evening) can be expanded. Therefore, even if the IC card 1 is separated from the external transmitting / receiving unit to some extent, it is possible to exchange wireless signals.
- Most of the coil L is embedded in the card body 7, but one surface of the connection terminal Lt at both ends of the coil L is connected to the wiring board 5 so that the stepped portion of the recess 7 a of the card body 7 is formed. It is exposed to.
- the card body 7 is made of a plastic such as, for example, polyvinyl chloride resin, polyolefin (polypropylene, etc.), polyethylene terephthalate (PET), or polyethylene terephthalate glycol (PET-G). Become. Use such relatively inexpensive plastic Thereby, the cost of the IC card 1 can be reduced. In addition, since harmful substances are not generated even if polypropylene, PET or PET-G is burned, the load on the environment can be reduced by using them as the material of the forceps body 7. Furthermore, since PET-G is amorphous and softer than PET, processing such as embossing can be facilitated by using PET-G as the material of the forceps body 2.
- FIG. 5 shows an example of the contact surface (second surface) of the wiring board 5 of the IC module 2.
- the board body of the wiring board 5 is made of, for example, a glass epoxy resin, and, for example, eight module terminals 4 (4a to 4h) are arranged on the contact surface in a state of being close to each other.
- the module terminals 4 are formed by applying gold (Au) plating on an exposed surface of a metal foil such as copper (Cu), and directly connected to connection terminals of an external transmission / reception device (reader / writer). This is a contact-type interface that electrically connects the transmitting / receiving device and the circuit in IC module 2.
- the module terminal 4a at the upper left of FIG. 5 is, for example, a terminal for supplying the power supply voltage on the high potential side.
- the module terminal 4b below it is, for example, a terminal for a reset signal.
- the module terminal 4c below it is a terminal for a clock signal.
- the relatively large module terminal 4e at the center is, for example, a terminal for supplying a low-potential power supply voltage (for example, a ground voltage) lower than the high-potential power supply voltage.
- the module terminal 4 g is, for example, a terminal for overnight input / output signals.
- the other module terminals 4 d, 4 f, and 4 h are non-connect terminals that can be used in the future, but have no assignment at present.
- FIG. 6 shows an example of the mold surface (first surface) of the wiring board 5 of the IC module 2.
- This mold surface is a surface on the opposite side of the contact surface.
- the sealing portion 6 a is provided at the center of the mold surface of the wiring board 5.
- the sealing portion 6a is made of, for example, an epoxy resin, and is formed, for example, in a planar rectangular shape.
- the antenna connection terminal 8a and the wirings 8b and 8c are arranged on the left and right sides of the sealing portion 6a in an exposed state.
- the distance from each antenna connection terminal 8a to the side surface (outer periphery) of the sealing portion 6a adjacent thereto is, for example, 0.1 mm or longer. It is designed to be.
- the antenna connection terminals 8a and the wirings 8b and 8c are formed by patterning gold on the exposed surface of a metal foil such as copper, for example.
- the wiring 8c is a part of the lead-out wiring for energization when a gold plating is applied to the exposed surfaces of the antenna connection terminal 8a and the wiring 8b by electrolytic plating.
- FIG. 7 shows an example of the mold surface from which the sealing portion 6a in FIG. 6 has been removed.
- FIG. 8 is a sectional view taken along the line Y1-Y1 in FIGS.
- FIG. 9 is a cross-sectional view taken along the line X 2 -X 2 in FIG.
- the sealing portion 6a is indicated by a broken line. The area indicated by the broken line is sealed by the sealing portion 6a.
- the IC chip 3 is mounted at the center of the mold surface of the wiring board 5 with its main surface (device forming surface) facing upward.
- the IC chip 3 has a semiconductor substrate made of, for example, silicon (Si) single crystal or the like, and has, on its main surface, a central processing unit, a ROM (Read Only Memory), a RAM (Random Access Memory), for example.
- An integrated circuit such as an EEPROM (Electrically Erasable Programmable ROM) and other arithmetic circuits, and a plurality of bonding pads 12 for extracting electrodes of the integrated circuit are formed.
- the ROM stores, for example, an execution program and an encryption algorithm.
- the RAM has, for example, a function as a memory for overnight processing.
- the above-described EEPROM has a function as a memory for storing data.
- a plurality of bonding holes 13 penetrating the upper and lower surfaces of the wiring board 5 are arranged on the left and right sides of the IC chip 3 at predetermined intervals along the vertical direction of FIG. A part of the back surface of the module terminal 4 is exposed from each of the bonding holes 13 and the exposed surface is plated with gold. That bondin One end of a bonding wire 14 made of, for example, a thin gold (Au) wire is joined to the module terminal 4 exposed from the hole 13. The other end of the bonding wire 14 is bonded to the bonding pad 12 of the IC chip 3. Thus, the predetermined bonding pad 12 of the IC chip 3 is electrically connected to the module terminal 4.
- the antenna connection terminal 8a is disposed further outside the row of the bonding holes 13.
- Each wiring 8 b formed integrally with each antenna connection terminal 8 a crosses the row of the bonding holes 13 in the region of the sealing portion 6 a toward the center of the wiring board 5.
- a wide portion 8d is formed integrally with the wiring 8b at a position in the middle of the extension of each wiring 8b (the position of the row of the bonding holes 13).
- One end of a bonding wire 14 is joined to the wide portion 8d.
- the other end of the bonding wire 14 is joined to the bonding pad 12 of the IC chip 3.
- the predetermined bonding pad 12 of the IC chip 3 is electrically connected to the wiring 8b.
- a wide connection terminal 8e is formed integrally with the wiring 8b at the end of each of the wirings 8b.
- the left and right wirings 8b and the connection terminals 8e are formed symmetrically.
- a capacitor C is electrically connected between the respective connection terminals 8 e so as to bridge the respective connection terminals 8 e.
- FIG. 10 shows a connection relationship between the capacitor C and the coil L for the antenna. Capacitor C is connected in parallel with coil L. The coil L and the capacitor C form a parallel resonance circuit.
- This parallel resonance circuit is a circuit section that forms the non-contact type interface of the IC card 1, and by providing this resonance circuit, the communication characteristics of the IC card 1 can be improved.
- the distance over which the IC card 1 can perform wireless communication can be increased, and the reliability of the wireless communication of the IC card 1 can be improved.
- the resonance frequency (that is, communication frequency) of this resonance circuit is, for example, 13.56 MHz.
- the communication distance can be set to, for example, about 0 to 70 cm.
- Fig. 11 is an enlarged cross-sectional view of the main part of the capacitor C (broken line X3-X3 in Fig. 7). Plan view).
- the capacitor C for example, a chip-type multilayer ceramic capacitor is used. That is, this capacitor C is electrically connected to the multi-layered electrodes 17a electrically connected to one connection terminal 16a of the capacitor C and the other connection terminal 16b of the capacitor C. And the multiple layers of electrodes 17 and are alternately stacked in the thickness direction of the capacitor C with the ceramic dielectric 18 interposed between the electrodes 17a and 17b. are doing.
- a relatively thin chip-type multilayer ceramic capacitor is used instead of a general-purpose chip-type multilayer ceramic capacitor due to a restriction on the height of the sealing portion 6a.
- the thickness of the capacitor C is, for example, about 250 / m.
- the accuracy of the resonance frequency of the resonance circuit can be improved.
- the capacitor C can be formed of a sheet-shaped capacitor, but in this case, the capacitance value varies, and the peak position of the resonance frequency may be shifted.
- ceramic capacitors have low stray capacitance, etc., and high accuracy of capacitance value.Because they are composed of ceramic and metal, they do not deteriorate much under high and low temperature environments and are extremely stable. By forming the capacitor C with a ceramic capacitor, a circuit design close to the theoretical value (resonance circuit design) becomes possible.
- the manufacturing process of the IC card 1 can be simplified. That is, when the capacitor C is formed of a sheet-like capacitor, the capacitance value varies widely, and trimming may be required. On the other hand, since the capacitance value of a ceramic capacitor is high and the trimming is not required, the production of the IC card 1 can be facilitated by forming the capacitor C with a ceramic capacitor, and the Shortening of manufacturing time and cost can be achieved.
- connection terminals 16a and 16b of the capacitor C are joined to the connection terminals 8e of the wiring board 5 by solder 20 and are electrically connected.
- a wiring board is basically unnecessary, and when a capacitor for a resonance circuit is provided, it is directly attached to the force body with low heat resistance (with the antenna coil provided in the force body). Direct connection), so high-temperature heat treatment cannot be performed, and the connection material between the capacitor for the resonance circuit and the coil for the antenna is generally a material that can be connected at a relatively low temperature, such as conductive resin paste.
- the present inventor has for the first time found that there is a problem that the value representing the amount of the signal that gives the bandwidth around the resonance frequency decreases, that is, the antenna sensitivity decreases, and the communication characteristics of the IC card deteriorate. I found it.
- the capacitor C since the capacitor C is mounted on the mold surface of the wiring board 5 made of a glass epoxy resin having relatively high heat resistance, the capacitor C is soldered with a high-temperature heat treatment. Can be connected by 0.
- the resistance between the capacitor C and the coil L can be reduced as compared to the conductive resin base, so that the loss of the resonance circuit can be reduced. .
- the Q value of the resonance circuit can be improved, and the sensitivity of the antenna can be improved.
- the communication characteristics of the IC chip 1 can be further improved. For this reason, for example, the distance over which the wireless communication of the IC device 1 can be performed can be made longer, and the reliability of the wireless communication of the IC device 1 can be further improved.
- solder 20 As the material of the solder 20, a material having a melting point higher than the temperature (for example, 180 degrees) at the time of the forming step (molding step) of the sealing portion 6a is selected. This is because in the first embodiment, the capacitor C is sealed with the sealing portion 6a, so that the solder 20 is not melted during the molding process.
- Specific solder 20 materials include, for example, lead (Pb) -tin (Sn) solder, tin-silver (Ag), tin-silver-copper, tin-silver-copper A so-called lead-free solder such as bismuth (B i), tin-bismuth, tin-copper or tin-zinc (Zn) can be used.
- the capacitor C as described above is sealed by the sealing portion 6a in the same manner as the IC chip 3 and the bonding wires 14 and the like.
- the capacitor C and the solder connection portion thereof can be protected from the outside by sealing the capacitor C with the sealing portion 6a, for example, weather resistance and moisture resistance can be reduced.
- the resistance of the solder connection portion to mechanical fatigue caused by bending of the IC card 1 and the like can be improved, so that peeling of the capacitor C can be suppressed or prevented. Therefore, the life of the IC card 1 can be improved.
- FIG. 12 is an overall plan view of the mold surface shown by removing the IC chip 3 and the capacitor C from FIG. 7 described above.
- FIG. 13 shows the arrangement of the antenna connection terminal 8a of the IC module 2 according to the first embodiment and the connection between the antenna connection terminal 8a and the coil L.
- FIG. 14 shows another arrangement of the antenna connection terminal 8a studied by the present inventors for comparison.
- two antenna connection terminals 8a are not arranged on the same side of the IC chip 3 and are different from the IC chip 3. It is arranged on the side.
- the two antenna connection terminals 8a are arranged on both left and right sides of the IC chip 3 so as to be symmetrical with respect to the IC chip 3, that is, in an opposite relationship to each other. Have been. If the two antenna connection terminals 8a are arranged on the same side of the IC chip 3 as shown in Fig. 14, the IC chip will be connected between the two antenna connection terminals 8a and from the two antenna connection terminals 8a. As a result of the formation of the stray capacitance C s between adjacent wirings 8 b extending to the third side or adjacent to the wiring forming the coil L for the antenna, the capacitance value of the capacitor forming the resonance circuit is designed. Value.
- the antenna connection terminals 8a are arranged on different sides of the IC chip 3 and are separated from each other, so that the stray capacitance C Since s can be hardly formed, the capacitance value of the capacitor C of the resonance circuit can be set to a value close to the design value.
- the layout of the antenna connection terminal 8a for connecting the coil L, the connection terminal 8e for mounting the capacitor C, and the bonding holes 13 can be increased. can do.
- the wiring board base is the base of the wiring board 5.
- FIG. 16 shows an example of a plan view of a main part of the wiring board matrix 5M.
- the wiring substrate matrix 5M is made of, for example, a tape-like thin glass epoxy resin.
- a plurality of sprocket holes 22 are regularly arranged near both ends in the short direction of the wiring substrate matrix 5M along the longitudinal direction of the wiring substrate matrix 5M.
- the sprocket hole 22 is a feed hole for feeding the tape-shaped wiring board base 5M to the tape.
- each unit area U R is an area for obtaining the wiring board 5 of one IC module 2.
- FIG. 17 shows an example of an enlarged plan view of a main part of a contact surface of the wiring board base 5M
- FIG. 18 shows an example of an enlarged plan view of a main part of a mold surface of the wiring board base 5M.
- four unit areas UR are illustrated.
- the module terminal 4 has already been formed in each unit region UR on the contact surface of the wiring substrate 5M.
- the wiring 23 is physically connected to the module terminal 4 at this stage.
- the wiring 23 has a function as a lead wiring for energization at the time of plating. Module terminal 4 and wiring 23 are simultaneously patterned. Also, as shown in FIG.
- each unit area UI on the mold surface of the wiring board base 5M has already been connected to the antenna connection terminal 8a, the wiring 8b, 8c, the wide area 8d, and the connection terminal 8e.
- -It is formed physically. Since the antenna connection terminal 8a, the wirings 8b and 8c, the wide area 8d, and the connection terminal 8e are also formed at the same time, the IC card 1 can be manufactured without increasing the cost.
- Such a wiring substrate matrix 5M is carried into an assembling apparatus in a state wound on a reel.
- FIG. 19 shows an example of an assembling apparatus 25 used in this step.
- the mounting process of the capacitor C is performed until the wiring substrate matrix 5M of the first reel 26a is sent to the second reel 26b (reel 'toe' reel connection).
- the solder 20 in the paste state is applied to the connection terminals 8e on the mold surface of the wiring substrate mother 5M.
- the solder 20 is made of the above-mentioned material, and uses a solder having a small flux.
- the 5 M portion of the wiring board matrix on which the solder application has been completed is sent to the chip mounting section 25 b of the assembling apparatus 25.
- the chip mounting portion 25b after aligning the connection terminal of the capacitor C sucked by the vacuum suction pad or the like with the connection terminal 8e of the wiring substrate 5M, press the capacitor C against the connection terminal 8e to temporarily Connecting.
- the 5 M portion of the wiring board matrix on which the chip mounting process has been completed is sent to the reflow heating section 25 c of the assembling apparatus 25.
- the solder 20 is melted by a heat treatment, and the connection terminal of the capacitor 20 and the connection terminal 8e of the wiring board base 5M are fixed and electrically connected.
- the reflow heating section 25c is provided with a shirt to shut off the heat of the reflow furnace. This makes it possible to adjust the amount of heating by closing the shirt at the stop and go stop when a trouble occurs. For example, when the capacitor C is mounted, the tape feed is temporarily stopped (ST0P), and after the process of mounting the capacitor C, the tape feed operation is performed again (GO). Say the action.
- FIG. 20 is an enlarged plan view of a main part of the mold surface of the wiring substrate matrix 5M after the above steps. A capacitor C is mounted between adjacent connection terminals 8e, 8e of each unit area UR. In the first embodiment, since the capacitor C is mounted on the wiring board base 5 M made of a glass epoxy resin film having high heat resistance, connection using the solder 20 becomes possible.
- an electrical characteristic inspection connection state and capacitance value measurement, etc.
- an appearance inspection of the capacitor C can be performed.
- the wiring (wiring 8c, etc.) of the wiring board base 5M is routed so that electrical inspection can be performed.
- the electrical characteristics inspection and the appearance inspection of the capacitor C can be performed in the integrated line on which the capacitor is mounted by the feeding operation of the tape-shaped wiring board base 5M. In this case, workability and efficiency are higher than when the above inspection is performed outside the integrated line. Can be improved and product management can be facilitated. Therefore,
- the ease of assembling the IC card 1 can be greatly improved. Also, the assembling time of the IC card 1 can be significantly reduced. Further, by performing the above-described inspection at the beginning of the above-mentioned integrated line, it is possible to grasp and sort out the characteristic failure and connection failure of the capacitor C in advance, so that the failure related to the capacitor C does not reach the IC card 1. In other words, it is possible to prevent a defective IC chip from becoming defective due to a defective capacitor C. Therefore, the yield of the IC card 1 can be improved, and the cost of the IC card 1 can be reduced.
- FIG. 21 shows an example of an assembling apparatus 27 used in this step. The process here is performed until the wiring board base 5M of the second reel 26b is sent to the third reel 26c (reel 'toe' reel connection).
- the IC chip mounting area on the mold surface of the wiring substrate mother 5M is applied using an epoxy adhesive or the like.
- the chip mounting portion 27 b of the assembling device 27 the IC chip 3 sucked by the vacuum suction pad or the like is aligned, and then pressed against the wiring board base 5 M to temporarily connect.
- the adhesive is melted by heat treatment, and the IC chip 3 is firmly fixed to the mold surface of the wiring substrate base 5 M (COT (Chip On Tape) , CB 2) in FIG.
- FIG. 22 is an enlarged plan view of a main part of the mold surface of the wiring substrate matrix 5M after the wire bonding step. Each unit area The bonding pad 12 of the IC chip 3 is electrically connected to the module terminal 4 and the wide area 8d by the bonding wire 14 (step WB in FIG. 15).
- the sealing parts 6 a of the plurality of unit regions UR are collectively formed by the transfer molding method. That is, the mold surface and the contact surface of each of the plurality of unit regions UR of the wiring board base 5M are sandwiched between the lower mold 27 e1 and the upper mold 27 e2 of the mold.
- a plurality of sealing portions 6a are collectively formed on the mold surface by, for example, pouring a glass epoxy resin into the mold cavity 27 e3.
- the temperature during the sealing step is, for example, about 180 degrees at maximum.
- the solder 20 and the like having a melting point higher than the temperature at the time of the sealing step are used, the solder 20 is not melted by the sealing step.
- the position of the injection port (gate) for pouring the sealing resin into the cavity 27 e 3 in the mold, the position of the capacitor C on the wiring substrate base 5M, and Are separated from each other. That is, if the capacitor C is located near the injection port, the resin melted during the molding process may hit the capacitor C, and a void may be generated due to entrainment. Therefore, in the first embodiment, by separating the position of the injection port from the capacitor C, it is possible to suppress or prevent the occurrence of voids in the sealing portion 6a.
- FIG. 23 is an enlarged plan view of a main part of the mold surface of the wiring substrate matrix 5M after the wire bonding step.
- the IC chip 3, the capacitor C, the bonding wires 14, the bonding holes 13 and the like in each unit area UR are covered with the sealing portion 6a.
- the antenna connection terminal 8a is exposed from the sealing portion 6a (step PKG in FIG. 15) o
- each of the IC modules 2 is cut out from the wiring board base 5M (step CUT in FIG. 15). Thereafter, the cut-out IC module 2 is fitted into the recess 7 a of the card body 7. At this time, the antenna connection terminal 8a of the IC module 2 and the coil L in the card body 7 are joined with an adhesive material that can be joined at a relatively low temperature, such as a conductive resin paste containing silver (FIG. 1). Step 5 MB). in this way To manufacture the IC card 1.
- the capacitor C In the manufacturing process of an IC card 1 having a capacitor C for a resonance circuit forming a general non-contact type interface, the capacitor C must be mounted on each of the force bodies 7 one by one. Therefore, the manufacturing process is complicated and the cost is increased.
- the capacitor C is mounted in the flow using the tape-shaped wiring substrate matrix 5M, and the capacitor C is incorporated into the IC module 2 during the manufacturing process. When the IC module 2 is attached to the card body 7, the capacitor C is also incorporated into the entire circuit of the IC card 1. For this reason, according to the first embodiment, it is possible to easily assemble the IC card 1 having the capacitor C for the resonance circuit forming the non-contact type interface. In addition, the cost of the IC card 1 can be reduced.
- FIG. 24 shows an example of a plan view of the molding surface of the wiring board 5 during the manufacturing process of the IC card 1 according to the second embodiment.
- the shape of the sealing portion is different from that of the sealing portion 6a of the first embodiment, and the connection region (the connection terminal 8) of the capacitor for the resonance circuit extends from the sealing portion 6b. e) is exposed.
- FIG. 25 is a plan view of the mold surface of the wiring board 5 after mounting the capacitor C in FIG. FIG. 25 is the same as FIG. 7 except that the inside of the sealing portion 6b is removed.
- the capacitor C is mounted outside the sealing portion 6b.
- the capacitor C is mounted after the step of forming the sealing portion 6b.
- the mounting may be performed in the state of the wiring board matrix 5M as in the first embodiment, or may be performed after the individual wiring boards 5 are cut out from the wiring board matrix 5M. Otherwise, it is the same as the first embodiment.
- the material and the forming process of the sealing portion 6b are the same as those of the sealing portion 6a, and therefore, the description is omitted.
- the following effects can be obtained in addition to the effects obtained in the first embodiment.
- the capacitor C by allowing the capacitor C to be mounted after the sealing process, the specifications of the coil L of the card body 7 of the IC card 1 If the value changes or the tuning value on the reader / writer side deviates due to the change of the capacitor, the capacitor C with the optimum capacitance value can be mounted according to the value of the coil L or the reader / writer. . Therefore, the resonance frequency of the non-contact type interface of the IC card 1 can be set to an optimum value. Also, by mounting the capacitor C outside the sealing portion 6b, the degree of freedom in selecting the material of the solder 20 can be improved because the solder 20 is not affected by the sealing temperature. . Furthermore, since the wiring substrate matrix 5M or the wiring substrate 5 which has been completed up to the step of forming the sealing portion 6b can be prepared and stored, the manufacturing time of the IC card 1 can be greatly reduced.
- the configuration is such that the shape of the sealing portion 6a of the IC card 1 is the same as that of the first embodiment, and the capacitor C for the resonance circuit can be mounted after the sealing step. An example will be described.
- FIG. 26 shows an example of a plan view of the mold surface of the wiring substrate 5 (wiring substrate base 5M) during the manufacturing process of the IC card 1 of the third embodiment.
- the sealing portion 6a is the same as that of the first embodiment, but the mounting area (connection terminal 8e) of the capacitor C is disposed outside the sealing portion 6a.
- the end of each wiring 8b of the wiring board 5 extends outside the region of the sealing portion 6a, and the connection terminal 8e is physically connected to the end of the wiring 8b. Is formed.
- FIG. 27 is a plan view of the entire mold surface after the capacitor C is mounted on the wiring board 5 of FIG. Also in the third embodiment, the capacitor C is mounted outside the sealing portion 6a. Also, in the manufacturing process of the IC card 1, the capacitor C is mounted after the process of forming the sealing portion 6a.
- the mounting step of the capacitor C may be performed in the state of the wiring board matrix 5M as in the first embodiment, or may be performed after the individual wiring boards 5 are cut out from the wiring board matrix 5M. . Otherwise, the configuration is the same as that of the first embodiment.
- the following effects can be obtained in addition to the effects obtained in the first and second embodiments. That is, there is no need to change the molds (the lower mold 27 e1 and the upper mold 27 e 2) of the mold part 27 e, Part 27 e can be used as is.
- FIG. 28 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) of the IC card 1 according to the fourth embodiment.
- Fig. 29 is a plan view of the mold surface of the wiring board 5 (wiring board matrix 5M) after mounting the IC chip 3 and the capacitor C1 (C) for the resonance circuit in Fig. 28 and passing through the wire bonding process. An example is shown.
- FIG. 30 shows an example of a plan view of the mold surface of the wiring substrate 5 (wiring substrate base 5M) after forming the sealing portion 6a in FIG.
- This capacitor C1 is mounted in the region of the sealing portion 6a.
- no capacitor is mounted on the connection terminal 8e2 outside the sealing portion 6a.
- it can be used as IC module 2.
- a capacitor for adjustment is mounted on the connection terminal 8e2 outside the sealing portion 6a.
- FIG. 31 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board matrix 5M) after mounting the resonance circuit capacitor C 2 (C) in FIG.
- the capacitor C2 is mounted outside the sealing portion 6a, and is connected in parallel to the capacitor C1 in the sealing portion 6a.
- the capacitance value of the capacitor for the resonance circuit can be finely adjusted after the sealing step. Also, since the wiring substrate matrix 5 M or the wiring substrate 5 which has been completed up to the step of forming the sealing portion 6 a containing the capacitor C 1 for the resonance circuit can be prepared and stored, the manufacturing time of the IC card 1 is reduced. Significantly Can be shortened.
- FIGS. 32 and 33 show an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) of the IC card 1 of the fifth embodiment.
- FIG. 32 is the same as FIG. 29 except that the inside of the sealing portion 6b is removed.
- the mounting area for the two capacitors C1 and C2 for the resonance circuit is disposed outside the sealing portion 6b.
- FIG. 32 illustrates a case where only one capacitor C 1 is mounted. At this stage, it may be used as IC module 2.
- FIG. 33 illustrates a case where two capacitors C 1 and C 2 are mounted.
- the capacitors CI and C2 may be mounted in the state of the wiring board base 5M as in the first to fourth embodiments, or may be mounted on the wiring board 5 cut out from the wiring board base 5M. May be.
- the fifth embodiment it is possible to obtain the same effects as those obtained in the first, second, third, and fourth embodiments (excluding the effect that the current mold can be used).
- the invention made by the inventor has been specifically described based on the embodiment.
- the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
- the wiring substrate is not limited to the glass epoxy resin, and for example, a polyimide resin having higher flexibility than the glass epoxy resin may be used.
- the present invention is not limited to this. Applicable to one domain.
- General non-contact IC force In this embodiment, the wiring board is not used. However, in the case of the present embodiment, the wiring board is incorporated in the force main body in the same manner as in the first to fifth embodiments. However, the module terminals 4 are not formed on the exposed surface of the wiring board in this case.
- the non-contact type face provided in the card body includes: a coil having a function as an antenna; and a capacitor connected in parallel to the coil to form a resonance circuit.
- the semiconductor device includes, for example, a credit card, a cash card, a card for an ETC (Electronic Toll Collection system), a commuter pass, a card for a public phone, a card for a mobile phone or an authentication card. It is suitable for use in IC (Integrated Circuit) cards that are being used in various fields such as transportation, communication, distribution, and authentication.
- ETC Electronic Toll Collection system
- a commuter pass a card for a public phone
- a card for a mobile phone or an authentication card.
- IC Integrated Circuit
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Credit Cards Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/006829 WO2004107263A1 (ja) | 2003-05-30 | 2003-05-30 | 半導体装置およびその製造方法 |
AU2003241968A AU2003241968A1 (en) | 2003-05-30 | 2003-05-30 | Semiconductor device and its manufacturing method |
JP2005500224A JP4471926B2 (ja) | 2003-05-30 | 2003-05-30 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/006829 WO2004107263A1 (ja) | 2003-05-30 | 2003-05-30 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004107263A1 true WO2004107263A1 (ja) | 2004-12-09 |
Family
ID=33485796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/006829 WO2004107263A1 (ja) | 2003-05-30 | 2003-05-30 | 半導体装置およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP4471926B2 (ja) |
AU (1) | AU2003241968A1 (ja) |
WO (1) | WO2004107263A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3024000A1 (fr) * | 2014-07-15 | 2016-01-22 | Oberthur Technologies | Entite electronique rfid a condensateur rapporte |
FR3047101A1 (fr) * | 2016-01-26 | 2017-07-28 | Linxens Holding | Procede de fabrication d’un module de carte a puce et d’une carte a puce |
JP2018011052A (ja) * | 2016-07-13 | 2018-01-18 | ゼネラル・エレクトリック・カンパニイ | 埋め込み型ドライフィルムバッテリーモジュールおよびその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09275184A (ja) * | 1995-06-29 | 1997-10-21 | Hitachi Maxell Ltd | 情報担体及びその製造方法 |
JP2000182017A (ja) * | 1998-12-18 | 2000-06-30 | Dainippon Printing Co Ltd | 接触型非接触型共用icカードおよびその製造方法 |
JP2001118043A (ja) * | 1999-10-18 | 2001-04-27 | Denso Corp | Idタグの製造方法 |
JP2002207982A (ja) * | 2001-01-10 | 2002-07-26 | Dainippon Printing Co Ltd | 接触非接触両用icモジュール及びicカード |
JP2003067695A (ja) * | 2001-08-28 | 2003-03-07 | Sharp Corp | 半導体装置 |
-
2003
- 2003-05-30 AU AU2003241968A patent/AU2003241968A1/en not_active Abandoned
- 2003-05-30 WO PCT/JP2003/006829 patent/WO2004107263A1/ja active Application Filing
- 2003-05-30 JP JP2005500224A patent/JP4471926B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09275184A (ja) * | 1995-06-29 | 1997-10-21 | Hitachi Maxell Ltd | 情報担体及びその製造方法 |
JP2000182017A (ja) * | 1998-12-18 | 2000-06-30 | Dainippon Printing Co Ltd | 接触型非接触型共用icカードおよびその製造方法 |
JP2001118043A (ja) * | 1999-10-18 | 2001-04-27 | Denso Corp | Idタグの製造方法 |
JP2002207982A (ja) * | 2001-01-10 | 2002-07-26 | Dainippon Printing Co Ltd | 接触非接触両用icモジュール及びicカード |
JP2003067695A (ja) * | 2001-08-28 | 2003-03-07 | Sharp Corp | 半導体装置 |
Non-Patent Citations (1)
Title |
---|
NIPPON MICROELECTRONICS KYOKAI: "IC-ka jisso gijutsu", KOGYO CHOSAKAI PUBLISHING CO., 20 February 1984 (1984-02-20), pages 107 - 113, XP002983062 * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3024000A1 (fr) * | 2014-07-15 | 2016-01-22 | Oberthur Technologies | Entite electronique rfid a condensateur rapporte |
FR3047101A1 (fr) * | 2016-01-26 | 2017-07-28 | Linxens Holding | Procede de fabrication d’un module de carte a puce et d’une carte a puce |
WO2017129904A1 (fr) * | 2016-01-26 | 2017-08-03 | Linxens Holding | Procédé de fabrication d'un module de carte à puce et d'une carte à puce |
CN108496187A (zh) * | 2016-01-26 | 2018-09-04 | 兰克森控股公司 | 用于制造芯片卡模块的方法和芯片卡 |
US10706346B2 (en) | 2016-01-26 | 2020-07-07 | Linxens Holding | Method for manufacturing a smart card module and a smart card |
CN108496187B (zh) * | 2016-01-26 | 2021-12-28 | 兰克森控股公司 | 用于制造芯片卡模块的方法和芯片卡 |
JP2018011052A (ja) * | 2016-07-13 | 2018-01-18 | ゼネラル・エレクトリック・カンパニイ | 埋め込み型ドライフィルムバッテリーモジュールおよびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4471926B2 (ja) | 2010-06-02 |
AU2003241968A1 (en) | 2005-01-21 |
JPWO2004107263A1 (ja) | 2006-07-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8011589B2 (en) | Wireless IC device and manufacturing method thereof | |
US6518885B1 (en) | Ultra-thin outline package for integrated circuit | |
AU690920B2 (en) | Multi-chip module | |
JP4656235B2 (ja) | アンテナ内蔵電子回路モジュールの製造方法 | |
US7924228B2 (en) | Storage medium with built-in antenna | |
US7528471B2 (en) | Integrated circuit incorporating wire bond inductance | |
US8546927B2 (en) | RFIC chip mounting structure | |
US6552694B1 (en) | Semiconductor device and fabrication method thereof | |
US20090130801A1 (en) | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same | |
US20050179121A1 (en) | IC module, and wireless information-storage medium and wireless information-transmitting/receiving apparatus including the IC wireless | |
US10467516B2 (en) | Component built-in device | |
WO2002013135A2 (en) | Structures and assembly methods for radio-frequency-identification modules | |
US20070018298A1 (en) | Optimized multi-apparation assembly | |
US7312528B2 (en) | Semiconductor device having antenna connection electrodes | |
JP6756805B2 (ja) | 相互接続領域を含む片面電子モジュールの作成方法 | |
JP4829956B2 (ja) | 半導体装置 | |
JPWO2007057954A1 (ja) | 半導体装置及びその製造方法 | |
JP4471926B2 (ja) | 半導体装置 | |
CN111626395A (zh) | 一种双界面安全芯片卡及制作方法 | |
JP2004355442A (ja) | 非接触データキャリア | |
JP2002207982A (ja) | 接触非接触両用icモジュール及びicカード | |
JP6913622B2 (ja) | Rfidタグ用基板、rfidタグおよびrfidシステム | |
KR101113839B1 (ko) | 반도체칩 및 상기 반도체칩의 제조방법 | |
JP2022164692A (ja) | Rfidタグ用基板、rfidタグおよびrfidシステム | |
JPH11145371A (ja) | 半導体集積回路装置用リードフレーム、および半導体集積回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2005500224 Country of ref document: JP |
|
122 | Ep: pct application non-entry in european phase |