WO2004088750A1 - ラティラルバイポーラcmos集積回路 - Google Patents
ラティラルバイポーラcmos集積回路 Download PDFInfo
- Publication number
- WO2004088750A1 WO2004088750A1 PCT/JP2004/003208 JP2004003208W WO2004088750A1 WO 2004088750 A1 WO2004088750 A1 WO 2004088750A1 JP 2004003208 W JP2004003208 W JP 2004003208W WO 2004088750 A1 WO2004088750 A1 WO 2004088750A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- mos transistor
- terminal
- channel mos
- current
- channel
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000004088 simulation Methods 0.000 description 23
- 238000010586 diagram Methods 0.000 description 17
- 230000003321 amplification Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
Definitions
- the present invention relates to a CMOS integrated circuit, and more particularly, to a lateral bipolar CMOS integrated circuit that operates in a mixed mode with a four-terminal MOS transistor and a lateral bipolar transistor included therein.
- CMOS integrated circuits have the characteristic that the power consumption density hardly increases even if the degree of integration is increased.However, as the degree of integration increases, the amount of current increases due to the carrier speed saturation effect even if the channel length is further shortened. However, the current driving force could not be increased, and when the integration degree of the CMOS integrated circuit increased, the RC load and the fan-out capacity load increased. For this reason, a CMOS integrated circuit that does not increase the amount of current even if the channel length is shortened could not cope with the increase in load due to such integration, and a device with a larger current drivability was required.
- DTMOS Dynamic
- Threshold Voltage MOS Threshold Voltage MOS transistors
- DTMOS Dynamic Threshold Voltage MOSFET
- DTMOS transistors have the following problems. That is, if (13 is set to 0.7 V or more, the exponential Since the counter current flows, the operation is abnormal and cannot be used. Even if Vdd is set to 0.7V, large power is consumed. Further, when Vdd is set to 0.7 V or less, the current driving force is reduced, and a non-negligible forward current flows.
- An object of the present invention is to provide a CMOS integrated circuit that can operate at high speed and has low energy.
- the present invention provides an inverter circuit including an n-channel MOS transistor and a p-channel MOS transistor, wherein a gate input connected to the gates of the n-channel MOS transistor and the p-channel MOS transistor is provided.
- n-type base terminals connected to the n-type substrate of the p-channel MOS transistor.
- the n-channel MOS transistor operates in the operation mode of the MOS transistor and the n-channel.
- the transistor operates in a mixed mode with the operation mode of the npn lateral bipolar transistor inherent in the MOS transistor, and the p-channel MOS transistor ,
- the conventional three-terminal DTMOS has the problem that the power consumption is large and ⁇ (1 cannot be used at 0.7 V or more, but it is extremely fast due to the current driving force of the lateral 'bipolar transistor operation.
- the present invention is a hybrid of a MOS transistor based on SOI and a lateral bipolar transistor, which is inherent in the structure, from the standpoint of utilizing the driving force. An integrated circuit to be handled as a terminal element is provided.
- the inverter circuit may include the gate input terminal Vin, the p-type base terminal, and the n-type base terminal as input terminals, the output terminal Vout as an output terminal, and the gate input terminal V high or low level input to in
- the present invention is also a lateral bipolar CMOS integrated circuit, which is an inverter circuit that outputs a voltage from an output terminal Vout as a voltage of an inverted level.
- the current of I bn is maintained at 0 while the input voltage to the gate input terminal Vin is substantially constant, and the input voltage to the gate input terminal Vin is switched from a low level to a high level.
- a forward pulse current flows from the current source Ibp to the p-type base terminal in synchronization with the switching, and the input voltage to the gate input terminal Vin switches from a high level to a low level.
- a Rati Lal bipolar CM_ ⁇ S integrated circuit characterized in that flow forward pulse current to the n-type base Ichisu terminal from the current source I bn in synchronism with the switching.
- the present invention includes a voltage source Vdd and a ground source Gnd, wherein the current source Ibp is a bull-up p-channel MOS transistor including a source terminal, a drain terminal and a substrate terminal, wherein the drain terminal is The source terminal and the substrate terminal are connected to the voltage source Vdd. The source terminal and the substrate terminal are connected to the voltage source Vdd. The current source lbn is connected to the source terminal.
- a pull-down n-channel MOS transistor including a drain terminal and a substrate terminal, wherein the drain terminal is connected to the n-type base terminal, and the source terminal and the substrate terminal are connected to the ground source Gnd.
- a lateral bipolar CM ⁇ S integrated circuit comprising a pull-down n-channel MOS transistor.
- the present invention uses an inverter circuit including the n-channel MOS transistor and the above-described p-channel MOS transistor as a CMOS standard cell in the operation mode of the MOS transistor, and supplies an output of the CM0S standard cell. It is also a lateral bipolar CMOS integrated circuit characterized in that it is used in the hybrid mode when a large load is connected.
- the lateral bipolar CMOS integrated circuit has a four-terminal n-channel and p-channel MOS transistor, By operating the lateral bipolar transistor of npn and pnp, which are structurally inherent in each of them, in a hybrid mode, high-speed charging and discharging is performed only during switching of the inverter circuit, and high-speed operation is possible and low energy Lateral bipolar CMOS integrated circuit can be realized.
- FIG. 1 is a schematic cross-sectional view of a lateral bipolar CMOS device according to the present embodiment.
- FIG. 2 is an equivalent circuit diagram of the lateral bipolar CMOS inverter circuit (LBCMOS) according to the embodiment.
- FIG. 3 is an equivalent circuit diagram of the n-channel MOS transistor.
- FIG. 5 is a layout diagram of the LB CMOS according to the present embodiment.
- FIG. 6 shows the waveforms of the input voltage and the current supplied from Ibp and Ibn.
- FIG. 7 shows a lateral bipolar CMOS inverter circuit according to the present embodiment.
- FIG. 4 is an equivalent circuit diagram of (LBCMOS).
- FIG. 8 is a layout diagram of the LBCMOS according to the present embodiment.
- FIG. 9 shows the waveforms of the input voltage and the gate voltages Vp and Vn.
- FIG. 10 is an equivalent circuit diagram of a conventional DTMOS according to a comparative example.
- FIG. 11 is an equivalent circuit diagram of the n-channel DTMOS.
- FIG. 12 is an equivalent circuit diagram of a p-channel DTMOS.
- FIG. 13 shows a pulse waveform of the input voltage.
- FIG. 14 shows the current I ds -voltage Vds characteristics of the n-channel DTMOS when Vgs is changed.
- FIG. 15 shows the current I Ids I-I voltage I Vds 1 characteristics of the p-channel DTMOS when I Vgs i is changed.
- Figure 16 shows the DT CMOS delay and power consumption.
- Figure 17 shows the energy and energy delay product of DT CMOS.
- FIG. 20 shows the current I Ids
- 0.7 V and I V g s
- Vds 1 1. 0 V is fixed.
- Figure 22 compares the delay and power consumption of the LB CMOS inverter circuit with CMOS and DT CMOS.
- Figure 23 compares the energy and energy delay product of the LB CMOS inverter circuit with those of CM ⁇ S and DT CMOS.
- Figure 24 compares the delay and power consumption of the LB CMOS inverter circuit with CMOS.
- Figure 25 compares the energy and energy delay product of the LB CMOS inverter circuit with that of CMOS.
- Figure 26 shows the delay and power consumption of the LB CMOS inverter circuit.
- Figure 27 shows the energy and energy delay product of the LB CMOS inverter circuit.
- Figure 28 shows the delay and power consumption of the LB CMOS inverter circuit.
- Figure 29 shows the energy and energy delay product of the LB CMOS inverter circuit.
- Figure 30 shows the delay and power consumption of the LBCMOS inverter circuit.
- Figure 31 shows the energy and energy delay product of the LB CMOS inverter.
- Figure 32 shows the delay and power consumption of the LBCMOS inverter circuit.
- Fig. 33 shows the energy and energy delay products of the LB CMOS inverter circuit.
- Figure 35 shows the energy and energy delay product of the LBCMOS inverter circuit.
- FIG. 1 is a schematic diagram of a cross section of a lateral bipolar CMOS (Lateral Bipolar CMOS) inverter circuit (hereinafter, referred to as “: LBCM0 S”) according to the present embodiment, which is entirely represented by 100.
- LBCM0 S lateral bipolar CMOS inverter circuit
- the LBCMOS 100 includes the silicon substrate 1.
- An n-channel MOS transistor 10 and a p-channel MOS transistor 20 are provided on a silicon substrate 1 via a buried oxide film 2 of silicon oxide.
- the n-channel M ⁇ S transistor 10 has a p-type substrate region 11 and n-type source regions 12 and n-type drain regions 13 provided on both sides thereof. These regions 11, 12, 13 are formed from silicon.
- the p-type substrate region 11 is designed to have a film thickness at which the partial depletion layer 14 is formed and an impurity concentration.
- a gate insulating film 1 made of silicon oxide is formed on the p-type substrate region 11.
- a gate electrode 16 made of polycrystalline silicon is provided through the gate electrode 5. By applying a voltage to the gate electrode 16, an n-channel (inversion layer) 17 is formed in the p-type substrate region 11.
- a p-channel MOS transistor 20 is provided on the buried oxide film 2.
- the p-channel MS transistor 20 has substantially the same structure as the n-channel MS transistor 10.
- On the buried oxide film 2 there are an n-type substrate region 21, a p-type source region 22 and a p-type drain region 23 sandwiching the n-type substrate region 21, and a gate insulating film 25 on the ⁇ -type substrate region 21.
- a gate electrode 26 is provided through the gate electrode.
- a partial depletion layer 24 is formed in the ⁇ -type substrate region 21, and a ⁇ channel 27 is formed by applying a voltage to the gate electrode 26.
- the n-channel MOS transistor 10 has a general MOS transistor structure, and has a p-type substrate region 11 other than the n-type source region 12 and the partial depletion layer 14, Type drain region 13 It is a lateral 'bipolar' transistor with npn structure.
- the n-channel MOS transistor 10 operates in a mode (hybrid mode) in which the operation mode of the MOS transistor and the operation mode of the bipolar transistor are mixed.
- hybrid mode the operation mode of the MOS transistor and the operation mode of the bipolar transistor are mixed.
- the p-channel MOS transistor 20 The details of the hybrid mode will be described later.
- FIG. 2 is an equivalent circuit diagram of the lateral bipolar CMOS inverter circuit (LBCMOS) according to the present embodiment, which is entirely represented by 200.
- LBCMOS lateral bipolar CMOS inverter circuit
- an n-channel MOS transistor 210 and a p-channel MOS transistor 220 are connected so as to form a CM-inverted S-inverted structure. That is, the gates and drains of both transistors 210 and 220 are connected to the input terminal Vin and the output terminal Vout, respectively.
- the source of the p-channel MOS transistor 220 is connected to the voltage source Vdd
- the source of the n-channel MOS transistor 210 is connected to the ground source Gnd.
- FIG. 5 is a layout diagram of the LBCMOS 200.
- Fig. 5 the input terminals of the current sources Ibp ⁇ Ibn are shown by substrate contacts, and the separation between n- and p-wells is assumed to be 6 mm.
- FIG. 6 shows the waveforms of the input voltage to the input terminal Vin and the current supplied from the current sources Ibp and Ibn when the LBCMOS is operated in the hybrid mode.
- the current source I bp synchronizes with the trapezoidal current pulse having the maximum current value of Imax.
- the current By flowing the current as a source current, a large collector current can be extracted from the npn lateral 'bipolar transistor, and the switching speed of the n-channel MOS can be accelerated.
- the base (n) .emitter (source) junction of the pnp lateral 'bipolar' transistor does not conduct current as zero bias.
- the current source I bn that supplies a forward current to the n-type substrate (base) terminal of the pnp lateral 'bipolar' transistor is used when the input voltage of the inverter circuit switches from a high level to a low level ( The switching time is synchronized only with 15 Ops), and a trapezoidal current pulse with a maximum current of Imax flows as the base current. This makes it possible to draw out a large collector current and accelerate the switching speed of the p-channel MOS during pnp lateral / bipolar / transistor operation. On the other hand, at such a timing, the base (p) 'emitter / source (source) junction of the npn lateral bipolar transistor becomes zero bias. And do not pass current.
- the base-emitter junction of both lateral bipolar transistors is used. Is applied to zero bias, and no base current flows in either case.
- the LBCMOS even if one of the transistors constituting the inverter circuit is in the ON state and operates at high speed, power consumption increases.
- the other transistor does not consume power in the off state.
- the increase in power consumption is more than the decrease in delay, so that the energy required for the operation of the entire LBCMOS can be reduced.
- the switching time (rise and fall) of the input voltage to the input terminal Vin is set to 150 ps, respectively, which is adopted from the circuit simulation waveform of the ring oscillator with the minimum length of the drain. Value.
- FIG. 7 is an equivalent circuit diagram of a lateral bipolar CMOS (LBCMOS) inverter circuit according to the present embodiment, which is represented by 300 in its entirety.
- LBCMOS lateral bipolar CMOS
- n-channel MOS transistor 310 and a p-channel MOS transistor 320 are connected to form a CMOS structure.
- the substrate (base) terminals of the two MOS transistors 310 and 320 constituting the inverter circuit are controlled.
- a forward current is applied to one of them. That is, as described later, when a forward current is applied to one substrate (base) terminal, control is performed so that no forward current is applied to the other substrate (base) terminal.
- FIG. 8 is a layout of such an LB CMOS 300.
- FIG. 9 shows the input voltage to the input terminal V in and the pulse waveforms of the gate voltages Vp and Vn of the two current sources when the LB CMOS 300 is operated in the hybrid mode.
- the input voltage to the input terminal V in switches from a low level (Gnd potential) to a high level (Vdd).
- the time required for switching (rising) is 150 ps.
- the gate voltage Vp of the MOS transistor 330 changes from the high level (Vdd) to the low level (Gnd), and after a lapse of a certain time (T1), the original high level (Vd Apply a trapezoidal pulse voltage returning to d). Accordingly, a substantially trapezoidal pulse current corresponding to the trapezoidal wave flows to the drain terminal of the MOS transistor 330.
- Such a pulse current becomes a base current of the npn lateral bipolar transistor included in the n-channel MOS transistor 310, draws a large collector current, and accelerates the switching speed of the n-channel MOS transistor 310.
- the gate voltage Vn of the MOS transistor 340 is maintained at a low level, and control is performed so that the transistor is turned off. As a result, no base current flows through the p-channel MOS transistor 320, and the p-channel MOS transistor 320 is kept off.
- the gate voltage Vn of the MOS transistor 340 is synchronized with the switching.
- the trapezoid changes from low level (Gnd) to high level (Vdd) and returns to the original low level (Gnd) after a certain time (Th) + Change.
- a substantially trapezoidal pulse current corresponding to the pulse voltage flows to the drain terminal of the MOS transistor 340.
- Such a pulse current becomes a base current of a pnp lateral bipolar transistor included in the n-channel MOS transistor 320, draws a large collector current, and accelerates the switching speed of the p-channel MOS transistor 320.
- the gate voltage Vp of the MOS transistor 330 is maintained at a high level, and control is performed so that the transistor is turned off. As a result, the base current does not flow through the n-channel MOS transistor 310, and is kept off.
- the inverter circuit when the inverter circuit is in a steady state, that is, when the input voltage is substantially constant at a high level or a low level, the base-emitter junction of both lateral 'bipolar' transistors is zero-biased. Is applied and no pace current flows.
- the LBCMOS 300 as in the case of the LBCMOS 200, one of the transistors constituting the inverter circuit is on, and even if the transistor operates at high speed and power consumption increases, the other transistor remains off. Does not consume power. Furthermore, the increase in power consumption can be reduced by the amount of delay reduction, thereby reducing the energy required for the entire LBCMOS operation.
- the application of a positive input voltage to the gate terminal is equivalent to applying a forward voltage to the base-emitter junction of the structurally intrinsic npn bipolar transistor.
- a forward voltage to the base-emitter junction of the structurally intrinsic npn bipolar transistor.
- the voltage applied to this junction that is, the value of the gate voltage
- a base current flows through the npn bipolar transistor, and a large collector current multiplied by the current amplification factor flows.
- the voltage of the base-emitter junction is lower than the built-in voltage, and the voltage source V dd is also lower than the built-in voltage.
- the source terminal and the drain terminal are zero-biased, a forward voltage is applied to the substrate terminal (that is, a terminal that is both a base and a gate) even when the n-channel DTMOS 410 is not on. If this happens, a base current that cannot be ignored will flow. Therefore, power is consumed even in a steady state where switching of the DTCMOS 400 does not occur.
- FIG. 13 shows the waveform of the input voltage from the input terminal Vin when the DTCMOS 400 is operated.
- the rise time and the fall time are each set to 15 Ops, which is equivalent to the rise time (fall time) obtained from the circuit simulation result of the ring oscillator of the same size CMOS inverter.
- n-channel DTMOS 410 operating in the hybrid mode of the n-channel MOS and the npn bipolar transistor is confirmed by circuit simulation.
- a simulation using the following main parameters was performed with the BSIM3 v3 model based on a 0.35 m CMOS process.
- the forward base current increases exponentially, causing a discontinuity in the voltage-current relationship.
- V T0 (P) — 0.238 V
- FIG. 15 shows the relationship between the current I.sub.IdsI and the voltage I.sub.VdsI when
- I Vgs I I Vbe I
- the forward base current increases exponentially, and a large discontinuity in voltage and current is seen. .
- Figures 16 (a) and (b) show the delay of the DTCMO Simba overnight (meaning the average rise and fall delays of the output; the same applies hereinafter) when the load capacitance and Vdd are changed, and Indicates power consumption.
- FIGS. 17 (a) and 17 (b) show the energy and energy delay product of the DT CMOS inverter when the load capacitance and Vdd are similarly varied. Energy can be approximated by power consumption X delay time, but the energy increases significantly when Vdd> 0.7 V because the increase in power consumption outweighs the decrease in delay time.
- the value obtained by multiplying this energy again by the delay is the energy delay product.
- the energy delay product is minimized by the coordinates shown in Fig. 17 (b) as (0.6, 0) ⁇ ( 0. 65, 25) (0, 7, 50) ⁇ (0, 7, 75) ⁇ (0, 7, 10 0).
- the current on the vertical axis is represented by a logarithm, and it can be seen that the current increases rapidly.
- FIG. 21 shows the relationship between the current I Ids I and the voltage I Vgs I when
- 0.7 V and
- 1.0 V.
- the current on the vertical axis is represented by a logarithm, and it can be seen that the current is increasing rapidly.
- Table 1 shows the results of such a circuit simulation.
- Table 1 a comparison was made of the delay time, power consumption, energy, and energy delay product of the ordinary CMO S ⁇ and the DTCM ⁇ S described in the above comparative example, and the LBCMOS according to the present invention.
- CMOS / LBCM ⁇ S, DTCMOS / LBCMOS It shows the ratio of characteristic values obtained on a road.
- Tables 2 to 4 below the comparison items of the simulation results are the same.
- Vdd 0.7V
- CI 0.5534pF
- Imax 75 ⁇ A
- Th 1 OOps
- the LB CMOS inverter that operates in the hybrid mode according to the present invention consumes 18% more power than the ordinary CMOS.
- the delay is reduced to 1/64, so the operating speed is 64 times faster, and 1/55 for energy.
- the operating speed is 2.5 times, the power consumption is 1/60, and the energy is 1/153.
- the LBCMOS inverter circuit has the highest speed and the lowest energy among the three types of inverter circuits.
- Figures 22 (a) and (b) show the changes in delay and power consumption when the load capacitance C1 is changed from 0 to 100.
- FIGS. 23 (a) and 23 (b) show changes in energy and energy delay product when the load capacity C 1 is changed from 0 to 100. Other conditions are the same as those in Table 1.
- CMOS has a very large delay and DTMS uses large power consumption.
- Vdd 1.0V
- CI 0.5534pF
- Imax 75 ⁇ .
- A, T 100ps
- the LB CMOS inverter operating in the hybrid mode according to the present invention consumes 14% more power than the normal CMOS.
- the delay will be as small as 1 ⁇ 3 ⁇ ⁇ ⁇ , and the operating speed will be 31 times faster.
- the energy is 1/27.
- FIGS. 24 (a) and (b) ′ show changes in delay and power consumption when the load capacitance C1 is changed from 0 to 100.
- Figures 25 (a) and 25 (b) show the changes in energy and energy delay product when the load capacity C.1 ... is changed from 0 to 100.
- Other conditions are the same as in Table 2. .
- pull-up / pull-down MOS transistors are used as two types of current sources.
- the circuit simulation results when the used LBCMOS is operated in the hybrid mode are described.
- Table 3 shows the results of such a circuit simulation. Table 3 compares the delay time, power consumption, energy, and energy delay product of the ordinary CM.0S, the DTCMOS described in the above comparative example, and the LBCMOS according to the present invention. . CMO'S / LBCMOS and DTCMOS / LBCMOS indicate the ratio of characteristic values obtained by these circuits. .
- the LB CMOS inverter circuit operating in the hybrid mode according to the present invention consumes 12% more power than the ordinary CMOS.
- the delay is less than 1/6, and thus the operating speed is a little over 6 times faster. Energy was also just over 1/6.
- the operating speed is 1/4 times slower than DTCMOS, but the power consumption is 1/61 and the energy is 1/15.
- DT CMOS has very high power consumption and is difficult to use in practice.
- FIGS. 28 (a) and 28 (b) show changes in delay and power consumption when the load capacitance C1 is changed from 0 to 100.
- FIG. FIGS. 29 (a) and 29 (b) show changes in energy and energy delay product when the load capacity C1 is changed from 0 to 100.
- Other conditions are the same as in Table 3.
- Vdd 1.0V
- CI 0.5534pF
- the LBCM-S-inverter operating in the hybrid mode according to the present invention consumes 27% more power than a normal CMOS.
- the delay is 1/20, and thus the operating speed is 20 times faster.
- Energy is 1/16.
- Figure 32 (a) and (b) show the LB CMOS receiver circuit when the pulse voltage holding time: Th (two T1) is fixed at 700 ps and Vdd is changed from 0.7 V to 1. IV. And the change in power consumption.
- FIGS. 33 (a) and 33 (b) show changes in energy and energy delay product when Vdd is changed from 0.7V to 1.IV under the same conditions.
- FIGS. 34 (a) and (b) show the LB CMOS inverters when Vdd is fixed at 0.7 V and Th (two T1) is changed from 10 Ops to 130 Ops. It is a simulation result of road delay and power consumption.
- CMOS inverter circuit In this circuit, charging and discharging are performed at high speed only at the time of switching, thereby realizing a CMOS integrated circuit that operates at high speed and has low energy.
- the base terminal of the bipolar transistor included in the two MOS transistors is controlled, and a forward current is applied to the base terminal of one of the MOS transistors in synchronization with the switching of the input voltage of the CMOS inverter circuit.
- the current amplification factor Driving power is greatly increased by extracting the doubled collector current. At the same time, do not allow current to flow to the base terminal of the other MOS transistor.
- the CMOS inverter circuit When the CMOS inverter circuit is in a steady state, do not allow current to flow through both base terminals.
- CMOS standard cell library it is possible to adopt a design method that incorporates the hybrid mode LBCMOS into the output of the standard cell requiring high driving power.
- CMOS standard cell library standard cells with high driving capability that can switch the large load of the RC RC fan capacity must be available. Therefore, a hybrid mode LBCM ⁇ S, in which a forward base current is applied and a drain current multiplied by the current amplification factor is drawn to increase the driving force, is prepared in a library.
- a revolutionary CM ⁇ S standard cell library Is realized. For example, add such LBCMOS to the output of standard cells such as logic gates with heavy loads on the critical path, bus drive circuits, and block output circuits. ⁇
- this mixed mode LBCM 0 S The operation speed is 20 times faster and the energy is 1/16 compared to.
- the delay time can be significantly reduced, and at the same time, the energy can be significantly reduced.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04719623A EP1617477A4 (en) | 2003-03-31 | 2004-03-11 | LATERAL BIPOLAR CMOS INTEGRATED CIRCUIT |
US10/551,266 US20070096219A1 (en) | 2003-03-31 | 2004-03-11 | Lateral bipolar cmos integrated circuit |
JP2005504146A JP4691624B2 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003095116 | 2003-03-31 | ||
JP2003-095116 | 2003-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004088750A1 true WO2004088750A1 (ja) | 2004-10-14 |
Family
ID=33127429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/003208 WO2004088750A1 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070096219A1 (ja) |
EP (1) | EP1617477A4 (ja) |
JP (1) | JP4691624B2 (ja) |
WO (1) | WO2004088750A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008072095A (ja) * | 2006-08-18 | 2008-03-27 | Advanced Lcd Technologies Development Center Co Ltd | 電子装置、表示装置、インターフェイス回路、差動増幅装置 |
US8531001B2 (en) * | 2011-06-12 | 2013-09-10 | International Business Machines Corporation | Complementary bipolar inverter |
US20140073106A1 (en) | 2012-09-12 | 2014-03-13 | International Business Machines Corporation | Lateral bipolar transistor and cmos hybrid technology |
US8958187B2 (en) | 2012-11-09 | 2015-02-17 | Analog Devices, Inc. | Active detection and protection of sensitive circuits against transient electrical stress events |
FR3001571B1 (fr) * | 2013-01-30 | 2016-11-25 | Commissariat Energie Atomique | Procede de programmation d'un dispositif memoire a commutation bipolaire |
US9293912B2 (en) | 2013-09-11 | 2016-03-22 | Analog Devices, Inc. | High voltage tolerant supply clamp |
US9634482B2 (en) | 2014-07-18 | 2017-04-25 | Analog Devices, Inc. | Apparatus and methods for transient overstress protection with active feedback |
US9966459B2 (en) * | 2014-09-04 | 2018-05-08 | Globalfoundries Inc. | Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors |
US10199369B2 (en) | 2016-03-04 | 2019-02-05 | Analog Devices, Inc. | Apparatus and methods for actively-controlled transient overstress protection with false condition shutdown |
US10177566B2 (en) | 2016-06-21 | 2019-01-08 | Analog Devices, Inc. | Apparatus and methods for actively-controlled trigger and latch release thyristor |
US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
US10861845B2 (en) | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289658A (ja) * | 1985-06-18 | 1986-12-19 | Fujitsu Ltd | 半導体集積回路 |
JPH10189957A (ja) * | 1996-12-26 | 1998-07-21 | Mitsubishi Electric Corp | 半導体集積回路 |
JPH10229166A (ja) * | 1997-02-14 | 1998-08-25 | Nec Corp | 発振回路および遅延回路 |
JP2000332132A (ja) * | 1999-04-20 | 2000-11-30 | Internatl Business Mach Corp <Ibm> | 本体スイッチ式soi(絶縁体上シリコン)回路及びその形成方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0836194B1 (en) * | 1992-03-30 | 2000-05-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
KR0169157B1 (ko) * | 1993-11-29 | 1999-02-01 | 기다오까 다까시 | 반도체 회로 및 mos-dram |
US5543650A (en) * | 1995-01-12 | 1996-08-06 | International Business Machines Corporation | Electrostatic discharge protection circuit employing a mosfet device |
JP3175521B2 (ja) * | 1995-01-27 | 2001-06-11 | 日本電気株式会社 | シリコン・オン・インシュレータ半導体装置及びバイアス電圧発生回路 |
JP3682801B2 (ja) * | 1995-06-22 | 2005-08-17 | 株式会社デンソー | スイッチ回路 |
JPH1027859A (ja) * | 1996-07-09 | 1998-01-27 | Yamaha Corp | 複合半導体素子 |
US6249027B1 (en) * | 1998-06-08 | 2001-06-19 | Sun Microsystems, Inc. | Partially depleted SOI device having a dedicated single body bias means |
US6147508A (en) * | 1998-08-20 | 2000-11-14 | International Business Machines Corp. | Power consumption control mechanism and method therefor |
KR100353471B1 (ko) * | 1998-12-23 | 2002-11-18 | 주식회사 하이닉스반도체 | 데이터 센스 앰프 |
US6246027B1 (en) * | 1999-10-28 | 2001-06-12 | Vivette Griffiths | Electrically heated tool for cutting hair |
US6864539B2 (en) * | 2002-07-19 | 2005-03-08 | Semiconductor Technology Academic Research Center | Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry |
-
2004
- 2004-03-11 US US10/551,266 patent/US20070096219A1/en not_active Abandoned
- 2004-03-11 WO PCT/JP2004/003208 patent/WO2004088750A1/ja active Application Filing
- 2004-03-11 EP EP04719623A patent/EP1617477A4/en not_active Withdrawn
- 2004-03-11 JP JP2005504146A patent/JP4691624B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289658A (ja) * | 1985-06-18 | 1986-12-19 | Fujitsu Ltd | 半導体集積回路 |
JPH10189957A (ja) * | 1996-12-26 | 1998-07-21 | Mitsubishi Electric Corp | 半導体集積回路 |
JPH10229166A (ja) * | 1997-02-14 | 1998-08-25 | Nec Corp | 発振回路および遅延回路 |
JP2000332132A (ja) * | 1999-04-20 | 2000-11-30 | Internatl Business Mach Corp <Ibm> | 本体スイッチ式soi(絶縁体上シリコン)回路及びその形成方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1617477A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPWO2004088750A1 (ja) | 2006-07-06 |
EP1617477A4 (en) | 2008-12-10 |
EP1617477A1 (en) | 2006-01-18 |
US20070096219A1 (en) | 2007-05-03 |
JP4691624B2 (ja) | 2011-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5567961A (en) | Semiconductor device | |
US4769561A (en) | Bipolar transistor-field effect transistor composite circuit | |
US5644266A (en) | Dynamic threshold voltage scheme for low voltage CMOS inverter | |
WO1998045948A1 (en) | Qmos digital logic circuits | |
WO2004088750A1 (ja) | ラティラルバイポーラcmos集積回路 | |
JPH08223026A (ja) | アウトプット信号レベルを改善した低電力型スタティック・ロジック回路を含む装置及び同装置の製造方法、並びにロジック信号の処理方法 | |
JP3463269B2 (ja) | Mosfet回路 | |
JPH03190426A (ja) | 集積BiCMOS回路 | |
Han et al. | CMOS ternary logic with a biristor threshold switch for low static power consumption | |
Sheikhian et al. | High-speed digital family using field effect diode | |
Zhang et al. | Optimization of dual-threshold independent-gate FinFETs for compact low power logic circuits | |
Liu et al. | PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies | |
Subramanyam et al. | Tunnel FET based low voltage static vs dynamic logic families for energy efficiency | |
Kim et al. | Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits | |
Miki et al. | Subfemtojoule deep submicrometer-gate CMOS built in ultra-thin Si film on SIMOX substrates | |
Chowdhury et al. | Tunnel FET based standard logic cell implementation: a circuit perspective | |
Moghaddam et al. | A low-voltage level shifter based on double-gate MOSFET | |
Choi | Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design | |
Akino et al. | A clock generator driven by a unified-CBiCMOS buffer driver for high speed and low energy operation | |
Akino et al. | A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter | |
Shin et al. | A high-speed low-power JFET pull-down ECL circuit | |
Prakash et al. | Optimization of Leakage Power Dissipation in CMOS Inverter using Self biased and W/L Scaling Techniques | |
Ijjada et al. | Design of low power and high speed inverter | |
Ray et al. | Novel Methodology of reduction in PDP for digital designs using FGMOS and LECTOR techniques | |
US20070267702A1 (en) | Dynamic threshold P-channel MOSFET for ultra-low voltage ultra-low power applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2005504146 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007096219 Country of ref document: US Ref document number: 10551266 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004719623 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 2004719623 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10551266 Country of ref document: US |