WO2004079381A1 - Configuration de circuit destinee a la detection d'un defaut dans un circuit logique de commutation - Google Patents

Configuration de circuit destinee a la detection d'un defaut dans un circuit logique de commutation Download PDF

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Publication number
WO2004079381A1
WO2004079381A1 PCT/DE2004/000425 DE2004000425W WO2004079381A1 WO 2004079381 A1 WO2004079381 A1 WO 2004079381A1 DE 2004000425 W DE2004000425 W DE 2004000425W WO 2004079381 A1 WO2004079381 A1 WO 2004079381A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit logic
circuit
detection device
programming
logic
Prior art date
Application number
PCT/DE2004/000425
Other languages
German (de)
English (en)
Inventor
Karl-Harald Hewel
Manfred Roth
Stefan RÜPING
Thomas Schweizer
Jean-Pierre Seifert
Dominik Wegertseder
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2004079381A1 publication Critical patent/WO2004079381A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory

Definitions

  • Circuit arrangement for the detection of a fault in a circuit logic
  • the invention relates to a circuit arrangement with at least one programmable circuit logic, which has a detection device for recognizing a hardware error of this circuit logic.
  • ASIC Application Specific Integrated Circuits
  • Typical examples are ASICs on chip cards for storing data or for implementing algorithms, for example for encryption.
  • Such a chip is usually manufactured according to the specifications of a customer, with the manufacturer first designing and then producing the integrated component in accordance with the mode of action which the chip is to have later.
  • a second programmable, but unprogrammed circuit logic is provided, which takes over the function of the first circuit logic in whole or in part after programming.
  • unprogrammed circuit logic characterizes circuit logic, the individual elements of which can be configured, but the circuit logic or parts thereof are not used during normal operation. The area marked as unprogrammed is not used and is therefore designed as a reserve.
  • An advantageous development of the invention is to provide a detection device which is at least connected to the first circuit logic and can detect a hardware fault thereof.
  • An embodiment of this invention is when the first circuit logic is designed as hard-wired circuit logic, the detection device being connected to the same for detecting errors.
  • a connection can be provided between the first and the second circuit logic, in order to enable the second programmed circuit logic to be connected to the communication interface.
  • the circuit arrangement has a programming device which is connected to the programmable circuit logic.
  • This programming device can advantageously have an interface for loading a data stream for programming the circuit logic.
  • the programming device is activated by the detection of a hardware error.
  • the programming interface of the programming device can be enabled by the detection device.
  • An advantageous embodiment of the invention is to provide the detection device for detecting a manipulation attempt on the circuit logic. Furthermore, it is expedient to connect the detection device to an erasing device which erases the programmed part of the circuit logic in the event of a manipulation attempt.
  • FIG. 1 shows a first exemplary embodiment of the invention
  • FIG. 2 shows a second exemplary embodiment of the invention
  • FIG. 3 shows a third exemplary embodiment
  • the circuit arrangement 1 according to the invention in FIG. 1 has two circuit logics S1 and S2 which can exchange data with one another via a connection V.
  • the circuit arrangement S2 can be coupled to external devices via an interface K. In normal operation, external devices communicate via the K interface exclusively with circuit logic S2.
  • the unprogrammed circuit logic S1 and the connection V remain inactive.
  • circuit logic S1 is programmed, it is connected to the circuit logic S2 via the now active connection V. Some functions that were previously performed by S2 are now performed by the circuit logic S1.
  • the circuit logic S1 has a connection to the external devices via the circuit logic S2 and the interface K. A selection of the functions to be taken over by the circuit logic S1 depends on the behavior of the circuit logic S2.
  • circuit logic S2 If, for example, during operation it is found that algorithms of the circuit logic S2 have to be expanded, this can be done by programming the circuit logic S1 accordingly. If parts of circuit logic S2 fail during operation, these can be replaced via circuit logic S1.
  • the circuit logic is not limited to one type.
  • FIG. 2 An advantageous further development of the invention for recognizing a failure of the circuit logic S2 is shown in FIG. 2.
  • the same devices have the same reference numbers. A re-explanation of already known elements is therefore omitted.
  • the circuit arrangement 1 For the detection of an error in circuit logic S2, which represents a failure of parts of this circuit logic, the circuit arrangement 1 has a detection device D1. In the present case, this is connected both to circuit logic S2 and to circuit logic S1.
  • the connection U2 or Ul is used to detect an error in the circuit logic.
  • the detection device monitors individual areas of the circuit logic S2 or the complete function of S2 via the connection U2.
  • the connections Ul, U2 can be used as monitoring Interface be formed or also have means for monitoring the individual areas.
  • the detection device for a function test sends a data stream to the circuit logic S2 via the connection U2, the result of which is known to the detection device.
  • the circuit logic S2 processes this data stream and sends a result back to the detection device D1, which compares it with the known result. This is done in Figure 2 via the connecting line U2 or Ul.
  • the detection device it is also possible for the detection device to carry out a function test via the interface K.
  • the detection device D1 In addition to a function test that always tests the complete circuit logic, it is possible to use the detection device D1 to test parts of the circuit logic connected to it via the connecting lines U2 or U1 in order to obtain more specific statements. This enables the affected area to be narrowed down if part of the circuit logic fails.
  • the detection device tests the individual logic blocks of the circuit logic S2. If a logic block fails, the circuit logic S1 takes over the function of the failed block via the connection V. As a result, the circuit logic S1 can be made significantly smaller and thus more cost-effective.
  • FIG. 4A and FIG. 4B A further development of the invention is shown in FIG. 4A and FIG. 4B.
  • the circuit arrangement 1 has a hard-wired circuit logic S2 and the associated circuitry Interface K and the programmable circuit logic S1 and the non-active connection K '.
  • the detection device D1 monitors the function of the circuit logic S2 via the connection U2.
  • the detection device Dl also contains an inactive connection U1 for monitoring the circuit logic S1 and a connection P1 to a programming device P.
  • the programming device P is connected to the programmable circuit logic S1 and a programming interface PS.
  • a data stream can be loaded into the programming device P via the programming interface PS, with the aid of which the circuit logic S1 is configured. If an error has been detected in the circuit logic S2, the detection device D1 communicates the type of the error to the programming device via the connection P1. This enables the programming device P to request a corresponding data stream for the configuration of the circuit logic S1.
  • the programming device can be designed in such a way that, with the aid of the information supplied by the detection device, the components necessary for programming are taken from a data stream.
  • the detection device can communicate the beginning and end of the sequence of a data stream, the programming device using only this sequence for programming.
  • connection K 'between the circuit logic S1 and S2 is active, and the circuit logic S1 replaces the failed functions of the circuit logic S2.
  • the detection device Dl now continues to monitor the still active areas of the circuit logic S2 and the programmed parts of the circuit logic S1.
  • the programming interface PS described in FIG. 4 is designed as a second special interface via which a Configuration data stream is loaded into the programming device P. However, it is possible to provide a connection between the programming device P and the interface K, so that a configuration data stream is loaded into the programming device P via the interface K. If the circuit logic is part of a chip card, it is easy to reprogram a normal chip card reader without having to provide special interfaces.
  • a switch P2 is provided, which is connected to the detection device D1 and separates the programming interface PS from the programming device P.
  • the programming device P is inactive and is only activated when a fault is detected by the detection device D1.
  • the circuit logic S1 and S2 are designed as programmable circuit logic. Both can be monitored by the detection device D1 and configured by the programming device P.
  • the switching means K1 or K2 make it possible for the programming device D1 to connect the respective circuit logic to the communication interface KS.
  • the detection device D1 activates the respective other circuit logic via the switches and simultaneously sends the signal for reprogramming the faulty circuit logic to the programming device P and the switch P2.
  • This means that continuous operation can also be achieved during the reconfiguration phase.
  • the programming device reprograms a circuit logic with the new algorithm and activates it again after the reprogramming.
  • an external signal can be sent to the detection device, so that the detection device is thereby shown an error in the monitored circuit logic. This can be done by the detection device monitoring the data sent by the circuit logic and evaluating a specific data sequence of the circuit logic as an error.
  • FIG. 3 shows a corresponding arrangement in which a programmable circuit logic S1 is connected to a communication interface KS.
  • a detection device M1 tests the communication data stream for manipulation attempts via a connection UM. Such a test can consist, for example, of evaluating the data sent to or coming from the circuit logic S1. If the data is outside a predetermined set of values, there has been a manipulation attempt. The detection device M1 then sends a signal to an erase device L, which erases the circuit logic S1 via the connection Ll.
  • a corresponding circuit arrangement which in addition to hard-wired circuit logic has at least one freely programmable circuit logic, is furthermore not limited to the mere replacement of a failed area of the hard-wired circuit logic.
  • the arrangement according to the invention can also be used for a functional expansion of the hard-wired circuit logic in a circuit arrangement.
  • circuit arrangements on a chip card should be mentioned here.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne une configuration de circuit comprenant un premier circuit logique de commutation (S2), une interface de communication (KS) et un circuit logique de commutation (S1) librement programmable et non utilisé, lequel est relié au premier circuit logique de commutation (S2) ou à l'interface de communication (KS) et qui, après une programmation, peut reprendre en partie ou en totalité les fonctions du premier circuit de commutation (S2).
PCT/DE2004/000425 2003-03-04 2004-03-04 Configuration de circuit destinee a la detection d'un defaut dans un circuit logique de commutation WO2004079381A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2003109313 DE10309313B4 (de) 2003-03-04 2003-03-04 Schaltungsanordnung zur Detektion eines Fehlers in einer Schaltungslogik
DE10309313.3 2003-03-04

Publications (1)

Publication Number Publication Date
WO2004079381A1 true WO2004079381A1 (fr) 2004-09-16

Family

ID=32891839

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000425 WO2004079381A1 (fr) 2003-03-04 2004-03-04 Configuration de circuit destinee a la detection d'un defaut dans un circuit logique de commutation

Country Status (2)

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DE (1) DE10309313B4 (fr)
WO (1) WO2004079381A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8136156B2 (en) 2006-09-28 2012-03-13 Infineon Technologies Ag Module with a controller for a chip card

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3738644A1 (de) * 1987-11-13 1989-05-24 Siemens Ag Digitale schaltungsanordnung
EP1020797A2 (fr) * 1999-01-11 2000-07-19 Koken Co., Ltd. Système informatique insensible aux défaillances
FR2824648A1 (fr) * 2001-05-14 2002-11-15 Gemplus Card Int Procede de protection d'un circuit logique contre des attaques exterieures, et unite logique contenant un circuit logique a proteger contre des attaques exterieures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777887A (en) * 1995-05-12 1998-07-07 Crosspoint Solutions, Inc. FPGA redundancy
US6209118B1 (en) * 1998-01-21 2001-03-27 Micron Technology, Inc. Method for modifying an integrated circuit
DE10101268A1 (de) * 2001-01-12 2002-07-25 Infineon Technologies Ag Integrierte Halbleiterschaltung
DE10149930A1 (de) * 2001-01-19 2002-08-08 Continental Teves Ag & Co Ohg Verfahren zur Separierung redundanter Systeme während des Designs von kundenspezifischen Schaltkreisen

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3738644A1 (de) * 1987-11-13 1989-05-24 Siemens Ag Digitale schaltungsanordnung
EP1020797A2 (fr) * 1999-01-11 2000-07-19 Koken Co., Ltd. Système informatique insensible aux défaillances
FR2824648A1 (fr) * 2001-05-14 2002-11-15 Gemplus Card Int Procede de protection d'un circuit logique contre des attaques exterieures, et unite logique contenant un circuit logique a proteger contre des attaques exterieures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8136156B2 (en) 2006-09-28 2012-03-13 Infineon Technologies Ag Module with a controller for a chip card

Also Published As

Publication number Publication date
DE10309313B4 (de) 2006-03-09
DE10309313A1 (de) 2004-09-23

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