WO2004075064A1 - 記録媒体の記録制御方法及び記録制御装置 - Google Patents
記録媒体の記録制御方法及び記録制御装置 Download PDFInfo
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- WO2004075064A1 WO2004075064A1 PCT/JP2004/000695 JP2004000695W WO2004075064A1 WO 2004075064 A1 WO2004075064 A1 WO 2004075064A1 JP 2004000695 W JP2004000695 W JP 2004000695W WO 2004075064 A1 WO2004075064 A1 WO 2004075064A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
Definitions
- the present invention relates to a recording control method and a recording control device for a recording medium such as a flash memory.
- the recording data handled by the NAND flash memory is configured as shown in Fig. 1, for example. That is, the recording data is read and written in small block units called pages, and erased in large block units called blocks having a plurality of pages.
- One page is composed of, for example, a data area of 512 bytes and a spare area (redundant part) of 16 bytes. Four bytes of the 16-byte spare area are used as an ECC (Error Correction Code) for error detection and correction.
- ECC Error Correction Code
- the method of controlling reading and writing of the flash memory is performed by a method described in, for example, Japanese Patent Application Laid-Open No. 2000-311104.
- the recording control device that controls reading and writing of the flash memory manages the physical address of the flash memory to which data has been written on a block basis by using a logical address.
- a logical-physical address conversion table for converting between a physical address and a logical address of the flash memory in units of blocks is provided.
- the recording control device uses the logical-physical address conversion table to control the address of the flash memory.
- the logical address is written to the spare area of each page.
- the spare area includes an updating flag indicating whether or not the writing of the logical address to the block is being performed.
- the updating flag is on ("0") when a write is in progress, and off ("1") when no write is in progress.
- the block to be written and the page to be written can be determined at random.However, in the write processing procedure in the same block, from the first page of the address number, There is a restriction that it must be performed according to the address order. In other words, in the same block, it is necessary to write in order from the page with the smallest address. For this reason, conventionally, even when writing in page units, the writing operation is performed in units of blocks including the page to be written.
- FIG. 2 is a diagram for explaining the outline of the data write operation in page units.
- the shaded blocks indicate pages on which data has already been written, and the blank blocks indicate the pages on which data has not been written yet.
- a write page is shown, and a stitched block indicates a new data write page where new data is written.
- FIG. 3 is a flowchart of the processing operation at the time of data writing, and mainly describes the processing executed by the above-described recording control device that controls reading and writing of the flash memory.
- the recording control device determines whether or not an instruction to write to the flash memory has been issued (step S 1). Performs other processing (step S2).
- step S1 If it is determined in step S1 that a write instruction has been issued, the recording control device determines the logical address of the block to be written and the page to be written (step S3), and sets the start address of the block of the logical address. Turn on the flag while updating the page (step S4).
- step S5 the write target block is evacuated to a spare free area prepared in the logical / physical address conversion table of the recording control device, and a free space in which a block having the same logical address as the logical address of the write target block can be written. Make a block area (step S5).
- step S5 will be further described with reference to FIG.
- the flash memory has the effective area from the logical block address A to the logical block address A + n-1 and the spare area for one block of the logical block address A + n.
- the spare area of the logical block address A + n has been erased and is an empty area.
- step S4 as shown in FIG. 4, the updating flag of the spare area in the first page of the block of the logical block address A + 3 is turned on.
- step S5 the recording control device changes the logical block address of the block having the logical block address A + 3, which is the write target block, to the logical block address A + n of the spare area on the logical-physical address conversion template. change. At this time, the logical address of the spare area on the block data of the logical block address A + 3 is not rewritten.
- the logical block address of the spare area whose logical block address was A + n is converted to A + 3 on the logical / physical address conversion table. This replacement of the logical address is performed so that A + 3 is written in the logical address of the spare area of the block to be newly written.
- the original block data to be written is stored in the spare area.
- the logical block address where the original block data to be written was saved is now vacant.
- step S5 When the processing of step S5 as described above is completed, the recording control device, as shown by adding 1 in FIG. 2, deletes all the pages in the address order preceding the page to be written. Then, the original block to be written is copied to the corresponding page in the write destination block area (step S6). At this time, the updating flag of the spare area of the first page of the block ahead of the copy is turned off.
- the recording control device writes the data of the write target page to the page corresponding to the write destination block area, as shown by 2-2 in FIG. 2 (step S7).
- the recording control device reads all pages in the address order after the page to be written from the original block to be written to the block area of the write destination from the original block to be written. Copy to the corresponding page (step S8).
- the recording control device logically stores the data of the original block to be written, which has been evacuated to the spare area. Is erased (step S9). As a result, the logical spare area becomes an empty area.
- step S10 determines whether or not the writing has been completed (step S10), and if not, returns to step S3 to determine the next block to be written and the page to be written. Then, the above processing is repeated. If it is determined in step S10 that the writing has been completed, this writing processing routine is ended. If the power supply voltage is cut off during the above-mentioned writing process due to a power failure, running out of battery, etc., the writing process will not be completed. In order to cope with such a case, conventionally, reset processing is performed when the power supply voltage is turned on again, so that no problem occurs in address management of the flash memory.
- FIG. 5 is a flowchart for explaining the reset processing when the power supply voltage is turned on again.
- the recording control device starts the reset processing shown in FIG. 5, and sets the logical address of the spare area of the first page of each block. To determine whether there are two blocks having the same logical address (step S21).
- the page data of the block at the rewriting destination is stored.
- the status is the same as the logical address in the upper spare area. Therefore, if the power is turned off during the write process, there will be two blocks with the same logical address.
- the updating flag is turned on in the original block to be rewritten, it can be distinguished from the replacement block in which the updating flag is off.
- step S21 if it is determined in step S21 that there are two blocks having the same logical address, it is determined that power has been cut off during the write process, and the update of the two blocks is performed.
- the data of the block whose middle flag is on is left, and all the data of the block whose update flag is off are erased (step S22). This returns to the state before the page write processing. Then, the reset process ends, and the process proceeds to the next process.
- step S21 when it is determined that there is only one block having the same logical address, there is no write process in progress , this reset process is terminated as it is, and the process proceeds to the next process.
- An object of the present invention is to solve the problems of the conventional technology as described above. It is an object of the present invention to provide a novel recording control method and recording control device for a recording medium. It is another object of the present invention to provide a recording control method and a recording control device that can increase the write processing speed as a recording control method for a recording medium such as a flash memory.
- the present invention proposes a small block of a predetermined number of data as a unit for reading and writing data overnight, and a large block composed of a plurality of small blocks as a unit for erasing data.
- Writing a small block in a large block is a recording control method for a recording medium performed in address order. Data is written to a first small block in a large block, and then data is written to a first small block in the large block.
- the second small block determines whether or not the address of the first small block in the large block is higher than the address of the first small block in the large block. If it is determined that the address is in the address order after the address of the block, data is written to the second small block.
- the present invention provides a small block having a predetermined number of data blocks as a unit for reading and writing data, a large block including a plurality of small blocks as a unit for erasing data blocks, and a small block in a large block.
- Block writing is a method of controlling recording on a recording medium in the order of addresses.
- the address order prior to the address of the first small block is included.
- the determining step when it is determined that the second small block has an address higher than the address of the first small block in the first large block, the first small block and the second small block are compared.
- a second copying step of copying the data of the small block in between to the corresponding address of the second large block, and after the second copying step, corresponding to the address of the second small block of the second large block A second writing step of writing data to the first address and a discriminating step, when it is determined that the second small block is in a large block different from the first large block, Block of A third copy step of copying the data of all the small blocks in the address order after the address of the first small block to a corresponding address of the second large block; and In the erasing step of erasing the data of the first first block and the recording control method, at the time of return after the write processing is interrupted, the address order of the second small block is the last small block address.
- a step of copying data of the small block corresponding to the first large block to the block address and an erasing step of erasing data of the first large block are performed.
- the address order of the second large block is the same as that of the large block addresses that are continuously empty when viewed from the last small block address.
- the first small block address of the second small block is set as the small program V address to start writing next in the second large block.
- a small block having a predetermined number of data is used as a unit for reading and writing data
- a large block including a plurality of small blocks is used as a unit for data erasure
- a recording control device for a recording medium in the order of addresses, wherein, when data writing to a first small block in a large block is completed, a second small block to be written next is a large block.
- a small block having a predetermined number of data blocks is used as a unit for reading and writing data
- a large block including a plurality of small blocks is used as a unit for erasing data
- a small block in the large block is used.
- a recording control device for recording on a recording medium in which addresses are written in the order of addresses, and among the first large blocks including the first small blocks, the small blocks having the address order prior to the address of the first small block.
- the data is erased First copying means for copying to an address corresponding to the second large block, and first writing means for writing data to an address corresponding to the address of the first small block in the second large block.
- Determining means for determining whether the second small block to be written next has an address order after the address of the first small block in the first large block; and When it is determined that the small block has an address ranking after the address of the first small block in the first large block, the small block data between the first small block and the second small block is determined.
- a second copying means for copying to a corresponding address of the second large block, and a second large block copied by the second copying means having a corresponding address of the address of the second small block.
- the second writing means for writing data and the determining means determine that the second small block is in a large block different from the first large block.
- Third copy means for copying all the small block data of the address order after the address of the first small block to the corresponding address of the second large block, and copy by the third copy means.
- Erasing means for erasing data of the first large block after the processing.
- the recording control device further includes a detecting unit that detects that the writing in the small block unit is interrupted in the middle, and a detecting unit that detects that the writing in the small block unit is interrupted in the middle.
- Erasing means for erasing the data of one large block.
- the recording control device further comprises a detecting means for detecting that the writing in small block units is interrupted halfway, and the detecting means interrupts the writing in small block units halfway.
- the address is detected, when the address order of the second large block is viewed from the last small block address, the first small block address of the consecutive small block addresses that are empty is determined. It is a small block address that starts the next writing in the second large block.
- FIG. 2 is a diagram for explaining a conventional recording control method for a NAND flash memory.
- FIG. 3 is a flowchart showing the procedure of a conventional recording control method for a NAND flash memory.
- FIG. 4 is a diagram for explaining a conventional recording control method for a NAND flash memory.
- FIG. 5 is a flowchart showing a reset processing procedure in a conventional recording medium recording control method.
- FIG. 6 is a block diagram showing the configuration of an IC recorder to which the recording medium recording control method according to the present invention is applied.
- Figure 7 is a diagram for explaining the memory area structure of the flash memory.
- 8 and 9 are a part of a flowchart showing the procedure of a recording control method for a recording medium according to the present invention.
- FIG. 10 is a diagram for explaining a recording control method for a recording medium according to the present invention.
- FIG. 11 is a flowchart showing the procedure of the reset process in the recording medium recording control method according to the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION A recording control method and a recording control device for a recording medium according to the present invention will be described below with reference to an example in which the method is applied to an IC (Integrated Circuit) recorder. .
- FIG. 6 is a block diagram showing a configuration of an IC recorder to which the present invention is applied.
- the IC recorder shown in Fig. 6 consists of a microcomputer
- the control unit 1 controls a flash memory 2 as a recording medium, a display control unit 4 that performs display control of an LCD (Lid Crystal Display) 3 as an example of a display element, and an operation input unit 5.
- An operation input unit interface 6 for connecting to the unit 1 and a USB (Universal Serial Bus) interface 7 are connected.
- the microcomputer constituting the control unit 1 includes a CPU (Central Processing Unit) 11, a program ROM (Read Only Memory) 12, and a random access memory (RAM) 13. are doing. It is also possible to use a microphone computer in which the program ROM 12 and the work area RAM 13 are external to the CPU.
- CPU Central Processing Unit
- program ROM Read Only Memory
- RAM random access memory
- a component part including the control unit 1 and the flash memory 2 is a part that constitutes an embodiment of a recording control device for a recording medium.
- the audio signal from the microphone 21 is supplied to the recording processing unit 23 through the amplifier 22.
- the recording processing unit 23 converts the audio signal into a digital signal and performs data compression under the control of the control unit 1.
- the control unit 1 receives the audio data from the recording processing unit 23 and writes it to the flash memory 2.
- the control unit 1 receives a reproduction instruction from the operation input unit 5 through the operation input unit interface 6, the control unit 1 reads audio data from the flash memory 2 and sends it to the reproduction processing unit 24. Under the control of the control unit 1, the reproduction processing unit 24 decompresses the received audio data and restores the digital audio signal to an analog audio signal.
- the reproduction processing unit 24 supplies the analog audio signal to an audio signal output terminal to which an earphone is connected, for example, through the amplifier 25. Further, the control unit 1 performs a predetermined display on the screen of the LCD 3 via the display control unit 4.
- a personal computer can be connected to the USB connector 8 via a USB cable. Then, the control unit 1 reads out the audio data recorded in the flash memory 2 and transfers the data to the personal computer through the USB interface 7, and transmits the data from the personal computer through the USB interface 7. Supplied and can be written to flash memory 2.
- audio data written to the flash memory 2 can be managed for each message, and a text comment can be added to the audio data for each message. Have been able to. The text comment is displayed on the LCD 3 screen.
- FIG. 7 is an explanatory diagram of the memory area of the flash memory 2 of this example.
- “BANK0” and “BANK1” and “EXTERNAL” are TOC (TableofCont ents) areas.
- “PCM D ATAJ is an area where audio data is written.
- EXTERNAL is the area where text comments are written.
- the number of characters that can be input per message of audio data is 256 bytes, and is assigned to one page. In other words, one text comment is assigned to one page.
- B ANK 0 and B ANK 1 each include "F ⁇ LDER INDEX X ADRE SSS TAGE”, "EXTERNAL MAP", “BL ANK MAP”, and "REV ISI ⁇ N” .
- “FOLDER I NDEX ADRE SSSTAGE” indicates where in the “PCM DATA” area the voice data for each message is located (in page units), and the text comment corresponding to the voice data is ⁇ EXTERNALJ Stores information for managing where (in page units) the area is located.
- EXTERNAL MAP J stores information for managing how character comments are written in the" EXTERNAL "area and which pages are free areas.
- BLANK MAP stores information on how audio data is written in “PCM DATA”.
- REV I SION manages a number indicating the number of revisions of “0” and “BANK 1”.
- an application software for writing a character comment is mounted on a personal computer connected through the US B INTERFACE 7.
- personal computers On the evening screen, a text comment entry field is displayed for each of a large number of messages stored in the flash memory 2, and the text comment is entered in the entry field.
- the input character comment data is transferred from the personal computer to the IC recorder via the USB interface 7, and the control unit 1 stores the transferred character comment data in the “EXTERNAL” area of the flash memory 2.
- the control unit 1 writes a character comment in the area of “EXTERNAL” by referring to “EXTERNAL MA PJ” and searching for an empty area.
- writing is performed in order of seven dress numbers, and writing is performed in order from the empty page area in the first order.
- FIG. 8 and FIG. 9 are flowcharts of a processing operation at the time of writing data to the flash memory 2 according to the present invention. This processing is executed by the CPU 11 of the control unit 1 in accordance with the program of the ROM 12. Is mainly described.
- control unit 1 determines whether or not an instruction to write to the flash memory 2 has been issued (step S101). If it is determined that the instruction to write has not been issued, the control unit 1 executes other processing. (Step S102).
- step S101 When it is determined in step S101 that a write instruction has been issued, the control unit 1 determines the logical address of the block to be written and the page to be written. (Step SI03), and turns on the updating flag of the first page of the block of the logical address (Step S104).
- step S105 The processing in step S105 is as described with reference to FIG.
- control unit 1 copies all page data in the address order before the page to be written from the original block to be written to the corresponding page in the block area of the write destination (step S 1 0 6). However, at this time, the updating flag of the spare area of the first page of the block ahead of the copy remains off.
- control unit 1 writes the data of the page to be written to the page corresponding to the block destination of the write destination (step S107).
- the processing up to this step S107 is the same as the processing of steps S1 to S7 in the flowchart of FIG. 3, which is a conventional write control procedure.
- step S107 after the page data has been written in step S107, instead of immediately copying all of the remaining pages after the page to be written as in the related art, the page where the writing has been completed is performed. Registers the page immediately after as the next write start position in the block and waits.
- step S111 in FIG. 9 it is determined whether or not the writing has been completed. If the writing has been completed, all the page data after the page to be written are replaced with the original block to be written. Is copied to the corresponding page of the write destination block area (step S112).
- Step S111 the write processing routine ends.
- step S111 determines whether or not the writing has not been completed. If it is determined in step S111 that the writing has not been completed, the control The part 1 determines the logical address of the next block to be written and the page to be written (step S114). Then, it is determined whether or not the determined next write target page is in the same block being written and is a post-order address of the page address written in step S107 ( Step S1 15).
- step S115 it is determined that the next page to be written is in the same block being written and is located at an address position after the page in which data was previously written.
- the control unit 1 transfers the data of all pages between the page in which the data was previously written and the next page to be written from the original block to be written to the block area of the write destination. Copy to the corresponding page (Step S116).
- step S is performed while the next page to be written is in the same block being written, and the last data is written in the previous block. Repeat the routine from 1 1 1 to step S 1 16 and return from step S 1 16 to step S 107.
- step S115 If it is determined in step S115 that the next page to be written is not in the same block being written, the control unit 1 writes all the page data after the last page to be written.
- the target block is copied from the original block to the corresponding page in the write destination block area (step S117).
- the control unit 1 logically erases the data in the original block to be written that has been evacuated to the spare area. (Step S118). Then, the process returns to step S104, and the processing steps after step S104 are repeated. Therefore, in the writing method according to the present invention, the designation of the page to be written is a page in the same block as shown by 1, 2, and 3 in FIG. If the pages are ranked, the pages 1, 2, and 3 are written at high speed as follows. That is, in the writing of the page (1), first, the page before the page (1) is the original block to be written as shown by (1) -1 in Fig. 10.
- pages to be written are pages in the same block. Therefore, if the address ranks occur sequentially and later, the copy of the required page and the write of the page to be written are repeated within one block, so that high-speed write processing can be performed. Will be possible.
- the character comment data is written in the order of the address number in the order of the address number, and the writing is performed in order from the empty page area in the first order.
- the write control method according to the above works effectively.
- FIG. 11 is a flowchart for explaining the reset processing when the power supply voltage is turned on again in the present invention.
- control unit 1 starts the reset processing shown in FIG. 11, and first searches for the logical address of the spare area of the first page of each block, and finds the block having the same logical address. It is determined whether there are two or not (step S 1 2 1).
- the state is the same as the logical address of the block to be rewritten. Therefore, when the power is turned off during the write process, there are two blocks with the same logical address. However, since the updating flag is turned on in the original block to be rewritten, it can be distinguished from the block at the rewriting destination where the updating flag is off.
- step S121 when it is determined in step S121 that there are two blocks having the same logical address, the control unit 1 determines that the power supply has been interrupted during the write processing. Then, both of these two blocks are left, and a search is made within the block where the updating flag is off, and when viewed from the last page in the address order of one block, the pages that are continuously free are Among them, the page having the highest address is detected (step S122).
- control unit 1 stores all the data of the pages following the page of the block whose update flag is on, including the detected page, in the corresponding page position of the block whose update flag is off. Copy (step S 1 2 3). When copying is completed, all data in the blocks whose updating flag is ON are erased (step S 1 2 4). Then, the reset process ends, and the process proceeds to the next process.
- step S121 If it is determined in step S121 that there is only one block having the same logical address, it is determined that there is no write process in progress, the reset process is terminated, and the process proceeds to the next process.
- step S122 a search is made in a block in which the updating flag is off, and when the address order is viewed from the last page, a continuous empty area is found.
- the page with the highest priority address is detected among the pages with, the corresponding page address position is changed to the next write in the block with the updating flag being off (write destination block).
- the reset process may be registered as the start position, and the process of steps S123 and S124 of FIG. 11 may not be performed.
- the reset processing is the stage at which step S107 in FIG. 8 is completed. Therefore, after the reset processing, the processing after step S111 in FIG. 9 is performed, and if the writing is completed, the step S12 equivalent to the processing in steps S123 and 124 in FIG. 11 is performed. The processing of steps 112 and S113 is performed. If the writing is not completed, the next block and page to be written are determined, and the above-described writing processing is performed.
- the present invention is applicable to all recording media in which address control similar to that of a NAND flash memory must be performed at the time of writing.
- the electronic device to which the present invention is applied is not limited to an IC recorder.
- the flash memory is not limited to a built-in electronic device.
- the flash memory may be a force-type memory and may be removable.
- the distinction between the write source and write destination blocks is as follows.
- the updating is performed using the updating flag included in the page data
- the distinction between the writing source block and the writing destination block is not limited to the method using such a flag.
- the management of the write control is performed using the logical / physical address conversion table, but the present invention is not limited to such a method.
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US10/545,488 US20060153025A1 (en) | 2003-02-20 | 2004-01-27 | Recording medium recording control method and recording control device |
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JP2003042983A JP3928724B2 (ja) | 2003-02-20 | 2003-02-20 | 記録媒体の記録制御方法および記録媒体の記録制御装置 |
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TWI232466B (en) * | 2003-10-28 | 2005-05-11 | Prolific Technology Inc | Method for updating data of non-volatile memory |
US7315916B2 (en) * | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
US7366826B2 (en) * | 2004-12-16 | 2008-04-29 | Sandisk Corporation | Non-volatile memory and method with multi-stream update tracking |
JP2007025001A (ja) * | 2005-07-12 | 2007-02-01 | Sony Corp | 音声記録装置、音声記録方法及び音声記録プログラム |
US9612954B2 (en) | 2008-12-31 | 2017-04-04 | Micron Technology, Inc. | Recovery for non-volatile memory after power loss |
JP6447469B2 (ja) * | 2015-11-23 | 2019-01-09 | 株式会社デンソー | 書換システム |
TWI643066B (zh) * | 2018-01-15 | 2018-12-01 | 慧榮科技股份有限公司 | 用來於一記憶裝置中重新使用關於垃圾收集的一目的地區塊之方法、記憶裝置及其控制器以及電子裝置 |
JP7213712B2 (ja) | 2019-02-14 | 2023-01-27 | キオクシア株式会社 | 不揮発性半導体記憶装置 |
CN112416811B (zh) * | 2020-11-18 | 2024-02-27 | 深圳市硅格半导体有限公司 | 基于数据关联度的垃圾回收方法、闪存及装置 |
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- 2003-02-20 JP JP2003042983A patent/JP3928724B2/ja not_active Expired - Fee Related
-
2004
- 2004-01-27 WO PCT/JP2004/000695 patent/WO2004075064A1/ja active Application Filing
- 2004-01-27 KR KR1020057015190A patent/KR20050111594A/ko not_active Application Discontinuation
- 2004-01-27 US US10/545,488 patent/US20060153025A1/en not_active Abandoned
- 2004-01-27 CN CNB2004800044979A patent/CN100440167C/zh not_active Expired - Fee Related
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JP2000311104A (ja) * | 1999-02-26 | 2000-11-07 | Sony Corp | 記録方法、管理方法、及び記録装置 |
JP2003015929A (ja) * | 2001-06-28 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 不揮発性メモリの制御方法 |
JP2003280979A (ja) * | 2002-03-20 | 2003-10-03 | Toshiba Corp | 情報記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
JP3928724B2 (ja) | 2007-06-13 |
KR20050111594A (ko) | 2005-11-25 |
CN100440167C (zh) | 2008-12-03 |
US20060153025A1 (en) | 2006-07-13 |
JP2004264912A (ja) | 2004-09-24 |
CN1751296A (zh) | 2006-03-22 |
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