WO2004071040A1 - Circuit de correction du decalage d'un convertisseur a/n - Google Patents

Circuit de correction du decalage d'un convertisseur a/n Download PDF

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Publication number
WO2004071040A1
WO2004071040A1 PCT/JP2003/001244 JP0301244W WO2004071040A1 WO 2004071040 A1 WO2004071040 A1 WO 2004071040A1 JP 0301244 W JP0301244 W JP 0301244W WO 2004071040 A1 WO2004071040 A1 WO 2004071040A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
output
circuit
offset
value
Prior art date
Application number
PCT/JP2003/001244
Other languages
English (en)
Japanese (ja)
Inventor
Kazuhiko Kiyomoto
Kouichi Komawaki
Nobuhiro Sakima
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Priority to PCT/JP2003/001244 priority Critical patent/WO2004071040A1/fr
Publication of WO2004071040A1 publication Critical patent/WO2004071040A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Definitions

  • the receiving circuit that receives the ⁇ 5 skin needs to A / D convert the received signal and digitally output the signal.
  • the received signal ⁇ iS width is not always ideal in microscopic view.
  • the vfc state may not be exactly the same. For example, if the DC offset has a deviation of 2% to 3%. Even if the A / D converter has an 8-bit interface, the resolution is substantially less than 8 bits. I can't. Therefore, in the receiving circuit, the DC offset is actually detected from ⁇ data overnight, and this is compensated for.
  • a method of detecting the DC offset there is a method of sampling a large number of A / D-fiber data and calculating the average of the data, and using the average value as the DC offset value.
  • the silent value and the minimum value of the data obtained by actually A / D converting the received signal are obtained, and the median value of the soft value and the minimum value and the A / D converter are calculated.
  • the method of detecting the DC offset by averaging the output of the A / D converter has a problem in that the input analog signal has noise. Since it has « ⁇ , it is necessary to average a considerable number of data (a few tens of samples) per night, and as with the method of setting up a digital filter, transport may be large.
  • the method of detecting the offset from the center of the ⁇ value and the minimum value of the received signal after A / D tandem and the center of the dynamic range is as follows. There are some things that are difficult to do.
  • the A / C circuit generates a noise signal such as noise of the operational amplifier itself in the AGC circuit.
  • D It is not possible to set zero for Konno to ⁇ : zero. Therefore, since it is not possible to produce a proper ⁇ -free pillow state, there is a high accuracy in offsetting and compensation.
  • the age at the thigh skin was explained, but in the evacuation communication! ⁇ Even at the end of the move, the DC offset of the A / D converter overnight caused the sex at the receiving part to be excessive. Then, there is a call quality that is not consistent.
  • the present invention corrects the offset amount applied to the A / D converter over a short period of time by a simple summary, and uses an inexpensive module with excellent demodulation characteristics even if an inexpensive A / D converter is used.
  • the purpose is to create a «® communication system.
  • a power supply regulator that outputs an input SE in response to an input sleep signal E and stops operation by an input sleep signal
  • the offset correction means for subtracting the average value from the A / D output value of the signal holding circuit as an offset correction amount.
  • FIG. 1 is a configuration diagram of a CDMA wireless system.
  • FIG. 2 is a diagram in the receiving unit (TRX) 8 of the device 2 according to the first aspect of the present invention
  • FIG. 3 is an example of the receiving unit (TRX) 8 Uchiya of the device 2 according to the first embodiment of the present invention.
  • FIG. 4 shows another example of the transmission section (TRX) 8 of the ⁇ arrangement 2 according to the first embodiment of the present invention. 1 The best ⁇ ⁇ to invention
  • the first aspect of the present invention relates to a variable amplifier that performs offset correction of an AZD converter overnight and performs ⁇ by applying 3 ⁇ 4E from a haze source regiure that is provided at a stage preceding the A / D converter. Shut down the SE line from the evening of the Hara Regi Yure, and by doing this, stop the variable operation to create a non-input pillow state for the A / D comparator. Comparing the amount of offset correction for one night.
  • the equipment configuration is simple, it is fffi-free, and it is possible to perform accurate offset correction. It is a tree.
  • Figure 1 shows the configuration of a typical CDMA (Code Division Multiple Access) wireless system.
  • the wireless network $ Lord device 1 is removed to the ⁇ tfe ⁇ device 2 and these are $$.
  • the device 2 'transmits / receives an anomalous lightning signal to / from the mobile communication transmission gear 3, and the upper line network 1 To send and receive signals via a wired interface (I / F).
  • This non-medical device 2 has 4 antennas, 5 receivers, 6 transmitters, 7 m (Transmitter &Receiver; TRX), 8 baseband signal processor (BB) 9 , D3 ⁇ 4 section, maintenance and decontamination, section 12.
  • TRX Transmitter &Receiver
  • BB baseband signal processor
  • the receptionist 1 received the non-woven word from antenna 3 and 4 via antennas 4 and 5 and received this signal, and received this signal as a receptionist 1
  • the spectrum is expanded to the weekly speech signal from the mmi it line network
  • TRX 8 Creates a radio-optimized signal modulated with a specific carrier frequency, and issues a no-acknowledgement signal from antennas 4 and 5. '
  • FIG. 1 shows the configuration of the non-S3 ⁇ 4 ( ⁇ 2), but the mobile unit S4j3 ⁇ 43 is similarly covered by the ⁇ ⁇ ⁇ receiving unit (TRX baseband signal difficulty unit (BB)).
  • TRX baseband signal difficulty unit (BB) TRX baseband signal difficulty unit
  • the words are multiplexed in sequence from the main terminal i at the end 3 in the «3 ⁇ 4t crane device 2 and the wireless network leg device 1 (in the upper part), and ⁇ or ⁇ ⁇ ⁇ or data 13 ⁇ 4 ⁇ between each other.
  • FIG. 2 shows zeros in the ⁇ receiver (TRX) 8 of the ascending station 2 in FIG.
  • TRX radio reception signal arriving from the mobile communication terminal 3 via the antennas 4 and 5 is separated into an analog I signal and a Q signal by the analog signal combining circuit 13, and these are separated into A / D converters 29 and 30.
  • a / D converters 29 and 30 Generates digital I signal and Q signal at.
  • the A / D converters 29 and 30 have an offset force even in the ⁇ force pillow state, so that i iff l and life deteriorate.
  • the radio reception signal arriving from the mobile terminal 3 via the antennas 4 and 5 is transmitted to the analog signal input circuit 13 via the isolator 14 by the analog signal receiver 15.
  • BPF bandpass filter
  • the mixers 2 1 and 2 2 respectively, almost heard the intermediate frequency signal supplied from the reactor 19, and the signal of the mixed wave and the difficult wave were mixed by the ⁇ 2 phase shifter 20.
  • / 2 It is converted to a base band with a difference between the two.
  • the base band signals of the two fibers are directly connected to the desired symbol level by the variable devices 25 and 26 via the capacitors 23 and 24.
  • the variable amplifiers 25 and 26 stop the power supply at the age when the external sleep signal is input, because the power supply is not supplied.
  • the digital I signal and Q signal are output to the base node signal at the later stage.
  • Part (BB) is 9 ⁇ .
  • ⁇ ? The desired input range of 0 is sent to the reception gain leg circuit 34 by the CPU-I / F circuit 35 in the digital signal input circuit 31 for 1S.
  • the reception gain circuit 34 the reception gain of the digital I signal and Q signal after A / D conversion, which is normal communication data, is obtained at any time, and the obtained reception gain is obtained from the CPU 36.
  • the desired input l ⁇ gffl ⁇ of the converter 29, 30 is the desired ⁇ ⁇ ⁇
  • the AGC signal is variably increased in the analog signal ⁇ circuit 13 5 5 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ 5 5 2 5 5 2 5 2 2 2 ⁇ ⁇ It operates so that adjustment mosquito ⁇ 1 Wa reception gain is always kept to a woven ⁇ .
  • the reception gain of the digital I signal and Q signal after AZD tandem which is usually ⁇ ® data, is larger than the desired gain: ⁇ is the reception gain.
  • the signal is sent to the variable amplifiers 25, 26 in the analog signal circuit 13, and the variable amplifiers 25, 26 suppress the amplitude of the analog I-Q signal to provide a desired reception gain.
  • a sleep signal is sent from the CPU 36 in the unit 2 to the regi- ure overnight 40 via the CPU-I / F circuit 35. Stop power supply line from 40 am at night.
  • the variable amplifiers 25 and 26 are controlled by applying a predetermined voltage from the Kasumihara regulation 40 to the source terminal V, but the supply of the original regulation 40 is stopped.
  • variable louvers 25 and 26 are stopped at one point, the A / D consoles 29 and 30 are set to the inactive state, and the offset amount is calculated. Can be.
  • This offset amount has a unique value for each AZD converter every night, and once measured, the value will not change.
  • the sleep signal is sent to the source signal 40 in the analog signal input / output circuit 13 via the CPU 36 and the CPU-I / F circuit 35 of the non-motion device 2 ⁇
  • 1 25, 26 is also stopped.
  • the A / D converters 29 and 30 enter a non-input state, so that the outputs of the converters 29 and 3.0 are input to the CPU 36 via the CPU-I / F circuit 35.
  • the output values of the A / D converters 29 and 30 are sampled »times, the average value is calculated, and the average value is offset to the flash memory 37 as 3 ft.
  • the offset correction means 4 1, 4 2 force for t supply Offset correction is performed by using the offset amount previously stored in the flash memory 37 from the output of the AD converter 29, 30 during use.
  • the CPU 36 may output the SLE EP signal to the vineyard leg 40 based on $ $ from an external $ 1 leg device 38 (such as a normal PC). Since there is no need to mount an S / W for offset correction in the CPU 36, the cost can be kept low.
  • an external ⁇ leg device 38 and a non-breeding device 2 are used for product output, and the CPU of the external leg device 38 outputs a SLEEP signal from the CPU 36 to the Kasumihara Regyuraya 40. I do. As a result, it will stop supplying power at Itahara supply at 40, and the operation of variable amplifiers 25, 26 will also be stopped.
  • the outputs of the A / D converters 29 and 30 are measured by the external leg device 38 via the CPU-I / F circuit 35 and the CPU 36 to calculate each offset amount. .
  • the calculated offset amount is used in the flash memory 37 after the product is shipped.
  • the offset correction may be performed by an HZW called an offset amount calculation “ ⁇ circuit 32, 33”.
  • the leg from CPU 36 will cause the SLE EP sign to squeeze at regular night 40 variably increase ⁇ ⁇ 25, 26 6 Ryotei, A / D Comparator 29, 30
  • the offset amount is calculated, and the offset amount is calculated.
  • ⁇ 2 and 3 3 calculate the offset amount in the pillow state and calculate the offset amount.
  • the output of the A / D converter 29, 30 is used as a correction amount.
  • the A / D compa- tor mounted on the Tanada touch device was described. Even if it is a child for the band, the output of the variable increase iigfl may be stopped by the sleep leg from the external device, and the offset amount may be measured, as long as the A / D converter can be used. You may.
  • the power supply regulation is stopped by the sleeve signal, the variable ⁇ P3 ⁇ 4D operation is stopped at ⁇ :, and the A / D offset amount is calculated in the ⁇ -force state. «Offset complement IE * can be obtained, and a device with good iil characteristics can be obtained.
  • variable increase was stopped at ⁇ : due to the original regi yule.
  • the LPFs 27 and 28 were composed of a recognizing element.
  • the A / D converter '29, 30 will be in the * t state, so it is not limited to a variable amplifier.
  • a configuration may be adopted in which any one of the circuit circuits is stopped due to the power source regulation.
  • the offset correction circuit for the A / D converter stops the operation of the A / D converter in front of the A / D converter by stopping the operation of the S / R converter in response to the sleep signal. Since the offset amount of the A / D converter is calculated in the pillow state, it is possible to calculate the male offset amount with a simple view, and it is applicable to wireless receivers using A / D converters and soya devices. can do.

Abstract

Un circuit de correction du décalage d'un convertisseur A/N utilise un signal de veille pour arrêter un régulateur d'alimentation électrique afin de stopper complètement le fonctionnement des circuits actifs présents dans des circuits de traitement de signal analogique et calcule la valeur de décalage du convertisseur A/N dans un état où il n'y a pas d'entrées. Le circuit de correction du décalage peut ainsi effectuer un calcul de la valeur de décalage correcte à l'aide d'une structure simple et peut être utilisé pour un appareil de récepteur radio utilisant des convertisseurs A/N et pour d'autres appareils également.
PCT/JP2003/001244 2003-02-06 2003-02-06 Circuit de correction du decalage d'un convertisseur a/n WO2004071040A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/001244 WO2004071040A1 (fr) 2003-02-06 2003-02-06 Circuit de correction du decalage d'un convertisseur a/n

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/001244 WO2004071040A1 (fr) 2003-02-06 2003-02-06 Circuit de correction du decalage d'un convertisseur a/n

Publications (1)

Publication Number Publication Date
WO2004071040A1 true WO2004071040A1 (fr) 2004-08-19

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PCT/JP2003/001244 WO2004071040A1 (fr) 2003-02-06 2003-02-06 Circuit de correction du decalage d'un convertisseur a/n

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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63208325A (ja) * 1987-02-25 1988-08-29 Toshiba Corp 前処理フイルタを備えたアナログ・デイジタル変換回路
JPH0477116A (ja) * 1990-07-17 1992-03-11 Fujitsu Ltd オフセット補正方式
JPH0998087A (ja) * 1995-09-29 1997-04-08 Fujitsu Ltd 信号処理回路におけるａ／ｄコンバータのオフセット電圧キャンセル方法、ａ／ｄコンバータのオフセット電圧キャンセル回路、及び、信号処理回路
JPH09168037A (ja) * 1995-12-15 1997-06-24 Matsushita Electric Ind Co Ltd ダイレクトコンバージョン受信機
JPH10135865A (ja) * 1996-10-31 1998-05-22 Nec Corp 通信装置
JPH10308686A (ja) * 1997-05-08 1998-11-17 Yagi Antenna Co Ltd 電源制御回路
JPH11154925A (ja) * 1997-11-21 1999-06-08 Hitachi Denshi Ltd ディジタル伝送装置
JPH11274929A (ja) * 1998-03-23 1999-10-08 Oki Electric Ind Co Ltd アナログ／ディジタル変換装置
JP2000092143A (ja) * 1998-09-17 2000-03-31 Nec Corp Ｄｃオフセットのキャンセルとキャリア検出しきい値測 定機能を備えた受信機とその制御方法
JP2000216836A (ja) * 1999-01-22 2000-08-04 Japan Radio Co Ltd Ｄｃオフセット調整回路及び方法
JP2001086176A (ja) * 1999-09-17 2001-03-30 Toyo Commun Equip Co Ltd ディジタル送受信機
JP2001245006A (ja) * 2000-02-29 2001-09-07 Matsushita Electric Ind Co Ltd 無線受信装置及び方法
JP2002290237A (ja) * 2001-03-27 2002-10-04 Yamatake Corp アナログ・ディジタル変換器及び制御装置

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63208325A (ja) * 1987-02-25 1988-08-29 Toshiba Corp 前処理フイルタを備えたアナログ・デイジタル変換回路
JPH0477116A (ja) * 1990-07-17 1992-03-11 Fujitsu Ltd オフセット補正方式
JPH0998087A (ja) * 1995-09-29 1997-04-08 Fujitsu Ltd 信号処理回路におけるａ／ｄコンバータのオフセット電圧キャンセル方法、ａ／ｄコンバータのオフセット電圧キャンセル回路、及び、信号処理回路
JPH09168037A (ja) * 1995-12-15 1997-06-24 Matsushita Electric Ind Co Ltd ダイレクトコンバージョン受信機
JPH10135865A (ja) * 1996-10-31 1998-05-22 Nec Corp 通信装置
JPH10308686A (ja) * 1997-05-08 1998-11-17 Yagi Antenna Co Ltd 電源制御回路
JPH11154925A (ja) * 1997-11-21 1999-06-08 Hitachi Denshi Ltd ディジタル伝送装置
JPH11274929A (ja) * 1998-03-23 1999-10-08 Oki Electric Ind Co Ltd アナログ／ディジタル変換装置
JP2000092143A (ja) * 1998-09-17 2000-03-31 Nec Corp Ｄｃオフセットのキャンセルとキャリア検出しきい値測 定機能を備えた受信機とその制御方法
JP2000216836A (ja) * 1999-01-22 2000-08-04 Japan Radio Co Ltd Ｄｃオフセット調整回路及び方法
JP2001086176A (ja) * 1999-09-17 2001-03-30 Toyo Commun Equip Co Ltd ディジタル送受信機
JP2001245006A (ja) * 2000-02-29 2001-09-07 Matsushita Electric Ind Co Ltd 無線受信装置及び方法
JP2002290237A (ja) * 2001-03-27 2002-10-04 Yamatake Corp アナログ・ディジタル変換器及び制御装置

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