WO2004071040A1

WO2004071040A1 - Offset correction circuit of a/d converter

Info

Publication number: WO2004071040A1
Application number: PCT/JP2003/001244
Authority: WO
Inventors: Kazuhiko Kiyomoto; Kouichi Komawaki; Nobuhiro Sakima
Original assignee: Mitsubishi Denki Kabushiki Kaisha
Priority date: 2003-02-06
Filing date: 2003-02-06
Publication date: 2004-08-19

Abstract

An offset correction circuit of an A/D converter uses a sleep signal to stop a power supply regulator to completely stop the operations of the active circuits within analog signal processing circuits, and calculates the offset amount of the A/D converter in a state where no inputs are provided. The offset correction circuit, therefore, can provide a correct offset amount calculation by use of a simple structure and can be applied for radio receiver apparatus using A/D converters and for other apparatuses.

Description

Specification

A / D Conno, "Overnight offset correction [¾ ¾

This is related to the offset amount of the A / D converter.

For example, modulation schemes such as the QPSK and SQAM schemes, and ith-wave television schemes that digitally transmit television signals are used. In these receiving circuits, the receiving circuit that receives the β5 skin needs to A / D convert the received signal and digitally output the signal. By the way, in the transposition of the 5 ^ symbol in these systems, due to noise and reflections of β¾, the received signal © iS width is not always ideal in microscopic view. The vfc state may not be exactly the same. For example, if the DC offset has a deviation of 2% to 3%. Even if the A / D converter has an 8-bit interface, the resolution is substantially less than 8 bits. I can't. Therefore, in the receiving circuit, the DC offset is actually detected from ωί data overnight, and this is compensated for.

As a method of detecting the DC offset, there is a method of sampling a large number of A / D-fiber data and calculating the average of the data, and using the average value as the DC offset value. As another method, the silent value and the minimum value of the data obtained by actually A / D converting the received signal are obtained, and the median value of the soft value and the minimum value and the A / D converter are calculated. The method of calculating the deviation from the center of the dynamic range as a DC offset value, and the method of constructing a high-pass fill by digital fill and extracting only the high frequencies.

On the other hand, as shown, No. 1 0—1 7 3 5 2 5 ^^ As shown, the AG C (Au to Matic Ga in Contro 1: The output is adjusted by the conversion circuit, and the 0 g width of the signal input to the A / D converter is suppressed to the minimum value (difficultly zero) to create a pseudo-no-input state. A / D Compa ' Output flat: There is also a method of compensating the f $ value as a DC offset value.

However, the method of detecting the DC offset by averaging the output of the A / D converter has a problem in that the input analog signal has noise. Since it has «^, it is necessary to average a considerable number of data (a few tens of samples) per night, and as with the method of setting up a digital filter, transport may be large.

In addition, the method of detecting the offset from the center of the ^ value and the minimum value of the received signal after A / D tandem and the center of the dynamic range is as follows. There are some things that are difficult to do.

Furthermore, in the method of controlling the output of the A / D converter in an AGC circuit while the output of the A / D converter is in an indiscriminate state, the A / C circuit generates a noise signal such as noise of the operational amplifier itself in the AGC circuit. D It is not possible to set zero for Konno to ^: zero. Therefore, since it is not possible to produce a proper λ-free pillow state, there is a high accuracy in offsetting and compensation. In the above, the age at the thigh skin was explained, but in the evacuation communication! ^ Even at the end of the move, the DC offset of the A / D converter overnight caused the sex at the receiving part to be excessive. Then, there is a call quality that is not consistent. Therefore, the present invention corrects the offset amount applied to the A / D converter over a short period of time by a simple summary, and uses an inexpensive module with excellent demodulation characteristics even if an inexpensive A / D converter is used. The purpose is to create a «® communication system.

Disclosure of the invention

According to the present invention, a power supply regulator that outputs an input SE in response to an input sleep signal E and stops operation by an input sleep signal;

A signal input circuit having a predetermined value HE output from the power supply regulator, a signal input circuit having a fiber circuit for stopping the operation, m, no input from the source regulator, i. A / D ^^ that A / D analogizes the output signal of the analog signal circuit

Output a repeat signal at the end of the source regulation to stop the operation of the source regulation, tin ^ Signal is lost due to no input from the night, and the circuit in the Ma circuit stops operating. 亂 3Α / Ί) ¾ ^ Φ Measure the output value and calculate the flat value of the output value Offset compensation ΐΕβ calculation stage,

Note 3 The offset correction means for subtracting the average value from the A / D output value of the signal holding circuit as an offset correction amount.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of a CDMA wireless system.

FIG. 2 is a diagram in the receiving unit (TRX) 8 of the device 2 according to the first aspect of the present invention;

FIG. 3 is an example of the receiving unit (TRX) 8 Uchiya of the device 2 according to the first embodiment of the present invention. FIG. 4 shows another example of the transmission section (TRX) 8 of the ^^^^ arrangement 2 according to the first embodiment of the present invention. ¹ The best 开 ^ to invention

Hereinafter, Embodiment 1 of the present invention will be described. The first aspect of the present invention relates to a variable amplifier that performs offset correction of an AZD converter overnight and performs 辦 by applying ¾E from a haze source regiure that is provided at a stage preceding the A / D converter. Shut down the SE line from the evening of the Hara Regi Yure, and by doing this, stop the variable operation to create a non-input pillow state for the A / D comparator. Comparing the amount of offset correction for one night. 無 The equipment configuration is simple, it is fffi-free, and it is possible to perform accurate offset correction. It is a tree.

Figure 1 shows the configuration of a typical CDMA (Code Division Multiple Access) wireless system. The wireless network $ Lord device 1 is removed to the ^ tfe ^ device 2 and these are $$. The device 2 'transmits / receives an anomalous lightning signal to / from the mobile communication transmission gear 3, and the upper line network 1 To send and receive signals via a wired interface (I / F). This non-medical device 2 has 4 antennas, 5 receivers, 6 transmitters, 7 m (Transmitter &Receiver; TRX), 8 baseband signal processor (BB) 9 , D¾ section, maintenance and decontamination, section 12.

At the time of this work, the receptionist 1 received the non-woven word from antenna 3 and 4 via antennas 4 and 5 and received this signal, and received this signal as a receptionist 1 | Via the fiberless receiving unit (TRX) 8 via the baseband signal, and then the speech through the pace node signal unit (BB) 9

»Output to network leg device ι. On the other hand, the spectrum is expanded to the weekly speech signal from the mmi it line network

(TRX) 8 Creates a radio-optimized signal modulated with a specific carrier frequency, and issues a no-acknowledgement signal from antennas 4 and 5. '

As described above, FIG. 1 shows the configuration of the non-S¾ (^ 2), but the mobile unit S4j¾3 is similarly covered by the 受信 ^ receiving unit (TRX baseband signal difficulty unit (BB)).

With such a configuration, the words are multiplexed in sequence from the main terminal i at the end 3 in the «¾t crane device 2 and the wireless network leg device 1 (in the upper part), andを or データ or data 1¾ ^ between each other. (

FIG. 2 shows zeros in the ^ receiver (TRX) 8 of the ascending station 2 in FIG. First, a radio reception signal arriving from the mobile communication terminal 3 via the antennas 4 and 5 is separated into an analog I signal and a Q signal by the analog signal combining circuit 13, and these are separated into A / D converters 29 and 30. Generates digital I signal and Q signal at. At this time, the A / D converters 29 and 30 have an offset force even in the λ force pillow state, so that i iff l and life deteriorate. There is an individual difference in the magnitude of the offset amount due to the difference in the waiting time of parts and the like every night of the A / D converter. For this reason, the offset amount of the A / D converter 29, 30 with no input pillow was actually measured, and it was changed to the normal (デジタル i I signal. Rising from the value of the Q signal Then, by performing offset correction of the A / D converter 29 and 30, the excellent {5} characteristic can be obtained. «^ Receiver (TRX) 8 The amplifiers 15, mi 6, 19 in the TRX 8 are variable. The power supply 40 reduces the voltage applied to the input source terminal Vin to a predetermined voltage, and outputs the SE from Vout. Also, by inputting the sleep signal (“L” or “H”) of Toyo to the S LE EP terminal, the operation of the S3 original Regyu-Ye 40 is stopped.

First, in the normal data communication mode, the radio reception signal arriving from the mobile terminal 3 via the antennas 4 and 5 is transmitted to the analog signal input circuit 13 via the isolator 14 by the analog signal receiver 15. Oscillator 16, mixer 17, and bandpass filter (BPF) 18, which are divided into two systems after being once traversed by the mid-Shu-Nada. Then, the mixers 2 1 and 2 2, respectively, almost heard the intermediate frequency signal supplied from the reactor 19, and the signal of the mixed wave and the difficult wave were mixed by the ΤΓΖ2 phase shifter 20. / 2 It is converted to a base band with a difference between the two. After that, the base band signals of the two fibers are directly connected to the desired symbol level by the variable devices 25 and 26 via the capacitors 23 and 24. The variable amplifiers 25 and 26 stop the power supply at the age when the external sleep signal is input, because the power supply is not supplied.

The low frequency filters (LPFs) 27 and 28, each of which acts as a channel, make unnecessary rounds (te analog I signals. Q signals »A / D connec. At 9 and 30, the digital I signal and Q signal are output to the base node signal at the later stage. Part (BB) is 9 ^. Here, 〇? The desired input range of 0 is sent to the reception gain leg circuit 34 by the CPU-I / F circuit 35 in the digital signal input circuit 31 for 1S.

In the reception gain circuit 34, the reception gain of the digital I signal and Q signal after A / D conversion, which is normal communication data, is obtained at any time, and the obtained reception gain is obtained from the CPU 36. The desired input l ^ gffl ^ of the converter 29, 30 is the desired λΛ ^ δ The AGC signal is variably increased in the analog signal 麵 circuit 13 5 5 ヘイヘイヘイ 5 5 2 5 5 2 5 2 2 振幅振幅It operates so that adjustment mosquito ^ ¹ Wa reception gain is always kept to a woven囲内.

For example, the reception gain of the digital I signal and Q signal after AZD tandem, which is usually Φ® data, is larger than the desired gain: ^ is the reception gain. The signal is sent to the variable amplifiers 25, 26 in the analog signal circuit 13, and the variable amplifiers 25, 26 suppress the amplitude of the analog I-Q signal to provide a desired reception gain.

However, as described above, in the AZD Comparator '29, 30 ', the offset amount peculiar to each individual that degrades the life is i ^ S, and these are corrected. 'I need it. Therefore, in the first embodiment of the present invention, as shown in FIG. 2, a sleep signal is sent from the CPU 36 in the unit 2 to the regi- ure overnight 40 via the CPU-I / F circuit 35. Stop power supply line from 40 am at night. The variable amplifiers 25 and 26 are controlled by applying a predetermined voltage from the Kasumihara regulation 40 to the source terminal V, but the supply of the original regulation 40 is stopped. As a result, the variable louvers 25 and 26 are stopped at one point, the A / D consoles 29 and 30 are set to the inactive state, and the offset amount is calculated. Can be. This offset amount has a unique value for each AZD converter every night, and once measured, the value will not change.

That is, the sleep signal is sent to the source signal 40 in the analog signal input / output circuit 13 via the CPU 36 and the CPU-I / F circuit 35 of the non-motion device 2 ^ With the stoppage of operation, the operation of variable increase || 1 25, 26 is also stopped. As a result, the A / D converters 29 and 30 enter a non-input state, so that the outputs of the converters 29 and 3.0 are input to the CPU 36 via the CPU-I / F circuit 35. In the CPD 36, the output values of the A / D converters 29 and 30 are sampled »times, the average value is calculated, and the average value is offset to the flash memory 37 as 3 ft.

Actually, the old device 2 is out of date: The offset correction means 4 1, 4 2 force for t supply Offset correction is performed by using the offset amount previously stored in the flash memory 37 from the output of the AD converter 29, 30 during use.

In the above example, a single tortoise source Regille night 40 was used. However, it is also possible to provide an unpleasant green field regular night and supply each source individually.

In addition, as shown in FIG. 3, the CPU 36 may output the SLE EP signal to the vineyard leg 40 based on $ $ from an external $ 1 leg device 38 (such as a normal PC). Since there is no need to mount an S / W for offset correction in the CPU 36, the cost can be kept low. On the tool side, an external Φ leg device 38 and a non-breeding device 2 are used for product output, and the CPU of the external leg device 38 outputs a SLEEP signal from the CPU 36 to the Kasumihara Regyuraya 40. I do. As a result, it will stop supplying power at Itahara supply at 40, and the operation of variable amplifiers 25, 26 will also be stopped. In such a stopped state, the outputs of the A / D converters 29 and 30 are measured by the external leg device 38 via the CPU-I / F circuit 35 and the CPU 36 to calculate each offset amount. . The calculated offset amount is used in the flash memory 37 after the product is shipped.

Further, as shown in FIG. 4, the offset correction may be performed by an HZW called an offset amount calculation “鹏 circuit 32, 33”. In other words, the leg from CPU 36 will cause the SLE EP sign to squeeze at regular night 40 variably increase Ψΐ ^ 25, 26 6 Ryotei, A / D Comparator 29, 30 The offset amount is calculated, and the offset amount is calculated. · 2 and 3 3 calculate the offset amount in the pillow state and calculate the offset amount.

Sometimes the output of the A / D converter 29, 30 is used as a correction amount.

In the above example, the A / D compa- tor mounted on the Tanada touch device was described. Even if it is a child for the band, the output of the variable increase iigfl may be stopped by the sleep leg from the external device, and the offset amount may be measured, as long as the A / D converter can be used. You may. As described above, according to the present invention, the power supply regulation is stopped by the sleeve signal, the variable 增 P¾D operation is stopped at ^ :, and the A / D offset amount is calculated in the λ-force state. «Offset complement IE * can be obtained, and a device with good iil characteristics can be obtained.

In the above example, the variable increase was stopped at ^: due to the original regi yule. However, for example, the LPFs 27 and 28 were composed of a recognizing element. By stopping the appointment of the A / D converter, the A / D converter '29, 30 will be in the * t state, so it is not limited to a variable amplifier. A configuration may be adopted in which any one of the circuit circuits is stopped due to the power source regulation.

S¾Jt available I, raw

The offset correction circuit for the A / D converter according to the present invention stops the operation of the A / D converter in front of the A / D converter by stopping the operation of the S / R converter in response to the sleep signal. Since the offset amount of the A / D converter is calculated in the pillow state, it is possible to calculate the male offset amount with a simple view, and it is applicable to wireless receivers using A / D converters and soya devices. can do.

Claims

The scope of the claims

1. Output SE by adding the SE to the specified value to the specified SE, and stop the operation by the sleep signal.

The signal is output by the SEE of the door that is output by the regille and the signal is output. A / D¾ ^ that A / D maintains the output signal of the signal combining circuit,

Attraction 3 Source regulation evening 3 Slip ί Outputs the sign to stop the operation of the grape field regulation evening, and the I3ft source regulation evening disappears so that the i word «Meeting in the circuit ^ I The circuit has stopped operating and the 3-signal fiber circuit has no output. Γ 3 3AZD »g | 0 Measures the output value and calculates the offset of the output value. When,

Note 3 Offset correction circuit, which includes offset correction means for subtracting from A / D ^ | ® output value.

2. Perform the output to a predetermined value and output the data, and use the sleep signal to stop the operation.

Part 3 Apologize for the fact that the specified value output by the 3rd party Harajuku Regulations is displayed, there is no input from the source Regyuyure: ^ ", with an organization circuit that stops operation,« Reception In addition to converting the signal into a base fiber, it separates the analog I signal from the analog I signal and the analog Q signal that is out of phase with the analog signal by 7 l2. Analog signal circuit to convert,

A memory that describes the amount of offset from the output value of the A / D converter. 3 The offset that executes the amount of offset from the Φ output value to the memory 3 Ιΐ¾ ί 3 ί 号号にスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープスリープ While the road fluctuates and the tooth 3f signal difficulty circuit is non-output, measure the lir A / D variable output value via the braided wire, calculate the average of the output values, and calculate Toshidaira: An offset compensation unit that outputs M to a 3 memory via a line, and is provided with an offset compensation unit.