JPH0998087A - Method and circuit for cancelling offset voltage of a/d converter in signal processing circuit and signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the signal processing with a high precision by detecting the offset voltage of an A/D converter each time to cancel the offset voltage. SOLUTION: A control circuit 53 turns off an analog switch 44 to block a read signal RD. An A/D converter 45 digitally converts the deleted state of the read signal RD. A discriminator 51 takes a digital value D from the A/D converter 45 and offset allowable values K and-K as the input to output a discrimination signal J to a control circuit 53. The control circuit 53 outputs first and second operation control data Ja and Jb to a multiplier 54 and an adder 55 based on the discrimination signal J from the discriminator 51. The multiplier 54 and the adder 55 obtain a new cancel accumulation value H from data Ja and Jb and an offset unit variation T and output this value to a second register 57. The cancel accumulation value H of the second register 57 is outputted to a D/A converter 59 and is converted to an analog voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset voltage canceling method for an A / D converter in a signal processing circuit, an offset voltage canceling circuit for an A / D converter, and a signal processing circuit.

In recent years, in hard disk devices such as magnetic disk devices, the density of hard disks and the read and write speeds are increasing. Along with this increase in density and speed, signal processing of signals read out from the recording medium by the drive head is required to be more accurate.

[0003]

2. Description of the Related Art Conventionally, in a hard disk device, data recorded on a magnetic disk as a recording medium is read by a drive head. The drive head outputs the read data as a read signal to the signal processing circuit for signal processing. The signal processing circuit handles the read signal output by the drive head as an analog output, and first converts the read signal into multiple bits,
The digital value and the reference value are compared and binarized. Then, the read signal binarized by the signal processing circuit is output to the disk controller, the content of the read signal is determined by the disk controller, and the user data is extracted and processed.

In the signal processing circuit, an A / D converter is used to digitally convert a read signal handled as an analog output into a plurality of bits. The characteristic of the digital value (output) with respect to the analog value (input) in this A / D converter is preferably a one-to-one characteristic L1 that passes through the origin as shown by the solid line in FIG. However, due to manufacturing variations of the A / D converter, there may be cases where the characteristics L2 and L3 do not pass through the origin, as shown by the broken line in FIG. In this case, the characteristic L
An A / D converter having 2 and L3 needs to perform so-called offset cancellation, which corrects only the displaced potential (offset voltages Δα and Δβ). The offset cancellation is performed at the time of shipping the integrated circuit device including the signal processing circuit or at the time of starting the operation of the signal processing circuit.

FIG. 6 shows a circuit for offset canceling the A / D converter 80. In FIG. 6, the register 81 inputs the offset cancel value from the disk controller via the external interface 82. This cancel value is set based on the offset voltage obtained by the inspection before shipment, and is output from the disk controller every time the disk device is started up. The register 81 stores the cancel value D /
Output to the A converter 83. D / A converter 83
Converts a cancellation value composed of a digital value into an analog value (analog voltage). The analog voltage is the resistance 84,
It is applied to a voltage dividing circuit composed of 85. And resistor 8
A voltage having a potential difference between this analog voltage and the reference voltage applied to the other end is applied between 4 and 85. This voltage is divided by a voltage division ratio determined by the resistance ratio of the resistors 84 and 85, and applied to the signal line 87 of the A / D converter 80 via the resistor 86. The voltage applied to the signal line 87 becomes a cancel voltage for offset cancellation. That is, the A / D converter 80 having the characteristic L2 shown by the broken line in FIG.
Then, the cancel voltage becomes −Δα. In the A / D converter 80 having the characteristic L3, the cancel voltage is Δβ.

As described above, the disk device completes the offset cancel process for the A / D converter 80 of the signal processing circuit immediately after the power is turned on. As a result, the signal processing circuit can perform highly accurate signal processing on the read signal output from the drive head.

[0007]

By the way, when the disk device is used for a long time, the A / D converter 8 is used.
The ambient temperature of 0 becomes high. The characteristic of the digital value (output) with respect to the analog value (input) in the A / D converter 80 varies depending on the ambient temperature. This fluctuation increases as the ambient temperature increases.

However, the offset canceling process is not performed once after the disk device is powered on. That is, the offset cancel voltage for the A / D converter 80 is fixed. Therefore, the offset voltage due to the increase in ambient temperature cannot be canceled by the offset canceling process.

The present invention has been made in order to solve the above-mentioned problems, and its purpose is to eliminate the need for performing an inspection for offset canceling in advance, and to deal with variations in manufacturing or variations in ambient temperature. Without A / D
Offset voltage canceling method of A / D converter in signal processing circuit capable of detecting offset voltage of converter and canceling offset voltage to perform highly accurate signal processing, offset voltage canceling circuit of A / D converter, and , Providing a signal processing circuit.

[0010]

In order to achieve the above object, the present invention according to claim 1 relates to the servo information recorded in each sector and the digital conversion processing of the read signal of the data information, respectively. In a signal processing circuit that is performed by a processing unit different from that for data information, when the processing unit for servo information is performing digital conversion processing on the read signal of servo information, the digital signal provided in the processing unit for data information is used. A / D in signal processing circuit for detecting offset voltage of A / D converter for conversion processing and canceling offset voltage of A / D converter
The method of canceling the offset voltage of the converter is the gist.

According to a second aspect of the present invention, an A / D converter for converting an input signal into a digital value, a digital value output from the A / D converter in a state where the input voltage disappears, and a predetermined allowable value. A discriminator for comparing whether or not there is a digital value within the allowable value, an arithmetic unit for cumulatively adding a predetermined offset unit change amount when the digital value is not within the allowable value, and the addition An offset voltage cancel circuit of an A / D converter including an offset cancel voltage supply circuit that outputs a value to the A / D converter as an offset cancel voltage for canceling the offset voltage of the A / D converter.

According to a third aspect of the present invention, the digital conversion processing of the read signal of the servo information and the data information recorded in each sector is performed by the first processing unit for the servo information and the second processing unit for the data information. In the signal processing circuit performed,
The second processing unit has an A / D converter for converting the data information into a digital signal, and the first processing unit performs a digital conversion process on a read signal of the servo information.
A switch that blocks the input of the servo information to the A / D converter, and operates the A / D converter when the first processing unit is performing a digital conversion process on a read signal of the servo information. When the control circuit and the first processing unit are performing digital conversion processing on the read signal of the servo information, the digital value from the A / D converter is compared with a predetermined allowable value and within the allowable value. A discriminator that determines whether or not there is a digital value, and if the digital value is not within the allowable value, a predetermined offset unit change amount is cumulatively added, and if it is within the allowable value, the offset at that time is added. An arithmetic unit for cumulative addition with the unit change amount set to 0,
The gist is a signal processing circuit including an offset cancel voltage supply circuit that outputs the added value from the arithmetic unit as an offset cancel voltage to an A / D converter.

According to a fourth aspect of the present invention, the digital conversion processing of the read signal of the servo information and the data information recorded in each sector is performed by the first processing unit for the servo information and the second processing unit for the data information. In the signal processing circuit performed,
The second processing unit includes an amplifier for amplifying the data information, an A / D converter for converting the data information amplified by the amplifier into a digital signal, and a signal for reading servo information by the first processing unit. A switch for blocking the input of the servo information to the amplifier when the digital conversion processing is performed, and a switch for blocking the servo information read signal when the first processing unit performs the digital conversion processing. A
When the first control circuit for operating the A / D converter and the first processing unit are performing digital conversion processing on the read signal of the servo information, the digital value from the A / D converter and a predetermined allowance A discriminator that compares the value with a discriminator that determines whether or not there is a digital value within the allowable value, and if the digital value is not within the allowable value, cumulatively adds a predetermined offset unit change amount, and within the allowable value. In the case of, the arithmetic unit for cumulatively adding the offset unit change amount at that time to 0 and the offset cancel voltage supply for outputting the added value from the arithmetic unit as the offset cancel voltage to the A / D converter via the amplifier. If the circuit and the digital value are within the allowable value, control is performed to increase the amplification factor of the amplifier, and the increase rate of the amplification factor is set to the arithmetic unit. A signal processing circuit provided by reducing the offset unit variation in lowered rate proportional to a second control circuit for controlling to cumulatively added as its gist.

According to a fifth aspect of the present invention, in a signal processing circuit having a processing unit for digitally converting a read signal of data information recorded in each sector by an A / D converter, the signal is recorded in a part of each data information. The read signal of the same continuous pattern is converted into a digital value by the A / D converter at 180 ° intervals of the signal waveform,
The offset voltage of the A / D converter is detected from the average value of the two digital values before and after read at intervals of
The gist is a method of canceling an offset voltage of an A / D converter in a signal processing circuit that cancels an offset voltage of a D converter.

According to a sixth aspect of the present invention, an A / D converter for converting an input signal into a digital value, an input signal supplying means for inputting a sine wave input signal to the A / D converter, and the sine wave input signal. A sampling control circuit that controls the A / D converter to perform digital conversion at intervals of 180 degrees, and two digital values before and after the digital conversion performed by the A / D converter are input, and the average of both digital values is input. An arithmetic unit that obtains a value and outputs the average value as an offset voltage at that time, and an offset cancel that generates an offset cancel voltage that cancels the offset voltage based on the offset voltage calculated by the arithmetic unit and outputs the offset cancel voltage to the A / D converter. The gist is an offset voltage cancel circuit of an A / D converter including a voltage supply circuit.

According to a seventh aspect of the present invention, the digital conversion processing of the read signal of the data information including the servo information recorded in each sector and a part of the information in which the read signal is a sine wave is performed.
The servo information is stored in the first processing unit, and the data information is stored in the second processing unit.
The processing unit of A / A converts the data information into digital data.
When the D converter and the second processing unit perform digital conversion processing on the read signal of the information whose read signal is a sine wave, the read signal of the information of the sine wave input to the A / D converter is converted into 180 A sampling control circuit for controlling digital conversion at an interval of
An arithmetic unit that inputs two digital values before and after being digitally converted by the / D converter, calculates an average value of both digital values, and outputs the average value as an offset voltage at that time,
The gist is a signal processing circuit including an offset cancel voltage supply circuit that generates an offset cancel voltage that cancels the offset voltage based on the offset voltage obtained by the arithmetic unit and outputs the offset cancel voltage to the A / D converter.

According to an eighth aspect of the present invention, in the signal processing circuit according to the seventh aspect, the information in which the read signal included in a part of the data information is a sine wave is a preamble recorded before the user data. A signal processing circuit that is a pattern is the gist of the invention.

(Operation) According to the invention of claim 1, when the processing section for servo information is performing digital conversion processing of the read signal of the servo information, the digital section provided in the processing section for data information. The offset voltage of the A / D converter for conversion processing is detected, and the offset voltage of the A / D converter is canceled. As a result, the offset canceling process of the A / D converter is performed every time the servo control is performed, so that the conversion can always be performed with high accuracy even if the ambient temperature changes.

According to the second aspect of the invention, the discriminator compares the digital value output from the A / D converter with a predetermined permissible value when the input voltage disappears, and the digital value is within the permissible value. Determine whether or not. If the digital value is not within the allowable value, the arithmetic unit cumulatively adds a predetermined offset unit change amount. The offset cancel voltage supply circuit generates an offset cancel voltage for canceling the offset voltage of the A / D converter based on the added value and outputs it to the A / D converter. As a result, the process for offset cancellation of the A / D converter is simply and automatically performed.

According to the invention of claim 3, the switch is the first
When the processing unit of (1) is digitally converting the read signal of the servo information, the servo information is blocked from being input to the A / D converter. When the servo information is cut off, the control circuit operates the A / D converter. The discriminator compares the digital value from the A / D converter with a predetermined allowable value and determines whether or not the digital value is within the allowable value. If the digital value is not within the allowable value, the arithmetic unit cumulatively adds a predetermined offset unit change amount. Further, when it is within the allowable value, the arithmetic unit cumulatively sets the offset unit change amount to 0. The offset cancel voltage supply circuit outputs the added value from the arithmetic unit to the A / D converter as an offset cancel voltage.

As a result, the offset canceling process of the A / D converter is performed every time the servo control is performed, so that the conversion can always be performed with high accuracy even if the ambient temperature changes. Moreover, the process for offset cancellation of the A / D converter is simply and automatically performed.

According to the invention of claim 4, the amplifier amplifies the data information and inputs it to the A / D converter. The switch blocks the servo information from being input to the amplifier when the first processing unit is digitally converting the read signal of the servo information. When the servo information is cut off by the switch, the first control circuit operates the A / D converter. The discriminator compares the digital value output from the A / D converter in the cutoff state with a predetermined allowable value to determine whether the digital value is within the allowable value. If the digital value is not within the allowable value, the arithmetic unit cumulatively adds a predetermined offset unit change amount.
In addition, when it is within the allowable value, the arithmetic unit cumulatively adds the offset unit change amount at that time as 0. The offset cancel voltage supply circuit outputs the added value from the arithmetic unit as an offset cancel voltage to the A / D converter via the amplifier. When the digital value is within the allowable value, the second control circuit controls to increase the amplification factor of the amplifier, and at the same time, reduces the amplification factor of the arithmetic unit with a reduction factor inversely proportional to the increase factor of the amplification factor. Control is performed so that the offset unit change amount is reduced and cumulative addition is performed.

As a result, the offset canceling process of the A / D converter is performed every time the servo control is performed, so that the conversion can always be performed with high accuracy even if the ambient temperature changes. Moreover, the process for offset cancellation of the A / D converter is simply and automatically performed.

According to the invention of claim 5, the signal is 1
The average value of the digital values of the front and rear two signals read at 80 degree intervals becomes the offset voltage itself of the A / D converter. The offset voltage of the A / D converter is canceled based on the average value. Therefore, the offset cancellation is performed every time when the data information is read, so that highly accurate conversion can be always performed even if the ambient temperature changes.

According to the sixth aspect of the present invention, the A / D converter inputs the sine wave input signal from the input signal supply means and performs digital conversion. The sampling control circuit controls the A / D converter to digitally convert a sine wave input signal at intervals of 180 degrees. The arithmetic unit inputs two digital values before and after being digitally converted by the A / D converter, calculates an average value of both digital values, and outputs the average value as an offset voltage at that time. The offset cancel voltage supply circuit generates an offset cancel voltage that cancels the offset voltage based on the offset voltage calculated by the arithmetic unit, and outputs the offset cancel voltage to the A / D converter.
As a result, just inputting a sine wave input signal
The process for offset cancellation of the converter is easily and automatically performed.

According to the invention of claim 7, the sampling control circuit digitally converts the read signal of the information which becomes the sine wave and is inputted to the A / D converter at intervals of 180 degrees. The arithmetic unit inputs two digital values before and after the 180-degree interval digitally converted by the A / D converter, calculates an average value of both digital values, and outputs the average value as an offset voltage at that time. The offset cancel voltage supply circuit generates an offset cancel voltage that cancels the offset voltage based on the offset voltage calculated by the arithmetic unit, and outputs the offset cancel voltage to the A / D converter.

Therefore, the offset cancellation is performed every time the data information is read, so that even if the ambient temperature changes, highly accurate conversion can be performed. Moreover, the process for offset cancellation of the A / D converter can be easily and automatically performed only by inputting the information that becomes a sine wave.

According to the invention of claim 8, since the information in which the read signal included in a part of the data information is a sine wave is the preamble pattern recorded before the user data, the user data is processed. Since the offset cancellation is always performed before the operation, the conversion can always be performed with high accuracy even if the ambient temperature changes.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the configuration of a magnetic disk device.
The magnetic disk 21 as a recording medium is rotated by a motor (not shown). The drive head 22 is attached to the tip of the arm 23. The arm 23 has a base end connected to the motor 24. When the motor 24 rotates in the normal and reverse directions, the arm 23 rotates in the normal and reverse directions. The drive head 22 moves in the radial direction of the magnetic disk 21 by the rotation of the arm 23. Drive head 22
Is composed of a magnetic head for reading data recorded on the magnetic disk 21 and writing data on the magnetic disk 21.

FIG. 3 shows an outline of the recording format of each sector of the magnetic disk 21. Each sector 30 is roughly divided into a servo information section 31 and a data information section 32. The servo information section 31 is an area in which the servo information of the sector 30 is recorded. The drive head 22 is adapted to seek the position of the target sector 30 by performing servo control based on the servo information recorded in the servo information section 31.

The data information section 32 includes the preamble part 3
2a, a training section 32b, a data section 32c and the like. The preamble part 32a is recorded with a preamble pattern as a part of the data information for determining the timing of reading the user data forming the data information recorded in the subsequent data part 32c, and all the preamble patterns are "1". Is recorded.
Incidentally, when the drive head 22 reads a preamble pattern having all contents “1”, the read signal RD becomes a sine wave. Since the preamble pattern is for determining the timing of reading the user data recorded in the data portion 32c, the preamble patterns recorded in the preamble portion 32a of each sector 30 are all the same pattern.

The read signal RD read by the drive head 22 is output to the signal processing circuit 40. The amplifier 41 provided in the signal processing circuit 40 uses the read signal RD
Is amplified and output to the signal processing unit 42. Signal processing unit 42
Is the read signal R read from the servo information section 31.
It includes a first processing unit 42a for signal processing D, and a second processing unit 42b for signal processing the read signal RD read from the data information section 32.

FIG. 2 shows a second processing section 42b which processes the read signal RD read from the data information section 32.
2 shows a block circuit of a main part of FIG. In FIG. 2, the gain control amplifier 43 inputs the read signal RD through the analog switch 44, amplifies the read signal RD, and the A / D converter 45.
Output to The A / D converter 45 uses the read signal RD
Is treated as an analog output and the analog value is digitally converted into a digital value. In the present embodiment, the A / D converter 45 converts the read signal RD, which is an analog signal, into a 6-bit digital value D.

The read signal RD converted into the 6-bit digital value D is binarized by being compared with a reference value by a comparator (not shown). Then, the binarized read signal RD
Is output to the disk controller 46 at the next stage. The disk controller 46 uses the binarized read signal R
D is input, the user data recorded in the data section 32c of the data information section 32 is extracted, and output to the external device via the input / output interface 47. Further, the disk controller 46 extracts the preamble pattern recorded in the preamble part 32a, and the A / D converter 4
The sampling signal for determining the sampling period of 5 is generated and output to the signal processing circuit 40.

Next, the offset cancel circuit 50 provided in the processing section 42b will be described. In FIG. 2, the discriminator 51 inputs the read signal RD converted into the 6-bit digital value D from the A / D converter 45. Further, the discriminator 51 includes a serial interface 52.
The 6-bit offset allowable values K and -K are input from the disk controller 46 via. In the present embodiment, the allowable values K and -K are set to decimal numbers 1 and -1.

When -K <D <K (decimal -1 <D <
1), the discriminator 51 outputs the determination signal J of “0” to the control circuit 53.
Output to When D ≦ −K (D ≦ −1 in decimal), the discriminator 51 outputs the determination signal J of “1” to the control circuit 53. When K ≦ D (1 ≦ D in decimal), the discriminator 51 outputs the determination signal J of “−1” to the control circuit 53.

The control circuit 53 as the first and second control circuits receives the servo control signal SB from the disk controller 46 and receives the offset cancel mode (hereinafter,
It is simply called the cancel mode). The control circuit 53 is connected to the analog switch 44, and turns off the analog switch 44 in the cancel mode to block passage of the read signal RD. The control circuit 53 is connected to the gain control amplifier 43 and controls the amplification factor of the amplifier 43. In the cancel mode, the control circuit 53 outputs a control signal for increasing the amplification factor of the amplifier 43 to twice the amplification factor in the read operation in a predetermined order.
Output to 3. Further, the control circuit 53 outputs a control signal for returning to the original amplification factor, that is, the amplification factor at the time of the read operation, to the amplifier 43 in the modes other than the cancel mode.

In the cancel mode, the control circuit 53 is based on the judgment signal J from the discriminator 51 and the multiplier 54.
And the adder 55 to the first and second operation control data Ja, J
b is output. The judgment signal J is "1" or "-".
When it is “1”, the control circuit 53 outputs the first operation control data Ja of “1” to the multiplier 54. When the amplification factor of the amplifier 43 is doubled, the control circuit 53 causes the multiplier 54 to output the first calculation control data Ja of "1" to "1/2".
Is output.

When the judgment signal J is "0", the control circuit 5
3 outputs the first operation control data Ja of “0” to the multiplier 54. Further, when the determination signal J is "-1" or "0", the control circuit 53 outputs the second operation control data Jb of "-1" to the adder 55. When the determination signal J is “1”, the control circuit 53 outputs the second operation control data Jb of “1” to the adder 55.

The multiplier 54 forming the arithmetic unit multiplies the offset unit change amount T held in the first register 56 by the first arithmetic control data Ja. That is, when the first calculation control data Ja is “1”, the multiplier 54 determines that the multiplication value Ta
(= 1 × T) is output to the adder 55. When the first operation control data Ja is “½”, the multiplier 54 outputs the multiplication value Ta (= (1/2) × T = T / 2) to the adder 55. Further, when the first calculation control data Ja is “0”,
The multiplier 54 adds the multiplication value Ta (= 0 × T = 0) to the adder 5
5 is output. The offset unit change amount T held in the first register 56 is input from the disk controller 46 via the serial interface 52.

The adder 55 constituting the arithmetic unit calculates the multiplication value Ta from the multiplier 54 based on the second arithmetic control data Jb.
(T, T / 2, or 0) and the cancel accumulated value H held in the second register 57 are added. When the second operation control data Jb is “1”, the adder 55 adds the cancellation accumulation value H and the multiplication value Ta, and the addition value (= H + T).
A) is output as a new cancellation accumulated value H to the second register 57 via the selector 58. When the second calculation control data Jb is “−1”, the adder 55 causes the multiplication value T
a is made negative and the negative multiplication value Ta is added to the cancellation accumulation value H, and the addition value (= H-Ta) is set as a new cancellation accumulation value H to the second register 57 via the selector 58. Output.

The selector 58 inputs the initial value H0 from the serial interface 54 and the addition value of the adder 55, that is, a new cancellation accumulation value H, and either one of them is selected based on the selection signal SEL from the control circuit 53. The value is output to the second register 57. That is, the control circuit 53 causes the selection signal S to select the initial value H0 at the same time when the cancel mode is entered.
The EL is output to the selector 58, and then the selection signal SEL for selecting a new cancellation accumulated value H is output to the selector 58. Therefore, in the cancel mode, the second register 57 holds the initial value H0 at the same time as the cancel mode, and then holds the accumulated value H from the adder 55. The initial value H0 is adapted to be input from the disk controller 46 via the serial interface 54 at the same time when the cancel mode is entered.
The operation timings for the arithmetic operations of the multiplier 54, the adder 55 and the register 56 are performed based on the control signal from the control circuit 53.

The cancellation accumulated value H of the second register 57 which constitutes the arithmetic unit is output to the D / A converter 59. D / that constitutes the offset cancel voltage supply circuit
The A converter 59 converts the cancellation accumulated value H into an analog voltage. That is, the larger the cancel accumulated value H, the larger the analog voltage becomes. D
The analog voltage converted by the A / A converter 59 is applied to the resistors 60 and 61 forming the offset cancel voltage supply circuit.
Is applied to the voltage dividing circuit. The voltage (divided voltage) at the connection point of the resistors 60 and 61 is determined by the resistance ratio of the resistors 60 and 61, and this divided voltage is used as the offset cancel voltage Vc to connect the analog switch 44 and the gain control amplifier 43 via the resistor 62. It is applied to the connecting signal line 63.
Therefore, the potential of the signal line 63 is changed by this offset cancel voltage Vc.

Next, the operation of the signal processing circuit 40 configured as described above will be described. When the hard disk device is in the servo control mode for seeking the drive head 22 to the target sector 30 for reading data, the disk controller 46 outputs the servo control signal SB to the second processing unit 42b. The control circuit 53 of the second processing unit 42b turns off the analog switch 44 based on the servo control signal SB. Therefore, during the servo control mode, the read signal RD read from the drive head 22 is not output to the gain control amplifier 43. That is, during the servo control mode, the read signal RD read from the drive head 22 is output to the first processing unit 42a that processes the read signal RD read from the servo information section 31 of the sector 30. Signal processing is performed in the processing unit 42a.

The control circuit 53 also controls the servo control signal SB.
The cancel mode is set based on. When in the cancel mode, the disk controller 46 selects the selector 58.
The initial value H0 (H0 = 0 for convenience of explanation) is input to the second register 57 via the, and the offset unit change amount T is input from the disk controller 46 to the first register 56 via the selector 58. It

Further, the discriminator 51 receives the offset allowable values K and −K from the disk controller 46 and the digital value D from the A / D converter 45. At this time, the potential of the signal line 63 of the gain control amplifier 43 becomes 0 potential because the read signal RD disappears. Therefore, the digital value D of the A / D converter 45 is 0 when it does not have an offset voltage.

If the A / D converter 45 has the digital value D equal to or less than the offset allowable value -K, that is, the offset voltage, the discriminator 51 outputs the determination signal J of "1" to the control circuit 53. . The control circuit 53 outputs the judgment signal J of "1".
Based on the first calculation control data J of “1”
a is output and the second operation control data J of "1" is output.
b is output to the adder 55.

The multiplier 54 multiplies the offset unit change amount T held in the first register 56 by the operation control data Ja and outputs the multiplication value Ta (= 1 × T) to the adder 55. The adder 55 calculates the multiplication value Ta (= T) from the multiplier 54 and the cancellation accumulation value H (the initial value H0 in this case) held by the second register 57 based on the second operation control data Jb of "1". (= 0) and addition (= 0 + Ta) is performed. The adder 55 outputs this added value (= Ta = T) to the second register 57 via the selector 58 as a new cancel accumulated value H (= T).

The cancellation accumulated value H (= T) held in the second register 57 is output to the D / A converter 59. The D / A converter 59 converts the cancellation accumulated value H into an analog voltage. The analog voltage converted by the D / A converter 59 is divided by a voltage dividing circuit including resistors 60 and 61, and this divided voltage is used as an offset cancel voltage Vc via the resistor 62 through the analog switch 44 and the gain control amplifier 43. Is applied to the signal line 63 that connects Therefore, the potential of the signal line 63 rises by the offset cancel voltage Vc.

When the potential of the signal line 63 increases from 0 volt by the offset cancel voltage Vc, the gain control amplifier 43 amplifies the increased voltage Vc and outputs A.
Output to the / D converter 45. A / D converter 45
Converts the amplified input voltage into a digital signal. The digital value D at that time increases to the plus side by the amount of the applied offset cancel voltage Vc (that is, the digital value D
Approaches the value side of 0). Then, the digital value D approaching the value side of 0 is input to the discriminator 51 as described above.

When the increased digital value D is still equal to or less than the offset allowable value -K, the discriminator 51 outputs the determination signal J of "1" to the control circuit 53 as described above.
The control circuit 53 controls the multiplier 5 based on the determination signal J of "1".
The first operation control data Ja of “1” is output to the No. 4 and the second operation control data Jb of “1” is output to the adder 55.

Therefore, the multiplier 54 has the multiplication value Ta (=
T) is output to the adder 55. The adder 55 adds the multiplication value Ta (= T) from the multiplier 54 and the cancellation accumulation value H (= T) held by the second register 57 based on the second operation control data Jb of “1”. (= T + T) is performed. The adder 55 outputs the added value (= 2T) to the second register 57 as a new cancel accumulated value H (= 2T). The D / A converter 59 has a cancel accumulated value H (=
2T) is converted to an analog voltage. D / A converter 5
The analog voltage converted by 9 is divided by the voltage dividing circuit,
This divided voltage is applied to the signal line 63 after being increased by the same potential as the offset cancel voltage Vc. Therefore, the potential of the signal line 63 further increases.

When the potential of the signal line 63 further increases from the previous offset cancel voltage Vc, the gain control amplifier 43 amplifies the increased voltage Vc and A / D.
Output to the converter 45. The A / D converter 45 digitally converts the amplified input voltage. The digital value D at that time is increased to the plus side by the voltage further applied from the previous offset cancel voltage Vc (that is,
The digital value D approaches the value side of 0). Then, the digital value D approaching the value side of 0 is input to the discriminator 51 as described above.

Then, the increased digital value D is -K
When <D <K, the discriminator 51 outputs the determination signal J of “0” to the control circuit 53. The control circuit 53 outputs the first operation control data Ja of “0” to the multiplier 54 based on the determination signal J of “0” and outputs the second operation control data Jb of “1” to the adder 55. .

The control circuit 53 outputs the first operation control data Ja of "0" to the multiplier 54 on the basis of the judgment signal J of "0" and the second operation control data Jb of "1" is added by the adder 55. Output to.

The multiplier 54 multiplies the offset unit change amount T held in the first register 56 by the operation control data Ja and outputs the multiplication value Ta (= 0 × T) to the adder 55. The adder 55 calculates the multiplication value Ta (= 0) from the multiplier 54 and the cancellation accumulation value H (= 2 held by the second register 57 based on the second operation control data Jb of “1”.
Addition (= 0 + 2T) with T). The adder 55 uses the addition value (= 2T) as a new cancellation accumulation value H (= 2T).
T) is output to the second register 57 via the selector 58. Therefore, in this case, the potential applied to the signal line 63 remains the offset cancel voltage Vc based on the previous cancellation accumulated value H (= 2T).

On the other hand, the control circuit 53 outputs a control signal for doubling the amplification factor of the gain control amplifier 43 based on the judgment signal J of "0". Therefore,
The amplifier 43 amplifies the voltage applied to the signal line 63 with a double amplification factor and outputs it to the A / D converter 45.
As a result, the A / D converter 45 digitally converts the input voltage amplified by this double amplification factor. The digital value D (offset voltage) at that time increases to the minus side by the voltage doubled. Then, the increased digital value D is input to the discriminator 51 as described above.

When the digital value D becomes equal to or less than the offset allowable value -K due to the increase, the discriminator 51 outputs the determination signal J of "1" to the control circuit 53 as described above. The control circuit 53 outputs the first calculation control data Ja of “1/2” to the multiplier 54 based on the determination signal J of “1”, and the second calculation control data Jb of “1” to the adder 55. Output.

Therefore, the multiplier 54 has the multiplication value Ta (= T
/ 2) is output to the adder 55. The adder 55 is "1"
Based on the second operation control data Jb of the above, the addition value Ta (= T / 2) from the multiplier 54 and the cancellation accumulation value H (= 2T) held in the second register 57 are added (= 5T / 2).
I do. The adder 55 outputs the added value (= 5T / 2) to the second register 57 as a new cancellation accumulated value H (= 5T / 2).

The D / A converter 59 converts the cancellation accumulated value H (= 5T / 2) into an analog voltage. D / A
The analog voltage converted by the converter 59 is divided by the voltage dividing circuit, and the divided voltage is further increased by the same potential as the offset cancel voltage Vc and applied to the signal line 63. Therefore, the potential of the signal line 63 further increases.

When the potential of the signal line 63 further increases from the previous offset cancel voltage Vc, the gain control amplifier 43 amplifies the increased voltage Vc and A / D.
Output to the converter 45. The A / D converter 45 digitally converts the amplified input voltage. The digital value D at that time is increased to the plus side by the voltage further applied from the previous offset cancel voltage Vc (that is,
The digital value D approaches the value side of 0). The digital value D approaching the value side of 0 is input to the discriminator 51 as described above.

When the digital value D becomes -K <D <K, the discriminator 51 outputs the determination signal J of "0" to the control circuit 53.
Output to The control circuit 53 outputs the first operation control data Ja of “0” to the multiplier 54 based on the determination signal J of “0” and outputs the second operation control data Jb of “1” to the adder 55. .

The control circuit 53 outputs the first operation control data Ja of "0" to the multiplier 54 based on the judgment signal J of "0", and the second operation control data Jb of "1" is added by the adder 55. Output to.

The multiplier 54 outputs the multiplication value Ta (= 0 × T) to the adder 55. The adder 55 calculates the multiplication value T from the multiplier 54 based on the second operation control data Jb of "1".
Addition (= 0 + 5T / 2) is performed with a (= 0) and the cancellation accumulated value H (= 5T / 2) held by the second register 57. The adder 55 uses the added value (= 5T / 2) as a new cancel accumulated value H (= 5T / 2) and the selector 58.
To the second register 57 via. Therefore, in this case, the potential applied to the signal line 63 remains the offset cancel voltage Vc based on the previous cancellation accumulated value H (= 5T / 2).

In this embodiment, when this state is reached, the control circuit 53 stops the process for offset cancellation. In this state, when the servo control ends and the target sector 30 is reached, the disk controller 46
Disappears the servo control signal SB. Servo control signal S
When B disappears, the control circuit 53 terminates the offset cancel mode and puts the offset cancel voltage Vc based on the cancellation accumulated value H (= 5T / 2) stored in the second register 57 into the signal line 63. To do. Therefore, at this time, the offset voltage of the A / D converter 45 is canceled by the offset cancel voltage Vc. Further, the control circuit 53 outputs a control signal for returning the gain of the gain control amplifier 43 to the original gain based on the end of the offset cancel mode.

Further, the control circuit 53 turns on the analog switch 44 and sends the read signal RD from the drive head 22 to the A / D via the gain control amplifier 43.
The state of read operation that enables input to the converter 45 is set.
Therefore, the read signal RD (data recorded in the data information section 32 of the sector 30) output from the drive head 22 is converted into the read signal RD converted into the digital value D by the A / D converter 45. At this time, A / D
Since the offset voltage that the converter 45 has at that time is canceled by the offset cancel voltage Vc, the converter 45 passes through the origin and has a one-to-one characteristic L1 as shown by the solid line in FIG. As a result, the A / D converter 45 can perform extremely high precision digital conversion of the analog output read signal RD.

Then, thereafter, each time the servo control mode is entered, that is, immediately before the read operation, the control circuit 53 enters the offset cancel mode to detect the offset voltage of the A / D converter 45 similar to the above and cancel the offset. The processing operation of is performed. In the above embodiment, the case where the offset voltage is negative has been described, but when the offset voltage is positive, it is canceled by subtracting the offset cancel voltage Vc.

Next, the effects that can be found from the above embodiment will be described below. (1) The offset cancel processing operation for canceling the offset voltage of the A / D converter 45 is performed every time servo control is performed, that is, always immediately before the read operation. Therefore, even if the characteristic of the digital value (output) with respect to the analog value (input) in the A / D converter 45 varies depending on the ambient temperature, the offset voltage is always canceled. As a result, the A / D converter 45 can perform highly accurate digital conversion in any state.

(2) Every time servo control is performed, A / D
Since the converter 45 performs the offset cancellation, it is not necessary to perform the inspection for the offset cancellation before shipping.

(3) In the offset cancel processing operation, even after the digital value D (offset voltage) of the A / D converter 45 is within the allowable value (-K <D <K),
The amplification factor of the gain control amplifier 43 is doubled, the offset voltage is doubled, and offset cancellation is performed on the expanded offset voltage. That is, the offset voltage of 1 LSB or less of the A / D converter 45 is detected. Therefore, A / D
Since the offset voltage of 1 LSB or less of the converter 45 can be canceled, more accurate digital conversion can be performed.

(4) Second processing section 42b during servo control
Since the offset cancel circuit 50 of FIG. 3 performs the offset cancel processing operation of the A / D converter 45, the offset cancel circuit 50 can cancel the offset without causing any trouble in the signal processing of the data recorded in the data information section 32 by the processing section 42b. .

The present invention is not limited to the above embodiment, but may be implemented in the following modes. (1) Although the amplification factor of the gain control amplifier 43 is changed to double, it may be changed to 1.5 times or 3 times as appropriate.

(2) The gain of the gain control amplifier 43 is changed once, but the number of changes may be changed appropriately. Also, the amplification factor is 1.5 times in addition to 2 times and 4 times.
It may be changed such as double, double 2.5 times.

(3) In the above embodiment, the initial value H0 was set to 0 for the sake of convenience. However, for example, an offset cancel voltage capable of canceling the offset voltage determined by manufacturing variations is set to the initial value H0. May be.

(4) In the above embodiment, the offset cancel voltage Vc is applied to the signal line 63 of the gain control amplifier 43, but the gain control amplifier 43 is used.
It may be applied to the signal line between the A / D converter 45 and the A / D converter 45.

(5) Although it is embodied in a magnetic disk device,
It may be embodied in an A / D converter of another disk device such as an optical disk device. (6) It may be embodied in an A / D converter other than the disk device.

(7) The offset cancel circuit 50 may be used for checking the offset voltage before shipment. That is, by calculating the offset accumulated value H at that time before shipment, the offset voltage due to manufacturing variations can be calculated.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 4 and 5. In this embodiment, a preamble portion 32a provided in the data information section 32 for each sector 30 of the magnetic disk 21 is used.
It focuses on the preamble pattern recorded in. That is, as described in the above embodiment, "1" is recorded in all preamble patterns. Then, when the preamble pattern is read by the drive head 22, the read signal RD becomes a sine wave. FIG. 5 shows the drive head 2 for the preamble pattern.
2 shows the waveform of the read signal RD read from No. 2. That is, the central portion of the 1-bit recording area is magnetized most strongly to the N pole (“1”), and the boundary portion between the 1-bit recording areas is weakly magnetized to the N pole. Therefore, the read signal RD becomes a sine wave in which the maximum amplitude value of the portion magnetized to the N pole is the maximum, and the minimum amplitude value of the portion magnetized to the N pole is the minimum.

Then, the read signal RD which is a sine wave is set to A
When there is no offset voltage in the A / D converter 45 during digital conversion by the / D converter 45, the maximum amplitude value of the portion magnetized to the N pole is the strongest and N is the weakest.
The absolute value is equal to the minimum amplitude value of the pole magnetized portion. Then, when the absolute values are not equal, it means that the A / D converter 45 has an offset voltage, and 1/2 of the difference is the offset voltage.

The present embodiment is based on the above premise, and the offset cancel circuit 50 of the first embodiment is different. Therefore, for convenience of explanation, the same components are designated by the same reference numerals and the details thereof are omitted.

FIG. 4 shows an essential block circuit of the second processing section 42b provided in the signal processing circuit 42 for processing the read signal RD read from the data information section 32.

The offset cancel circuit 70 includes a control circuit 71, first to third registers 72a to 72c, an average value calculator 73, an adder 74, a selector 75, a serial interface 76, a D / A converter 77 and a resistor 78a to.
And 78c.

Control circuit 7 as sampling control circuit
No. 1 is in the cancel mode only for a certain period (while the read signal RD of the preamble pattern is output) when the servo control signal SB from the disk controller 46 disappears. The control circuit 71 is connected to the analog switch 44, and turns off the analog switch 44 when the servo control signal SB is being output.
Disappears, the analog switch 44 is turned on. The control circuit 71 is connected to the gain control amplifier 43, and outputs a control signal for increasing the amplification factor of the amplifier 43 to twice the amplification factor of the read operation in the cancel mode. In addition, the control circuit 71 outputs a control signal to the amplifier 43 to restore the original amplification factor, that is, the amplification factor at the time of the read operation, to the amplifier 43 in the modes other than the cancel mode.

The control circuit 71 also controls the servo control signal SB.
Disappears, the sampling signal CK is input from the disk controller 46, the sampling signal CK is output to the A / D converter 45, and is output to each circuit of the offset cancel circuit 70. A / D converter 45
Responds to the rising edge of the sampling signal CK and converts the analog value of the read signal RD at that time into a digital value D.

The output timing of the sampling signal CK is predetermined. That is, as shown in FIG.
The read signal RD in the bit storage area is detected at four positions at 90-degree intervals. Therefore, when the A / D converter 45 digitally converts the read signal RD in the 1-bit storage area, if there is no offset voltage in the A / D converter 45, they are sampled every other one, that is, at intervals of 180 degrees. The sum of the digital values D becomes 0. When there is an offset voltage, 1/2 of the sum of the digital values D sampled every other is the offset voltage.

The first register 72a constituting the arithmetic unit is
A / D converter 45 in response to the sampling signal CK
The read signal RD converted to the 6-bit digital value D from is input, and the digital value D previously stored and held is output to the second register 72b in the next stage. The second register 72b constituting the arithmetic unit inputs the digital value D from the first register 72a in response to the sampling signal CK, and the digital value D previously stored and held is stored in the average value arithmetic unit 73 of the next stage. Output to.

The average value calculator 73 constituting the calculator receives the digital value D from the second register 72b and the digital value D from the A / D converter 45 in response to the sampling signal CK. That is, the average value calculator 73 receives two digital values D before and after sampled at every other interval, that is, at 180-degree intervals. Average value calculator 73
Calculates the average value Tb, that is, the offset voltage by adding the two digital values D and then dividing by two.

That is, as described above, when the A / D converter 45 has no offset voltage, one of them is positive and the other is negative, and their absolute values are the same. Therefore, the sum of the digital values D is 0. Become. If there is an offset voltage, one is positive and the other is negative, and the absolute values are different, so the average value is the offset voltage of the A / D converter 45 at that time. The direction of the offset voltage can be known by the sign of the average value. The positive average value Tb at this time is
The offset voltage exists on the plus side (corresponding to the characteristic L2 in FIG. 7), and in the case of the negative average value Tb, the offset voltage exists on the minus side (corresponding to the characteristic L3 in FIG. 7). When the amplification factor of the amplifier 43 is doubled, the arithmetic unit 73 halves the average value Tb based on the control signal from the control circuit 71 and outputs it.

The average value calculator 73 calculates the calculated average value Tb,
That is, the offset voltage is reversed in polarity and output to the adder 74. In response to the sampling signal CK, the adder 74, which constitutes a calculator, adds the average value Tb (offset voltage) from the average value calculator 73 and the cancellation accumulated value H held by the third register 72c. The adder 74 adds the cancel accumulated value H and the average value Tb, and adds the added value (= H ±
Ta) as a new cancellation accumulated value H and the selector 75
To the third register 72c via.

The selector 75 inputs the initial value H0 from the serial interface 76 and the added value of the adder 74, that is, a new cancel accumulated value H, and selects one of them based on the selection signal SEL from the control circuit 71. The value is output to the third register 72c. That is, the control circuit 71 outputs the selection signal SEL for selecting the initial value H0 to the selector 75 at the same time when it enters the cancel mode, and then outputs the selection signal SEL for selecting a new cancel accumulated value H to the selector 75.
Output to Therefore, the third register 72c holds the initial value H0 at the same time when it enters the cancel mode, and then holds the accumulated value H from the adder 74. The initial value H
0 is input from the disk controller 46 via the serial interface 76 at the same time when the cancel mode is entered.

The third register 72c constituting the arithmetic unit is
A new cancellation accumulated value H is input in response to the sampling signal CK, and the accumulated value H is output to the D / A converter 77. The D / A converter 77 that constitutes the offset cancel voltage supply circuit converts the cancel accumulated value H into an analog voltage. The analog voltage converted by the D / A converter 77 is applied to the voltage dividing circuit including the resistors 78a and 78b that form the offset cancel voltage supply circuit. Voltage at connection point of resistors 78a and 78b (divided voltage)
Is applied as an offset cancel voltage Vc to the signal line 63 connecting the analog switch 44 and the gain control amplifier 43 via the resistor 78c. Therefore, the potential of the signal line 63 is changed by this offset cancel voltage Vc.

Next, the operation of the second processing section 42b configured as described above will be described. When the servo control of the hard disk device is finished and the servo control signal SB disappears, the control circuit 71 turns on the analog switch 44. Therefore, the second processing unit 42b uses the target sector 30
The read signal RD of the data information section 32 is input. Then, first, the read signal RD based on the preamble pattern recorded in the preamble portion 32a is input. This read signal RD is converted into a digital value D,
It is binarized and output to the disk controller 46.
At this time, the disk controller 46 outputs to the control circuit 71 the sampling signal CK generated based on the binarized read signal RD based on the preamble pattern.

The control circuit 71 also controls the servo control signal SB.
Disappears, the mode becomes the cancel mode for a certain period. When in the cancel mode, the initial value H0 is set in the third register 72c from the disk controller 46 via the selector 75.
(For convenience of explanation, it is assumed that H0 = 0.) Is input.

Further, the first register 72a has an A / D
The first digital value D1 of the read signal RD based on the preamble pattern from the converter 45 is input in response to the sampling signal CK. At this time, the control circuit 71
The average value calculator 73 and the adder 74 are controlled so as not to operate until the third digital value D3 is input to the first register 72a.

When the third digital value D3 is output from the A / D converter 45, the average value calculator 73 outputs the digital value D3 and the digital value D1 from the second register 72b.
And are input to calculate the average value Tb (= (D1 + D3) / 2). This average value Tb is the A / D converter 4 at that time.
The offset voltage is 5. At this time, if the A / D converter 45 has a negative offset voltage, the average value Tb becomes a negative value.

The negative average value Tb is output to the adder 74. The adder 74 uses the average value Tb from the average value calculator 73.
And the cancellation accumulated value H held in the third register 72c
(In this case, initial value H0 = 0) and addition (= 0 + Tb)
I do. The adder 74 outputs the added value (= Tb) as a new cancellation accumulated value H (= Tb) to the third register 72c via the selector 75.

The cancellation accumulated value H (= Tb) held in the third register 72c is output to the D / A converter 77. The D / A converter 77 displays the cancel accumulated value H
To an analog voltage. The analog voltage converted by the D / A converter 77 is divided by a voltage dividing circuit including resistors 78a and 78b, and this divided voltage is used as an offset cancel voltage Vc via the resistor 78c and the analog switch 44 and the gain control amplifier 43. Signal line 6 connecting
3 is applied. The potential of the signal line 63 rises by the offset cancel voltage Vc.

Therefore, since the offset cancel voltage Vc with respect to the average value Tb (offset voltage) obtained by the average value calculator 73 is applied, the A / D converter 45
Offset voltage is canceled.

Then, after the offset cancel voltage Vc is applied, the control circuit 71 once stops the calculation of the average value Ta, and the gain of the gain control amplifier 43 is set to 2%.
Double it. The control circuit 7 again with the amplification factor doubled.
1 calculates the average value Ta. A / D converter 45
Converts the read signal RD in the amplified preamble pattern into a digital signal. Then, the arithmetic processing previously performed is similarly performed to obtain an average value Ta (offset voltage) under the amplifier 43 having a double amplification factor. Since the amplification factor of the amplifier 43 is doubled, the obtained average value Tb is halved, and a new offset cancel voltage is added based on the average value Tb which is ½. Vc is obtained and applied to the signal line 63. Therefore, the offset cancel voltage Vc corresponding to the average value Tb (offset voltage) obtained by the amplifier 43 having the double amplification factor obtained by the average value calculator 73 is applied, and thus the A / D converter 45. The offset voltage of 1 is canceled with a higher precision.

In this embodiment, when this state is reached, the control circuit 71 stops the process for offset cancellation. In this state, when the offset cancel mode for a certain period ends, that is, when the reading of the preamble portion ends, the control circuit 71 sets the offset cancel voltage Vc based on the cancel accumulated value H (= Tb) stored in the third register 72c. The state is applied to the signal line 63. Therefore, at this point, the offset voltage of the A / D converter 45 is equal to the offset cancel voltage V
Canceled at c. Further, the control circuit 71 outputs a control signal for returning the gain of the gain control amplifier 43 to the original gain based on the end of the offset cancel mode.

Therefore, the read signal RD of the training section 32b and the data section 32c of the subsequent data information section 32.
Is converted into a read signal RD converted into a digital value D by the A / D converter 45. At this time, the A / D converter 45 has its own offset voltage canceled by the offset cancel voltage Vc, so that the A / D converter 45 passes through the origin as shown by the solid line in FIG. Becomes As a result, the A / D converter 45
Allows very accurate digital conversion of the analog output read signal RD.

Thereafter, every time the preamble pattern of the preamble part 32a of the data information section 32 is read, the control circuit 71 enters the offset cancel mode and detects the offset voltage of the A / D converter 45 similar to the above to cancel the offset. The processing operation of is performed.
In the above embodiment, the case where the offset voltage is negative has been described, but when the offset voltage is positive, it is canceled by subtracting the offset cancel voltage Vc.

Next, the effects that can be found from the above embodiment will be described below. (1) The offset cancel processing operation of canceling the offset voltage of the A / D converter 45 is performed every time the preamble pattern of the preamble part 32a of the data information section 32 is read. Therefore, even if the characteristic of the digital value (output) with respect to the analog value (input) in the A / D converter 45 varies depending on the ambient temperature, the offset voltage is always canceled. As a result, the A / D converter 45 can perform highly accurate digital conversion in any state.

(2) Each time the preamble pattern of the preamble part 32a is read, the A / D converter 45
Since the offset cancellation is performed, it is not necessary to perform the inspection for the offset cancellation before shipping.

(3) In the offset cancel processing operation, the gain of the gain control amplifier 43 is doubled, the offset voltage is doubled, and the offset cancellation is performed on the expanded offset voltage. . That is, 1 LSB of the A / D converter 45
The following offset voltage is detected. Therefore,
Since the offset voltage of 1 LSB or less of the A / D converter 45 can be canceled, more accurate digital conversion can be performed.

The present invention is not limited to the above embodiment, but may be carried out in the following modes. (1) Although the amplification factor of the gain control amplifier 43 is changed, it may be performed only once without changing it. Also in this case, similar high-accuracy signal processing can be performed, and inspection before shipment can be eliminated.

(2) In the above embodiment, the average value Tb (offset voltage) is calculated based on one average value calculation, but a plurality of average values Tb are calculated and the plurality of average values Tb are calculated.
The average value of b may be used as the offset voltage of the A / D converter 45.

(3) Although the amplification factor of the gain control amplifier 43 is changed to double, it may be changed to 1.5 times or 3 times as appropriate. (4) The gain of the gain control amplifier 43 is changed once, but the number of changes may be changed appropriately. In addition, the amplification rate is 1.5 times, 2 times 2.5, in addition to 2 times and 4 times.
You may change, such as double.

(5) In the above embodiment, the offset cancel voltage Vc is applied to the signal line 63 of the gain control amplifier 43.
It may be applied to the signal line between the A / D converter 45 and the A / D converter 45.

(6) In the above embodiment, the initial value H0 was set to 0 for the sake of convenience. However, for example, the offset cancel voltage capable of canceling the offset voltage determined by the manufacturing variation is set to the initial value H0. May be.

(7) In the above embodiment, the offset voltage is detected based on the read signal RD of the preamble pattern of the preamble section 32a. However, if there is a signal other than the preamble pattern that outputs a sine wave signal, the offset voltage is detected. You may implement using a signal.

(8) In the above embodiment, the processing unit 42a for processing the read signal RD read from the servo information section 31 and the processing for processing the read signal RD read from the data information section 32. Although it is embodied in a disk device including a signal processing unit 42 including a unit 42b,
It may be embodied in a disk device that collectively processes both information sections 31 and 32 and the read signal RD read by one processing unit.

(9) The offset cancel circuit 50 of the first embodiment may be added to the second embodiment. In this case, more accurate offset cancellation can be performed.

(10) Although it is embodied as a magnetic disk device, it may be embodied as an A / D converter for other disk devices such as an optical disk device. (11) It may be embodied in an A / D converter other than the disk device. In this case, it is necessary to create a signal such as the read signal RD of the preamble pattern.

(12) The offset cancel circuit 70 may be used for checking the offset voltage before shipment. That is, the offset voltage due to manufacturing variations can be obtained by inputting a signal such as the read signal RD of the preamble pattern before shipment and obtaining the average value Ta or the accumulated offset value H at that time.

(13) In the above embodiment, the sector format is provided with the servo information section 31 and the data information section 32. However, the sector format does not have the servo information section 31, that is, the so-called servo surface servo system. It may be embodied in a disk device.

In the above embodiments, technical ideas not described in the claims will be described below together with their effects. (1) In a signal processing circuit in which digital conversion processing of read signals of servo information and data information recorded in each sector is performed by different processing units for servo information and data information, a processing unit for servo information is provided. When the read signal of the servo information is subjected to digital conversion processing, the offset voltage of the A / D converter for digital conversion processing provided in the processing section for data information is detected and A / D is detected.
While canceling the offset voltage of the D converter, when the processing unit for the data information performs the digital conversion processing of the read signal of the data information, the read signal of the same pattern recorded in a part of each data information is converted into the signal waveform. The digital value is converted by the A / D converter at 180 degree intervals, and the offset voltage of the A / D converter is detected from the average value of the digital values of the two signals read at the 180 degree intervals. A / in the signal processing circuit that cancels the offset voltage of the converter
Offset canceling method of D converter. Therefore, more accurate offset cancellation can be performed.

[0119]

As described above in detail, according to the present invention, it is not necessary to perform an inspection for offset cancellation in advance, and the A / D at each time is irrelevant regardless of manufacturing variations or ambient temperature fluctuations. There is an excellent effect that the offset voltage of the converter is detected and the offset voltage is canceled to perform highly accurate signal processing.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of a magnetic disk device according to a first embodiment.

FIG. 2 is an electric block circuit diagram of a processing unit according to the first embodiment.

FIG. 3 is a diagram showing an outline of a sector recording format.

FIG. 4 is an electric block circuit diagram of a processing unit according to the second embodiment.

FIG. 5 is an explanatory diagram showing a relationship between a read signal of a preamble pattern and a sampling signal.

FIG. 6 is a block circuit diagram illustrating a conventional offset cancel circuit.

FIG. 7 is a characteristic diagram for explaining an offset voltage of an A / D converter.

[Explanation of symbols]

 21 magnetic disk 22 drive head 30 sector 31 servo information section 32 data information section 32a preamble section 40 signal processing circuit 42 signal processing section 42a first processing section 42b second processing section 43 analog switch 44 gain control amplifier 45 A / D Converter 51 Discriminator 53,71 Control circuit 54 Multiplier 55,74 Adder 59,77 D / A converter 73 Average value calculator K, -K Offset allowable value T Offset unit change amount

Claims (8)

[Claims] 1. A processing for servo information in a signal processing circuit in which digital conversion processing of a read signal of servo information and data information recorded in each sector is performed by different processing units for servo information and data information, respectively. The offset voltage of the A / D converter for digital conversion processing provided in the processing section for data information is detected while the section is performing digital conversion processing of the read signal of servo information A method of canceling an offset voltage of an A / D converter in a signal processing circuit that cancels a voltage. 2. An A / D for converting an input signal into a digital value.
A converter; a discriminator that compares a digital value output from the A / D converter with a predetermined permissible value in a state where the input voltage disappears and discriminates whether or not there is a digital value within the permissible value; When the digital value is not within the allowable value, an arithmetic unit that cumulatively adds a predetermined offset unit change amount, and the added value as an offset cancel voltage for canceling the offset voltage of the A / D converter
An offset voltage cancel circuit for an A / D converter, which comprises an offset cancel voltage supply circuit for outputting to an A / D converter. 3. A signal processing circuit for performing digital conversion processing of a read signal of servo information recorded in each sector and a read signal of data information in the first processing unit for servo information and in the second processing unit for data information, respectively. In the above, in the second processing unit, an A / D converter that digitally converts the data information, and when the first processing unit performs digital conversion processing of a read signal of servo information, the servo information is The A / D
A switch for blocking input to the converter; a control circuit for operating the A / D converter when the first processing unit is performing digital conversion processing on a read signal of servo information; When the processing unit is performing a digital conversion process on the read signal of the servo information, the digital value from the A / D converter is compared with a predetermined allowable value to determine whether the digital value is within the allowable value. Discriminator to perform the above, and if the digital value is not within the allowable value, a predetermined offset unit change amount is cumulatively added, and if it is within the allowable value, the offset unit change amount at that time is set to 0 and cumulative addition is performed. And an offset cancel voltage supply circuit for outputting the added value from the arithmetic unit as an offset cancel voltage to the A / D converter. Signal processing circuit. 4. A signal processing circuit in which digital conversion processing of a read signal of servo information and data information recorded in each sector is performed by a first processing unit for servo information and a second processing unit for data information, respectively. In the second processing unit, an amplifier that amplifies the data information, an A / D converter that digitally converts the data information amplified by the amplifier, and the first processing unit is a servo information controller. A switch for blocking the input of the servo information to the amplifier when the read signal is digitally converted, and a digital conversion process for the servo information read signal by the first processing unit. A first control circuit for operating the A / D converter, and the first processing unit performing digital conversion processing on a read signal of servo information, the A / D A discriminator that compares the digital value from the converter with a predetermined allowable value to determine whether the digital value is within the allowable value, and if the digital value is not within the allowable value, a predetermined offset The unit change amount is cumulatively added, and if it is within the allowable value, an arithmetic unit for cumulatively adding the offset unit change amount at that time as 0, and the added value from the arithmetic unit as an offset cancel voltage via the amplifier. An offset cancel voltage supply circuit for outputting to the A / D converter, and when the digital value is within an allowable value, control is performed so as to increase the amplification factor of the amplifier, and the operation unit of the amplification factor of the amplifier is controlled. A second control circuit for controlling such that the offset unit change amount is reduced at a rate of decrease inversely proportional to the rate of increase and cumulative addition is performed. . 5. A signal processing circuit having a processing unit for digitally converting a read signal of data information recorded in each sector by an A / D converter, the same continuous data recorded in a part of each data information. The read signal of the pattern is converted into a digital value by the A / D converter at 180-degree intervals of the signal waveform, and the offset of the A / D converter from the average value of the two digital values before and after read at the 180-degree intervals. A method for canceling an offset voltage of an A / D converter in a signal processing circuit that detects a voltage and cancels the offset voltage of the A / D converter. 6. An A / D for converting an input signal into a digital value.
A converter, an input signal supply means for inputting a sine wave input signal to the A / D converter, and sampling for controlling the A / D converter to digitally convert the sine wave input signal at intervals of 180 degrees. A control circuit, an arithmetic unit for inputting two digital values before and after being digitally converted by the A / D converter, obtaining an average value of both digital values, and outputting the average value as an offset voltage at that time; An offset voltage cancel circuit for an A / D converter, which comprises an offset cancel voltage that cancels the offset voltage based on the offset voltage obtained by the above and outputs the offset cancel voltage to the A / D converter. 7. A digital conversion process of a read signal of data information including servo information recorded in each sector and a part of the read signal is a sine wave. The servo information is processed by the first processing unit. Is a signal processing circuit respectively performed in a second processing unit, wherein the second processing unit includes an A / D converter that digitally converts the data information, and a signal read by the second processing unit is a sine wave. When the digital read processing of the read signal of the information
A sampling control circuit that controls the read signal of the information that becomes the sine wave that is input to the converter to be digitally converted at an interval of 180 degrees; Then, an arithmetic unit that obtains an average value of both digital values and outputs the average value as an offset voltage at that time; and an offset cancel voltage that cancels the offset voltage based on the offset voltage obtained by the arithmetic unit, and generates the A A signal processing circuit, comprising: an offset cancel voltage supply circuit for outputting to a / D converter. 8. The signal processing circuit according to claim 7, wherein the information in which a read signal included in a part of the data information is a sine wave is a preamble pattern recorded before user data. circuit.