JPH05335953A - A/d converter - Google Patents

Abstract

PURPOSE: To accurately and quickly convert a digital signal by converting the upper bit data of the digital signal by parallel conversion and converting its lower bit data by sequential comparision conversion. CONSTITUTION: The A/D converter is provided with plural parallel type A/D conversion parts 303, 304 for converting an inputted analog signal into plural upper bit data each of which consists of plural bits by parallel conversion and a sequential comparison type A/D conversion part 305 for correcting the least significant bit of each upper bit data and generating lower bit data by converting the converted digital value into an analog value again and sequentially comparing the converted analog value with the inputted analog value. In the case of converting an analog signal into a digital signal, the upper bit data of the digital signal is converted by parallel conversion, the lower bit data is converted by sequential comparison conversion, and at the time of converting the lower bit data, the least significant bit in the upper bit data is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter incorporated in an MCU (micro controller unit) for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art Conventionally, an MCU has a ROM,
Memory such as RAM, memory controller, interrupt controller, clock generator, input / output port and A
It is composed of peripheral devices such as a D converter. When the analog voltage signal recorded on the hard disk and read by the head is input, the AD converter built in the MCU converts the analog voltage value into a digital value such as 4 bits or 8 bits, and converts the analog value. It outputs the digital value to the CPU via the internal bus.
U executes predetermined processing based on these digital values.

[0003]

The conventional AD converter incorporated in the MCU is a successive conversion method in which an input analog voltage is compared with a reference voltage one by one and converted into a digital value, or the input analog voltage is once input. The flash (parallel) method that converts to a digital value of several bits is adopted. However, in the case of the flash method, for example, if an attempt is made to convert to a 10-bit digital value, the number of comparators for converting to a digital value becomes very large, and not only can it not be accommodated in the same chip as the CPU, but also the cost is high. There was a problem of causing the rise of. On the other hand, in the case of the successive approximation method, for example, if an attempt is made to convert into a 10-bit digital value, only one bit of data can be obtained by one operation, so the input analog signal is compared with the reference voltage 10 times. However, there was a problem that conversion could not be performed at high speed.

[0004]

In order to solve such a problem, the present invention provides a plurality of parallel AD converters for converting an input analog signal into a plurality of higher-order bit data each having a plurality of bits. And converting the digital value converted by the plurality of parallel AD converters into an analog value again and performing successive comparison between the converted analog value and the input analog signal. It is provided with a successive approximation type AD conversion unit that corrects the least significant bit and generates lower bit data.

[0005]

Therefore, when an analog signal is converted into a digital signal, the upper bit data of the digital signal is converted by parallel conversion, the lower bit data is converted by successive approximation conversion, and the upper bit data is converted when the lower bit data is converted. Since the least significant bit in the data is corrected, high-accuracy analog-to-digital high-speed conversion can be realized, and the number of parts during conversion can be reduced.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an apparatus using an AD converter according to the present invention. This device is a hard disk control device that controls a hard disk.
In FIG. 1, reference numeral 1 is a control unit that controls reading and writing of data from and to a hard disk by executing a program, and 2 is a peripheral unit including peripheral circuits for controlling the hard disk. These control unit 1 and peripheral unit 2 are one chip. Has been converted.

The control unit 1 controls the CPU 10, the SPM control unit 11 that controls the speed of a motor that rotates a hard disk (hereinafter, SPM), and the voice coil motor (hereinafter, VCM) that positions the head. VCM
The control unit 12, a head control unit 13 that controls the head, an HDC control unit 14 that controls a hard disk control circuit (hereinafter, HDC) described later, and a power supply monitoring unit 15 that monitors the power supplied to the control unit 1. Is being done,
The peripheral section 2 includes comparators 20 to 25, amplifiers 26 to 28, an AD converter 30 that converts an analog signal into a digital signal,
DA converter 3 for converting a digital signal into an analog signal
1, 32, events that control the occurrence of events
The processor array (hereinafter referred to as EPA) section 35 to 37 and a reset circuit 38.

Further, as the components connected to the peripheral portion 2, a head 40, a read / write portion 41 for reading / writing data from / to the head 40, a data separation circuit 42, H.
There are a DC 43, a RAM 44, a bus 45 for exchanging data with a higher-level device such as a personal computer, a VCM driver 46 for driving a VCM, an edge detector 47, an SPM driver 49 for driving an SPM, and transistors Q1 to Q3.

Next, the general operation of the hard disk control device configured as described above will be described. When there is an access request to the hard disk from the host device via the bus 45, HDC 43, and HDC control unit 14, the CPU 1
0 instructs the SPM control unit 11 to rotate the hard disk at a constant speed. This instruction causes SPM
The control unit 11 drives the SPM driver 49 via the EPA 37, and as a result, the rotation of the SPM 48 causes the hard disk to rotate at a constant speed. At this time, the CPU 10
Instructs the VCM control unit 12 to move the VCM to a predetermined position on the hard disk in order to read / write predetermined data from / to the hard disk, and the head control unit 13 to read / write data from / to the hard disk. Instruct you to do so.

That is, the VCM control unit 12 which has received the instruction from the CPU 10 first instructs the VCM driver 46 in the moving direction of the VCM and sends a predetermined digital signal to the DA converter 31. This digital signal is converted into a predetermined amount of analog signal, and then the amplifier 26 and the transistor Q
1, the signal is output to the transistor Q2 via the amplifier 27, and as a result, the VCM is driven by the VCM driver 46, and the head 40 moves to a desired position. On the other hand, the head controller 13 that has received the instruction from the CPU 10 causes the read / write unit 4 to
1 to control the data from the host device via the bus 45, the HDC 43, the RAM 44, and the data separation circuit 42 by the head 40 at a desired position on the hard disk, and the data recorded on the hard disk is the data separation circuit 42. , HDC 43, RAM 44, and bus 45 to the upper device.

Next, FIG. 2 is a block diagram of an AD converter 30 used in such a hard disk controller. In the figure, reference numeral 300 is an AD control unit, 301 is an input circuit for inputting an analog signal selected from n-channel analog signals, 302 is a sample hold circuit for holding the input analog signal for a predetermined time, 303, 30
Reference numeral 4 is a 4-bit parallel AD conversion unit capable of converting an input analog signal into a 4-bit digital value at high speed, and 304 is a 4-bit parallel AD generating the lower 4 bits for converting the analog signal into a 4-bit digital value. Converter, 30
Reference numeral 5 is composed of a small number of parts, and in order to expand the input analog signal to a 10-bit digital value, a successive approximation AD conversion unit for correcting the 8-bit digital value by 1 LSB and generating a lower 2-bit digital value. , 306
Is a register for storing these converted digital data. Also, 307 is a bus interface, 308
Is an internal bus, and 310 is a resistor ladder circuit including a resistor 311 and a tap decoder 312.

That is, when converting an analog signal into a 10-bit digital data signal, first, the 4-bit parallel AD conversion unit 303 converts it into 4-bit digital data to obtain higher 4-bit data. That is, the 4-bit parallel AD conversion unit 303 is divided by the level of the input analog signal and the resistance ladder circuit 310 into the tap / decoder 31.
The 4-bit digital data is generated at high speed by comparison with the reference voltage Vref via 2 and stored in the register 306.
FIG. 3A is a diagram showing a principle of such AD conversion called a flash method. For example, three reference voltages 1 / 4V to 3 / 4V via the tap decoder 312 are compared with comparators # 1 to # 1. The analog input signal INPUT is applied to the + input terminal of each # 3 and the analog input signal INPUT is applied to the + input terminal. The 3-bit comparison result data is converted into 2-bit digital data a and b by the encoder 313 and stored in the register 306. Therefore, in order to obtain 4-bit digital data from the 4-bit parallel AD conversion unit 303, the number of comparators is 2 ⁴ −1.
= 15 are required.

In this way, the 4-bit parallel AD conversion unit 303
4 bits of high-order digital data is generated by, and the analog signal level at that time is, for example, at the level indicated by the cross mark in FIG.
A detailed level is obtained by further dividing the space into 16 parts. That is, at this time, in the tap decoder 312 in the resistance ladder circuit 310, for example, in FIG.
The connection of the reference voltage Vref is changed so that the voltage between them can be divided into 16, and the reference voltage divided into 16 is compared with the analog input voltage by the 4-bit parallel AD conversion unit 304. Digital data is stored in the register 306 as medium 4-bit digital data. Thus, the two 4-bit parallel AD conversion units 3
An analog signal is converted into 8-bit digital data by 03 and 304. In this case, the total number of comparators of the two parallel AD converters is 2 × 15 = 30, and the number of comparators (2 ¹⁶ −1 = 25) when directly converting to 8-bit data.
It is possible to perform AD conversion with an extremely small number of comparators as compared with (5).

The 8-bit digital data thus obtained uses the 8-bit data as high-order definite digital data, and the successive approximation AD conversion unit 305 adds 1 LSB correction and further low-order 2 bits to the digital data. Will be stored in the register as a 10-bit digital signal. FIG. 3C is a diagram showing an example of such a successive approximation A / D conversion unit. In the successive approximation A / D conversion, correction of 1 LSB and lower 2 bits are added to 8-bit digital data generated by the flash method. 1
Used to extend to 0 bit digital data.
As shown in FIG. 3C, when n-bit digital data is confirmed, "1" is added to the least significant bit (n
+1) bit digital data is generated, and this (n + 1)
The bit digital data is converted into an analog signal d by the DA conversion unit 314 and applied to one input terminal of the comparator # 5, and the analog input signal INPUT is applied to the other input terminal. The comparator # 5 compares these signals, and if the output of the comparator # 5 is "H" level, the least significant bit remains "1", and if the output is "L" level, the least significant bit is "0". As a result, (n + 1) -bit data is generated. In addition, in the last 2-bit AD conversion, the least significant bit of the preceding 8-bit data is redundantly converted again. This is performed in order to correct the difference in the data width of 1 LSB between 8-bit data and 10-bit data, and to correct the difference in the influence of noise on the plurality of AD converters. The 10-bit digital data generated in this manner is stored in the register 306, and the CPU via the bus interface 307 and the internal bus 308 as required.
It is output to 10.

Usually, when an analog signal is converted into a digital signal, the least significant bit in the converted data is affected by noise or the like and causes an error. Further, since the amount of this noise changes with time, when the final conversion result is obtained using a plurality of AD converters, the amount of noise in each conversion is superimposed and reflected on the final conversion result. Sometimes. In the present invention, high-order 4-bit data to medium-order 4
When converting bit data or middle 4-bit data to lower 2-bit data, perform conversion including the least significant bit in the upper bits to prevent errors from appearing in the final result. It is the one. As a result, the final conversion value of the digital signal converted by using the plurality of AD converters has an error only in the least significant 10th bit, which is the result of the last AD conversion performed out of all 10 bits. Since it exists, a highly accurate digital signal can be obtained. As described above, when the AD conversion from the upper bit to the lower bit is performed, the correction is performed by including the least significant bit in the upper bits. Therefore, as shown in FIG. , The change between the middle and lower bits does not become discontinuous but has continuous linearity.

[0016]

As described above, according to the present invention,
When converting an analog signal to a digital signal, the upper bit data of the digital signal is converted by parallel conversion that enables high-speed conversion, and the lower bit data is converted by successive approximation conversion with a small number of parts, thus reducing the number of parts. In addition, since the least significant bit in the higher-order bit data is corrected during the successive conversion, the digital signal can be converted with high accuracy and at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus to which an AD converter according to the present invention is applied.

FIG. 2 is a detailed block diagram of the AD converter.

FIG. 3 is a diagram showing an example of conversion by the AD converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control part 2 peripheral part 10 CPU 30 AD converter 300 AD control part 303,304 4-bit parallel AD conversion part 305 successive approximation AD conversion part 306 register 310 resistance ladder circuit # 1- # 6 comparator 314 DA conversion part

Claims (1)

[Claims] 1. An AD converter built in an MCU for converting an input analog signal into a digital signal, wherein a plurality of parallel ADs for converting the input analog signal into a plurality of higher-order bit data each consisting of a plurality of bits. The conversion unit and the digital signals converted by the plurality of parallel AD conversion units are converted into analog signals again,
A successive approximation type AD conversion unit that corrects the least significant bit in the upper bit data and generates lower bit data for bit length extension by performing successive comparison between the converted analog signal and the input analog signal. An AD converter characterized by comprising: