JPH0477116A - Offset-correction system - Google Patents

Abstract

PURPOSE:To automatically perform the offset correction at a digital signal level by extracting sign bits while subtracting an offset correction value from an input digital signal obtained after A/D converting an analog signal and outputting a carry when continuously detecting the identical code. CONSTITUTION:When the output digital signal of the identical polarity is continued over the period corresponding to more than 1/2 of the maximum cycle of the input signal receiving the band limit, an offset detection means 4 transmits the carry after deciding the period is non-input period without input signals and the offset exists. A correction value storage means 5 starts the setting of the offset correction value, and the carry is counted up or down by an addition means for each prescribed cycle during the identical polarity is continued in the output digital signal. Since it indicates the correction value reaches a proper amount when the polarity of the output signal is different from the former sampled value, the increase and decrease of calculated values is stopped, this proper amount of correction value is subtracted from the digital input signal after that, and the offset correction is performed.

Description

[Detailed Description of the Invention] [Summary] Regarding an offset correction method for removing DC offset generated in an A/D converter, etc., when the input analog signal to be handled is an audio signal or an acoustic signal, the input signal is intermittent and Focusing on the fact that there is always a no-signal period, the aim is to set an appropriate offset correction value for this period and automatically perform offset correction at the digital signal level, by A/D converting the analog signal. subtracting means for subtracting an offset correction value from the input digital signal obtained by the input digital signal to output an output digital signal; code extraction means for extracting a sign bit from the output digital signal; offset detection means for outputting a carry when a carry is detected; and correction value storage means for up-counting or down-counting the carry according to the polarity of the sign bit and supplying the counted value to the subtraction means as the offset correction value. The offset correction value is obtained from the digital signal during the no-signal period of the analog signal.

[Industrial application field]

The present invention relates to an offset correction method in an A/D conversion circuit to which analog signals are intermittently input.

BACKGROUND ART Recently, methods have been widely used in which telephone voice signals, broadcast-level audio signals, and the like are converted into digital signals, and data compression and echo cancellation processing are performed using digital circuits.

In this case, if a DC component (offset) generated in the A/D converter is superimposed on the digital signal, it will have a negative effect on subsequent data processing, so it is necessary to remove the offset.

[Conventional technology]

Conventional offset correction methods include a method in which analog integration is performed using the sign bit of a digital signal after A/D conversion, and the integration is subtracted from an analog input signal using a differential amplifier.

Figure 5 shows an offset correction circuit for this purpose.
Regarding the digital signal that has been digitally converted by the A/D conversion circuit, the sign detection circuit 6 checks the sign bit at each sampling period and determines the reference voltage VR*f input to the integrator 7 according to the polarity of the digital signal. The polarity is switched and integration is performed, and the result is added to the differential amplifier circuit 8 and subtracted from the input analog signal to correct the DC offset. This is a method of analogically subtracting this from the input analog signal as equivalent to the integral or offset of the sign. Another method is an offset correction method in which a timing for offset correction is forcibly generated, the input analog signal is stopped during this timing, and the digital output during this period is considered to be equivalent to the offset and is subtracted digitally. There is also.

[Problem to be solved by the invention]

The former analog integration method requires the integrator and arithmetic circuit to be constructed from analog circuits, which poses the problem of increased circuit scale. Further, in the latter method of forcibly providing correction timing, there is a problem that there are restrictions on the applicable method because the signal processing period is interrupted during this correction period.

The present invention was created in view of the above problems, and focuses on the fact that when the input analog signal handled is a voice signal or acoustic signal, the input signal is intermittent and there is always a no-signal period. The purpose of this invention is to automatically perform offset correction at the digital signal level by setting an appropriate offset correction value.

subtracting means 2 for subtracting an offset correction value from a digital signal and outputting an output digital signal; code extraction means 3 for extracting a sign bit from the output digital signal; offset detection means 4 that outputs a carry when the code bit is detected; and a correction value memory that counts up or down the carry according to the polarity of the sign bit and supplies the counted value to the subtraction means (2) as the offset correction value. This problem is solved by the offset correction method of the present invention, which has means 5 and obtains an offset correction value from the digital signal during the no-signal period of the analog signal.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of the offset correction method of the present invention.

As shown in Figure 1, the above problem occurs when the output digital signal of the same polarity continues for a period equivalent to 1/2 or more of the maximum period of the input deca signal obtained by A/D conversion of the analog signal. assumes that it is an unmanned period with no input signal and that an offset exists, and issues a carry. Then, the correction value storage means 5 starts setting the offset correction value, and changes the held count value in the direction of decreasing the offset value by one count corresponding to ILSH of the digital signal. After that, while the output digital signal continues to have the same polarity, the predetermined frequency value is ILS.
It monotonically increases or decreases by H minutes, and the value is subtracted from the input digital signal as the first offset correction value by the subtraction means ÷. If the polarity of the output signal is different from the previous sample value, this indicates that the correction value has reached an appropriate amount, so the count value stops increasing or decreasing, and this appropriate amount of correction value is subtracted from subsequent digital input signals to perform offset correction. .

In this way, the offset correction value can be adjusted during the unmanned period.
Since the setting is automatically made by changing minute amounts of B, the output level of the output digital signal does not suddenly change due to offset correction, and offset correction can be automatically performed without distortion.

〔Example〕

The present invention will be explained in detail below with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, showing a case where offset correction is realized in hardware using a digital circuit.
FIG. 3 is an operation time chart. FIG. 4 is a diagram showing a processing procedure (program) when this method is implemented by a programmable digital signal processor.

In FIG. 2, 1 is an A/D converter that converts an original analog signal such as an audio signal that is intermittently input into a digital signal. In this example, seven telephone voice signals are A/D converted into a frequency band of 0°3 to 3.4 using an 8kHz sampling clock, and this A/D converter l includes a DC amplifier, so there is no drift. It is assumed that a DC shift occurs due to etc., and a DC offset occurs in the input digital signal (2) after A/D conversion.

2 is a subtracter, which receives the digital signal from the A/D converter l.
and an offset correction value (2) consisting of digital data to be described later are input, and an output digital signal (2) obtained by subtracting the latter from the former is output.

3 is a code extraction circuit that extracts a code bit representing polarity from the output digital signal (2) consisting of a plurality of bits. Reference numeral 4 denotes offset detection means, which includes a sign change detection circuit 41 which checks whether the sign bit of the digital output signal has changed from the previous data every sampling period and outputs a detection pulse ■ when a change in sign is detected; Reset by pulse ■ and count sampling clock pulses n
It consists of an advance counter 42. This n is the number of sampling pulses corresponding to a correction period T that is 1/2 or more of the period of the lowest frequency of the original analog signal. In this example, the sampling period is 0.125μ5 (8KHz), and the maximum period corresponding to the lowest frequency of the input signal is l÷
Since 0.3 kI (z = 3.3 ms), the number of clocks that provide 1/2 or more of this period is set to n = 20, and when 20 clocks are counted, a carry ■ is output.

5 is a correction value storage means consisting of an up/down counter;
The carry of the n-ary counter 42 is input to the clock terminal, and if the polarity sign at that time is positive, 1 is added to the count value of the counter at that time, and if it is negative, 1 is subtracted from the count value. The count value of this up/down counter is input to the subtracter 42 as an offset correction amount, and is digitally subtracted from the next digital input.

The operation of the above embodiment will be explained with reference to the time chart shown in FIG.

First, the input digital signal ■ on which the DC offset value A is superimposed is input to the subtracter.If the initial value of the count value of the up-down counter is 0, the offset correction value becomes 0, and the subtracter corrects the offset. Therefore, the input offset value appears as is in the output digital signal. While the original analog signal is being input, the polarity of the output digital signal changes at a time interval slightly larger than 1/2 of the maximum period, so the sign change detection circuit 4
Since the n-ary counter 42 is frequently reset by the reset signal (2) from 1, the carry (2) is not output. When the input of the original analog signal disappears and there is a no-signal period, the same polarity continues as long as the output digital signal ■ includes an offset, so the n-ary counter 42 calculates the period T (2
A carry is output every 0 clock), and the count value of the up/down counter 5 increases or decreases in steps of ILSB of the digital signal every period T in the direction toward the offset value.

Then, if you repeat this process by increasing the correction value by the amount equivalent to ILSB and subtracting it from the input signal, the offset correction value will gradually increase, and when it reaches the correction value equivalent to the offset value, the polarity of the digital signal after correction will be changed. Since the representing sign bit is inverted at intervals shorter than the period T in response to the noise level, the n-ary counter no longer outputs a carry and the correction value setting operation ends.After that, when the original analog signal is input, the subtracter This correction value is subtracted from the input digital signal to output an offset-corrected output digital signal.

When the offset value changes due to drift or the like, the above operation is automatically performed for each unmanned section, and the count value of the up/down counter always outputs the correct offset correction value.

Next, as a second embodiment, a case will be described in which this method is implemented using a digital signal processor (hereinafter referred to as DSP). A/D
The converted analog signal is usually subjected to digital signal processing such as digital compression and echo cancellation by a DSP. A DSP is an LSI that has multipliers, adders, data storage memory, program storage memory, microinstruction control circuits, etc. mounted on a single chip. By repeating addition, the above-mentioned processing that was previously performed in analog circuits is performed digitally.

FIG. 4 shows a processing flow when the function of the offset correction circuit described above is processed by software in a DSP using an offset correction processing program. The input analog signal and sampling period are the same as in FIG. 2.

Sl: Input digital signal X0 at sampling time n is input.

82; Find the input digital signal x' after offset correction by subtracting the previous offset correction value 0Fn-+ held by the offset register in the DSP from X.

S3: Extract the sign Sx of the polarity bit of x'.

S4. S5; Compare Sxa with the sign 5xa-r of the corrected digital signal output one sample before, and if the polarities are the same, increase the count register in the DSP by 1.

If the polarities are different, the process of S9 is performed.

S6. S7. S8: When the value of the count register reaches 20, add 1 or subtract l to the value of the offset register depending on the value of the polarity sign at that time. As a result, the offset correction value held by the offset register is updated to reduce the offset by the ILSB of the input digital signal. If the number does not reach 20, it is not a no-signal period, so SIO processing is performed.

S9. Clear the count register value to 0.

S10: Digital signal X' after correction of the current input by a predetermined main processing program. After digital signal processing is performed on the data, the process returns to step 1 and offset correction processing is performed on the next input data.

In this way, before entering the main processing program, the corrected data after subtracting the offset correction value for the previous sample is monitored, and if the same sign continues for 20 or more data, the offset correction value is updated, and from the next time onwards, the offset correction value is updated. Offset correction is performed using this updated offset correction value, and this is repeated until the number of consecutive identical codes becomes 20 or less, thereby automatically setting the offset correction value to an appropriate value. If this correction method is executed by software using a DSP in this way, offset correction can be easily performed by simply adding a correction program to the front of the main processing program without providing a special circuit.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a small number of digital circuits or digital processing programs, it is possible to automatically correct the offset of the input digital signal, and it is possible to automatically correct the offset of the input digital signal. Efficient offset correction is possible without using large-scale analog circuits.

3-Sign extraction circuit 4-Offset detection means, 41
- sign change detection circuit, 42 - n-ary counter, 5 - up/down counter (correction value storage means).

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the offset correction method of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a timing chart showing the operation of FIG. 2, and FIG. FIG. 5 is a diagram showing a processing flow when the method of the present invention is implemented by software. FIG. 5 is a diagram showing a conventional offset correction circuit. Tsuboshufjir7cho2.7tonesumasaδyumisasulhifte'K
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Claims (1)

[Claims] Subtracting means (2) for subtracting an offset correction value from an input digital signal obtained by A/D converting an analog signal to output an output digital signal, and extracting a sign bit from the output digital signal. code extraction means (3); and offset detection means (4) that examines changes in the code bit and outputs a carry when the same code is detected consecutively.
and correction value storage means (5) that counts up or down the carry according to the polarity of the sign bit and supplies the counted value to the subtraction means (2) as the offset correction value, An offset correction method characterized by obtaining an offset correction value from a digital signal during a signal-free period.