JP2917178B2 - Clock multiplication signal control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit for controlling an output clock of a clock multiplication circuit used for an optical transmission device and a multiplex repeater in a digital signal transmission system.
More specifically, the present invention relates to a clock-multiplied signal control circuit capable of controlling an output signal when a signal multiplied to an output is obtained without an input signal due to the influence of noise or the like.

BACKGROUND ART In a clock multiplication circuit, for example, in a general digital system, a system that performs processing by inputting at a speed V and outputting at a speed V has a phase margin with respect to processing in the system. This is a case in which the speed of the main processing unit is set to V / x in order to provide it. In order to output a signal processed at such a speed V / x from the system at a speed V, data is converted to a speed V based on a clock obtained by multiplying a clock at a speed V / x used for processing by x times. Need to convert.

In the case described above, a clock multiplication circuit is required.
A conventional clock multiplier circuit is provided with a limiter amplifier to recover a loss until a signal is input to an input terminal of the clock multiplier circuit, an insertion loss of a band reactor, and the like. In order to sufficiently recover the loss, this limiter amplifier has a large gain of about 32 dB.
However, if the gain of the limiter amplifier is large, the noise input may be amplified even when there is no input signal. When the noise is amplified, a signal having the same amplitude and frequency as a multiplied clock obtained when an input signal is present is obtained at the output terminal.

Although there is no suitable document regarding a clock multiplication signal control circuit for controlling the output of such a multiplication circuit, Japanese Patent Application Laid-Open No. 56-47139 discloses an output clock control. The control circuit disclosed in this publication has a configuration in which a circuit for detecting a signal break and a gate circuit are inserted between a reproduced clock signal output and an output terminal. However, with the control circuit having such a configuration, especially when the clock signal is a high-frequency signal, the gate circuit to be inserted is required to have high-performance electrical characteristics such as a rise time. However, such gate circuits are expensive and costly. In addition, the number of connection points of the high-frequency signal increases due to the insertion of the gate circuit, which may cause deterioration of the waveform of the clock signal.

Accordingly, it is an object of the present invention to provide a clock multiplied signal control circuit which has solved the drawbacks of the conventional clock multiplying circuit and control circuit.

DISCLOSURE OF THE INVENTION In a clock multiplication signal control circuit of the present invention, a clock multiplication circuit for multiplying and outputting an input clock signal, an amplifier for amplifying an output of the clock multiplication circuit, and a peak detection circuit for detecting an amplitude value of the input signal A comparison circuit for comparing the amplitude value detected by the peak detection circuit with a predetermined first reference voltage, and switching means for switching the second reference voltage of the amplifier of the clock multiplication circuit by the output of the comparison circuit Are provided.

Further, the switching means has an analog switch circuit whose input is controlled by an output of the comparison circuit via an input switching terminal, and when the information indicates that the input to the input switching terminal is at a high level, When the open end is selected as the input of the analog switch circuit and the information indicating that the input to the input switching terminal is at a low level, the maximum potential of the signal input to the amplifier as the input of the analog switch circuit Select the terminal set to the level of.

Further, the second reference voltage inside the amplifier becomes a self-bias potential set by the amplifier when the input of the analog switch circuit is connected to the open end, and the input of the analog switch circuit is input to the amplifier. When connected to a terminal set to the level of the maximum potential of the signal to be input, the level of the signal input to the amplifier becomes the level of the maximum potential.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a clock multiplication signal control circuit according to the present invention. FIG. 2 is a timing chart of the clock multiplication signal control circuit of the present invention. FIG. 3 shows a peak detection circuit.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 shows a clock multiplication signal control circuit according to the present invention. FIG. 2 is a timing chart of the clock multiplication signal control circuit of FIG. A configuration example of the clock multiplication circuit is shown in a portion surrounded by a dotted line in FIG. Input terminal 1 is connected to capacitor 2. The capacitor 2 is connected to the first limiter amplifier 3. Terminal 4 is the first
Is the open end of the limiter amplifier 3. The output of the first limiter amplifier 3 is connected to the Exclusive-Nor gate 6.
The inverted output of the limiter amplifier 3 is connected to the Exclusive-Nor gate 6 via the delay line 5. Exclusive-N
The output of the or gate 6 is connected to a zone furnace 7, and the output of the zone furnace 7 is connected to a second limiter amplifier 8. An output terminal 17 and an output terminal 18 for obtaining an inverted signal thereof are connected to the second limiter amplifier 8.

The connection relation of the parts constituting the control circuit will be described. The input terminal 1 is connected to a peak detection circuit 9. The peak detection circuit 9 is connected to the comparison circuit 10. The comparison circuit 10 is also connected from a reference voltage input terminal 11. The comparison circuit 10 is connected to the analog switch 12 via the input switching terminal 13. The analog switch 12 is provided with input terminals 14 and 15. Further, the analog switch 12 is connected to the limiter amplifier 8 via the logical threshold reference terminal 16.

The operation of such a clock multiplication signal control circuit will be described. First, the operation of the part configuring the clock multiplication circuit will be described. The input terminal 1 receives a clock signal having a period of 2T. The waveform of the input signal A is shown in FIG. The amplitude of the input signal indicated by A may be reduced due to loss or the like in the process of being input to the input terminal 1. Therefore, the signal A is first input to the capacitor 2 of the clock multiplication circuit.
The level of the signal is adjusted. The output signal of the capacitor 2 is input to the first limiter amplifier 3. The limiter amplifier is an amplifier that sets a limit value of an amplified signal.
Here, the limit value is set to the amplitude value of the signal to be input. By shaping the waveform in the first limiter amplifier 3, the amplitude of the signal A lost due to the loss is recovered. The signal whose waveform has been shaped and the amplitude of which has been recovered is B in FIG.
Shown in

The signal B is input to the Exclusive-Nor gate 6. Considering that the frequency is multiplied by four, assuming that the period is 2T and the pulse width is T, the inverted signal C of the signal B is input to the delay line 5 and is delayed by (1/4) T period. In the case of this clock multiplication signal control circuit, if the multiplication number is N, it is delayed by (1 / N) T. The signal D delayed by the delay line 5 is also input to the Exclusive-Nor gate 6. For this reason,
Exclusive-Nor gate 6 receives signals B and D. The exclusive-Nor gate 6 performs an exclusive OR operation on the signal B and the signal D to obtain a signal E. The waveform of the signal E is shown in FIG. The signal E is input to the zone furnace 7. The zone furnace wave device 7 is configured by a surface acoustic wave (SAW) filter. The frequency component of the multiplied clock required by the band reactor 7 can be extracted. In this embodiment, 4
Considering the multiplication, a waveform having a quadruple frequency is extracted, and a signal F is obtained. The waveform of the signal F output from the zone furnace 7 is shown in FIG. As shown in FIG.
The signal F, which is a signal obtained by multiplying the signal, has waveform deterioration due to insertion loss of the SAW filter and power loss when passing through the band reactor 7. In order to recover this loss, the output of the band reactor 7 is input to the second limiter amplifier 8. The second limiter amplifier 8 is also the first limiter amplifier 3
The limit value of the amplified signal is the amplitude of the multiplied signal to be obtained. The deterioration of the waveform of the signal F is recovered by the second limiter amplifier 8.

Next, the operation of the parts constituting the control circuit will be described. The signal A input to the input terminal 1 is input not only to the capacitor 2 of the clock multiplication circuit but also to the peak detection circuit 9. The configuration of the peak detection circuit 9 is shown in FIG. The peak detection circuit 9 of this embodiment is composed of a diode 9a and a capacitor 9b. Diode 9a is diode 9a
Signal having a voltage equal to or higher than the forward voltage of
A signal having a voltage lower than the forward voltage is not passed. Here, the forward voltage of the diode 9a is equal to the input signal A.
Use a diode smaller than the amplitude value of. By providing the diode 9a, when a clock whose amplitude is smaller than the forward voltage of the diode 9a is input, the signal does not pass and a zero-level output is obtained from the peak detection circuit 9, which will be described later. The operation is the same as when noise is input. Although the diode 9a and the capacitor 9b are provided as the peak detection circuit 9 in this embodiment, the peak value can be detected by the operation described below with only the capacitor.

The signal input to the peak detection circuit 9 is a diode 9a
After that, the capacitor 9b is gradually charged to the peak value of the amplitude. If there is an input clock, the signal A is charged to the peak value of the amplitude of the signal A, and the peak detection circuit 9 detects this peak value.

The peak value is input to the comparison circuit 10. The peak value of the amplitude is compared with the first reference voltage input from the reference voltage input terminal 11 by the comparison circuit 10. The first reference voltage is set to be smaller than the amplitude value of the clock signal input in advance. The comparison circuit 10 outputs an H-level signal when the peak value of the amplitude output from the peak detection circuit 9 is larger than the first reference voltage, and outputs an L-level signal when the amplitude is smaller than the first reference voltage. Therefore, when there is an input clock, the peak value of the amplitude detected by the peak detection circuit 9 is always higher than the first reference voltage, and the output of the comparison circuit 10 is an H level signal. The output signal of the comparison circuit 10 is input to the input switching terminal 13 of the analog switch circuit 12.

When the signal input to the input switching terminal 13 is at the H level, the input terminal 14 is selected as the input of the analog switch circuit 12. The analog switch circuit 12 controls the value of the second reference voltage inside the second limiter amplifier 8 according to the value of the voltage of the input terminal connected thereto. The analog switch circuit 12 is connected to the second limiter amplifier 8 via the logic threshold reference terminal 16. When the input terminal 14 is selected as the input of the analog switch circuit 12, the input terminal 14 is open and the second reference voltage controlled via the logical threshold reference terminal 16 is applied to the second limiter amplifier 8 Self-biased to the DC potential of The second limiter amplifier 8 outputs an H level signal when the input signal is larger than the second reference voltage, and outputs an L level signal when the input signal is smaller. .

Therefore, a signal G obtained by recovering the loss of the signal F input to the second limiter amplifier 8 is obtained at the output terminal 17 of the second limiter amplifier 8. Also, an inverted signal H of the signal G
Is obtained at the output terminal 18. The waveform of the signal G is shown in FIG.
H shows the waveform of the signal H. Thus, a clock output signal obtained by multiplying the input signal by four is obtained at the output terminals 17 and 18.

The case where there is no input signal at the input terminal 1 will be described. Even when there is no input signal, some noise may be input. When the gain of the first limiter amplifier 3 is large in the clock multiplier circuit, the noise is amplified. In such a case, the clock multiplier circuit multiplies the signal in the same manner as in the case where there is an input signal, and a multiplied signal is obtained as the signal F, which is input to the second limiter amplifier 8.

On the other hand, this noise is also input to the control circuit. Due to the diode 9a of the peak detection circuit 9, noise with small amplitude is not recognized. The portion where the amplitude of the noise that has passed through the diode 9a is large is charged by the capacitor 9b. However, since the portion without input to the capacitor 9b is long, it is hardly charged. Values are on the order of zero. This substantially zero level signal is compared with the first reference voltage at the reference voltage input terminal 11 by the comparison circuit 10. The first reference voltage is a value slightly smaller than the value of the amplitude of the input clock signal, and is larger than the level of almost zero. For this reason, since the detected peak value of the amplitude is smaller than the first reference voltage, the output of the comparison circuit 10 is an L level signal. When the L-level output of the comparison circuit 10 is input to the input switching control terminal 13 of the analog switch circuit 12, the input terminal 15 is selected as the input of the analog switch circuit 12. The input terminal 15 is set to the level of the highest potential of the signal input to the second limiter amplifier. Therefore, the second reference voltage controlled via the logical threshold reference terminal 16 is set to the level of the highest potential of the input signal of the second limiter amplifier.

When comparing the signal F input to the second limiter amplifier 8 with the second reference voltage, the value of the signal F is always smaller than the second reference voltage. For this reason, the second limiter amplifier 8
As a result, an L level signal which is information that the signal F is smaller than the second reference voltage is obtained, and a stable L level signal is obtained at the output terminal 17.

As described above, even in a case where the gain of the limiter amplifier provided in the multiplier circuit is large and the noise is also amplified and a multiplied signal is obtained, the control circuit detects that there is no input signal, and the limiter detects the absence of the input signal. The output signal can be controlled by comparison with the reference voltage by the amplifier.

Further, the configuration of the clock multiplication circuit is not limited to this, and various configurations can be considered. Further, the part of the control circuit used in the clock multiplication signal control circuit can be used for controlling output signals of a receiver and the like other than the clock multiplication circuit.

INDUSTRIAL APPLICABILITY As described above, the clock multiplied signal control circuit according to the present invention is effectively used in a digital signal processing device that processes high-speed signals, such as an optical transmission device, a multiplex relay device, and a switching device.

Claims (2)

(57) [Claims] A clock multiplication circuit for multiplying and outputting an input clock signal input from an input terminal; an amplifier for amplifying an output of the clock multiplication circuit; and a peak detection circuit for detecting an amplitude value of the input clock signal. A comparison circuit for comparing an amplitude value detected by the peak detection circuit with a first reference voltage set in advance to be smaller than the amplitude value of the input clock signal; and an output of the comparison circuit for the amplifier of the clock multiplication circuit. Switching means for switching a second reference voltage, the switching means having an analog switch circuit whose input is controlled by the output of the comparison circuit, wherein the analog switch circuit has a value of the voltage of the input terminal Controls the value of the second reference voltage inside the amplifier, and the output of the comparison circuit is detected by the peak detection circuit. When the width value is information that the level is higher than the first reference voltage, an open end is selected as an input of the analog switch circuit, and the second reference voltage is a self-bias set by the amplifier. Potential, the amplifier outputs a signal from the clock multiplication circuit, and the output of the comparison circuit is information that the amplitude value detected by the peak detection circuit is at a level lower than the first reference voltage. In some cases, the terminal set to the level of the maximum potential of the signal input to the amplifier as the input of the analog switch circuit is selected, and the second reference voltage becomes the maximum potential of the signal input to the amplifier. And a clock multiplying signal control circuit, wherein the amplifier outputs only a stable signal. 2. The amplifier outputs an H-level signal when a signal from the clock multiplying circuit is larger than the second reference voltage, and outputs a signal from the clock multiplying circuit than the second reference voltage. 2. The clock multiplication signal control circuit according to claim 1, wherein an L level signal is output when the signal is small.