Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
  • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
  • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
  • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]

Definitions

• the present invention relates generally to the field of signal distribution and, in particular, to improved signal reception in a network or other computing environment in which a signal may take several paths to its destination, each path having an associated delay.
• a resource is shared among several or many devices. Numerous devices may be interconnected and various signals are transmitted among the devices. A signal from a source device may be directed to a selected target device. However, because of multiple-path delays or congestion, the signal taken by one path will arrive at the target device at a slightly different time relative to the signal taken by another path or experiencing a different congestion scenario (that is, delays due to other signals having a higher priority). In either situation, a delay variation will exist among the signals. As illustrated schematically in Fig.
• a multiple-path delay refers to the delay which occurs when, due to the architecture of a system, such as a network 100, a signal or packet of information may take multiple paths before reaching the target device, with a delay being introduced by each path.
• a packet being transmitted from a first device 102 to a second device 104 may be routed along several paths (simultaneously or in turn), such as a first path 1 10, 1 12, 114, 1 16 and 118 and a second path 1 10, 120, 1 18 (where path legs are connected by routers, switches or other devices 130).
• Fig. 2A represents an exemplary clock reference signal which is transmitted by a source device (also known as a "conductor").
• the reference signal should be precisely reproduced at precisely the same time at the target or destination device (also known as a "performer"), as illustrated in Fig. 2B.
• a delay will occur in the actual signal, as is apparent in Fig. 2C.
• the signal may be received at the target device at various time as illustrated in Fig. 2D.
• CobraNetTM One network architecture which has been developed by the Peak Audio division of Cirrus Logic, Inc. is an audio network marketed under the name CobraNetTM.
• CobraNet technology allows uncompressed, real-time, single- or multiple-channel digital audio, clocking and control data to be transmitted over an Ethernet network. Audio sources, signal processing, amplification and sound projection may be distributed throughout a facility, all interconnected by Ethernet CAT-5 or optical cabling. Thus, any (single or multiple) audio input may be routed to any (single or multiple) audio output with each input and each output being capable of being processed and amplified individually.
• FIG. 3 is a block diagram of an exemplary PLL 300.
• a signal is received at a first input of a phase-sensitive detector 302 which compares the phase of the reference signal at the first input with the phase of a signal received at a second input.
• the detector 302 outputs a voltage signal which is proportional to the phase difference and transmitted to a low pass filter 304.
• the filtered signal is then transmitted to a local clock or voltage-controlled oscillator (VCO) 306.
• VCO voltage-controlled oscillator
• the output of the VCO 302 is a sine wave locked to the predominant frequency of the signal input to the detector 302.
• the low pass filter 304 provides an averaging function such that the frequency of the signal output by the VCO 306 represents an average of the delays of the multiple signals received from the source. Because both the delays and the variations are not constant, it will be appreciated that the "average” will also vary. While a noisy environment such as this may be modeled by a normally distributed noise signal (see Fig. 4A), the probability curve of an actual communication system is asymmetrical and bounded at some minimum quantity due to physical propagation limitations and fixed processing overhead, as shown in Fig. 4B. And, although such a probability curve may be satisfactory for small, local networks in which the network architecture is controllable, it is not satisfactory in larger network environments, including wide area and wireless networks which have a wider range of delay variation as shown in Fig. 4C.
• the present invention provides apparatus and methods for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal to noise ration seen by a PLL.
• the present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop.
• the processor includes a sealer, such as an exponential sealer, providing asymmetrical error weighting to enhance the contribution of signals with a smaller delay (shorter path).
• the processor further includes a self-adjusting threshold to prevent the PLL from free running in the "masked" state for an extended period of time.
• the level threshold is gradually reduced, thus decreasing the width of the mask, until many errors are ignored and only a fixed percentage of the lowest delay signals from the detector are passed to the low pass filter to enable the PLL to regain lock.
• methods for processing a signal are provided to exploit the presence of a shortest path.
• FIG. 4A is a probability curve illustrating a normally distributed noise signal
• Fig. 4B is a probability curve illustrating the effects of delay variations in the reception by a destination device of a signal from a source device in a small network or one having little congestion
• Fig. 4B is a probability curve illustrating the effects of delay variations in the reception by a destination device of a signal from a source device in a large network or one having much congestion
• Fig. 5 is a block diagram of a first embodiment of the apparatus of the present invention
• Fig. 6 is a block diagram of a second embodiment of the apparatus of the present invention
• Fig. 5 is a block diagram of one embodiment of circuitry 500 of the present invention.
• the detector 500 includes a dual-input phase-sensitive detector 502, a low pass filter 504, and a voltage-controlled oscillator 506, elements common to the PLL of Fig. 3.
• the device 500 includes a processor 520, such as an exponential sealer 508, coupled between the detector 502 and the low pass filter 504.
• the sealer 508 exaggerates the effects of small errors (which represent small delays and are close to the ideal in Fig. 4B) and reduces the effects of larger errors (which represent larger errors and are farther from the ideal). Thus, while the device generates an average, the average generated is closer to the ideal.
• Fig. 4B the effects of small errors
• larger errors which represent larger errors and are farther from the ideal
• the device 600 includes a dual-input phase-sensitive detector 602, a low pass filter 604, and a voltage-controlled oscillator 606 and a processor 620 comprising a memory element 608, a comparator 610 and a switching element 612. Additionally, the processor 620 includes a second low pass filter 618. The input to the second low pass filter 618 is coupled to receive the output of the comparator 610 and the output of the second low pass filter 618 is coupled to the second input of the comparator 610. Thus, the second low pass filter 618 will generate a threshold Th which varies as the output of the comparator 610 changes.
• the error signal e is greater than the threshold Th, the actual input (output from the detector 602) is ignored and the previous input level (stored in the memory element 608) is input to the first low pass filter 604.
• the second low pass filter 618 gradually increases the level of the threshold Th such that eventually, the actual input will be lower than the threshold Th and the comparator 610 will cause the switching element 612 to move to the normal position whereupon a lock may be retained.
• An optional exponential sealer 614 may be coupled between the switched terminal of the switching element 612 and the input to the low pass filter 604 or between the output of the detector 602 and the first switched terminal to further enhance the operation of the device 600.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Data Exchanges In Wide-Area Networks (AREA)

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Applications Claiming Priority (2)

Publications (2)

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• 2002
  • 2002-12-04 US US10/310,554 patent/US6973152B2/en not_active Expired - Lifetime
• 2003
  • 2003-11-25 EP EP03796744A patent/EP1593198A4/en not_active Withdrawn
  • 2003-11-25 JP JP2004557626A patent/JP2006511107A/ja active Pending
  • 2003-11-25 AU AU2003298023A patent/AU2003298023A1/en not_active Abandoned
  • 2003-11-25 WO PCT/US2003/038821 patent/WO2004051874A2/en not_active Ceased

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