CS520190A3 - Distributed synchronization process for wireless fast packet communication system - Google Patents

Description

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BACKGROUND OF THE INVENTION The present invention relates to the switching of voice and data packets and, in particular, to the disassembled synchronization method of a wireless fast packet communication system.

Voice and data switching is known from the well-known technique. Packet switching is also known. In the past, however, synchronization to control the devices transmitting and receiving packets of information in the voice and data packet switching was a problem. This problem was related to the dynamic allocation of packet bandwidth between individual peripheral devices related to the switch for voice information and data information. Another problem was the network interface architecture for the switcher. The suture interfacesarchitecture of the prior art switches used the same bus for both data and control. In conjunction with the dynamic bandwidth allocation problem on the bus, the interface interface architecture resulted in the switcher having small switching capacity and throughput. This is because automatic data loggers are connected to the apartment by apartment. In packet data switches, it claims processors. These performance issues are becoming more significant in connection with modern fast packet protocols. It would therefore be desirable to create radio and data packets with enhanced architecture.

The key to solving this problem of packet interconnect architecture is the way to achieve synchronization of packets transferred between different nodes and user terminals. Failure to achieve this goal is likely to result in an unacceptable acceptance relationship, usually caused by frequency differences, differences in deflection control, phase differences due to modulation signal, and the like.

This object is achieved by an exploded synchronization method for a wireless fast packet communication system, comprising a head unit transmitting one frame synchro-lowering packet in each frame, wherein in accordance with the present invention, the time stamp indication that is transmitted by said count is included in said packet the bytes from the beginning of the network interface data area to the first byte of the following packet synchronization sequence end, and the said time transmission indication is extracted in the receiver, this indication being compared; with receiving time information relative to the time of receipt of this; the packet is propagated, the delay propagation is set, when it is marked, and the network interface data area * is set to find the shortest time. '

The invention further relates to an apparatus for performing the above method, characterized in that the transmitter comprises means for including the indication of the frame time being transmitted to said packet by subtracting bytes from the beginning of the network interface data area to the first one. a downstream end of a packet synchronization sequence, a means for extracting said transmission time indication, a means for comparing said indication with a reception time data, 3 relative to a reception time of said packet, a means for adjusting the delay time, a means for determining when a fault is significant and a means for adjusting said network interface data area to find synchronization in the shortest time.

The exploded synchronization method and apparatus of the invention allow a common packet structure to be used to combine both voice and data in a single switch. It includes not only bandwidth within the voice or data area of the frame, but also between voice and data areas.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a first embodiment of a wireless fast packet connection system according to the invention, FIG. 2 shows a frame for a first embodiment, FIG. FIG. 4 shows a packet data area within the frame, FIG. 5 a typical network topology for the first embodiment, FIG. 6 a first synchronization time diagram for the first embodiment, FIG. the synchronization method of the invention.

FIG. 1 shows a block diagram of a first embodiment of a wireless fast packet communication system 100 according to the invention. A node and a user terminal are shown here. It will be apparent to those skilled in the art that multiple user terminals may be used. For simplicity, only one is shown in FIG. 4 Following is a description of processing a voice signal of a published switched telephone network 133 to a high frequency channel 111 in a node 103.

Voice input from the public switched telephone network 1,33 is compressed and filtered by the telephone interface 135 and is routed to the analog-to-digital converter 137. From there, it is stored in voice packets in the local memory 212 of the main processor 222 and is routed through the main processor via the FIFO to the local memory 141 of the slave processor 143. Here, the sub-processor forwards the packet to the territorially limited network copier 145 for its high frequency transmission. the device 22Z and the co-processor of the territorially limited network convert it to serial data stream 222 · A high frequency device 22Zz comprising an antenna receiver and transmitter generates a high frequency signal and leads it to a high frequency antenna 221 ·

The software contained in the panel of spatially limited network and software contained in the main processors in computer systems perform all the above and the following functions. Following is a description of the processing of the voice signal of the high frequency channel 211 into the telephone 222 in the user terminal 101. The user terminal comprises a high frequency antenna 222 coupled to the antenna combiner 22Z of the receiver. The power supply and control of the high frequency device provided by the lines 222- The high frequency device 22Z the cost serial data wicker from the high frequency signal 211a leads the serial data stream 113 to the co-processor 115 of the territorially limited network. Within the computer system, the LAN Local Area Network panel, which contains the downlink processor 115Z and its associated local memory 212 / data stream, receives the stream and converts it into voice packets 119 of the subordinate processor 217. The slave processor then extracts and then passes the packet usage to the unit. 121 FIFO of the main processor dolocone memory 223 for reconstructing loudly using software contained in a computer system using a digital-to-analog converter 225 in a computer system. The telephone interface 127 expands and filters the output analog voice signal and submits it to the telephone129. In particular, the local ringing of the telephone is ensured by the fact that the fast data packets are processed together in the above system up to and including the main processor memory unit 123, and the main processor then stores the ringing indication on the input-output gate 132 and this indication is then fed to telephone interface 127 and is routed to telephony 129.

For proper operation of the system, there will be a periodic repetition period which includes bidirectional signaling and packet data. This frame 2C0 is shown in FIG. 2. In the voice and fixed data area, there are several time slots 'allocated' to fixed speed data. voice, k t e r e j s o u bez k o l i z ρri; The node m. it is responsible for collision detection. Within the voice and fixed data area, the format shown in FIG. 3 applies. The format shown in FIG.

Each transmission within the frame may be coded to increase the accuracy of the received data. If this code uses multiple copies of the original data, the time of similar packet arrivals may be different. In this case, the software algorithm compensates for these different arrival times.

The system allows maximum spectral efficiency by assigning the desired bandwidth to each of the users of the common transmission path. As mentioned above, existing systems did not allocate bandwidth on demand, but rather allocate bandwidth at system startup. As a result, this system takes advantage of the fast forwarding technology and allows the creation of circuit and non-circuit connections across the system.

FIG. 5 shows a typical network topography 500 of a first embodiment. Here, a series of Zn / nodes is shown, namely nodes N, N, in this case Nc. Also shown are a series of -i-2/5 / n / terminals T1 through T, in this case T1. The nodes together with the JL-0-4 m and the terminals communicate on a shared transport path via a fast packet switching mechanism, wherein the one-way packet switching mechanism is controlled based on the bandwidth allocation eliminating collisions between the individual units that may have access to common transmission • z- <. * ·: .S'1 V; - · 'λ' · <· - i · · i Λ- track. 7 The basic process for obtaining frame synchronization between two network interface units is really very simple. To begin with, suppose one unit "barrel" and carry exactly one frame synchronization parame in each frame. This packet must include a "frame time" that is transmitted, counted in bytes from the beginning of the network interface data area to the first byte header / first byte following the packet synchronization sequence. The approximate position of this packet within the frame must be known in the receiver to meet the unconditional stability requirements during the initial portion of the sequence. There is only one important feature - the process used to initially obtain synchronization must take into account the interference induced by the receiver commands in the network interface control memory. Indeed, the operation of the receiver is quite simple. It extracts the transmission time described above and compares it with the time data acquisition provided by the networking interface with respect to the propagation of the delay in the buffer memories and the switching device. Assuming that a significant error occurs, it must then determine the correct direction for rebuilding its network interface to find synchronization in the shortest time. The desired setting will always be between the negative half and the positive half of the frame.

This total calculated error is then divided by the stability factor, such as 16, to maintain stability in a situation where one device can receive from several other unsynchronized devices. Further checks are then carried out to take into account the limit case and to limit the alignment to whole words (even even addresses) as required by the conventional network interface concept.

The overall scheme also allows you to determine the exact moment when synchronization is reached and / or slowly / determine lost synchronization. This is achieved by the formation of the global variable "in-sync". This variable is decremented to a value of one / with a lower limit of zero / at each interruption of the frame, and is incremented by δ / up to the upper limit, which depends on the size of the data system, such as 400 / each time the frame synchronization parser is processed, which does not require frame time adjustment, i.e., each time it is found that frame timing synchronization is perfect. When "in-sync" is zero, this system is out of sync. The code for performing both of these algorithms is shown in Tab. AND.

The remaining problem of obtaining synchronization encounters repeated access commands required by the receiver to control the packet indicating incorrect synchronization. The receiver access control sequence is intended to interfere with the packet receiving process if it occurs during a packet. One way in which this is accomplished is that each frame includes a "receiver" sequence consisting of the following commands: 8 t 8 Ϊ 9 - all clear the bus - enable the receiver - select the antenna - set the network interface as the destination of the bus - set the radio as the bus source.

If the packet synchronization detector specifies a mismatch, it will be set when it encounters that sequence, or when the power intergas detects that a data tracker representing a valid header has been passed / when the cyclic code header check fails.

The problem that arises is shown in FIG. 6. The problem arises when the first synchronization packet is decoded, if receiving the clock signal of the device is somewhat faster than at the node (which is, of course, half the time). The calculated device then shifts the receiving frame to the left, thus placing the control sequence just at the top of the next received synchronization packet. At this time, a different synchronization parame- ter will be received, the left adjustment will be calculated and the sequence repeated. Thus, the net effect is to adjust the control sequence with the sync memory rather than frame alignment. The solution is simple - to place a control sequence of exactly half of the frame from the expected moment of the sync pake. This is shown in Fig. 7. In this case, the first packet is unlikely to be accepted. However, the relative frame times will soon be fluctuating and no matter how the relative position of the receiver is moving. The first received ti 10 λ ·; the packet in the right direction to move the control sequence away from the packet, since the change will be the least desired.

Of course, once the frame is synchronized, the above-mentioned driver sequence will be removed and replaced by an operative structure.

Once the approximate frame synchronization has been achieved by all devices, each device in the system (all nodes, UIMs and NIMs) will continue to synchronize on average all frame clock signals it may encounter, including its own. This concept results in the best overall timing behavior and thus the shortest required watchdogs between packets from different devices. For example, a four-node chain may exhibit a frame time difference of 6 bytes from the first to the last, whereby the average difference will depend on the relative idling clock frequencies of the four cipher interactions concerned and may remain at the worst of the above.

By contrast, the averaging method causes the average difference to remain at zero. Furthermore, it is necessary to take into account the failure, ie the adequate operation in case of failure. For example, if the system consists of nodes, and the other node is subordinate to the first and perhaps the second, what is salty if the other fails? If control is a synchronization priority, this failure must be detected and the priority is not-'(·

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· <- W »7? F wrw * 11 - -¾. In contrast, the averaging scheme performs an appropriate adjustment in the corresponding sense.

For example, the clock signals may have a frequency accuracy of 5 parts per million. For frame size 375C, this means a maximum loss of 2.5.10 ^. 3750 = C, C375 bytes per frame for two clock signals that are as far apart as possible, ie one at the top of the spectrum and the other at the bottom. This means that a single word adjustment will be required every 27 frames in this limit case.

There are several potential solutions to the problem of getting synchronization between multiple nodes in a wide system. Easier to define a priority order and allow each node to start broadcasting only after it has been heard and bound to the next highest unit in the priority structure. This is characterized by the fact that it can be very simple to design, but requires each node to 'eat' the identity of its highest node in the structure, there is an additional problem of determining the right action if the higher node is never heard. more difficult.

The variables available in each node include both the frame phase and the absolute frame rate, and the frame size can vary within wide limits and not be fixed to "system" speed until full synchronization is achieved. Correctly selected frame rate and phase

The random number MHS will almost certainly provide an adequate initialization process if the random number generators in each node can be provided with different numbers in order to avoid identical actions from the same start point as it can be recovered from recovery after a major power outage.

This requirement may be met by including an electronic serial number in each unit. For example, in one frame structure, each node sends a frame synchronization packet on each sector in each frame. However, it is appropriate that each lel sector sector transmits a frame synchronization signal every 4 th frame. This allows UIH / NIIi modules to re-evaluate their local options for every 24 frames / 48 msec and, in the worst case scenario, to update frame synchronization every 24 frames, i. still in the 27th worst case limit, calculated above.

This reduction of frame synchronization packets means that it is possible to achieve a more efficient frame arrangement for the price of the software required to change the "fixed" portion of the data in the network interface buffer at the end of each frame. frame and UIM / NIH transfer to the beginning to simplify software timing considerations.

The invention is not limited to the above embodiment and relates to various variations of the exploded synchronization method for a wireless fast packet communication system according to the present invention.

Claims (2)

IEKE &amp; ŽIXSÍZSF An exploded synchronization method for a wireless fast packet communication system, the system comprising a main unit transmitting a single frame synchronous packet in each frame, characterized in that an indication is provided in said packet. the frame time being transmitted by subtracting the bytes from the beginning of the network interface data area to the first byte following the end of the packet synchronization sequence, and the transmission time indication being extracted at the receiver, this indication being compared to the receiving time data the delay propagation is adjusted relative to the time of receipt of the packet, it is determined when there is a significant error and the said data interface of the network interface for finding the synchronization in the shortest time. έ 1 2. An apparatus for performing a disassembled synchronous method for a wireless fast packet communication system according to item 1, the system comprising a main unit transmitting one frame synchronization packet in each frame, characterized in that the transmitter comprises means for including an indication the frame time being transmitted to that pake-! here, by subtracting the bytes from the beginning of the data area of the network interface to the first byte following the end of the packet synchronization sequence, the means for extracting said transmission time indication, the means for comparing said information with the receiving time data relative to the time received of said packet, means for adjusting delay propagation, means for determining when a fault is present, and means for adjusting said network interface data area to find synchronization in the shortest time. ΐά a