JPS61163740A - Time division multiplex communication device - Google Patents
Time division multiplex communication deviceInfo
- Publication number
- JPS61163740A JPS61163740A JP359785A JP359785A JPS61163740A JP S61163740 A JPS61163740 A JP S61163740A JP 359785 A JP359785 A JP 359785A JP 359785 A JP359785 A JP 359785A JP S61163740 A JPS61163740 A JP S61163740A
- Authority
- JP
- Japan
- Prior art keywords
- switching
- circuit
- station
- signal
- time slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野〕
この発明は電話、データおよび画像情報をディジタル化
して時分割多重化方式により伝送する時分割多重通信装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time division multiplex communication device that digitizes telephone, data and image information and transmits the digitalized information using a time division multiplex system.
第2図は従来回路の端末機器のデータを多重化する回路
構成例であり、図において(1)は端末機器と接続する
為の端末インターフェース回路、(2)は伝送路インタ
ーフェース回路、16)はフレーム同期発生回路、I9
)はパターン発生回路である。これら(1) 、 +2
1 、 (61および19)により一つの局(親局ある
いはその子局)を構成している。Figure 2 is an example of a circuit configuration for multiplexing data of terminal equipment in a conventional circuit. In the figure, (1) is a terminal interface circuit for connecting with terminal equipment, (2) is a transmission line interface circuit, and Frame synchronization generation circuit, I9
) is a pattern generation circuit. These (1), +2
1, (61 and 19) constitute one station (master station or its slave station).
次に動作に−】いて説明する。Next, the operation will be explained.
伝送路からの受信データは伝送符号(例えはCMI符号
)からNRZ符号に菱換し、受信データのフレーム同期
の抽出を行なった後フレーム同期発生回路(6)から発
生する装置のフレーム同期に送受信のデータを同期させ
る。Received data from the transmission path is converted from a transmission code (for example, a CMI code) to an NRZ code, and after extracting the frame synchronization of the received data, the frame synchronization generated by the frame synchronization generation circuit (6) is transmitted and received by the device. synchronize data.
パターン発生回路191は複数の端末インターフェース
(11からの送受信データをそれぞれの送受信バスに入
出力するタイムスロットを固定的に制御しており、その
各タイムスロットに対応する端末インタフェース(1)
を順次伝送路インタフェース(21を介して伝送路に接
続する。The pattern generation circuit 191 fixedly controls time slots for inputting/outputting data sent and received from a plurality of terminal interfaces (11) to and from each transmission/reception bus, and selects a terminal interface (1) corresponding to each time slot.
are sequentially connected to the transmission line via the transmission line interface (21).
従来の時分割多重通信装置は以上の様に構成されている
ので特定の端末インターフェース(端末機器)が未使用
状態であ−】でもその端末インタフェースは同定的にタ
イムスロットを占有する為、伝送効率が悪くなり、より
多くの情報を随時自由に伝送できないなどの問題点かぁ
−】だ。Conventional time-division multiplex communication equipment is configured as described above, so even if a specific terminal interface (terminal device) is unused, that terminal interface occupies a time slot in a specific manner, so the transmission efficiency decreases. Is there a problem with this, such as getting worse and not being able to freely transmit more information at any time?
この発明は上記のような問題点を解消する為になされた
ものでタイムスロットを必要に応じて切替え伝送効率の
良い時分割多重自信装置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a time division multiplexing system which switches time slots as necessary and has good transmission efficiency.
この発明に係る時分割多重通信装置は互いに異なるタイ
ムスロットパターンを発生する多重化パ9−ン発生メモ
リを複数個設け、これを必要に応じかつ各局間の同期フ
レームに位相同期させて切替制御して当該端末インタフ
ェースのタイムスロット変更を行うものである。The time division multiplex communication device according to the present invention is provided with a plurality of multiplex pattern generation memories that generate mutually different time slot patterns, and controls switching as necessary by synchronizing the phase with the synchronization frame between each station. This is used to change the time slot of the terminal interface.
この発明におけるタイムスロットの切替制御は親局およ
び子局間で相対的に切替信号を制御している為、誤動作
あるいはフレームの同期はずれが無い無瞬断のタイムス
ロット切替え、および伝送効率の高い送受信を実現する
ことが可能となる。Since the time slot switching control in this invention relatively controls the switching signals between the master station and the slave station, it is possible to switch time slots without any malfunction or lose frame synchronization, and to achieve highly efficient transmission and reception. It becomes possible to realize this.
以下、この発明の一実施例を第1図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
図において、(1)は端末インターフェース回路、(2
1は伝送路インターフェース回路、;3)は切替1d号
発生回路、(4目よ切替信号検出回路、(5)は切替信
号転送回路、(6)はフレーム同期発生回路、(7)は
多重化パターン切替回路、(8)は多重化パターン発生
用メモリー、qLlは制御回路である。In the figure, (1) is a terminal interface circuit, (2
1 is a transmission line interface circuit, 3) is a switching 1d generation circuit, (4th is a switching signal detection circuit, (5) is a switching signal transfer circuit, (6) is a frame synchronization generation circuit, and (7) is a multiplexing circuit. A pattern switching circuit, (8) a memory for multiplexed pattern generation, and qLl a control circuit.
次に動作に−】いて説明する。Next, the operation will be explained.
各端末インターフェース(1)の使用状態は制御回路(
1Gにより監視しておりタイムスロットの切替えが生じ
た時は親および子局装置すのパターン発生用メモリー1
81の内容をお互いに転送確認し運送照合が終了すれば
親局の切替信号発生回路(3)から切替レディー信号を
送出する。子局では親局から送られてくる切替レディ信
号を切換信号検出回路+4+で受けてその切替えタイミ
ングを検出し切替動作準備に入ると同時に親局に向けて
同内容の信号を切替信号転送回路15)を介して転送す
る。The usage status of each terminal interface (1) is determined by the control circuit (
1G, and when a time slot switch occurs, the pattern generation memory 1 of the parent and slave stations is monitored.
When the contents of 81 are mutually transferred and confirmed and the transportation verification is completed, a switching ready signal is sent from the switching signal generating circuit (3) of the master station. In the slave station, the switching signal detection circuit +4+ receives the switching ready signal sent from the master station, detects the switching timing, and prepares for switching operation, and at the same time sends a signal with the same content to the master station. ).
親局では子局から転送される切換信号を切換信号検出回
路(4)で受けて子局装置が正常な切替え準備に入−〕
たことを検出すると同時に、次の段階でフレーム同期に
位相同期された切替制御(要求)信号を多重化パターン
切替回路(7)に出力して自局の多重化パターン発生メ
モリー(8)を切替える。At the master station, the switching signal detection circuit (4) receives the switching signal transferred from the slave station, and the slave station equipment prepares for normal switching.
At the same time, in the next step, a switching control (request) signal phase-synchronized with frame synchronization is output to the multiplex pattern switching circuit (7) to switch the multiplex pattern generation memory (8) of the own station. .
一方、子局では親局の切替制御信号に従属同期して、同
メモリー(8)を切替えることにより無瞬断のタイムス
ロット切替えを行うことができる。On the other hand, the slave station can perform time slot switching without momentary interruption by switching the same memory (8) in subordinate synchronization with the switching control signal of the master station.
なお、上記実施例では親局装置、子局装置を別々に構成
したが実際の装置では親子両方の機能を合せて構成し、
システムにより設定して用いるようにできる。また親局
、子局とも複数になっても同様の効果を奏する。In the above embodiment, the master station device and the slave station device are configured separately, but in an actual device, the functions of both the parent station device and the slave station device are configured together.
It can be set and used by the system. Further, even if there are a plurality of master stations and slave stations, the same effect can be achieved.
以上のように、この発明によれば互いに異なるタイムス
ロットパターンを発生する多重化パターン発生メモリを
複数個設け、これを相手局と同期させて切替制御するよ
うに構成したので、フレーム同期はずれのない無瞬断の
タイムスロット切替えができ、伝送効率の高い送受信が
できる効果がある。As described above, according to the present invention, a plurality of multiplex pattern generation memories that generate mutually different time slot patterns are provided, and the switching control is performed in synchronization with the other station, so that there is no frame synchronization. It has the effect of allowing time slot switching without instantaneous interruption and enabling transmission and reception with high transmission efficiency.
【図面の簡単な説明】
第1図はこの発明の一実施例による時分割多重通信装置
のブロック回路図、第2図は従来の時分割多重通信装置
のブロック回路図である。
(1)は端末インターフェース回路、(2)は伝送路イ
ンターフェース回路、(3;は切替信号発生回路、(4
)は切替信号検出回路、+5)は切替信号転送回路、(
6)はフレーム同期発生回路、17+は多重化パターン
切替回路、(8)は多重化パターン発生メモリ、U■は
制御回路である。
なお、図中同一符号は同−又は相当部分を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram of a time division multiplex communication device according to an embodiment of the present invention, and FIG. 2 is a block circuit diagram of a conventional time division multiplex communication device. (1) is a terminal interface circuit, (2) is a transmission line interface circuit, (3; is a switching signal generation circuit, (4) is a
) is a switching signal detection circuit, +5) is a switching signal transfer circuit, (
6) is a frame synchronization generation circuit, 17+ is a multiplex pattern switching circuit, (8) is a multiplex pattern generation memory, and U■ is a control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ら各端末インタフェースに送受信データの同期フレーム
に位相同期したタイムスロットを割当て、各端末インタ
フェースの送受信データを時分割多重方式にて伝送する
多重通信装置において、互いに異なるタイムスロットパ
ターン(アドレス)を発生出力する複数個の多重化パタ
ーン発生メモリ、これら多重化パターン発生メモリのタ
イムスロットパターンを切替出力する切替回路、伝送す
べき他局とのタイムスロットを照合してその伝送路を形
成すると共に上記同期フレームに位相同期して上記切替
回路を切替制御する切替制御手段を備えたことを特徴と
する時分割多重通信装置。In a multiplex communication device in which each station has a plurality of terminal interfaces, time slots that are phase-synchronized with a synchronization frame of transmitted and received data are assigned to each of these terminal interfaces, and the transmitted and received data of each terminal interface is transmitted in a time division multiplexing method, A plurality of multiplexed pattern generation memories that generate and output mutually different time slot patterns (addresses), a switching circuit that switches and outputs the time slot patterns of these multiplexed pattern generation memories, and a time slot that collates with other stations to be transmitted. 1. A time division multiplex communication device comprising a switching control means for forming a transmission path using the synchronization frame and for controlling switching of the switching circuit in phase synchronization with the synchronization frame.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP359785A JPS61163740A (en) | 1985-01-12 | 1985-01-12 | Time division multiplex communication device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP359785A JPS61163740A (en) | 1985-01-12 | 1985-01-12 | Time division multiplex communication device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61163740A true JPS61163740A (en) | 1986-07-24 |
Family
ID=11561881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP359785A Pending JPS61163740A (en) | 1985-01-12 | 1985-01-12 | Time division multiplex communication device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61163740A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63314931A (en) * | 1987-06-18 | 1988-12-22 | Mitsubishi Electric Corp | Branch transmission system for multiplex signal |
-
1985
- 1985-01-12 JP JP359785A patent/JPS61163740A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63314931A (en) * | 1987-06-18 | 1988-12-22 | Mitsubishi Electric Corp | Branch transmission system for multiplex signal |
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