WO2004051763A3 - Verfahren zum herstellen einer speicherzelle, speicherzelle und speicherzellen-anordnung - Google Patents

Verfahren zum herstellen einer speicherzelle, speicherzelle und speicherzellen-anordnung Download PDF

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Publication number
WO2004051763A3
WO2004051763A3 PCT/DE2003/003935 DE0303935W WO2004051763A3 WO 2004051763 A3 WO2004051763 A3 WO 2004051763A3 DE 0303935 W DE0303935 W DE 0303935W WO 2004051763 A3 WO2004051763 A3 WO 2004051763A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
electrically conductive
conductive areas
production
arrangement
Prior art date
Application number
PCT/DE2003/003935
Other languages
English (en)
French (fr)
Other versions
WO2004051763A2 (de
Inventor
Franz Hofmann
Franz Kreupl
Original Assignee
Infineon Technologies Ag
Franz Hofmann
Franz Kreupl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Franz Hofmann, Franz Kreupl filed Critical Infineon Technologies Ag
Priority to DE10393702T priority Critical patent/DE10393702B4/de
Priority to US10/537,534 priority patent/US20060154467A1/en
Priority to AU2003289813A priority patent/AU2003289813A1/en
Publication of WO2004051763A2 publication Critical patent/WO2004051763A2/de
Publication of WO2004051763A3 publication Critical patent/WO2004051763A3/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Abstract

Die Erfindung betrifft ein Verfahren zum Herstellen einer Speicherzelle, eine Speicherzelle und eine Speicherzellen-Anordnung. Bei dem Verfahren zum Herstellen einer Speicherzelle wird in und/oder auf einem Substrat (301) ein erster elektrisch leitfähiger Bereich (311) ausgebildet. Ferner wird ein zweiter elektrisch leitfähiger Bereich (313) in einem vorgegebenen Abstand zu dem ersten elektrisch leitfähigen Bereich derart ausgebildet, dass zwischen dem ersten und dem zweiten elektrisch leitfähigen Bereich ein Hohlraum (321) gebildet wird. Der erste und der zweite elektrisch leitfähige Bereich werden derart eingerichtet, dass bei Anlegen einer ersten Spannung an die elektrisch leitfähigen Bereiche aus Material von mindestens einem der elektrisch leitfähigen Bereiche eine den Abstand zwischen den elektrisch leitfähigen Bereichen zumindest teilweise überbrückende Struktur gebildet wird. Bei Anlegen einer zweiten Spannung an die elektrisch leitfähigen Bereiche wird Material einer den Abstand zwischen den elektrisch leitfähigen Bereichen zumindest teilweise überbrückenden Struktur zurückbildet.
PCT/DE2003/003935 2002-12-03 2003-11-27 Verfahren zum herstellen einer speicherzelle, speicherzelle und speicherzellen-anordnung WO2004051763A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10393702T DE10393702B4 (de) 2002-12-03 2003-11-27 Verfahren zum Herstellen einer Speicherzelle, Speicherzelle und Speicherzellen-Anordnung
US10/537,534 US20060154467A1 (en) 2002-12-03 2003-11-27 Method for the production of a memory cell, memory cell and memory cell arrangement
AU2003289813A AU2003289813A1 (en) 2002-12-03 2003-11-27 Method for the production of a memory cell, memory cell and memory cell arrangement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10256486A DE10256486A1 (de) 2002-12-03 2002-12-03 Verfahren zum Herstellen einer Speicherzelle, Speicherzelle und Speicherzellen-Anordnung
DE10256486.8 2002-12-03

Publications (2)

Publication Number Publication Date
WO2004051763A2 WO2004051763A2 (de) 2004-06-17
WO2004051763A3 true WO2004051763A3 (de) 2004-09-30

Family

ID=32403688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/003935 WO2004051763A2 (de) 2002-12-03 2003-11-27 Verfahren zum herstellen einer speicherzelle, speicherzelle und speicherzellen-anordnung

Country Status (5)

Country Link
US (1) US20060154467A1 (de)
CN (1) CN100428519C (de)
AU (1) AU2003289813A1 (de)
DE (2) DE10256486A1 (de)
WO (1) WO2004051763A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004052647B4 (de) * 2004-10-29 2009-01-02 Qimonda Ag Methode zur Verbesserung der thermischen Eigenschaften von Halbleiter-Speicherzellen im Herstellungsverfahren und nichtflüchtige, resistiv schaltende Speicherzelle
CN100461482C (zh) * 2004-11-17 2009-02-11 株式会社东芝 开关元件、线路转换设备和逻辑电路
DE102005016244A1 (de) 2005-04-08 2006-10-19 Infineon Technologies Ag Speicherzelle, Speichereinrichtung und Verfahren zu deren Herstellung
US8101942B2 (en) * 2006-09-19 2012-01-24 The United States Of America As Represented By The Secretary Of Commerce Self-assembled monolayer based silver switches
JP5216254B2 (ja) * 2007-06-22 2013-06-19 株式会社船井電機新応用技術研究所 メモリ素子アレイ
JP2009049287A (ja) * 2007-08-22 2009-03-05 Funai Electric Advanced Applied Technology Research Institute Inc スイッチング素子、スイッチング素子の製造方法及びメモリ素子アレイ
JP5455415B2 (ja) * 2009-04-10 2014-03-26 株式会社船井電機新応用技術研究所 ナノギャップ電極を有する素子の製造方法
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8350316B2 (en) * 2009-05-22 2013-01-08 Macronix International Co., Ltd. Phase change memory cells having vertical channel access transistor and memory plane
JP2013232494A (ja) 2012-04-27 2013-11-14 Sony Corp 記憶素子、半導体装置およびその動作方法、ならびに電子機器

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WO1997048032A2 (en) * 1996-05-30 1997-12-18 Axon Technologies Corporation Programmable metallization cell and method of making
WO2002021598A1 (fr) * 2000-09-01 2002-03-14 Japan Science And Technology Corporation Dispositif electronique a conductance controlable
WO2002037572A1 (fr) * 2000-11-01 2002-05-10 Japan Science And Technology Corporation Reseau a pointes, circuit non, et circuit electronique contenant ceux-ci
WO2003028124A1 (fr) * 2001-09-25 2003-04-03 Japan Science And Technology Agency Dispositif electrique comprenant un electrolyte solide

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US5879955A (en) * 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
EP1044452B1 (de) * 1997-12-04 2003-03-19 Axon Technologies Corporation Programmierbare metallisierungsstruktur mit oberflächennaher verfestigung undherstellungsverfahren dafür
US6635914B2 (en) * 2000-09-08 2003-10-21 Axon Technologies Corp. Microelectronic programmable device and methods of forming and programming the same
US6344674B2 (en) * 2000-02-01 2002-02-05 Taiwan Semiconductor Manufacturing Company Flash memory using micro vacuum tube technology
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Publication number Priority date Publication date Assignee Title
WO1997048032A2 (en) * 1996-05-30 1997-12-18 Axon Technologies Corporation Programmable metallization cell and method of making
WO2002021598A1 (fr) * 2000-09-01 2002-03-14 Japan Science And Technology Corporation Dispositif electronique a conductance controlable
EP1329958A1 (de) * 2000-09-01 2003-07-23 Japan Science and Technology Corporation Elektronische einrichtung mit steuerbarem leitwert
WO2002037572A1 (fr) * 2000-11-01 2002-05-10 Japan Science And Technology Corporation Reseau a pointes, circuit non, et circuit electronique contenant ceux-ci
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WO2003028124A1 (fr) * 2001-09-25 2003-04-03 Japan Science And Technology Agency Dispositif electrique comprenant un electrolyte solide

Non-Patent Citations (2)

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Also Published As

Publication number Publication date
US20060154467A1 (en) 2006-07-13
CN100428519C (zh) 2008-10-22
AU2003289813A1 (en) 2004-06-23
CN1720625A (zh) 2006-01-11
WO2004051763A2 (de) 2004-06-17
DE10393702B4 (de) 2010-04-15
DE10256486A1 (de) 2004-07-15
DE10393702D2 (de) 2005-07-21

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