WO2004040768A1 - Circuit de detection de gain par comparaison de phases, circuit de detection de synchronisation erronee et circuit a boucle a phase asservie - Google Patents

Circuit de detection de gain par comparaison de phases, circuit de detection de synchronisation erronee et circuit a boucle a phase asservie Download PDF

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Publication number
WO2004040768A1
WO2004040768A1 PCT/JP2002/011319 JP0211319W WO2004040768A1 WO 2004040768 A1 WO2004040768 A1 WO 2004040768A1 JP 0211319 W JP0211319 W JP 0211319W WO 2004040768 A1 WO2004040768 A1 WO 2004040768A1
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Prior art keywords
phase
data
signal
identification
phase comparison
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PCT/JP2002/011319
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English (en)
Japanese (ja)
Inventor
Kouichi Suzuki
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2004547995A priority Critical patent/JP3908764B2/ja
Priority to PCT/JP2002/011319 priority patent/WO2004040768A1/fr
Publication of WO2004040768A1 publication Critical patent/WO2004040768A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • Phase comparison gain detection circuit Phase comparison gain detection circuit, false synchronization detection circuit, and PLL circuit
  • the present invention relates to a phase comparison gain detection circuit, a false synchronization detection circuit, and a PLL circuit, and particularly to a PLL circuit that can be applied to a case where a reference cook signal is extracted from received data in an optical transceiver for optical communication, and
  • the present invention relates to a phase comparison gain detection circuit and a false synchronization detection circuit that can be applied thereto.
  • FIG. 1A shows a general configuration of a PLL circuit for clock extraction.
  • the phase difference between the clock signal CL, which is the output of the VCO (voltage controlled oscillation circuit) 40, and the input data DA is detected by the phase comparator 10, and the charge pump 20 is driven according to the detected output.
  • a current proportional to the output of the phase comparator is supplied to the loop filter 30.
  • the supply current is smoothed by the loop filter 30, and the result is fed back to VC400.
  • FIG. 1B is a circuit diagram showing an example of the configuration of the loop filter 30.
  • the loop filter 30 is composed of a series circuit of a resistor R and a capacitor C, and has a function of smoothing an input current and converting it into an output voltage.
  • the PLL circuit can obtain the clock signal CL synchronized with the input data signal DA.
  • the phase comparison gain in phase comparator 10 is Kp
  • the current amplitude in charge pump 20 is Ic
  • the transfer function of loop filter 30 is F (s)
  • the gain of VCO KV.
  • Open loop gain [ ⁇ ⁇ I c ⁇ F (s) ⁇ Kv] / s
  • open loop gain [Kp ⁇ Ic ⁇ R ⁇ KvZs] ⁇ [1 + 1 / s CR]
  • closed loop gain [ ⁇ ⁇ Ic ⁇ R ⁇ ⁇ ⁇ (1 + s CR)] / [s ⁇ 2 ⁇ CR + Kp ⁇ Ic ⁇ R ⁇ Kv ⁇ (1 + sCR)]
  • the closed loop gain power-off frequency is a frequency at which the open loop gain becomes 0 dB, and is proportional to the respective gains of the phase comparator 10, the charge pump 20, and the VC040 (Fig. 2A). See).
  • the cutoff frequency becomes high, and as a result, the output jitter tends to increase.
  • the cutoff frequency is low, which tends to reduce the phase margin and increase peaking. In that case, the phase error response tends to be poor.
  • the closed-loop characteristic as the jitter characteristic of PLL is equivalent to a so-called jitter transfer, and is represented by the amplification factor of the output jitter with respect to the input jitter when the PLL is locked. This value is better as the response speed of PLL is slower.
  • jitter tolerance which is an index of how much jitter the PLL can withstand in a licked state, conversely, the higher the response speed of the PLL, the greater the tolerance. Therefore, they are in a trade-off relationship with each other.
  • FIG. 3 is a block diagram showing an example of an identification timing signal extraction circuit to which the PLL method is applied.
  • the data of the input data signal DA is extracted by the identification circuit 100 based on the clock signal CL extracted by the PLL circuit function as described above.
  • a PLL circuit in such an optical transmitting and receiving circuit unlike a PLL circuit used in a general frequency synthesizer, random data is input as an input data signal. Therefore, when the frequency of the input signal fluctuates greatly, the level of the frequency component value to be extracted relatively decreases, and as a result, the PLL loop gain decreases and the operation becomes unstable.
  • FIG. 4 shows a well-known half-rate clock Bang— A circuit example when a Bang circuit is applied is shown.
  • two D-FF (D-flip-flop) circuits detect the input data signal DA and detect the edge of the clock signal for data identification by delaying it by ⁇ / 2 phase.
  • the data identification operation is performed by the clock signals CL and.
  • the exclusive OR circuit EXOR performs an exclusive OR operation on the resulting signals Da and Db to obtain a signal Dc.
  • the exclusive OR sum Dc becomes an intermittent signal as shown in FIG.
  • the exclusive logical sum output Dc is likely to be a continuous signal.
  • the level of the signal obtained through such a low-pass filter by the charge pump 20 and the loop filter 30 with respect to such a phase comparison result is, as shown in FIG.
  • the output level of the low-pass filter becomes high.
  • the oscillation frequency of VCO 40 is controlled according to the output level of the low-pass filter.
  • the VCO oscillation frequency is reduced to act to delay the phase of the clock signal CL in accordance with the phase of the data signal.
  • the VCO oscillation frequency increases, and acts to advance the phase of the clock signal with respect to the data signal.
  • FIGS. 14A and 14B show examples of output waveforms of the phase comparator 10 having the configuration as shown in FIG.
  • the ideal output characteristic shown by the broken line is actually shown by the solid line due to the input jitter, the effect of the setup and hold operation characteristics of the D-FF circuit in the phase comparator, etc.
  • the waveform is rounded as described above.
  • the waveform becomes rounded depending on the edge ratio of the input data.
  • the loop gain of the PLL circuit fluctuates, thereby causing the above-mentioned unstable circuit operation. Disclosure of the invention
  • an object of the present invention is to provide a PLL circuit capable of providing a stable PLL circuit operation irrespective of fluctuations in the edge ratio and duty of input data, effects of circuit characteristics, and the like.
  • phase comparison operations are performed with different phase conditions with respect to identification of an input data signal, and the phase comparison gain is detected by comparing the respective phase comparison results. Therefore, it is possible to detect the on-time phase comparison gain in consideration of the fluctuation factors of the phase comparison gain such as the edge ratio and duty of the input data signal and the setup and hold characteristics of the discriminator. As a result, on-time and accurate loop gain compensation control can be realized by controlling the loop gain of the PLL circuit based on the phase comparison detection result.
  • FIGS. 1A and 1B are diagrams showing a configuration of a conventional PLL circuit.
  • FIGS. 2A and 2B are diagrams illustrating the loop gain of the PLL circuit.
  • FIG. 3 is an explanatory diagram of the operation of the conventional PLL circuit.
  • FIG. 4 is a diagram showing a circuit example of a conventional half-rate clock Bang-Bang phase comparator.
  • FIG. 5 is a diagram for explaining the data identification phase.
  • FIG. 6 is a time chart (part 1) of each signal in the circuit of FIG.
  • FIG. 7 is a time chart (part 2) of each signal in the circuit of FIG.
  • FIG. 8 is a time chart (part 3) of each signal in the circuit of FIG.
  • FIG. 9 is a time chart (part 4) of each signal in the circuit of FIG.
  • FIG. 10 is a time chart (part 5) of each signal in the circuit of FIG.
  • FIG. 11 is a time chart (part 6) of each signal in the circuit of FIG.
  • FIG. 12 is a time chart (part 7) of each signal in the circuit of FIG.
  • FIG. 13 is a time chart (No. 8) of each signal in the circuit of FIG.
  • FIGS. 1A and 4B are diagrams (part 1) for explaining the state of deterioration of the phase comparison characteristic.
  • FIG. 15 is a circuit block diagram of an example of a PLL circuit having a phase comparison gain compensation function.
  • FIG. 16 is a circuit diagram showing an example of the phase comparison gain detection circuit.
  • FIG. 17 is a diagram (part 2) for explaining the state of deterioration of the phase comparison characteristic.
  • FIG. 18 is a block diagram of one embodiment of the present invention.
  • FIG. 19 is a diagram for explaining the principle of detecting the phase comparison gain by the configuration shown in FIG.
  • FIG. 20 is a circuit diagram of one embodiment of the present invention.
  • FIG. 21 is a time chart of each signal in the circuit shown in FIG.
  • FIG. 22 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG. 20.
  • FIG. 23 is a circuit diagram of a P-mode according to an embodiment of the present invention using the phase comparison detection circuit having the configuration shown in FIG.
  • FIG. 25 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG.
  • FIG. 26 is a circuit diagram of a false synchronization detecting circuit according to still another embodiment of the present invention.
  • FIG. 27 is a diagram for explaining the principle of false synchronization detection by the configuration shown in FIG. Description of the preferred embodiment
  • the gain change of the PLL circuit (for example, the circuit shown in FIG. 15) as described above is compensated by detecting the gain of VC040, the gain of phase comparator 10 is detected based on the edge rate of data DA. Then, a method of adjusting the output current of the charge pump 20 based on the detection result, or adjusting the capacitance value or the resistance value of the filter 30 and compensating the same can be considered.
  • the gain of the phase comparison note 10 is detected by the phase comparison gain circuit 210, and the characteristics of the charge pump are controlled by the control circuit 220 based on the detection result.
  • the phase comparator 10 has a sawtooth phase comparison characteristic (see FIG. 17) like a well-known Hogge phase comparator as shown in FIG. 16, for example, the phase period is determined.
  • the output amplitude determines the gain.
  • the phase comparison gain compensating circuit as shown in FIG. 15 the fluctuation of the amplitude due to the fluctuation of the edge ratio of the data is detected. That is, in this case, the output of the EXOR circuit 21 3 becomes “H” when the data has an edge, that is, “H” when the data changes, and “L” when there is no data.
  • the edge rate of the data can be detected by averaging this with L PF (a circuit using R and C).
  • the control circuit 220 compensates for the fluctuation of the output amplitude of the phase detector by adjusting the current of the charge pump 20.
  • phase comparison gain is determined according to the stochastic fluctuation of the phase comparator output.
  • the fluctuation factors of the phase comparison gain include, in addition to the fluctuation of the data edge ratio, (1) the jitter of the input data, and (2) the input data.
  • the jitter of the input data, the duty of the input data, and the setup / hold characteristics of the discriminator (FF) of the phase comparator vary.
  • a circuit for accurately detecting a change in the phase comparison gain due to the change and the like is also possible.
  • FIG. 18 is a principle diagram of one embodiment of the present invention.
  • the phase comparison detector 300 includes a phase comparator 311, which receives a clock signal CL for identifying the data DA as an input, and delays the data identification clock signal CL by a predetermined time to generate a clock signal CL. It comprises a delay unit 313 for outputting, a phase comparator 312 having the delayed clock signal CL, as an input, LPFs 314 and 315 for smoothing the output, and a difference voltage detection circuit 316.
  • the data identification operation is performed by the two clock signals CL and CL having different phases, respectively.
  • a desired phase comparison gain is detected from the time difference between each of the phase comparator outputs D 1 and D 2 and the clock signals CL and CL ′, that is, from the predetermined delay time. This makes it possible to detect the phase comparison gain that incorporates the setup and hold time of the phase comparator, the edge rate and jitter of the input data, and the fluctuation of the duty and the parallelism, etc. Therefore, by controlling based on the detection output, the loop gain of the entire PLL circuit can be compensated so as to be constant. Therefore, a stable response characteristic is obtained, and a PLL circuit satisfying a desired jitter transfer characteristic can be provided.
  • FIG. 19 shows the output levels of the phase comparators 311 and 312 for explaining the principle of the embodiment of the present invention.
  • the phase comparison characteristics in FIG. 19 correspond to those shown in FIGS. 14A and 14B. I do.
  • the phase comparison output is The rate of change, that is, AVZ ( ⁇ t / T), corresponds to the phase comparison gain Kp.
  • AV is the difference voltage between the values D 1 and D 2 obtained by smoothing the phase comparison output under different phase conditions
  • ⁇ t is the delay unit 313 that provides the difference in the phase conditions.
  • T is the signal period of the clock signal.
  • FIG. 20 shows a configuration of a phase comparison detection circuit according to an embodiment of the present invention, which further embodies the configuration of FIG.
  • This circuit is a phase comparison gain detection circuit to which a Bang-Bang phase comparator using a half-rate clock is applied.
  • the circuit is provided with data discriminators 411, 412, data edge detection discriminator 413, and phase comparison gain detection discriminator 414 as discriminators (FF).
  • a circuit 431 that performs a logic operation between the data identification FF output DO a and the data edge detection FF output DOc as an OR circuit (EX OR). Similarly, a logic between the data identification FF output DO b and the data edge detection FF output DO c.
  • the appearance probability of the H level at the output P h1 of the EXOR circuit 441 is approximately equal to the appearance probability of the H level at the output P h 2 of the EXOR 442. Become equal.
  • the appearance probability of the H level is higher than each of the former. That is, EXOR circuit
  • the probability that DO a and DO d as inputs of 443 match is the probability that DO a and DO c as inputs of EXOR circuit 441 match or DO b and DO c as inputs of EXOR circuit 442 This is because the probability of matching is lower.
  • the occurrence probability of the A-system data in the signal DO d is smaller than the appearance probability of the A-system data in the signal DO c, and similarly, the occurrence probability of the B-system data in the signal DO c This is because the appearance probability of A-system data in DO d is smaller.
  • the clock signal C Lb intentionally delayed by a predetermined time ⁇ t is generated to perform data identification, and the identification result data is identified by the clock CL not delayed by At.
  • Exclusive OR with the data of the identified result.
  • an exclusive OR of the identification result data obtained by performing the data identification using the edge detection clock signal CLa and the identification result data obtained by using the clock CL which is not delayed by ⁇ t is calculated.
  • the result of these two types of exclusive OR is smoothed by LPF, and the level difference is divided by the phase obtained by standardizing the delay amount ⁇ t with the period T to obtain the phase comparison gain Kp.
  • a delay ⁇ t is intentionally generated after synchronization is established, and a clock signal (signal C Lb in the examples of FIGS. 20 and 21) is generated in a pseudo manner in synchronization with the data signal DA.
  • Pseudo-synchronous shift The same data signal DA is identified by the clock signal. Then, the exclusive OR output between the identification data obtained therefrom and the data identified by the clock signal CLa delayed by ⁇ / 2 is smoothed to obtain a “pseudo synchronization shift” phase comparison detection value.
  • the exclusive data between the identification data identified by the clock signal CL in the synchronized state and the data identified by the clock signal CLa also delayed by ⁇ 2 The value obtained by smoothing the logical sum output, that is, "the phase comparison detection value at the time of synchronization" is compared. It can be said that the larger the difference between the comparison results, the higher the phase comparison detection sensitivity to the phase difference between the data signal DA and the clock signal CL, which is synonymous with the higher phase comparison gain.
  • the phase comparison gain incorporating all of the current edge ratio, duty, setup / hold characteristics of each discriminator (FF), and the like is obtained, and therefore, it is very accurately turned on. Effective phase comparison gain of time Is possible.
  • FIG. 23 shows an example of a PLL circuit having a phase comparison gain compensation function according to an embodiment of the present invention.
  • the phase comparison output Ph 1 and Ph 3 of the phase comparator detection circuit 400 having the configuration of FIG. A / D converter 510 that converts the difference voltage between the two into a digital signal, compares the digital difference voltage with a predetermined reference value, adjusts the output current of the charge pump based on the comparison result, and thereby adjusts the PL. It has a configuration to compensate for the loop gain of the L circuit.
  • the data outputs D Oa and DOb of the phase comparison detection circuit 400 shown in FIG. 20 can be used as they are as the reproduction data of the input data. That is, these data outputs DOa and DOb correspond to the outputs of the identification circuit 100 in FIG.
  • the loop gain of the PLL circuit is determined based on the phase comparison output difference voltage between the “pseudo-synchronization” identification signal and the “synchronization” identification signal obtained by the phase comparison detection circuit 400. For control, it is possible to provide a PLL circuit having an accurate loop gain compensation function taking into account the current input signal characteristics and phase comparison circuit characteristics.
  • the control circuit 520 is not limited to the circuit configuration shown in FIG. 23, and the transfer function F (s) of the filter 30 and the gain of the VC040, which determine the loop gain of the PLL circuit other than the output current amplitude Ic of the charge pump, It goes without saying that a configuration may be adopted in which the loop gain of the PLL circuit is compensated by controlling Kv and the like.
  • the Bang-angang phase comparator using the half-rate clock is applied to the phase comparison detection circuit 400.
  • the phase comparison characteristic using the full-rate clock has a sawtooth waveform.
  • the present invention can be applied to a phase comparator as shown in FIG. FIG. 24 shows a circuit configuration example of the phase comparison detection circuit in that case.
  • the discriminator 611 that identifies the data signal DA at the timing of the clock signal C and the data signal DA are delayed by a predetermined amount by the delay signal 622 from the clock signal CL.
  • a discriminator 612 for discriminating by.
  • EXO which takes the exclusive OR of each of the discrimination outputs DO 1 and DO 2 by these discriminators 611 and 612 and the data signal DA R631, 632 are provided, and low-pass filters 641, 642 for smoothing the outputs of these EXORs 631, 632 are provided.
  • FIG. 25 is a diagram for explaining the difference voltage obtained in that case.
  • the difference voltage ⁇ between the outputs Ph 1, Ph 2 of the LPFs 64 1, 642 detected here and Ph 2 is the delay phase amount obtained by standardizing ⁇ t, which is the delay amount by the delay unit 622, with the period T.
  • ⁇ t / T which represents, the phase comparison gain Kp can be obtained (see the following equation).
  • the control circuit 520 shown in FIG. 23 determines the loop gain determining factor parameters such as the current amplitude value Ic of the charge pump 20. By compensating the loop gain, the loop gain of the PLL circuit is compensated.
  • the phase comparison gain can be compensated even when there is a gain variation due to factors other than the edge rate of the input data.
  • the phase comparator may have another configuration, and has a function of delaying or advancing the phase of the clock signal CL or the phase of the input data signal DA by a predetermined amount, and has a circuit configuration similar to the phase comparator.
  • a PLL circuit may be configured by incorporating the detection circuit. As described above, according to the present invention, the phase comparison gain is compensated for in accordance with the variation of the phase comparator of the PLL circuit and the jitter of the input data, etc. It is possible to stabilize the jitter frequency characteristics while maintaining the same, thereby improving the performance of the PLL circuit.
  • FIG. 26 and FIG. 27 are diagrams for explaining an erroneous synchronization detection device according to another embodiment of the present invention.
  • FIG. 26 is substantially the same as the circuit configuration of FIG. 18, and the corresponding components are denoted by the same reference numerals, and redundant description will be omitted.
  • a sawtooth wave characteristic as shown by a broken line in FIG. 27 is used as a phase comparator of the PLL circuit. It is assumed that there is a property. That is, it has a characteristic that a detection voltage output according to the detected phase difference changes in a sawtooth waveform according to the detected phase difference.
  • a phase lock is applied at an intermediate portion of the rising ramp portion of the sawtooth wave, that is, at a point P in the figure, so that a central portion between signal change points of the input data signal DA, that is, The phase of the clock signal CL can be locked so that data can be identified at the timing of the center of the clock (see Fig. 5).
  • the waveform distortion as shown by the solid line in FIG. 27 may occur in the sawtooth characteristic due to the fluctuation of the duty of the input data signal DA, and the like.
  • the PLL circuit may erroneously lock the phase at point Q in Fig. 27.
  • erroneous synchronization occurs, and the clock signal performs data identification at the timing of the crosspoint of the data eye pattern, so that the identification data is likely to be erroneous.
  • the phase comparison detection output of the phase comparator It depends on the delay amount ⁇ t given by 3 1 3 and 6 2 2.
  • the amount of change has a characteristic that depends on the absolute phase between the data signal DA and the clock signal CL. That is, when the phase difference between the data signal DA and the clock signal CL is near zero, that is, when the data is identified at the timing of the center of the eye pattern of the data signal DA (see FIG. 5), the data can be correctly identified.
  • the exclusive OR result of the identification signal and the data signal DA indicates that even if the data identification timing is delayed by the delay device 3 13, as long as the delay ⁇ t is somewhat smaller than the period T, the delay Only a difference approximately proportional to the amount occurs.
  • the possibility of identifying correct data is about 50%.
  • the delay is delayed by the predetermined amount ⁇ t from that timing, and the delay amount At exceeds the above-mentioned indeterminate state (dead zone) and is large enough to be an identification timing at which data can be identified almost accurately, correct data identification is performed. Is nearly 100%.
  • the discrimination result based on such a discrimination timing is significantly different from the discrimination result when there is no delay (that is, when the discrimination rate is about 50% in an undefined state). The difference is much larger than in the case of the above-described identification near the center of the eye pattern.
  • the present invention includes the following configurations.
  • Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain
  • First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal
  • Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount
  • Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal
  • a phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit. (Configuration 2)
  • the first phase comparison means detects a phase relationship between the input data signal and the identification timing signal in a substantially synchronized state
  • the second phase comparison means is a phase comparison gain detection circuit configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
  • phase relationship between the input data signal and the identification timing signal is determined.
  • a phase comparison gain detection circuit for detecting a phase comparison gain when comparing phases
  • Phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a second predetermined amount for shifting the identification timing. And a phase comparison gain detection circuit.
  • Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain
  • the phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
  • a phase comparison gain detection circuit comprising phase comparison gain detection means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparison means and a predetermined amount for shifting the identification timing of the identification timing signal.
  • phase comparison gain detecting circuit according to the above configuration 3 or 4, wherein the data correlation detection between the data in the first and second phase comparing means has a configuration realized by an exclusive OR operation.
  • phase comparison gain detection circuit according to the above configuration 5, wherein the exclusive OR output is smoothed and input to the phase comparison gain detection means.
  • phase comparison gain detection circuit according to any one of the above configurations 3 to 6, wherein each data is identified by a flip-flop circuit.
  • An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal
  • Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount
  • Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal
  • An erroneous synchronization state is detected based on a difference between respective outputs of the first and second phase comparison means. Erroneous synchronization detection circuit.
  • An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • a false synchronization detection means for detecting a false synchronization state based on the difference between the outputs of the first and second phase comparison means.
  • An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • First phase comparing means for comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal.
  • the phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
  • An erroneous synchronization detection circuit comprising erroneous synchronization detection means for detecting an erroneous synchronization state based on a difference between respective outputs of the first and second phase comparison means.
  • a PLL circuit comprising at least one of the phase comparison gain detection circuit of any of the above configurations 1 to 7 and the false synchronization detection circuit of any of the above configurations 8 to 11.
  • a control circuit for controlling the loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit, and a control for controlling the phase lock operation based on the false synchronization detection result of the false synchronization detection circuit A PLL circuit further comprising at least one control circuit of the circuits.
  • the control circuit is configured to change at least one of a current amplitude of a charge pump constituting the PLL circuit, a transfer function of a loop filter, and a control gain of a VCO;
  • the PLL circuit having the above configuration 11.
  • Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain
  • a phase comparison gain detection step for detecting a phase comparison gain based on a difference between output values obtained in each of the first and second phase comparison steps and a predetermined amount for shifting the phase relation in the phase relation shift step.
  • Phase comparison gain detection method Phase comparison gain detection method.
  • the input data signal and the identification timing signal are substantially synchronized. Detect the phase relationship between the two states,
  • a phase comparison detection method configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
  • phase relationship between the input data signal and the identification timing signal is determined.
  • a phase comparison step of detecting a phase comparison gain based on a difference between comparison output values in each of the first and second phase comparison steps and a second predetermined amount that shifts the identification timing is compared.
  • a phase comparison gain detection method comprising a gain detection step.
  • Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain
  • a first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal.
  • the data of the input data signal is obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
  • An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • An erroneous synchronization detection method configured to detect an erroneous synchronization state based on a difference between respective outputs in the first and second phase comparison stages.
  • An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • An error synchronization detection method including an error synchronization detection step of detecting.
  • An erroneous synchronization detection circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
  • a first phase comparison step of comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal;
  • the phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
  • An erroneous synchronization detection method comprising: an erroneous synchronization detection step of detecting an erroneous synchronization state based on a difference between outputs in each of the first and second phase comparison steps.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un circuit de détection de gain par comparaison de phases d'une boucle à phase asservie, dans lequel une comparaison de phases est mise en oeuvre entre un signal de données DA et un signal d'horloge CL ; et une comparaison de phases est mise en oeuvre entre le signal de données DA et un signal d'horloge CL', obtenu en appliquant au signal d'horloge CL une valeur de retard spécifiée ; et un gain par comparaison de phases est détecté sur la base de la différence entre les résultats respectifs de la comparaison de phases et la valeur de retard spécifiée.
PCT/JP2002/011319 2002-10-30 2002-10-30 Circuit de detection de gain par comparaison de phases, circuit de detection de synchronisation erronee et circuit a boucle a phase asservie Ceased WO2004040768A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004547995A JP3908764B2 (ja) 2002-10-30 2002-10-30 位相比較利得検出回路、誤同期検出回路及びｐｌｌ回路
PCT/JP2002/011319 WO2004040768A1 (fr) 2002-10-30 2002-10-30 Circuit de detection de gain par comparaison de phases, circuit de detection de synchronisation erronee et circuit a boucle a phase asservie

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2002/011319 WO2004040768A1 (fr) 2002-10-30 2002-10-30 Circuit de detection de gain par comparaison de phases, circuit de detection de synchronisation erronee et circuit a boucle a phase asservie

Publications (1)

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WO2004040768A1 true WO2004040768A1 (fr) 2004-05-13

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007053414A3 (fr) * 2005-10-31 2007-09-13 Teradyne Inc Méthode et appareil d’ajustement de signaux d’horloge synchrone

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01215122A (ja) * 1988-02-24 1989-08-29 Hitachi Ltd 位相同期信号発生回路
JPH0730415A (ja) * 1993-07-12 1995-01-31 Oki Electric Ind Co Ltd Ｐｌｌ回路
WO2001054283A1 (fr) * 2000-01-17 2001-07-26 Fujitsu Limited Boucle a phase asservie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01215122A (ja) * 1988-02-24 1989-08-29 Hitachi Ltd 位相同期信号発生回路
JPH0730415A (ja) * 1993-07-12 1995-01-31 Oki Electric Ind Co Ltd Ｐｌｌ回路
WO2001054283A1 (fr) * 2000-01-17 2001-07-26 Fujitsu Limited Boucle a phase asservie

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007053414A3 (fr) * 2005-10-31 2007-09-13 Teradyne Inc Méthode et appareil d’ajustement de signaux d’horloge synchrone
JP2009514361A (ja) * 2005-10-31 2009-04-02 テラダイン、 インコーポレイテッド 同期クロック信号を調整する方法および装置
US7593497B2 (en) 2005-10-31 2009-09-22 Teradyne, Inc. Method and apparatus for adjustment of synchronous clock signals

Also Published As

Publication number Publication date
JP3908764B2 (ja) 2007-04-25
JPWO2004040768A1 (ja) 2006-03-02

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